[gem5-users] scheduling of readreq (ifetch) misses that happen on the same cycle
Hello, I am having a question on how requests and responses are being routed. If on the same tick, I have a request made from both of the caches, and it is or example a miss request, so an access to L2 is needed. How is determined which one will be scheduled first? For example, I have this: 5567000: system.cpu.icache: ReadReq (ifetch) 65900 miss 5567000: system.secondmainCpu.icache: ReadReq (ifetch) 65900 miss So, the request is made on the same cycle. And it is for the same packet as I want. And here are the responses: 5624000: system.secondmainCpu.icache: Handling response to 65900 5624000: system.secondmainCpu.icache: Block for addr 65900 being updated in Cache 5633000: system.cpu.icache: Handling response to 65900 5633000: system.cpu.icache: Block for addr 65900 being updated in Caches >From what I have seen the response in the cpu.icache arrives ALWAYS 9000 ticks >later (I have checked it in all my traces). Any explanation on why that happens? and secondly, whether I can somewhere which one will be served first? Thanks, Ignatios ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] cache blk is neither Writable nor Readable
Hello again, I moved forward a little bit from my previous question and the things are more weird right now. I have made some changes in the gem5 and I have these: For example for some read requests in the data cache: 3789000: system.secondmainCpu.dcache: ReadReq b8cf8 hit 3789000: system.secondmainCpu.dcache: pkt->needsExclusive(): false 3789000: system.secondmainCpu.dcache: blk->isWritable(): false 3789000: system.secondmainCpu.dcache: blk->isReadable(): false 3789000: system.secondmainCpu.dcache: cache_impl.hh, incMissCount for b8cf8, called 3789000: system.secondmainCpu.dcache: ::timingAccess in cache_impl.hh. We have a miss So although it is a hit, because the block is not readable() the code deals with it as a miss and not only the stats are increased like it is a miss but also the actions for a miss are performed. Similarly, in a WriteReq the block needs to be Writable and needExclusive(), but the isWritable is false and it agains considered as a miss. So my question is where the block is inserted in the cache because something is not set up correctly ? Where the isWritable() or isReadable() are being set ? Thanks, Ignatios ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] different number of misses in the trace file and in the generated stats.txt
Hello all, I have made some changes in the gem5 (add one extra core) and the result is that for the second core the number of dcache.WriteReq_misses is differtent in the stats.txt with the misses that I can count in the trace file (while for the first cpu they are the same). For example, I can see 13 misses and the measured are 94, which is a great difference while in bigger benchmarks, I expect less than 10.000 misses and I have over 100.000 in my stats file. I am counting as a miss in the trace file lines like this: system.secondmainCpu.dcache: WriteReq b58a8 miss that come from the cache_impl.hh file where: DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(), pkt->req->isInstFetch() ? " (ifetch)" : "", pkt->getAddr(), (blk) ? "hit" : "miss"); Where the counter for the stats is being incremented in order to see why the two numbers are not equal for my second cpu.dcache? Thanks, Ignatios ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Assertion instsToExecute.empty() failed
Hello all, I try to run a workload and I am having 2 cores. My workload consists of 100 intervals. If I try to switch between cores frequently (for example there are some cases that I want to switch at consecutive intervals like 17,18,19,20,21) then I get the following assertion: Assertion instsToExecute.empty() failed If the switches are not that often or if I use other workload with infrequent switches as well, the problem goes away. Why that might be? Thanks, Ignatios ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] question on number of Readreq_accesses across different simulations
Hello, I have made some modification in the gem5 code so as to have 2 cores and change the workload between them (so that in the first intervals for example run the code in the first core and then switch to the second one and so on). I have a question on the results I get: Does the number of icache.ReadReq_accesses for example be the same in every interval with the number of when running on only one core. What I mean is this: 1. I will first run my simulation only on core A. And in every interval I have some numbers for icache.ReadReq_accesses, for example. 2. Now I am running the simulation and I switch cores during execution. Does the number of icache.ReadReq_accesses should be the same as in the previous interval for each interval? Like icache.ReadReq_accesses of interval 1 of current simulation to be equal with icache.ReadReq_accesses of itnerval 2 of previous one, and what changes to be the simulation time. Or am I missing something? because If I print some traces I can see something like this for example: ONE CORE - interval 0: system.cpu.icache: ReadReq (ifetch) 41940 hit system.cpu.icache: ReadReq (ifetch) 41e00 miss system.cpu.icache: ReadReq (ifetch) 41e80 miss system.cpu.icache: ReadReq (ifetch) 40e40 hit system.cpu.icache: ReadReq (ifetch) 41e80 hit system.cpu.icache: ReadReq (ifetch) 40e00 hit CORE SWITCHING - interval 0: system.cpu.icache: ReadReq (ifetch) 41940 hit system.cpu.icache: ReadReq (ifetch) 41980 miss --different packet->addr() --missing packet system.cpu.icache: ReadReq (ifetch) 40e40 hit --missing packet system.cpu.icache: ReadReq (ifetch) 40e00 hit Is it logical or I have done something wrong? Regards, Ignatios ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] warn: allocating bonus target for snoop appears thousands of times - simulation is slower than expected
Hello,
in my last emails I had a problem when simulating for large of instructions
(100 intervals of 10M instructions each), the assertion !freeList.empty() was
raised.
What actually made my system, run without any problem theoretically is that In
increased the number of MSHRQueue in src/mem/cache/base.cc from 4 to 8 like
this:
BaseCache::BaseCache(const Params *p)
: MemObject(p),
mshrQueue("MSHRs", p->mshrs, 8, MSHRQueue_MSHRs),
and now my program terminates correctly.
However, during simulation I get a thousands of these warnings:
warn: allocating bonus target for snoop
and the system is considerably slower than it should be. Normally the
simulation should finish in an a hour and a half but this takes more than 3
hours.
I have made modifications to memory-objects and I am using ARM architecture.
My questions are:
1. Is it a problem that I increased the number of MSHRQueue?
2. Is the warning worrying? Might it be that because of that warning my system
has became slower?
regards,
Ignatios
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[gem5-users] assertion !freeList.empty is raised()
Hello, I still have an issue with the above assertion. (is in mem/cache/mshr_queue.cc) I am using ARM architecture. If I use only one core, then it runs withoun any problem no matter for how many instructions I will simulate. If I use two cores, then if I simulate for a few instructions (like until 10k for warm-up and fast-fwd and 5 itnervals of 10k each) it plays without any problem. If I try to simulate for more, then the assertion is raised. When the assertion is raised, the number of allocated entries is 5, if it plays any difference. I really do not know where to look at, and why that might happen? What is freeList used for? From which part of the code, entries are deleted and why that happen only on my large benchmarks with 2 cpus, while for one cpu, it plays without any problem. I can see that is being called when a cache miss happen and then an mshr miss (from the cache_impl.hh).r Then the allocateMissBuffer is called for the mshrQueue, which tries to call mq->allocate. And then the assertion is raised. Any hint on where to lack, or any way of surpassing it? regards, Ignatios ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] cannot add debug message to mshr_queue.cc
Hello,
I am trying to place that code inside mem/cache/mshr_queue.cc
if (!freeList.empty()){
DPRINTF(Cache,"!freeList.empty() returns True\n");
} else {
DPRINTF(Cache,"!freeList.empty() returns False\n");
}
and I have included:
#include "debug/Cache.hh"
but gem5 cannot compile and I get this error:
build/ARM/mem/cache/mshr_queue.cc: In member function 'MSHR*
MSHRQueue::allocate(Addr, int, Packet*&, Tick, Counter)':
build/ARM/mem/cache/mshr_queue.cc:171:17: error: 'Cache' was not declared in
this scope
build/ARM/mem/cache/mshr_queue.cc:171:17: note: suggested alternative:
build/ARM/debug/Cache.hh:12:19: note: 'Debug::Cache'
build/ARM/mem/cache/mshr_queue.cc:171:57: error: 'DPRINTF' was not declared in
this scope
build/ARM/mem/cache/mshr_queue.cc:173:17: error: 'Cache' was not declared in
this scope
build/ARM/mem/cache/mshr_queue.cc:173:17: note: suggested alternative:
build/ARM/debug/Cache.hh:12:19: note: 'Debug::Cache'
build/ARM/mem/cache/mshr_queue.cc:173:58: error: 'DPRINTF' was not declared in
this scope
In all other files I could add debug messages with the same way but not in
here. Why is that?
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Re: [gem5-users] Assertion `instcount <= 1500' failed and Assertion `!freeList.empty()' when having more than one cpus - problem remains
Well, although my copy of gem5 was earlier of the day, I can see this code in my files as well :/ I tried also with debug and before the abortion I see messages like these: 0: [sn:1] not destroyed 1500 times. What should I do? If I use smaller intervals (instead of 1M or 10M, 10K for example) it works fine. Thanks, > Date: Sat, 4 May 2013 14:50:47 -0400 > From: ged...@rtems.org > To: gem5-users@gem5.org > Subject: Re: [gem5-users] Assertion `instcount <= 1500' failed and Assertion > `!freeList.empty()' when having more than one cpus > > What CPU? > > I hit this assertion with x86 FS and found it was due to some missing > code and submitted a patch: http://reviews.gem5.org/r/1828/ > > The problem was fixed already for ARM. > > The assertion does not necessarily have to do with instructions > executed by your benchmark.. I would guess the freeList empty problem > is related. Commenting out assertions is not usually the right way to > fix things. :) > > You might like to use gem5.debug to gather more information about what > is breaking. > > On Sat, May 4, 2013 at 1:07 PM, ignacio charalabidis > wrote: > > Hello, > > > > I was able to run all my benchmarks for whatever number of instructions and > > intervals I had chosen so far, for each core separately. > > > > Now, I am using more than one cores and the following assertions happen: > > > > Assertion `instcount <= 1500' failed > > > > I read somewhere that I can comment it out. I did and then this assertion is > > raised: > > > > Assertion `!freeList.empty()' failed > > > > Why that happen? If I use less instructions this does not happen, but I want > > to perform the previous ones. > > Any hint on that? > > > > I am running using gem5.opt. > > > > > > > > > > > > ___ > > gem5-users mailing list > > gem5-users@gem5.org > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Assertion `instcount <= 1500' failed and Assertion `!freeList.empty()' when having more than one cpus
Hmm thanks I will check it out. I am using ARM architecture and have defined custom CPUs. There were given to me actually, so there should not be a problem with that, I suppose. I will look at the patch, since my version of gem5 is earlier as I can see and I haven't applied that patch. Thanks, > Date: Sat, 4 May 2013 14:50:47 -0400 > From: ged...@rtems.org > To: gem5-users@gem5.org > Subject: Re: [gem5-users] Assertion `instcount <= 1500' failed and Assertion > `!freeList.empty()' when having more than one cpus > > What CPU? > > I hit this assertion with x86 FS and found it was due to some missing > code and submitted a patch: http://reviews.gem5.org/r/1828/ > > The problem was fixed already for ARM. > > The assertion does not necessarily have to do with instructions > executed by your benchmark.. I would guess the freeList empty problem > is related. Commenting out assertions is not usually the right way to > fix things. :) > > You might like to use gem5.debug to gather more information about what > is breaking. > > On Sat, May 4, 2013 at 1:07 PM, ignacio charalabidis > wrote: > > Hello, > > > > I was able to run all my benchmarks for whatever number of instructions and > > intervals I had chosen so far, for each core separately. > > > > Now, I am using more than one cores and the following assertions happen: > > > > Assertion `instcount <= 1500' failed > > > > I read somewhere that I can comment it out. I did and then this assertion is > > raised: > > > > Assertion `!freeList.empty()' failed > > > > Why that happen? If I use less instructions this does not happen, but I want > > to perform the previous ones. > > Any hint on that? > > > > I am running using gem5.opt. > > > > > > > > > > > > ___ > > gem5-users mailing list > > gem5-users@gem5.org > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Assertion `instcount <= 1500' failed and Assertion `!freeList.empty()' when having more than one cpus
Hello, I was able to run all my benchmarks for whatever number of instructions and intervals I had chosen so far, for each core separately. Now, I am using more than one cores and the following assertions happen: Assertion `instcount <= 1500' failed I read somewhere that I can comment it out. I did and then this assertion is raised: Assertion `!freeList.empty()' failed Why that happen? If I use less instructions this does not happen, but I want to perform the previous ones. Any hint on that? I am running using gem5.opt. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Slave and Master Ports in gem5 vol.2
Thanks for the suggestion Andrea,
sorry about that. I will look at this.
Regards,
Ignatios
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Sun, 28 Apr 2013 21:45:08 +0100
Subject: Re: [gem5-users] Slave and Master Ports in gem5 vol.2
Hi Ignatios,
Once again, I think the topic is pretty far beyond what I would consider "user"
concerns, and I would argue the thread should move to the dev list.
I don't think there are any issues in the C++ code you are referring to. More
likely something goes wrong in your Python configuration or in your
implementation of getMasterPort for the modified object. I would suggest
starting with a very simple Python
script connecting the ports you want (avoid the complex fs/se and CPU config
etc to ensure you actually control every step of what is happening). Once that
is under control, set a breakpoint in your getMasterPort and ensure that is is
actually returning the
port you intend when called with the appropriate string.
Good luck.
Andreas
From: ignacio charalabidis
Reply-To: gem5 users mailing list
Date: Sunday, 28 April 2013 19:42
To: gem5 users mailing list
Subject: Re: [gem5-users] Slave and Master Ports in gem5 vol.2
Well, I think I have found the mistake but I do not know where it comes from.
So, inside the pyobject.cc there is that code in the connectPorts
// generic master/slave port connection
BaseMasterPort& masterPort = mo1->getMasterPort(name1, i1);
BaseSlavePort& slavePort = mo2->getSlavePort(name2, i2);
my_inform("!! WILL CONNECT: %s WITH %s \n",name1,name2);
my_inform("!! MasterPort %s <-> Slaveport %s
\n",masterPort.name(),slavePort.name());
masterPort.bind(slavePort);
the output is this:
debug info: !! WILL CONNECT: second_icache_port WITH second_cpu_side
debug info: !! MasterPort system.cpu.second_icache_port Slaveport
system.secondmainCpu.icache.cpu_side
Despite is says it will connect it with second_cpu_side, it connects_it with
cpu_side.
Any help why that might happen? Where is this function that is being called?
in the port.cc it does not take arguments, so I guess it's not that, and in the
mem_object.cc it does not return anything.
Thanks,
Ignatios
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Sat, 27 Apr 2013 20:28:33 +0100
Subject: Re: [gem5-users] Slave and Master Ports in gem5
That looks alright. Make sure the cpu also has an if-statement for
"second_icache_port" in getMasterPort and that it returns a unique port.
The string name on the right hand side in the Python description has no
importance.
Andreas
From: ignacio charalabidis
Reply-To: gem5 users mailing list
Date: Saturday, 27 April 2013 20:11
To: gem5 users mailing list
Subject: Re: [gem5-users] Slave and Master Ports in gem5
Thanks Andrea,
as far as the 1 is concerned I am doing this:
icache_port = MasterPort("Instruction Port")
dcache_port = MasterPort("Data Port")
second_icache_port = MasterPort("Second Instruction Port")
_cached_ports = ['icache_port', 'dcache_port','second_icache_port']
and then the connections seems correct to me.
Is there anything else? Does the name inside the Master Port plays any role?
Because for example, I haven't used Second Instruction Port anywhere else.
Do I need to create a new class for example, or it is not a problem that
icache_port and second_icache_port use the same?
Thanks,
Ignatios
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Sat, 27 Apr 2013 20:02:10 +0100
Subject: Re: [gem5-users] Slave and Master Ports in gem5
I would think there are three places where things could be going wrong:
1 In the python code where the ports are being connected
2 In the getMaster/SlavePort in the cache where the name from the python code
is mapped to an actual port instance
3 In the port subclass used
Andreas
From: ignacio charalabidis
Reply-To: gem5 users mailing list
Date: Saturday, 27 April 2013 19:50
To: "gem5-users@gem5.org"
Subject: [gem5-users] Slave and Master Ports in gem5
Hello,
in my config.ini file, I am having this:
icache_port=system.cpu.icache.cpu_side
second_icache_port=system.secondmainCpu.icache.second_cpu_side
I have made some modificiations in order to have two ports in my cpus and in my
caches.
But then in my code, for example when I have this:
MasterPort::sendTimingReq(PacketPtr pkt)
{
...
DPRINTF(MyFlag, "return value port name %s\n",_slavePort->name());
...
}
I see this output:
system.mainCpu.icache_port: return value port name system.cpu.icache.cpu_side
which is correct.
But for the second_icache_port i see this:
system.mainCpu.second_icache_port: return value port name
system.secon
Re: [gem5-users] Slave and Master Ports in gem5 vol.2
Well, I think I have found the mistake but I do not know where it comes from.
So, inside the pyobject.cc there is that code in the connectPorts
// generic master/slave port connection
BaseMasterPort& masterPort = mo1->getMasterPort(name1, i1);
BaseSlavePort& slavePort = mo2->getSlavePort(name2, i2);
my_inform("!! WILL CONNECT: %s WITH %s \n",name1,name2);
my_inform("!! MasterPort %s <-> Slaveport %s
\n",masterPort.name(),slavePort.name());
masterPort.bind(slavePort);
the output is this:
debug info: !! WILL CONNECT: second_icache_port WITH second_cpu_side
debug info: !! MasterPort system.cpu.second_icache_port Slaveport
system.secondmainCpu.icache.cpu_side
Despite is says it will connect it with second_cpu_side, it connects_it with
cpu_side.
Any help why that might happen? Where is this function that is being called?
in the port.cc it does not take arguments, so I guess it's not that, and in the
mem_object.cc it does not return anything.
Thanks,
Ignatios
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Sat, 27 Apr 2013 20:28:33 +0100
Subject: Re: [gem5-users] Slave and Master Ports in gem5
That looks alright. Make sure the cpu also has an if-statement for
"second_icache_port" in getMasterPort and that it returns a unique port.
The string name on the right hand side in the Python description has no
importance.
Andreas
From: ignacio charalabidis
Reply-To: gem5 users mailing list
Date: Saturday, 27 April 2013 20:11
To: gem5 users mailing list
Subject: Re: [gem5-users] Slave and Master Ports in gem5
Thanks Andrea,
as far as the 1 is concerned I am doing this:
icache_port = MasterPort("Instruction Port")
dcache_port = MasterPort("Data Port")
second_icache_port = MasterPort("Second Instruction Port")
_cached_ports = ['icache_port', 'dcache_port','second_icache_port']
and then the connections seems correct to me.
Is there anything else? Does the name inside the Master Port plays any role?
Because for example, I haven't used Second Instruction Port anywhere else.
Do I need to create a new class for example, or it is not a problem that
icache_port and second_icache_port use the same?
Thanks,
Ignatios
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Sat, 27 Apr 2013 20:02:10 +0100
Subject: Re: [gem5-users] Slave and Master Ports in gem5
I would think there are three places where things could be going wrong:
1 In the python code where the ports are being connected
2 In the getMaster/SlavePort in the cache where the name from the python code
is mapped to an actual port instance
3 In the port subclass used
Andreas
From: ignacio charalabidis
Reply-To: gem5 users mailing list
Date: Saturday, 27 April 2013 19:50
To: "gem5-users@gem5.org"
Subject: [gem5-users] Slave and Master Ports in gem5
Hello,
in my config.ini file, I am having this:
icache_port=system.cpu.icache.cpu_side
second_icache_port=system.secondmainCpu.icache.second_cpu_side
I have made some modificiations in order to have two ports in my cpus and in my
caches.
But then in my code, for example when I have this:
MasterPort::sendTimingReq(PacketPtr pkt)
{
...
DPRINTF(MyFlag, "return value port name %s\n",_slavePort->name());
...
}
I see this output:
system.mainCpu.icache_port: return value port name system.cpu.icache.cpu_side
which is correct.
But for the second_icache_port i see this:
system.mainCpu.second_icache_port: return value port name
system.secondmainCpu.icache.cpu_side
I think at somewhere, I should define what the slave port is going to be, but
I do not know where to do that. I have checked for my secondCPU as well and the
same things happen. Although it appears correctly in the config.ini file, it
does not return what
it supposes to return. Instead it returns the same slave port as the
icache_port.
Any help?
Edit:
For example, in the BaseCPU::takeOverFrom, in the base.cc file,If I call these:
BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
BaseSlavePort &second_inst_peer_port =
oldCPU->getSecondInstPort().getSlavePort();
they will return the same although:
oldCPU->getInstPort() is icache_port
oldCPU->getSecondInstPort() is second_icache_port
They will both return
system.cpu.icache.cpu_side as their slave port.
regards,
Ignatios
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Re: [gem5-users] Slave and Master Ports in gem5 - a correction
ok, in Python side I have only added this:
icache_port = MasterPort("Instruction Port")
dcache_port = MasterPort("Data Port")
second_icache_port = MasterPort("Second Instruction Port")
_cached_ports = ['icache_port', 'dcache_port','second_icache_port']
and in the addprivateL1caches inside the BaseCPU.py I use this:
def addPrivateSplitL1Caches(self, ic, dc, second_ic=None, wc = None, dwc =
None):
#print "%s-%s-%s-%s" %(ic,dc,second_ic,second_dc)
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self.second_icache_port = second_ic.second_cpu_side
That's the only changes, I made in the python codes. So, I guess I am using the
default methods for connecting the CPU to the L1.
What is weird to me is that in the config.ini connections appear to be correct:
f.e dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
second_icache_port=system.secondmainCpu.icache.second_cpu_side
The problem happens after a switchCpus is called, because in the takeOver>From
function these:
BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
BaseSlavePort &second_inst_peer_port =
oldCPU->getSecondInstPort().getSlavePort();
return the same.
So I guess it is something wrong from the beginning (python side maybe since I
haven't made many changes in that side).
But I do not understand why, since :
1. I have defined second_icache_port to be MasterPort.
2. I have defined system.secondmainCpu.icache.second_cpu_side to be SlavePort.
3. I have connected them through python as I showed earlier.
and
I expect the getSecondInstPort().getSlavePort(); to be
system.secondmainCpu.icache.second_cpu_side and not system.Cpu.icache.cpu_side
Where else in Python should I look into?
Thanks for your time,
Ignatios
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Sat, 27 Apr 2013 21:05:58 +0100
Subject: Re: [gem5-users] Slave and Master Ports in gem5 - a correction
Well, the starting point here should be to ensure that the Python code is doing
the right thing. How is the cached_ports of the BaseCPU used in your code? If
you tell the CPU to connect L1s through the "normal" methods then the original
cached_ports will
not even be used.
If the C++ bit is right (which seems to be the case), then I would suggest to
ensure the python code is doing what you want it to do. What are you connected
it to and how?
Andreas
From: ignacio charalabidis
Reply-To: gem5 users mailing list
Date: Saturday, 27 April 2013 20:52
To: "gem5-users@gem5.org"
Subject: [gem5-users] Slave and Master Ports in gem5 - a correction
Actually a correction,
code in BaseCPU::getMasterPort(const string &if_name, PortID idx) is called
with the correct output. The problem happens with the slaveports defined for
these MasterPorts.
I want my icache_port and my second_icache_port to have different slave ports.
From: ign...@hotmail.com
To: gem5-users@gem5.org
Subject: RE: [gem5-users] Slave and Master Ports in gem5
Date: Sat, 27 Apr 2013 22:40:50 +0300
You mean inside the base.cc.
In there I have this:
BaseMasterPort &
BaseCPU::getMasterPort(const string &if_name, PortID idx)
{
DPRINTF(MyFlag, "BaseCPU::getMasterPort : %s\n",if_name);
// Get the right port based on name. This applies to all the
// subclasses of the base CPU and relies on their implementation
// of getDataPort and getInstPort. In all cases there methods
// return a CpuPort pointer.
/*changes in code made by IGN - 18 Apr*/
if (if_name == "dcache_port") {
DPRINTF(MyFlag, "IGN: getDataPort is returned");
return getDataPort();
}
else if (if_name == "icache_port")
return getInstPort();
else if (if_name == "second_icache_port")
return getsecondInstPort();
else
return MemObject::getMasterPort(if_name, idx);
}
Actually this code is never called, because I do not see my debug message being
printed out.
or in the port.cc where the problem occurs:
MasterPort::sendTimingReq(PacketPtr pkt)
{
DPRINTF(MyFlag, "return value port name %s\n",_slavePort->name());
assert(pkt->isRequest());
return _slavePort->recvTimingReq(pkt);
}
_slavePort is always the same, no matter if my first or second data port is the
MasterPort.
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Sat, 27 Apr 2013 20:28:33 +0100
Subject: Re: [gem5-users] Slave and Master Ports in gem5
That looks alright. Make sure the cpu also has an if-statement for
"second_icache_port" in getMasterPort and that it returns a unique port.
The string name on the right hand si
[gem5-users] Slave and Master Ports in gem5 - a correction
Actually a correction,
code in BaseCPU::getMasterPort(const string &if_name, PortID idx) is called
with the correct output. The problem happens with the slaveports defined for
these MasterPorts.
I want my icache_port and my second_icache_port to have different slave ports.
From: ign...@hotmail.com
To: gem5-users@gem5.org
Subject: RE: [gem5-users] Slave and Master Ports in gem5
Date: Sat, 27 Apr 2013 22:40:50 +0300
You mean inside the base.cc.
In there I have this:
BaseMasterPort &
BaseCPU::getMasterPort(const string &if_name, PortID idx)
{
DPRINTF(MyFlag, "BaseCPU::getMasterPort : %s\n",if_name);
// Get the right port based on name. This applies to all the
// subclasses of the base CPU and relies on their implementation
// of getDataPort and getInstPort. In all cases there methods
// return a CpuPort pointer.
/*changes in code made by IGN - 18 Apr*/
if (if_name == "dcache_port") {
DPRINTF(MyFlag, "IGN: getDataPort is returned");
return getDataPort();
}
else if (if_name == "icache_port")
return getInstPort();
else if (if_name == "second_icache_port")
return getsecondInstPort();
else
return MemObject::getMasterPort(if_name, idx);
}
Actually this code is never called, because I do not see my debug message being
printed out.
or in the port.cc where the problem occurs:
MasterPort::sendTimingReq(PacketPtr pkt)
{
DPRINTF(MyFlag, "return value port name %s\n",_slavePort->name());
assert(pkt->isRequest());
return _slavePort->recvTimingReq(pkt);
}
_slavePort is always the same, no matter if my first or second data port is the
MasterPort.
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Sat, 27 Apr 2013 20:28:33 +0100
Subject: Re: [gem5-users] Slave and Master Ports in gem5
That looks alright. Make sure the cpu also has an if-statement for
"second_icache_port" in getMasterPort and that it returns a unique port.
The string name on the right hand side in the Python description has no
importance.
Andreas
From: ignacio charalabidis
Reply-To: gem5 users mailing list
Date: Saturday, 27 April 2013 20:11
To: gem5 users mailing list
Subject: Re: [gem5-users] Slave and Master Ports in gem5
Thanks Andrea,
as far as the 1 is concerned I am doing this:
icache_port = MasterPort("Instruction Port")
dcache_port = MasterPort("Data Port")
second_icache_port = MasterPort("Second Instruction Port")
_cached_ports = ['icache_port', 'dcache_port','second_icache_port']
and then the connections seems correct to me.
Is there anything else? Does the name inside the Master Port plays any role?
Because for example, I haven't used Second Instruction Port anywhere else.
Do I need to create a new class for example, or it is not a problem that
icache_port and second_icache_port use the same?
Thanks,
Ignatios
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Sat, 27 Apr 2013 20:02:10 +0100
Subject: Re: [gem5-users] Slave and Master Ports in gem5
I would think there are three places where things could be going wrong:
1 In the python code where the ports are being connected
2 In the getMaster/SlavePort in the cache where the name from the python code
is mapped to an actual port instance
3 In the port subclass used
Andreas
From: ignacio charalabidis
Reply-To: gem5 users mailing list
Date: Saturday, 27 April 2013 19:50
To: "gem5-users@gem5.org"
Subject: [gem5-users] Slave and Master Ports in gem5
Hello,
in my config.ini file, I am having this:
icache_port=system.cpu.icache.cpu_side
second_icache_port=system.secondmainCpu.icache.second_cpu_side
I have made some modificiations in order to have two ports in my cpus and in my
caches.
But then in my code, for example when I have this:
MasterPort::sendTimingReq(PacketPtr pkt)
{
...
DPRINTF(MyFlag, "return value port name %s\n",_slavePort->name());
...
}
I see this output:
system.mainCpu.icache_port: return value port name system.cpu.icache.cpu_side
which is correct.
But for the second_icache_port i see this:
system.mainCpu.second_icache_port: return value port name
system.secondmainCpu.icache.cpu_side
I think at somewhere, I should define what the slave port is going to be, but
I do not know where to do that. I have checked for my secondCPU as well and the
same things happen. Although it appears correctly in the config.ini file, it
does not return what
it supposes to return. Instead it returns the same slave port as the
icache_port.
Any help?
Edit:
For example, in the BaseCPU::takeOverFrom, in the base.cc file,If I call these:
BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
BaseSlaveP
Re: [gem5-users] Slave and Master Ports in gem5
You mean inside the base.cc.
In there I have this:
BaseMasterPort &
BaseCPU::getMasterPort(const string &if_name, PortID idx)
{
DPRINTF(MyFlag, "BaseCPU::getMasterPort : %s\n",if_name);
// Get the right port based on name. This applies to all the
// subclasses of the base CPU and relies on their implementation
// of getDataPort and getInstPort. In all cases there methods
// return a CpuPort pointer.
/*changes in code made by IGN - 18 Apr*/
if (if_name == "dcache_port") {
DPRINTF(MyFlag, "IGN: getDataPort is returned");
return getDataPort();
}
else if (if_name == "icache_port")
return getInstPort();
else if (if_name == "second_icache_port")
return getsecondInstPort();
else
return MemObject::getMasterPort(if_name, idx);
}
Actually this code is never called, because I do not see my debug message being
printed out.
or in the port.cc where the problem occurs:
MasterPort::sendTimingReq(PacketPtr pkt)
{
DPRINTF(MyFlag, "return value port name %s\n",_slavePort->name());
assert(pkt->isRequest());
return _slavePort->recvTimingReq(pkt);
}
_slavePort is always the same, no matter if my first or second data port is the
MasterPort.
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Sat, 27 Apr 2013 20:28:33 +0100
Subject: Re: [gem5-users] Slave and Master Ports in gem5
That looks alright. Make sure the cpu also has an if-statement for
"second_icache_port" in getMasterPort and that it returns a unique port.
The string name on the right hand side in the Python description has no
importance.
Andreas
From: ignacio charalabidis
Reply-To: gem5 users mailing list
Date: Saturday, 27 April 2013 20:11
To: gem5 users mailing list
Subject: Re: [gem5-users] Slave and Master Ports in gem5
Thanks Andrea,
as far as the 1 is concerned I am doing this:
icache_port = MasterPort("Instruction Port")
dcache_port = MasterPort("Data Port")
second_icache_port = MasterPort("Second Instruction Port")
_cached_ports = ['icache_port', 'dcache_port','second_icache_port']
and then the connections seems correct to me.
Is there anything else? Does the name inside the Master Port plays any role?
Because for example, I haven't used Second Instruction Port anywhere else.
Do I need to create a new class for example, or it is not a problem that
icache_port and second_icache_port use the same?
Thanks,
Ignatios
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Sat, 27 Apr 2013 20:02:10 +0100
Subject: Re: [gem5-users] Slave and Master Ports in gem5
I would think there are three places where things could be going wrong:
1 In the python code where the ports are being connected
2 In the getMaster/SlavePort in the cache where the name from the python code
is mapped to an actual port instance
3 In the port subclass used
Andreas
From: ignacio charalabidis
Reply-To: gem5 users mailing list
Date: Saturday, 27 April 2013 19:50
To: "gem5-users@gem5.org"
Subject: [gem5-users] Slave and Master Ports in gem5
Hello,
in my config.ini file, I am having this:
icache_port=system.cpu.icache.cpu_side
second_icache_port=system.secondmainCpu.icache.second_cpu_side
I have made some modificiations in order to have two ports in my cpus and in my
caches.
But then in my code, for example when I have this:
MasterPort::sendTimingReq(PacketPtr pkt)
{
...
DPRINTF(MyFlag, "return value port name %s\n",_slavePort->name());
...
}
I see this output:
system.mainCpu.icache_port: return value port name system.cpu.icache.cpu_side
which is correct.
But for the second_icache_port i see this:
system.mainCpu.second_icache_port: return value port name
system.secondmainCpu.icache.cpu_side
I think at somewhere, I should define what the slave port is going to be, but
I do not know where to do that. I have checked for my secondCPU as well and the
same things happen. Although it appears correctly in the config.ini file, it
does not return what
it supposes to return. Instead it returns the same slave port as the
icache_port.
Any help?
Edit:
For example, in the BaseCPU::takeOverFrom, in the base.cc file,If I call these:
BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
BaseSlavePort &second_inst_peer_port =
oldCPU->getSecondInstPort().getSlavePort();
they will return the same although:
oldCPU->getInstPort() is icache_port
oldCPU->getSecondInstPort() is second_icache_port
They will both return
system.cpu.icache.cpu_side as their slave port.
regards,
Ignatios
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you a
Re: [gem5-users] Slave and Master Ports in gem5
Thanks Andrea,
as far as the 1 is concerned I am doing this:
icache_port = MasterPort("Instruction Port")
dcache_port = MasterPort("Data Port")
second_icache_port = MasterPort("Second Instruction Port")
_cached_ports = ['icache_port', 'dcache_port','second_icache_port']
and then the connections seems correct to me.
Is there anything else? Does the name inside the Master Port plays any role?
Because for example, I haven't used Second Instruction Port anywhere else.
Do I need to create a new class for example, or it is not a problem that
icache_port and second_icache_port use the same?
Thanks,
Ignatios
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Sat, 27 Apr 2013 20:02:10 +0100
Subject: Re: [gem5-users] Slave and Master Ports in gem5
I would think there are three places where things could be going wrong:
1 In the python code where the ports are being connected
2 In the getMaster/SlavePort in the cache where the name from the python code
is mapped to an actual port instance
3 In the port subclass used
Andreas
From: ignacio charalabidis
Reply-To: gem5 users mailing list
Date: Saturday, 27 April 2013 19:50
To: "gem5-users@gem5.org"
Subject: [gem5-users] Slave and Master Ports in gem5
Hello,
in my config.ini file, I am having this:
icache_port=system.cpu.icache.cpu_side
second_icache_port=system.secondmainCpu.icache.second_cpu_side
I have made some modificiations in order to have two ports in my cpus and in my
caches.
But then in my code, for example when I have this:
MasterPort::sendTimingReq(PacketPtr pkt)
{
...
DPRINTF(MyFlag, "return value port name %s\n",_slavePort->name());
...
}
I see this output:
system.mainCpu.icache_port: return value port name system.cpu.icache.cpu_side
which is correct.
But for the second_icache_port i see this:
system.mainCpu.second_icache_port: return value port name
system.secondmainCpu.icache.cpu_side
I think at somewhere, I should define what the slave port is going to be, but
I do not know where to do that. I have checked for my secondCPU as well and the
same things happen. Although it appears correctly in the config.ini file, it
does not return what
it supposes to return. Instead it returns the same slave port as the
icache_port.
Any help?
Edit:
For example, in the BaseCPU::takeOverFrom, in the base.cc file,If I call these:
BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
BaseSlavePort &second_inst_peer_port =
oldCPU->getSecondInstPort().getSlavePort();
they will return the same although:
oldCPU->getInstPort() is icache_port
oldCPU->getSecondInstPort() is second_icache_port
They will both return
system.cpu.icache.cpu_side as their slave port.
regards,
Ignatios
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient,
please notify the sender immediately and do not disclose the contents
to any other person, use it for any purpose, or store or copy the information
in any medium. Thank you.
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Slave and Master Ports in gem5
Hello,
in my config.ini file, I am having this:
icache_port=system.cpu.icache.cpu_side
second_icache_port=system.secondmainCpu.icache.second_cpu_side
I have made some modificiations in order to have two ports in my cpus and in my
caches.
But then in my code, for example when I have this:
MasterPort::sendTimingReq(PacketPtr pkt)
{
...
DPRINTF(MyFlag, "return value port name %s\n",_slavePort->name());
...
}
I see this output:
system.mainCpu.icache_port: return value port name system.cpu.icache.cpu_side
which is correct.
But for the second_icache_port i see this:
system.mainCpu.second_icache_port: return value port name
system.secondmainCpu.icache.cpu_side
I think at somewhere, I should define what the slave port is going to be, but
I do not know where to do that. I have checked for my secondCPU as well and the
same things happen. Although it appears correctly in the config.ini file, it
does not return what it supposes to return. Instead it returns the same slave
port as the icache_port.
Any help?
Edit:
For example, in the BaseCPU::takeOverFrom, in the base.cc file,If I call these:
BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
BaseSlavePort &second_inst_peer_port =
oldCPU->getSecondInstPort().getSlavePort();
they will return the same although:
oldCPU->getInstPort() is icache_port
oldCPU->getSecondInstPort() is second_icache_port
They will both return
system.cpu.icache.cpu_side as their slave port.
regards,
Ignatios
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] fatal error cpu does not have any master port
Thanks Andrea for your reply. Ok I will try to figure it out or think a different way and not spam the list again for that topic. Basically I would be happy if you can advice me on that: I am having 2 cpus with private L1 caches. What I am doing so far in my simulation is changing the workload from one cpu to another, without unbinding/binding the caches that was happening earlier in the switchCpus function. So every interval, my workload run in a a different cpu. The way I understand it so far, is that when the cpu is switched_out then the caches are kept coherent, but not warm. Now, I want to extend that and to be able to keep my cache warm. And I thought one way of doing so was to have two ports, instead of one (so each cpu is connected with the two caches) and duplicate every request to the "cache of the idle cpu". So let me give you an example: Lets assume I am having 32kb caches. My workload is working on an array of 32kB, so it fits in the cache. Then I switch from core B to core A. Now cache A also gets filled up with the data. However, say the workload moves on to a second array of 32kB. Slowly cache A fills up with the second array, but cache B still holds the first array and nothing from the second. I think this is what happening now and this is what I mean "kept cold". What I want is to keep cacheB warm --with the data of the second array in my example, even if its cpu was idle. Regards, Ignatios From: andreas.hans...@arm.com To: gem5-users@gem5.org Date: Sun, 21 Apr 2013 16:42:42 +0100 Subject: Re: [gem5-users] fatal error cpu does not have any master port Hi Ignatios, I think this topic is far beyond the "user" list and even quite a deep dive for the "dev" list. The short answer is: You cannot simply use another instance of the same subclass of the port as it is tied to the LSQ and fetch unit and the port calls them, and they call the port. Thus, when you add a new port it is just dangling on the side in the C++ world. The longer answer: Figure out what it is you really want to do, e.g. spread the load between two cache ports? Is this really the easiest way of doing it. If the purpose is to have multiple ports, why not make it a vector port to start with? In any of these cases, you will need to do a significant amount of changes to the O3 CPU, the LSQ, the fetch unit, the caches etc. I'm happy to look at a patch, but ultimately you'll have to familiarise yourself with all the aforementioned bits and pieces. Andreas From: ignacio charalabidis Reply-To: gem5 users mailing list Date: Sunday, 21 April 2013 14:41 To: "gem5-users@gem5.org" Subject: Re: [gem5-users] fatal error cpu does not have any master port Thanks Andrea, > You have to create a new port, not just hand over the same one Ok I created a new port also in the .cc file that I needed. Now the system is set up correctly as i can see in the config file. Now for my second_icache_port for example I am receiving some panic messages during warm-up like this one: panic: system.cpu.second_icache_port was not expecting a timing snoop request @ cycle 159000 while using the --debug-flag=Cache,CachePort,CacheRepl I get these: 151000: system.cpu.icache: set 5b: moving blk 496c0 to MRU 151000: system.cpu.icache: ReadReq (ifetch) 496d4 hit 151000: system.cpu.icache: set 5b: moving blk 496c0 to MRU 151000: system.cpu.icache: ReadReq (ifetch) 496c0 hit 158000: system.cpu.icache: ReadReq (ifetch) 49700 miss 158000: system.cpu.icache.mem_side: Asserting bus request for cause 0 >you also have to make use of the two ports and somehow distribute the >outgoing requests Can you give me a hint on where to look at because I am lost. For example, -where are these requests for example. I am not sure why for example it is the second_icache_port that was not expecting the timing snoop request and not the icache_port (because it works if I do not add the second_icache_port) since they are of the same type (ICachePort). Thanks, Ignatios From: andreas.hans...@arm.com To: gem5-users@gem5.org Date: Thu, 18 Apr 2013 14:48:38 +0100 Subject: Re: [gem5-users] fatal error cpu does not have any master port You have to create a new port, not just hand over the same one. This change is rather complex in fact. Once the extra port is there you also have to make use of the two ports and somehow distribute the outgoing requests and keep the view between the two coherent. Andreas -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___
Re: [gem5-users] fatal error cpu does not have any master port
Thanks Andrea, > You have to create a new port, not just hand over the same one Ok I created a new port also in the .cc file that I needed. Now the system is set up correctly as i can see in the config file. Now for my second_icache_port for example I am receiving some panic messages during warm-up like this one: panic: system.cpu.second_icache_port was not expecting a timing snoop request @ cycle 159000 while using the --debug-flag=Cache,CachePort,CacheRepl I get these: 151000: system.cpu.icache: set 5b: moving blk 496c0 to MRU 151000: system.cpu.icache: ReadReq (ifetch) 496d4 hit 151000: system.cpu.icache: set 5b: moving blk 496c0 to MRU 151000: system.cpu.icache: ReadReq (ifetch) 496c0 hit 158000: system.cpu.icache: ReadReq (ifetch) 49700 miss 158000: system.cpu.icache.mem_side: Asserting bus request for cause 0 >you also have to make use of the two ports and somehow distribute the >outgoing requests Can you give me a hint on where to look at because I am lost. For example, -where are these requests for example. I am not sure why for example it is the second_icache_port that was not expecting the timing snoop request and not the icache_port (because it works if I do not add the second_icache_port) since they are of the same type (ICachePort). Thanks, Ignatios From: andreas.hans...@arm.com To: gem5-users@gem5.org Date: Thu, 18 Apr 2013 14:48:38 +0100 Subject: Re: [gem5-users] fatal error cpu does not have any master port You have to create a new port, not just hand over the same one. This change is rather complex in fact. Once the extra port is there you also have to make use of the two ports and somehow distribute the outgoing requests and keep the view between the two coherent. Andreas ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] cpu port is in my configs.ini twice - SOLVED
Sorry for sending again, but I was able to solve it. Just in case anyone has the same issue. Removing the: self.second_icache = second_ic self.second_dcache = second_dc fixed it as it was needed. So now I have : def addPrivateSplitL1Caches(self, ic, dc, second_ic=None, second_dc=None,iwc = None, dwc = None): self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self.second_icache_port = second_ic.second_cpu_side self.second_dcache_port = second_dc.second_cpu_side #end of code self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: if iwc and dwc: self.itb_walker_cache = iwc self.dtb_walker_cache = dwc self.itb.walker.port = iwc.cpu_side self.dtb.walker.port = dwc.cpu_side self._cached_ports += ["itb_walker_cache.mem_side", \ "dtb_walker_cache.mem_side"] else: self._cached_ports += ["itb.walker.port", "dtb.walker.port"] # Checker doesn't need its own tlb caches because it does # functional accesses only if self.checker != NULL: self._cached_ports += ["checker.itb.walker.port", \ "checker.dtb.walker.port"] and it is working properly! From: ign...@hotmail.com To: gem5-users@gem5.org Date: Sat, 20 Apr 2013 18:49:27 +0300 Subject: [gem5-users] cpu port is in my configs.ini twice Hello, I have in my system 2 cpus with separate L1 D and I caches. Each of these caches has two ports (cpu_side and second_cpu_side) because I want to connect with both of the cpus. So I am having these: Cpu has: dcache_port, second_dcache_port, icache_port, second_icache_port and cache has: cpu_side, second_cpu_side and mem_side. I have made the appropriate changes in the .py and .hh,.cc files. So I am calling this: system.cpu.addPrivateSplitL1Caches(icache, dcache, newicache, newdcache) and then this: system.secondcpu.addPrivateSplitL1Caches(newicache, newdcache, icache, dcache) and my addPrivateSplitL1Caches def is this: def addPrivateSplitL1Caches(self, ic, dc, second_ic=None, second_dc=None,iwc = None, dwc = None): self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side #code added by IGN - 17 Apr self.second_icache = second_ic self.second_dcache = second_dc self.second_icache_port = second_ic.second_cpu_side self.second_dcache_port = second_dc.second_cpu_side #end of code self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: if iwc and dwc: self.itb_walker_cache = iwc self.dtb_walker_cache = dwc self.itb.walker.port = iwc.cpu_side self.dtb.walker.port = dwc.cpu_side self._cached_ports += ["itb_walker_cache.mem_side", \ "dtb_walker_cache.mem_side"] else: self._cached_ports += ["itb.walker.port", "dtb.walker.port"] # Checker doesn't need its own tlb caches because it does # functional accesses only if self.checker != NULL: self._cached_ports += ["checker.itb.walker.port", \ "checker.dtb.walker.port"] But the problem is that in my config I see: [system.secondcpu.second_dcache], [system.secondcpu.second_icache] , [system.secondcpu.dcache] or [system.secondcpu.icache] twice and i do not see at all: [system.cpu.second_dcache] or [system.cpu.second_dcache] or [system.cpu.dcache] or [system.cpu.dcache] Any idea on why that might happen? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] cpu port is in my configs.ini twice
Hello, I have in my system 2 cpus with separate L1 D and I caches. Each of these caches has two ports (cpu_side and second_cpu_side) because I want to connect with both of the cpus. So I am having these: Cpu has: dcache_port, second_dcache_port, icache_port, second_icache_port and cache has: cpu_side, second_cpu_side and mem_side. I have made the appropriate changes in the .py and .hh,.cc files. So I am calling this: system.cpu.addPrivateSplitL1Caches(icache, dcache, newicache, newdcache) and then this: system.secondcpu.addPrivateSplitL1Caches(newicache, newdcache, icache, dcache) and my addPrivateSplitL1Caches def is this: def addPrivateSplitL1Caches(self, ic, dc, second_ic=None, second_dc=None,iwc = None, dwc = None): self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side #code added by IGN - 17 Apr self.second_icache = second_ic self.second_dcache = second_dc self.second_icache_port = second_ic.second_cpu_side self.second_dcache_port = second_dc.second_cpu_side #end of code self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: if iwc and dwc: self.itb_walker_cache = iwc self.dtb_walker_cache = dwc self.itb.walker.port = iwc.cpu_side self.dtb.walker.port = dwc.cpu_side self._cached_ports += ["itb_walker_cache.mem_side", \ "dtb_walker_cache.mem_side"] else: self._cached_ports += ["itb.walker.port", "dtb.walker.port"] # Checker doesn't need its own tlb caches because it does # functional accesses only if self.checker != NULL: self._cached_ports += ["checker.itb.walker.port", \ "checker.dtb.walker.port"] But the problem is that in my config I see: [system.secondcpu.second_dcache], [system.secondcpu.second_icache] , [system.secondcpu.dcache] or [system.secondcpu.icache] twice and i do not see at all: [system.cpu.second_dcache] or [system.cpu.second_dcache] or [system.cpu.dcache] or [system.cpu.dcache] Any idea on why that might happen? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] fatal error cpu does not have any master port
Thanks again Andrea for your reply. Can you give me some guidance on that? I do
not find any material that I should look into :/
Besides the implementation,I have a more important question at the end of the
mail.
For example, to begin with the creation of the new port:
in cpu.hh file I see this definition:
virtual CpuPort &getDataPort() { return dcachePort; }
So the way I have it right now, will always return dcachePort and I have to
change it in something like this:
virtual CpuPort &getSecondDataPort() { return second_dcachePort; } ?
and add in the cpu.hh this:
DcachePort second_dcacheport;
and in the cpu.cc
dcachePort(&iew.ldstQueue, this),
inside the FullO3CPU::FullO3CPU(DerivO3CPUParams *params)
Is it more what I need to do for creation of the port ?
And more important, if you can answer on that, because if the answer is
negative then the above do not have a special meaning. I want to have 2 caches
for the following reason. I want to keep both of the caches attached to a core,
in order to keep them both of them warm all the time. Actually, imagine like a
2x2 grid where I am having 2 cpus with its own private cache. But I want when
cpuA is running, and cpuB is switched_out, to keep the cache of cpuB warm. So I
thought that I could send the request also in that cpu, and in order to do so I
need to define another one port in my cpu and in my cache. Does it make sense?
Is the approach correct?
Hope you can answer on that,
Regards,
Ignatios
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Thu, 18 Apr 2013 14:48:38 +0100
Subject: Re: [gem5-users] fatal error cpu does not have any master port
You have to create a new port, not just hand over the same one. This change is
rather complex in fact. Once the extra port is there you also have to make use
of the two ports and somehow distribute the outgoing requests and keep the view
between the two
coherent.
Andreas
From: ignacio charalabidis
Reply-To: gem5 users mailing list
Date: Thursday, 18 April 2013 14:44
To: "gem5-users@gem5.org"
Subject: Re: [gem5-users] fatal error cpu does not have any master port
Thank Andrea,
So I changed in the base.cc into this:
if ((if_name == "dcache_port") || (if_name == "second_dcache_port"))
return getDataPort();
else if ((if_name == "icache_port") || (if_name == "dcache_port"))
return getInstrPort();
and also added the same for the cache.
Is that all?
And one more question? Should I change my getDataPort to return masterPort or
can I leave it to return cpuPort? Will it make any difference?
Because now my program gets aborted at cycle0 so I have missed something.
Thanks,
Ignatios
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Thu, 18 Apr 2013 11:19:26 +0100
Subject: Re: [gem5-users] fatal error cpu does not have any master port
You need to also get the C++ code to recognise it and return the right port ref.
You have updated the Python code, but there is still no port to match it in the
C++ object.
Andreas
From: ignacio charalabidis
Reply-To: gem5 users mailing list
Date: Thursday, 18 April 2013 04:25
To: "gem5-users@gem5.org"
Subject: [gem5-users] fatal error cpu does not have any master port
I am getting this error:
fatal: system.secondmainCpu does not have any master port named
second_dcache_port
@ cycle 0
[getMasterPort:build/ARM/mem/mem_object.cc, line 54]
However, in my config file I do see the port:
[system.secondmainCpu]
children=dcache dtb fuPool icache interrupts isa itb second_dcache
second_icache tracer
...
dcache_port=system.secondmainCpu.dcache.cpu_side
icache_port=system.secondmainCpu.icache.cpu_side
second_dcache_port=system.secondmainCpu.second_dcache.second_cpu_side
second_icache_port=system.secondmainCpu.second_icache.second_cpu_side
and the way I declare it in my code is this:
in my BaseCache.py
cpu_side = SlavePort("Port on side closer to CPU")
mem_side = MasterPort("Port on side closer to MEM")
second_mem_side = MasterPort("Second Port on side closer to MEM")
second_cpu_side = SlavePort("Port on side closer to second CPU")
and in my BaseCpu.py
def addPrivateSplitL1Caches(self, ic, dc, second_ic, second_dc,iwc = None, dwc
= None):
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self.second_icache = second_ic
self.second_dcache = second_dc
self.second_icache_port = second_ic.second_cpu_side
self.second_dcache_port = second_dc.second_cpu_side
self._cached_ports = ['icache.mem_side',
'dcache.mem_side','second_icache.second_mem_side','second_dcache.second_mem_side']
Why that happens? I just copied the code for
Re: [gem5-users] fatal error cpu does not have any master port
Thank Andrea,
So I changed in the base.cc into this:
if ((if_name == "dcache_port") || (if_name == "second_dcache_port"))
return getDataPort();
else if ((if_name == "icache_port") || (if_name == "dcache_port"))
return getInstrPort();
and also added the same for the cache.
Is that all?
And one more question? Should I change my getDataPort to return masterPort or
can I leave it to return cpuPort? Will it make any difference?
Because now my program gets aborted at cycle0 so I have missed something.
Thanks,
Ignatios
From: andreas.hans...@arm.com
To: gem5-users@gem5.org
Date: Thu, 18 Apr 2013 11:19:26 +0100
Subject: Re: [gem5-users] fatal error cpu does not have any master port
You need to also get the C++ code to recognise it and return the right port ref.
You have updated the Python code, but there is still no port to match it in the
C++ object.
Andreas
From: ignacio charalabidis
Reply-To: gem5 users mailing list
Date: Thursday, 18 April 2013 04:25
To: "gem5-users@gem5.org"
Subject: [gem5-users] fatal error cpu does not have any master port
I am getting this error:
fatal: system.secondmainCpu does not have any master port named
second_dcache_port
@ cycle 0
[getMasterPort:build/ARM/mem/mem_object.cc, line 54]
However, in my config file I do see the port:
[system.secondmainCpu]
children=dcache dtb fuPool icache interrupts isa itb second_dcache
second_icache tracer
...
dcache_port=system.secondmainCpu.dcache.cpu_side
icache_port=system.secondmainCpu.icache.cpu_side
second_dcache_port=system.secondmainCpu.second_dcache.second_cpu_side
second_icache_port=system.secondmainCpu.second_icache.second_cpu_side
and the way I declare it in my code is this:
in my BaseCache.py
cpu_side = SlavePort("Port on side closer to CPU")
mem_side = MasterPort("Port on side closer to MEM")
second_mem_side = MasterPort("Second Port on side closer to MEM")
second_cpu_side = SlavePort("Port on side closer to second CPU")
and in my BaseCpu.py
def addPrivateSplitL1Caches(self, ic, dc, second_ic, second_dc,iwc = None, dwc
= None):
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self.second_icache = second_ic
self.second_dcache = second_dc
self.second_icache_port = second_ic.second_cpu_side
self.second_dcache_port = second_dc.second_cpu_side
self._cached_ports = ['icache.mem_side',
'dcache.mem_side','second_icache.second_mem_side','second_dcache.second_mem_side']
Why that happens? I just copied the code for the first port in order to create
a new one.
Thanks,
Ignatios
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[gem5-users] fatal error cpu does not have any master port
I am getting this error:
fatal: system.secondmainCpu does not have any master port named
second_dcache_port
@ cycle 0
[getMasterPort:build/ARM/mem/mem_object.cc, line 54]
However, in my config file I do see the port:
[system.secondmainCpu]
children=dcache dtb fuPool icache interrupts isa itb second_dcache
second_icache tracer
...
dcache_port=system.secondmainCpu.dcache.cpu_side
icache_port=system.secondmainCpu.icache.cpu_side
second_dcache_port=system.secondmainCpu.second_dcache.second_cpu_side
second_icache_port=system.secondmainCpu.second_icache.second_cpu_side
and the way I declare it in my code is this:
in my BaseCache.py
cpu_side = SlavePort("Port on side closer to CPU")
mem_side = MasterPort("Port on side closer to MEM")
second_mem_side = MasterPort("Second Port on side closer to MEM")
second_cpu_side = SlavePort("Port on side closer to second CPU")
and in my BaseCpu.py
def addPrivateSplitL1Caches(self, ic, dc, second_ic, second_dc,iwc = None, dwc
= None):
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self.second_icache = second_ic
self.second_dcache = second_dc
self.second_icache_port = second_ic.second_cpu_side
self.second_dcache_port = second_dc.second_cpu_side
self._cached_ports = ['icache.mem_side',
'dcache.mem_side','second_icache.second_mem_side','second_dcache.second_mem_side']
Why that happens? I just copied the code for the first port in order to create
a new one.
Thanks,
Ignatios
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[gem5-users] add ports in a CPU
Hello,
I would like to add more ports in my CPU in order to connect it with more than
one caches.
So in the /src/cpu/BaseCpu.py I changed these lines:
icache_port = MasterPort("Instruction Port")
dcache_port = MasterPort("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
to
icache_port = MasterPort("Instruction Port")
dcache_port = MasterPort("Data Port")
second_icache_port = MasterPort("Instruction Port")
second_dcache_port = MasterPort("Data Port")
_cached_ports = ['icache_port',
'dcache_port','second_icache_port','second_dcache_port']
Now I will do the same in the BaseCache.py file where the cpu_sides are defined.
Am I right so far?
Do I need to duplicate the mem_side port as well?
And finally, in the function AddPrivateL1Caches where the connection takes
place is it enough to simply add these lines:
self.second_icache_port = ic.second_cpu_side
self.second_dcache_port = dc.second_cpu_side
Is there anything that I am missing?
Thanks,
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[gem5-users] send read request to more than one cpus
Hello, I am having the following infrastructure: system.l2 = l2cache system.tol2bus = CoherentBus() system.l2.cpu_side = system.tol2bus.master system.l2.mem_side = system.membus.slave system.cpu.addPrivateSplitL1Caches(icache, dcache) system.cpu.createInterruptController() system.cpu.connectAllPorts(system.tol2bus, system.membus) system.secondCpu.addPrivateSplitL1Caches(newicache, newdcache) system.secondCpu.createInterruptController() system.secondCpu.connectAllPorts(system.tol2bus, system.membus) So I have 2 cpus with private L1 caches. I am able to switch between these cpus. I am also aware that when one cpu is left idle, its cache remains coherent. What I want now is this: Lets assume cpuA starts running and then it switched to cpuB. Its cache will hold some data, and I want whenever cpuB makes a read request in its own cache, then to duplicate that request and send it also to cacheA (that of cpuA). In that way, cacheA for example will always kept warm and hold the updated values. Can you give me a hint on where to look at or a different approach? Another example is this: If my caches are, say, 32kB large.The application is working on an array of 32kB, so it fits in the cache. Then I switch from core B to core A. Now cache A also gets filled up with the data. However, say the application moves on to a second array of 32kB. Slowly cache A fills up with the second array, but cache B wll still hold the first array and nothing from the second. So the way I am thinking it is that somehow I should update the value in the idle cpu, and one way is by duplicating the request in that cpu, too. (and maybe ignore the response from that cpu). Any hint? Thanks, Ignatios ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] difference between commit.committedInsts and commitedInsts
What's the difference between: system.cpuname.commit.committedInsts #number of Instructions committed and system.cpuname.committedInsts #number of Instructions simulated? Why these two numbers are different? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] wrong number of cpu.commitedInsts after switchCpus
I am having 2 cpus with separate L1 caches and I am switching the workload between them. The problem is that only in the first change between these two cores, no matter when it happens I see in the system.secondcpu.commit.commitedInsts almost double the instructions. if for example my interval is of 1.000.000 instructions then the stats for the commitedInsts will look like this: Interval Number cpu number of Instructions Warm-up mainCpu 1 0 mainCpu 10321426 1 mainCpu 10300316 2 secondmainCpu 20562199 3 secondmainCpu 10255865 4 mainCpu 10246056 5 mainCpu 10234633 6 mainCpu 10225544 7 secondmainCpu 10218624 8 secondmainCpu 10212943 9 secondmainCpu 10206362 Why is that? I am sure that I miss something but I cannot see what is it. Thanks, ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] deschedule an event from a cpu after switching
Hello, I am performing a switch between two O3CPUs which are defined as below: If I run in .opt mode with debug-Flag=O3CPUAll enabled the following assertion is being raised: gem5.opt: build/ARM/cpu/o3/cpu.cc:592: void FullO3CPU::tick() [with Impl = O3CPUImpl]: Assertion `!switchedOut()' failed. which is logical since after the switching, the mainCpu->switchedOut is True. In the trace file I see this: 20350024000: system.mainCpu: Scheduling next tick! 20350024000: system.mainCpu.iq: Processing FU completion [sn:28238748] 20350024000: system.mainCpu: CPU already running. 20350024000: system.mainCpu: Switching out 20350024000: system.mainCpu: switchOut in cpu.cc file called 20350024000: system.secondmainCpu: takeOverFrom in cpu.cc file called 0350024000: system.secondmainCpu: Stage 3 already active. 20350024000: system.mainCpu: Cpu is switched out! 20350025000: system.mainCpu: FullO3CPU: Ticking main, FullO3CPU. why it still tries to run the tick() in the system.mainCpu? Regards, Ignatios ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] switching workload into another cpu
Hello,
in my simulation I am having 3 cores- an atomic one used for the fast
forwarding and other 2 used for the main simulation.
I want to be able to change my workload from one core to another. How to do
that?
I have done the following.
Run the fast-fwd and then switchCpus from atomic to cpuA.
Lets say my workload has 3 intervals, I want in the last one to run on the cpuB.
I have implemented my own switchWorkloadCpu function which does exactly what
the switchCpus() does, except it calls takeWorkloadOverFrom instead
takeOverFrom.
The implementation of takeWorkLoadOverFrom is identical to that of
takeOverFrom, but I haven't included the binding and the un-binding of the
caches since I want these two cores to have separate caches.
So, the workload runs successfully on the cpuA for interval 1,2 and in the last
one it should run on the cpuB. However, there are 4 commited instructions on
the cpuA and none oon the cpuB and my simulation stops with the fatal error
simulare() limit reached.
What to do?
here is my takeWorkloadOverFrom:
BaseCPU::takeWorkloadOverFrom(BaseCPU *oldCPU)
{
assert(threadContexts.size() == oldCPU->threadContexts.size());
assert(_cpuId == oldCPU->cpuId());
assert(_switchedOut);
assert(oldCPU != this);
_pid = oldCPU->getPid();
_taskId = oldCPU->taskId();
_switchedOut = false;
ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
ThreadContext *newTC = threadContexts[i];
ThreadContext *oldTC = oldCPU->threadContexts[i];
newTC->takeOverFrom(oldTC);
CpuEvent::replaceThreadContext(oldTC, newTC);
assert(newTC->contextId() == oldTC->contextId());
assert(newTC->threadId() == oldTC->threadId());
system->replaceThreadContext(newTC, newTC->contextId());
/* This code no longer works since the zero register (e.g.,
* r31 on Alpha) doesn't necessarily contain zero at this
* point.
if (DTRACE(Context))
ThreadContext::compare(oldTC, newTC);
*/
BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort();
BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort();
BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort();
BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort();
// Move over any table walker ports if they exist
if (new_itb_port) {
assert(!new_itb_port->isConnected());
assert(old_itb_port);
assert(old_itb_port->isConnected());
BaseSlavePort &slavePort = old_itb_port->getSlavePort();
old_itb_port->unbind();
new_itb_port->bind(slavePort);
}
if (new_dtb_port) {
assert(!new_dtb_port->isConnected());
assert(old_dtb_port);
assert(old_dtb_port->isConnected());
BaseSlavePort &slavePort = old_dtb_port->getSlavePort();
old_dtb_port->unbind();
new_dtb_port->bind(slavePort);
}
// Checker whether or not we have to transfer CheckerCPU
// objects over in the switch
CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
if (oldChecker && newChecker) {
BaseMasterPort *old_checker_itb_port =
oldChecker->getITBPtr()->getMasterPort();
BaseMasterPort *old_checker_dtb_port =
oldChecker->getDTBPtr()->getMasterPort();
BaseMasterPort *new_checker_itb_port =
newChecker->getITBPtr()->getMasterPort();
BaseMasterPort *new_checker_dtb_port =
newChecker->getDTBPtr()->getMasterPort();
// Move over any table walker ports if they exist for checker
if (new_checker_itb_port) {
assert(!new_checker_itb_port->isConnected());
assert(old_checker_itb_port);
assert(old_checker_itb_port->isConnected());
BaseSlavePort &slavePort =
old_checker_itb_port->getSlavePort();
old_checker_itb_port->unbind();
new_checker_itb_port->bind(slavePort);
}
if (new_checker_dtb_port) {
assert(!new_checker_dtb_port->isConnected());
assert(old_checker_dtb_port);
assert(old_checker_dtb_port->isConnected());
BaseSlavePort &slavePort =
old_checker_dtb_port->getSlavePort();
old_checker_dtb_port->unbind();
new_checker_dtb_port->bind(slavePort);
}
}
}
interrupts = oldCPU->interrupts;
interrupts->setCPU(this);
oldCPU->interrupts = NULL;
if (FullSystem) {
for (ThreadID i = 0; i < size; ++i)
threadContexts[i]->profileClear();
if (profileEvent)
schedule(profileEvent, cu
[gem5-users] Heterogeneous architecture in gem5
Hi,
I want to build a heterogeneous system using gem5. I am having 2 cpus (cpuA and
cpuB) and one workload. What I want to do first is to run the benchmark on the
one and leave the other inactive.
My cores parapmeter are the following:
...
mainCpu.switched_out=fastfwd
mainCpu.workload = process
mainCpu.cpu_id = 0
l2cache = ARML2Cache()
secondmainCpu.switched_out=True
secondmainCpu.workload = process
secondmainCpu.cpu_id = 1
I want secondmainCpu to be inactive so I have set its switched_out to True.
for the fast-fwd I am using atomicCpus and then I am switching to the mainCpu
and the secondmainCpu mentioned above.
# Choose the CPU to use initially.
if fastfwd:
startCpu = funcCpu
secondCpu =secondfuncCpu
print "CPU configuation for fast-fwd"
else:
startCpu = mainCpu
secondCpu = secondmainCpu
print "CPU for main simulation"
if fastfwd:
exitEvent = m5.simulate()
if exitEvent.getCause() == "all threads reached the max instruction count":
print "Finished fast-forwarding, switching CPUs"
m5.drain(system)
m5.changeToTiming(system)
m5.switchCpus([(system.mediumcpu, system.secondmainCpu),(system.cpu,
system.mainCpu)])
m5.resume(system)
else:
fatal("Error fast-forwarding: " + exitEvent.getCause())
The problem is that in the main simulation, no matter which core I set active,
it is like my benchmark runs only on secondmainCpu since in the stats always
secondmainCpu.numcycles is different to zero and maincpu.numCycles is 0.
I have also added my own instruction that sets switch_out to True. So code for
my simulation is this:
...
m5.setswitchTrue(system.secondmainCpu)
...
# Repeatedly simulate and dump stats.
numIntervals = 0
while options.max_intervals == 0 or numIntervals < options.max_intervals:
exitEvent = m5.simulate()
if exitEvent.getCause() == "all threads reached the max instruction count":
print "Finished interval", numIntervals, "so dumping stats"
m5.stats.dump()
m5.stats.reset()
maxInsts += options.interval_length
system.mainCpu.setMaxInstsAllThreads(maxInsts)
system.secondmainCpu.setMaxInstsAllThreads(maxInsts)
numIntervals += 1
elif exitEvent.getCause() == "target called exit":
break
else:
fatal("Error simulating: " + exitEvent.getCause())
where setSwitchTrue is being used for setting switced_out to True and here is
its code (in the base.cc):
void
BaseCPU::setswitchTrue()
{
_switchedOut=true;
}
At first I want to run all of the intervals on the one core, without any
switching. Just to simulate with one core active and the other one inactive,
and then vice versa.
Any hints?
Thanks,
Ignatios
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[gem5-users] Multiple cores to run the same benchmark in turns
Hello, I want to run the following. I am having 2 different cores, with separate L1 caches and I want them to run the same benchmark. So what I want to do for example is : if my benchmark has 2 intervals, to run the first interval on the one core and the second one in the other. While one core is running I want the other one to do nothing. If I run all the intervals on the same core, my simulation completes successfully. So now I want to do the following: Try to perform that switch. I have set swiched_out for core B (the one initially doing nothing) to True. So, I did this: m5.switchCpus([(system.CpuA,system.CpuB)]) and I am getting this error: File "/src/python/m5/simulate.py", line 272, in switchCpus "New CPU (%s) is already active." % (new_core,) RuntimeError: New CPU (system.CpuB) is already active. Why is it active? I have set system.cpuB.switced_out to True for that reason (to be inactive). Here is the switchCpus from the simulate.py (where the exception is being raised). def switchCpus(cpuList): if not isinstance(cpuList, list): raise RuntimeError, "Must pass a list to this function" for item in cpuList: if not isinstance(item, tuple) or len(item) != 2: raise RuntimeError, "List must have tuples of (oldCPU,newCPU)" old_cpu_set = set([old_cpu for old_cpu, new_cpu in cpuList]) for old_cpu, new_cpu in cpuList: if not isinstance(old_cpu, objects.BaseCPU): raise TypeError, "%s is not of type BaseCPU" % old_cpu if not isinstance(new_cpu, objects.BaseCPU): raise TypeError, "%s is not of type BaseCPU" % new_cpu if new_cpu in old_cpu_set: raise RuntimeError, \ "New CPU (%s) is in the list of old CPUs." % (old_cpu,) if not new_cpu.switchedOut(): raise RuntimeError, \ "New CPU (%s) is already active." % (new_cpu,) if old_cpu.switchedOut(): raise RuntimeError, \ "Old CPU (%s) is inactive." % (new_cpu,) Regards, ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
