[PATCH] ahci: qoriq: update the port register settings

[andy . tang]

From: Yuantian Tang 

The default values for Port register PORT_PHY2 and PORT_PHY3
are better, no need to overwrite them.
The following boards are affected: ls208x, ls1088a, ls1043a,
ls1046a, ls1028a and ls1012a.

Signed-off-by: Yuantian Tang 
---
 drivers/ata/ahci_qoriq.c | 12 
 1 file changed, 12 deletions(-)

diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 5b46fc9aeb4a..896e4dba8500 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -32,8 +32,6 @@
 
 /* port register default value */
 #define AHCI_PORT_PHY_1_CFG0xa003fffe
-#define AHCI_PORT_PHY2_CFG 0x28184d1f
-#define AHCI_PORT_PHY3_CFG 0x0e081509
 #define AHCI_PORT_TRANS_CFG0x0829
 #define AHCI_PORT_AXICC_CFG0x3fff
 
@@ -197,8 +195,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
   ECC_DIS_ARMV8_CH2,
   qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
-   writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
-   writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@@ -206,8 +202,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
 
case AHCI_LS2080A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
-   writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
-   writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@@ -221,8 +215,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
   ECC_DIS_ARMV8_CH2,
   qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
-   writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
-   writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@@ -238,8 +230,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
   ECC_DIS_LS1088A,
   qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
-   writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
-   writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
@@ -247,8 +237,6 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
 
case AHCI_LS2088A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
-   writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
-   writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
-- 
2.17.1

[PATCH 2/2] ARM: dts: ls1021a: update calibration table for TMU module

[andy . tang]

From: Yuantian Tang 

Update the calibration table to make the temperature more accurate.

Signed-off-by: Yuantian Tang 
---
 arch/arm/boot/dts/ls1021a.dtsi | 77 --
 1 file changed, 37 insertions(+), 40 deletions(-)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 827373ef1a54..0d569be0d2b2 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -288,46 +288,43 @@
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f0 0x0 0x1>;
interrupts = ;
-   fsl,tmu-range = <0xb 0xa0026 0x80048 0x30061>;
-   fsl,tmu-calibration = <0x 0x000f
-  0x0001 0x0017
-  0x0002 0x001e
-  0x0003 0x0026
-  0x0004 0x002e
-  0x0005 0x0035
-  0x0006 0x003d
-  0x0007 0x0044
-  0x0008 0x004c
-  0x0009 0x0053
-  0x000a 0x005b
-  0x000b 0x0064
-
-  0x0001 0x0011
-  0x00010001 0x001c
-  0x00010002 0x0024
-  0x00010003 0x002b
-  0x00010004 0x0034
-  0x00010005 0x0039
-  0x00010006 0x0042
-  0x00010007 0x004c
-  0x00010008 0x0051
-  0x00010009 0x005a
-  0x0001000a 0x0063
-
-  0x0002 0x0013
-  0x00020001 0x0019
-  0x00020002 0x0024
-  0x00020003 0x002c
-  0x00020004 0x0035
-  0x00020005 0x003d
-  0x00020006 0x0046
-  0x00020007 0x0050
-  0x00020008 0x0059
-
-  0x0003 0x0002
-  0x00030001 0x000d
-  0x00030002 0x0019
-  0x00030003 0x0024>;
+   fsl,tmu-range = <0xb 0x9002c 0x6004e 0x30066>;
+   fsl,tmu-calibration = <0x 0x0020
+  0x0001 0x0024
+  0x0002 0x002a
+  0x0003 0x0032
+  0x0004 0x0038
+  0x0005 0x003e
+  0x0006 0x0043
+  0x0007 0x004a
+  0x0008 0x0050
+  0x0009 0x0059
+  0x000a 0x005f
+  0x000b 0x0066
+
+  0x0001 0x0023
+  0x00010001 0x002b
+  0x00010002 0x0033
+  0x00010003 0x003a
+  0x00010004 0x0042
+  0x00010005 0x004a
+  0x00010006 0x0054
+  0x00010007 0x005c
+  0x00010008 0x0065
+  0x00010009 0x006f
+
+  0x0002 0x0029
+  0x00020001 0x0033
+  0x00020002 0x003d
+ 

[PATCH 1/2] arm64: dts: freescale: update calibration table for TMU module

[andy . tang]

From: Yuantian Tang 

Update the calibration table to make the temperature more accurate.
Three platforms have been updated: ls1012a, ls1043a and ls1046a.

Signed-off-by: Yuantian Tang 
---
 .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 63 ---
 .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 78 ++-
 .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 72 +
 3 files changed, 112 insertions(+), 101 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 5be686a0de54..b3683cda7f5b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -293,43 +293,46 @@
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f0 0x0 0x1>;
interrupts = <0 33 0x4>;
-   fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
-   fsl,tmu-calibration = <0x 0x0026
-  0x0001 0x002d
+   fsl,tmu-range = <0xb 0x9002a 0x6004c 0x60062>;
+   fsl,tmu-calibration = <0x 0x0025
+  0x0001 0x002c
   0x0002 0x0032
   0x0003 0x0039
   0x0004 0x003f
   0x0005 0x0046
-  0x0006 0x004d
-  0x0007 0x0054
-  0x0008 0x005a
-  0x0009 0x0061
-  0x000a 0x006a
-  0x000b 0x0071
-
-  0x0001 0x0025
-  0x00010001 0x002c
+  0x0006 0x004c
+  0x0007 0x0053
+  0x0008 0x0059
+  0x0009 0x005f
+  0x000a 0x0066
+  0x000b 0x006c
+
+  0x0001 0x0026
+  0x00010001 0x002d
   0x00010002 0x0035
   0x00010003 0x003d
   0x00010004 0x0045
-  0x00010005 0x004e
-  0x00010006 0x0057
-  0x00010007 0x0061
-  0x00010008 0x006b
-  0x00010009 0x0076
-
-  0x0002 0x0029
-  0x00020001 0x0033
-  0x00020002 0x003d
-  0x00020003 0x0049
-  0x00020004 0x0056
-  0x00020005 0x0061
-  0x00020006 0x006d
-
-  0x0003 0x0021
-  0x00030001 0x002a
-  0x00030002 0x003c
-  0x00030003 0x004e>;
+  0x00010005 0x004d
+  0x00010006 0x0055
+  0x00010007 0x005d
+  0x00010008 0x0065
+  0x00010009 0x006d
+
+  0x0002 0x0026
+  0x00020001 0x0030
+  0x00020002 0x003a
+  0x00020003 0x0044
+  0x00020004 0x004e
+  0x00020005 0x0059
+  0x00020006 0x0063
+
+  0x0003 0x0014
+  0x00030001 0x0021
+  

RE: [PATCH] ahci: qoriq: enable acpi support in qoriq ahci driver

[Andy Tang]

Hi Axboe,

Please take some times reviewing this patch.

Thanks,
Andy

> -Original Message-
> From: andy.t...@nxp.com 
> Sent: 2020年8月17日 16:22
> To: ax...@kernel.dk
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Andy Tang
> ; Udit Kumar 
> Subject: [PATCH] ahci: qoriq: enable acpi support in qoriq ahci driver
> 
> From: Yuantian Tang 
> 
> This patch enables ACPI support in qoriq ahci driver.
> 
> Signed-off-by: Udit Kumar 
> Signed-off-by: Yuantian Tang 
> ---
>  drivers/ata/ahci_qoriq.c | 20 +---
>  1 file changed, 17 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c index
> a330307d3201..5b46fc9aeb4a 100644
> --- a/drivers/ata/ahci_qoriq.c
> +++ b/drivers/ata/ahci_qoriq.c
> @@ -6,6 +6,7 @@
>   *   Tang Yuantian 
>   */
> 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -80,6 +81,12 @@ static const struct of_device_id ahci_qoriq_of_match[] =
> {  };  MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
> 
> +static const struct acpi_device_id ahci_qoriq_acpi_match[] = {
> + {"NXP0004", .driver_data = (kernel_ulong_t)AHCI_LX2160A},
> + { }
> +};
> +MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match);
> +
>  static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
> unsigned long deadline)
>  {
> @@ -255,6 +262,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv
> *hpriv)  static int ahci_qoriq_probe(struct platform_device *pdev)  {
>   struct device_node *np = pdev->dev.of_node;
> + const struct acpi_device_id *acpi_id;
>   struct device *dev = >dev;
>   struct ahci_host_priv *hpriv;
>   struct ahci_qoriq_priv *qoriq_priv;
> @@ -267,14 +275,18 @@ static int ahci_qoriq_probe(struct platform_device
> *pdev)
>   return PTR_ERR(hpriv);
> 
>   of_id = of_match_node(ahci_qoriq_of_match, np);
> - if (!of_id)
> + acpi_id = acpi_match_device(ahci_qoriq_acpi_match, >dev);
> + if (!(of_id || acpi_id))
>   return -ENODEV;
> 
>   qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
>   if (!qoriq_priv)
>   return -ENOMEM;
> 
> - qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
> + if (of_id)
> + qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
> + else
> + qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data;
> 
>   if (unlikely(!ecc_initialized)) {
>   res = platform_get_resource_byname(pdev,
> @@ -288,7 +300,8 @@ static int ahci_qoriq_probe(struct platform_device
> *pdev)
>   }
>   }
> 
> - qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
> + if (device_get_dma_attr(>dev) == DEV_DMA_COHERENT)
> + qoriq_priv->is_dmacoherent = true;
> 
>   rc = ahci_platform_enable_resources(hpriv);
>   if (rc)
> @@ -354,6 +367,7 @@ static struct platform_driver ahci_qoriq_driver = {
>   .driver = {
>   .name = DRV_NAME,
>   .of_match_table = ahci_qoriq_of_match,
> + .acpi_match_table = ahci_qoriq_acpi_match,
>   .pm = _qoriq_pm_ops,
>   },
>  };
> --
> 2.17.1

[PATCH] ahci: qoriq: enable acpi support in qoriq ahci driver

[andy . tang]

From: Yuantian Tang 

This patch enables ACPI support in qoriq ahci driver.

Signed-off-by: Udit Kumar 
Signed-off-by: Yuantian Tang 
---
 drivers/ata/ahci_qoriq.c | 20 +---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index a330307d3201..5b46fc9aeb4a 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -6,6 +6,7 @@
  *   Tang Yuantian 
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -80,6 +81,12 @@ static const struct of_device_id ahci_qoriq_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
 
+static const struct acpi_device_id ahci_qoriq_acpi_match[] = {
+   {"NXP0004", .driver_data = (kernel_ulong_t)AHCI_LX2160A},
+   { }
+};
+MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match);
+
 static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
  unsigned long deadline)
 {
@@ -255,6 +262,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
 static int ahci_qoriq_probe(struct platform_device *pdev)
 {
struct device_node *np = pdev->dev.of_node;
+   const struct acpi_device_id *acpi_id;
struct device *dev = >dev;
struct ahci_host_priv *hpriv;
struct ahci_qoriq_priv *qoriq_priv;
@@ -267,14 +275,18 @@ static int ahci_qoriq_probe(struct platform_device *pdev)
return PTR_ERR(hpriv);
 
of_id = of_match_node(ahci_qoriq_of_match, np);
-   if (!of_id)
+   acpi_id = acpi_match_device(ahci_qoriq_acpi_match, >dev);
+   if (!(of_id || acpi_id))
return -ENODEV;
 
qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
if (!qoriq_priv)
return -ENOMEM;
 
-   qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
+   if (of_id)
+   qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
+   else
+   qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data;
 
if (unlikely(!ecc_initialized)) {
res = platform_get_resource_byname(pdev,
@@ -288,7 +300,8 @@ static int ahci_qoriq_probe(struct platform_device *pdev)
}
}
 
-   qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
+   if (device_get_dma_attr(>dev) == DEV_DMA_COHERENT)
+   qoriq_priv->is_dmacoherent = true;
 
rc = ahci_platform_enable_resources(hpriv);
if (rc)
@@ -354,6 +367,7 @@ static struct platform_driver ahci_qoriq_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = ahci_qoriq_of_match,
+   .acpi_match_table = ahci_qoriq_acpi_match,
.pm = _qoriq_pm_ops,
},
 };
-- 
2.17.1

[PATCH 2/2 v2] arm64: dts: ls208xa: add more thermal zone support

[andy . tang]

From: Yuantian Tang 

There are 7 thermal zones in ls208xa soc. Add the other thermal zone
nodes to enable them.

Signed-off-by: Yuantian Tang 
---
v2:
- remove useless alert trip
- add cooling-map to core cluster zones.

 .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 141 --
 1 file changed, 132 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 41102dacc2e1..cc36c969dd9d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -79,20 +79,62 @@
};
 
thermal-zones {
-   cpu_thermal: cpu-thermal {
+   ddr-controller1 {
polling-delay-passive = <1000>;
polling-delay = <5000>;
+   thermal-sensors = < 1>;
 
+   trips {
+   ddr-ctrler1-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   ddr-controller2 {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 2>;
+
+   trips {
+   ddr-ctrler2-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   ddr-controller3 {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 3>;
+
+   trips {
+   ddr-ctrler3-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   core-cluster1 {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
thermal-sensors = < 4>;
 
trips {
-   cpu_alert: cpu-alert {
-   temperature = <75000>;
+   core_cluster1_alert: core-cluster1-alert {
+   temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
-   cpu_crit: cpu-crit {
-   temperature = <85000>;
+
+   core-cluster1-crit {
+   temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
@@ -100,14 +142,95 @@
 
cooling-maps {
map0 {
-   trip = <_alert>;
+   trip = <_cluster1_alert>;
cooling-device =
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
-   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>;
+   };
+   };
+   };
+
+   core-cluster2 {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 5>;
+
+   trips {
+   core_cluster2_alert: core-cluster2-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   core-cluster2-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   map0 {
+   trip = <_cluster2_alert>;
+   cooling-device =
  

[PATCH 1/2 v2] arm64: dts: ls1088a: add more thermal zone support

[andy . tang]

From: Yuantian Tang 

There are 2 thermal zones in ls1088a soc. Add the other thermal zone
node to enable it.
Also update the values in calibration table to make the temperatures
monitored more precise.

Signed-off-by: Yuantian Tang 
---
v2:
- remove useless alert trip

 .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 94 +++
 1 file changed, 56 insertions(+), 38 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 169f4742ae3b..b961a896ede7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -130,19 +130,19 @@
};
 
thermal-zones {
-   cpu_thermal: cpu-thermal {
+   core-cluster {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = < 0>;
 
trips {
-   cpu_alert: cpu-alert {
+   core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
 
-   cpu_crit: cpu-crit {
+   core-cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -151,7 +151,7 @@
 
cooling-maps {
map0 {
-   trip = <_alert>;
+   trip = <_cluster_alert>;
cooling-device =
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
@@ -164,6 +164,20 @@
};
};
};
+
+   soc {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 1>;
+
+   trips {
+   soc-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
};
 
timer {
@@ -210,45 +224,49 @@
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
interrupts = <0 23 0x4>;
-   fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+   fsl,tmu-range = <0xb 0x9002a 0x6004c 0x70062>;
fsl,tmu-calibration =
/* Calibration data group 1 */
-   <0x 0x0026
-   0x0001 0x002d
-   0x0002 0x0032
-   0x0003 0x0039
-   0x0004 0x003f
-   0x0005 0x0046
-   0x0006 0x004d
-   0x0007 0x0054
-   0x0008 0x005a
-   0x0009 0x0061
-   0x000a 0x006a
-   0x000b 0x0071
+   <0x 0x0023
+   0x0001 0x002a
+   0x0002 0x0030
+   0x0003 0x0037
+   0x0004 0x003d
+   0x0005 0x0044
+   0x0006 0x004a
+   0x0007 0x0051
+   0x0008 0x0057
+   0x0009 0x005e
+   0x000a 0x0064
+   0x000b 0x006b
/* Calibration data group 2 */
-   0x0001 0x0025
-   0x00010001 0x002c
-   0x00010002 0x0035
-   0x00010003 0x003d
-   0x00010004 0x0045
-   0x00010005 0x004e
-   0x00010006 0x0057
-   0x00010007 0x0061
-   0x00010008 

RE: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more thermal zone support

[Andy Tang]

Hi Shawn,

Do you think it is ok if the cooling devices are shared between thermal zones?

BR,
Andy

> -Original Message-
> From: Amit Kucheria 
> Sent: 2020年6月30日 14:47
> To: Andy Tang 
> Cc: Shawn Guo ; Leo Li ; Rob
> Herring ; lakml ;
> open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> ; LKML 
> Subject: Re: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more thermal
> zone support
> 
> Caution: EXT Email
> 
> On Tue, Jun 30, 2020 at 12:07 PM Andy Tang  wrote:
> >
> >
> >
> > > -Original Message-----
> > > From: Amit Kucheria 
> > > Sent: 2020年6月30日 13:37
> > > To: Andy Tang 
> > > Cc: Shawn Guo ; Leo Li ;
> > > Rob Herring ; lakml
> > > ;
> > > open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> > > ; LKML 
> > > Subject: Re: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more
> > > thermal zone support
> > >
> > > Caution: EXT Email
> > >
> > > On Tue, Jun 30, 2020 at 10:58 AM Andy Tang 
> wrote:
> > > >
> > > >
> > > >
> > > > > -Original Message-
> > > > > From: Amit Kucheria 
> > > > > Sent: 2020年6月30日 13:12
> > > > > To: Andy Tang 
> > > > > Cc: Shawn Guo ; Leo Li
> > > > > ; Rob Herring ; lakml
> > > > > ;
> > > > > open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> > > > > ; LKML
> > > > > 
> > > > > Subject: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more
> > > > > thermal zone support
> > > > >
> > > > > Caution: EXT Email
> > > > >
> > > > > On Tue, Jun 30, 2020 at 8:56 AM  wrote:
> > > > > >
> > > > > > From: Yuantian Tang 
> > > > > >
> > > > > > There are 2 thermal zones in ls1088a soc. Add the other
> > > > > > thermal zone node to enable it.
> > > > > > Also update the values in calibration table to make the
> > > > > > temperatures monitored more precise.
> > > > > >
> > > > > > Signed-off-by: Yuantian Tang 
> > > > > > ---
> > > > > >  .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 100
> > > > > > +++---
> > > > > >  1 file changed, 62 insertions(+), 38 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > > > > b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > > > > index 36a799554620..ccbbc23e6c85 100644
> > > > > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > > > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > > > > @@ -129,19 +129,19 @@
> > > > > > };
> > > > > >
> > > > > > thermal-zones {
> > > > > > -   cpu_thermal: cpu-thermal {
> > > > > > +   core-cluster {
> > > > > > polling-delay-passive = <1000>;
> > > > > > polling-delay = <5000>;
> > > > > > thermal-sensors = < 0>;
> > > > > >
> > > > > > trips {
> > > > > > -   cpu_alert: cpu-alert {
> > > > > > +   core_cluster_alert:
> > > > > core-cluster-alert
> > > > > > + {
> > > > > > temperature =
> > > <85000>;
> > > > > > hysteresis =
> <2000>;
> > > > > > type = "passive";
> > > > > > };
> > > > > >
> > > > > > -   cpu_crit: cpu-crit {
> > > > > > +   core_cluster_crit:
> > > > > > + core-cluster-crit {
> > > > > > temperature =
> > > <95000>;
> > > > > > hysteresis =
> <2000>;
> > > > > >   

RE: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more thermal zone support

[Andy Tang]

> -Original Message-
> From: Amit Kucheria 
> Sent: 2020年6月30日 14:47
> To: Andy Tang 
> Cc: Shawn Guo ; Leo Li ; Rob
> Herring ; lakml ;
> open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> ; LKML 
> Subject: Re: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more thermal
> zone support
> 
> Caution: EXT Email
> 
> On Tue, Jun 30, 2020 at 12:07 PM Andy Tang  wrote:
> >
> >
> >
> > > -Original Message-----
> > > From: Amit Kucheria 
> > > Sent: 2020年6月30日 13:37
> > > To: Andy Tang 
> > > Cc: Shawn Guo ; Leo Li ;
> > > Rob Herring ; lakml
> > > ;
> > > open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> > > ; LKML 
> > > Subject: Re: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more
> > > thermal zone support
> > >
> > > Caution: EXT Email
> > >
> > > On Tue, Jun 30, 2020 at 10:58 AM Andy Tang 
> wrote:
> > > >
> > > >
> > > >
> > > > > -Original Message-
> > > > > From: Amit Kucheria 
> > > > > Sent: 2020年6月30日 13:12
> > > > > To: Andy Tang 
> > > > > Cc: Shawn Guo ; Leo Li
> > > > > ; Rob Herring ; lakml
> > > > > ;
> > > > > open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> > > > > ; LKML
> > > > > 
> > > > > Subject: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more
> > > > > thermal zone support
> > > > >
> > > > > Caution: EXT Email
> > > > >
> > > > > On Tue, Jun 30, 2020 at 8:56 AM  wrote:
> > > > > >
> > > > > > From: Yuantian Tang 
> > > > > >
> > > > > > There are 2 thermal zones in ls1088a soc. Add the other
> > > > > > thermal zone node to enable it.
> > > > > > Also update the values in calibration table to make the
> > > > > > temperatures monitored more precise.
> > > > > >
> > > > > > Signed-off-by: Yuantian Tang 
> > > > > > ---
> > > > > >  .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 100
> > > > > > +++---
> > > > > >  1 file changed, 62 insertions(+), 38 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > > > > b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > > > > index 36a799554620..ccbbc23e6c85 100644
> > > > > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > > > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > > > > @@ -129,19 +129,19 @@
> > > > > > };
> > > > > >
> > > > > > thermal-zones {
> > > > > > -   cpu_thermal: cpu-thermal {
> > > > > > +   core-cluster {
> > > > > > polling-delay-passive = <1000>;
> > > > > > polling-delay = <5000>;
> > > > > > thermal-sensors = < 0>;
> > > > > >
> > > > > > trips {
> > > > > > -   cpu_alert: cpu-alert {
> > > > > > +   core_cluster_alert:
> > > > > core-cluster-alert
> > > > > > + {
> > > > > > temperature =
> > > <85000>;
> > > > > > hysteresis =
> <2000>;
> > > > > > type = "passive";
> > > > > > };
> > > > > >
> > > > > > -   cpu_crit: cpu-crit {
> > > > > > +   core_cluster_crit:
> > > > > > + core-cluster-crit {
> > > > > > temperature =
> > > <95000>;
> > > > > > hysteresis =
> <2000>;
> > > > > > type = "critical";
> @@
> > > > > -150,7
> > > > > 

RE: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more thermal zone support

[Andy Tang]

> -Original Message-
> From: Amit Kucheria 
> Sent: 2020年6月30日 13:37
> To: Andy Tang 
> Cc: Shawn Guo ; Leo Li ; Rob
> Herring ; lakml ;
> open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> ; LKML 
> Subject: Re: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more thermal
> zone support
> 
> Caution: EXT Email
> 
> On Tue, Jun 30, 2020 at 10:58 AM Andy Tang  wrote:
> >
> >
> >
> > > -Original Message-----
> > > From: Amit Kucheria 
> > > Sent: 2020年6月30日 13:12
> > > To: Andy Tang 
> > > Cc: Shawn Guo ; Leo Li ;
> > > Rob Herring ; lakml
> > > ;
> > > open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> > > ; LKML 
> > > Subject: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more thermal
> > > zone support
> > >
> > > Caution: EXT Email
> > >
> > > On Tue, Jun 30, 2020 at 8:56 AM  wrote:
> > > >
> > > > From: Yuantian Tang 
> > > >
> > > > There are 2 thermal zones in ls1088a soc. Add the other thermal
> > > > zone node to enable it.
> > > > Also update the values in calibration table to make the
> > > > temperatures monitored more precise.
> > > >
> > > > Signed-off-by: Yuantian Tang 
> > > > ---
> > > >  .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 100
> > > > +++---
> > > >  1 file changed, 62 insertions(+), 38 deletions(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > > b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > > index 36a799554620..ccbbc23e6c85 100644
> > > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > > @@ -129,19 +129,19 @@
> > > > };
> > > >
> > > > thermal-zones {
> > > > -   cpu_thermal: cpu-thermal {
> > > > +   core-cluster {
> > > > polling-delay-passive = <1000>;
> > > > polling-delay = <5000>;
> > > > thermal-sensors = < 0>;
> > > >
> > > > trips {
> > > > -   cpu_alert: cpu-alert {
> > > > +   core_cluster_alert:
> > > core-cluster-alert
> > > > + {
> > > > temperature =
> <85000>;
> > > > hysteresis = <2000>;
> > > > type = "passive";
> > > > };
> > > >
> > > > -   cpu_crit: cpu-crit {
> > > > +   core_cluster_crit:
> > > > + core-cluster-crit {
> > > > temperature =
> <95000>;
> > > > hysteresis = <2000>;
> > > > type = "critical"; @@
> > > -150,7
> > > > +150,7 @@
> > > >
> > > > cooling-maps {
> > > > map0 {
> > > > -   trip = <_alert>;
> > > > +   trip =
> > > <_cluster_alert>;
> > > > cooling-device =
> > > > <
> > > THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > > > <
> > > > THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -163,6 +163,26 @@
> > > > };
> > > > };
> > > > };
> > > > +
> > > > +   soc {
> > > > +   polling-delay-passive = <1000>;
> > > > +   polling-delay = <5000>;
> > > > +   thermal-sensors = < 1>;
> > > > +
> > > > +   trips {
> > > > +   soc-alert {
> > > > +   temperature =
> <85000>;
> >

RE: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more thermal zone support

[Andy Tang]

> -Original Message-
> From: Amit Kucheria 
> Sent: 2020年6月30日 13:12
> To: Andy Tang 
> Cc: Shawn Guo ; Leo Li ; Rob
> Herring ; lakml ;
> open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> ; LKML 
> Subject: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more thermal zone
> support
> 
> Caution: EXT Email
> 
> On Tue, Jun 30, 2020 at 8:56 AM  wrote:
> >
> > From: Yuantian Tang 
> >
> > There are 2 thermal zones in ls1088a soc. Add the other thermal zone
> > node to enable it.
> > Also update the values in calibration table to make the temperatures
> > monitored more precise.
> >
> > Signed-off-by: Yuantian Tang 
> > ---
> >  .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 100
> > +++---
> >  1 file changed, 62 insertions(+), 38 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > index 36a799554620..ccbbc23e6c85 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > @@ -129,19 +129,19 @@
> > };
> >
> > thermal-zones {
> > -   cpu_thermal: cpu-thermal {
> > +   core-cluster {
> > polling-delay-passive = <1000>;
> > polling-delay = <5000>;
> > thermal-sensors = < 0>;
> >
> > trips {
> > -   cpu_alert: cpu-alert {
> > +   core_cluster_alert:
> core-cluster-alert
> > + {
> > temperature = <85000>;
> > hysteresis = <2000>;
> > type = "passive";
> > };
> >
> > -   cpu_crit: cpu-crit {
> > +   core_cluster_crit: core-cluster-crit {
> > temperature = <95000>;
> > hysteresis = <2000>;
> > type = "critical"; @@
> -150,7
> > +150,7 @@
> >
> > cooling-maps {
> > map0 {
> > -   trip = <_alert>;
> > +   trip =
> <_cluster_alert>;
> > cooling-device =
> > <
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > <
> > THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -163,6 +163,26 @@
> > };
> > };
> > };
> > +
> > +   soc {
> > +   polling-delay-passive = <1000>;
> > +   polling-delay = <5000>;
> > +   thermal-sensors = < 1>;
> > +
> > +   trips {
> > +   soc-alert {
> > +   temperature = <85000>;
> > +   hysteresis = <2000>;
> > +   type = "passive";
> > +   };
> > +
> > +   soc-crit {
> > +   temperature = <95000>;
> > +   hysteresis = <2000>;
> > +   type = "critical";
> > +   };
> > +   };
> > +   };
> 
> You should also add a cooling-maps section for this thermal zone given that it
> has a passive trip type. Otherwise there is no use for a passive trip type.
It is better to have a cooling device. But there is only one cooling device on 
this platform
which is used by core-cluster. So there is no extra cooling device for it.
This zone can take action when critical temp is reached. So it is still useful.
What do you suggest? 

BR,
Andy
> 
> > };
> >
> > timer {
> > @@ -209,45 +229,49 @@
> > compatible = "fsl,qoriq-tmu";
> > reg = <0x0 0x1f8 0x0 0x1>;
> >   

[PATCH 2/2] arm64: dts: ls208xa: add more thermal zone support

[andy . tang]

From: Yuantian Tang 

There are 7 thermal zones in ls208xa soc. Add the other thermal zone
nodes to enable them.

Signed-off-by: Yuantian Tang 
---
 .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 132 +-
 1 file changed, 126 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 3944ef16ec60..019e99826645 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -78,28 +78,88 @@
};
 
thermal-zones {
-   cpu_thermal: cpu-thermal {
+   ddr-controller1 {
polling-delay-passive = <1000>;
polling-delay = <5000>;
+   thermal-sensors = < 1>;
 
-   thermal-sensors = < 4>;
+   trips {
+   ddr-ctrler1-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   ddr-ctrler1-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   ddr-controller2 {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 2>;
+
+   trips {
+   ddr-ctrler2-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   ddr-ctrler2-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   ddr-controller3 {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 3>;
 
trips {
-   cpu_alert: cpu-alert {
-   temperature = <75000>;
+   ddr-ctrler3-alert {
+   temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
-   cpu_crit: cpu-crit {
+
+   ddr-ctrler3-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   core-cluster1 {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 4>;
+
+   trips {
+   core_cluster1_alert: core-cluster1-alert {
temperature = <85000>;
hysteresis = <2000>;
+   type = "passive";
+   };
+
+   core_cluster1_crit: core-cluster1-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
type = "critical";
};
};
 
cooling-maps {
map0 {
-   trip = <_alert>;
+   trip = <_cluster1_alert>;
cooling-device =
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
@@ -112,6 +172,66 @@
};
};
};
+
+   core-cluster2 {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 5>;
+
+   trips {
+   core-cluster2-alert {
+   temperature = <85000>;
+

[PATCH 1/2] arm64: dts: ls1088a: add more thermal zone support

[andy . tang]

From: Yuantian Tang 

There are 2 thermal zones in ls1088a soc. Add the other thermal zone
node to enable it.
Also update the values in calibration table to make the temperatures
monitored more precise.

Signed-off-by: Yuantian Tang 
---
 .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 100 +++---
 1 file changed, 62 insertions(+), 38 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 36a799554620..ccbbc23e6c85 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -129,19 +129,19 @@
};
 
thermal-zones {
-   cpu_thermal: cpu-thermal {
+   core-cluster {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = < 0>;
 
trips {
-   cpu_alert: cpu-alert {
+   core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
 
-   cpu_crit: cpu-crit {
+   core_cluster_crit: core-cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -150,7 +150,7 @@
 
cooling-maps {
map0 {
-   trip = <_alert>;
+   trip = <_cluster_alert>;
cooling-device =
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
@@ -163,6 +163,26 @@
};
};
};
+
+   soc {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 1>;
+
+   trips {
+   soc-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   soc-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
};
 
timer {
@@ -209,45 +229,49 @@
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f8 0x0 0x1>;
interrupts = <0 23 0x4>;
-   fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+   fsl,tmu-range = <0xb 0x9002a 0x6004c 0x70062>;
fsl,tmu-calibration =
/* Calibration data group 1 */
-   <0x 0x0026
-   0x0001 0x002d
-   0x0002 0x0032
-   0x0003 0x0039
-   0x0004 0x003f
-   0x0005 0x0046
-   0x0006 0x004d
-   0x0007 0x0054
-   0x0008 0x005a
-   0x0009 0x0061
-   0x000a 0x006a
-   0x000b 0x0071
+   <0x 0x0023
+   0x0001 0x002a
+   0x0002 0x0030
+   0x0003 0x0037
+   0x0004 0x003d
+   0x0005 0x0044
+   0x0006 0x004a
+   0x0007 0x0051
+   0x0008 0x0057
+   0x0009 0x005e
+   0x000a 0x0064
+   0x000b 0x006b
/* Calibration data group 2 */
-   0x0001 0x0025
-   0x00010001 0x002c
-   0x00010002 0x0035
-   0x00010003 0x003d
-   

[PATCH 1/2] arm64: dts: ls1046a: add more thermal zone support

[andy . tang]

From: Yuantian Tang 

There are 5 thermal zones in ls1046a soc. Add the rest thermal zone
nodes to enable them.

Signed-off-by: Yuantian Tang 
---
 .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 88 ++-
 1 file changed, 84 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index d4c1da3d4bde..9896379309d8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -117,19 +117,79 @@
};
 
thermal-zones {
-   cpu_thermal: cpu-thermal {
+   ddr-controller {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 0>;
+
+   trips {
+   ddr-ctrler-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   ddr-ctrler-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   serdes {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 1>;
+
+   trips {
+   serdes-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   serdes-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   fman {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 2>;
+
+   trips {
+   fman-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   fman-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   core-cluster {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = < 3>;
 
trips {
-   cpu_alert: cpu-alert {
+   core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
 
-   cpu_crit: cpu-crit {
+   core_cluster_crit: core-cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -138,7 +198,7 @@
 
cooling-maps {
map0 {
-   trip = <_alert>;
+   trip = <_cluster_alert>;
cooling-device =
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
@@ -147,6 +207,26 @@
};
};
};
+
+   sec {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 4>;
+
+   trips {
+   sec-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   sec-crit {
+   temperature 

[PATCH 2/2] arm64: dts: ls1043a: add more thermal zone support

[andy . tang]

From: Yuantian Tang 

There are 5 thermal zones in ls1043a soc. Add the
rest thermal zone nodes to enable them.

Signed-off-by: Yuantian Tang 
---
 .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 88 ++-
 1 file changed, 84 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 3b641bd43229..17497b0d3542 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -149,19 +149,79 @@
};
 
thermal-zones {
-   cpu_thermal: cpu-thermal {
+   ddr-controller {
polling-delay-passive = <1000>;
polling-delay = <5000>;
+   thermal-sensors = < 0>;
 
+   trips {
+   ddr-ctrler-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   ddr-ctrler-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   serdes {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 1>;
+
+   trips {
+   serdes-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   serdes-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   fman {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 2>;
+
+   trips {
+   fman-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   fman-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   core-cluster {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
thermal-sensors = < 3>;
 
trips {
-   cpu_alert: cpu-alert {
+   core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
-   cpu_crit: cpu-crit {
+
+   core_cluster_crit: core-cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -170,7 +230,7 @@
 
cooling-maps {
map0 {
-   trip = <_alert>;
+   trip = <_cluster_alert>;
cooling-device =
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
@@ -179,6 +239,26 @@
};
};
};
+
+   sec {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 4>;
+
+   trips {
+   sec-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   sec-crit {
+   temperature 

RE: [EXT] Re: [PATCH] arm64: dts: ls1028a: add one more thermal zone support

[Andy Tang]

-Original Message-
From: Daniel Lezcano  
Sent: 2020年5月25日 19:08
To: Andy Tang ; shawn...@kernel.org; robh...@kernel.org; 
mark.rutl...@arm.com; catalin.mari...@arm.com; will.dea...@arm.com
Cc: devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; 
linux-kernel@vger.kernel.org
Subject: [EXT] Re: [PATCH] arm64: dts: ls1028a: add one more thermal zone 
support

Caution: EXT Email

On 25/05/2020 09:38, Yuantian Tang wrote:
> There are 2 thermal zones in ls1028a soc. Current dts only includes 
> one. This patch adds the other thermal zone node in dts to enable it.

For my personal information, is there a cooling device for the DDR?

A: There is only one cooling device which is used by core-cluster sensor zone.
So there is no cooling device for DDR.

BR,
Andy 

> Signed-off-by: Yuantian Tang 
> ---
>  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 22 
> ++-
>  1 file changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index 055f114cf848..bc6f0c0f85da 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -129,11 +129,31 @@
>   };
>
>   thermal-zones {
> - core-cluster {
> + ddr-controller {
>   polling-delay-passive = <1000>;
>   polling-delay = <5000>;
>   thermal-sensors = < 0>;
>
> + trips {
> + ddr-ctrler-alert {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + ddr-ctrler-crit {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + core-cluster {
> + polling-delay-passive = <1000>;
> + polling-delay = <5000>;
> + thermal-sensors = < 1>;
> +
>   trips {
>   core_cluster_alert: core-cluster-alert {
>   temperature = <85000>;
>


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 Blog

RE: [PATCH] arm64: dts: lx2160a: add more thermal zone support

[Andy Tang]

PING.

BR,
Andy

> -Original Message-
> From: Yuantian Tang 
> Sent: 2020年4月17日 14:16
> To: shawn...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com;
> catalin.mari...@arm.com; will.dea...@arm.com
> Cc: devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; Andy Tang 
> Subject: [PATCH] arm64: dts: lx2160a: add more thermal zone support
> 
> There are 7 thermal zones in lx2160a soc. Add the rest thermal zone node to
> enable them.
> Also correct one of the values for tmu-calibration property.
> 
> Signed-off-by: Yuantian Tang 
> ---
>  .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 130 +-
>  1 file changed, 125 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index ae1b113ab162..abaeb587de48 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -436,19 +436,19 @@
>   };
> 
>   thermal-zones {
> - core_thermal1: core-thermal1 {
> + cluster6-7 {
>   polling-delay-passive = <1000>;
>   polling-delay = <5000>;
>   thermal-sensors = < 0>;
> 
>   trips {
> - core_cluster_alert: core-cluster-alert {
> + cluster6_7_alert: cluster6-7-alert {
>   temperature = <85000>;
>   hysteresis = <2000>;
>   type = "passive";
>   };
> 
> - core_cluster_crit: core-cluster-crit {
> + cluster6_7_crit: cluster6-7-crit {
>   temperature = <95000>;
>   hysteresis = <2000>;
>   type = "critical";
> @@ -457,7 +457,7 @@
> 
>   cooling-maps {
>   map0 {
> - trip = <_cluster_alert>;
> + trip = <_7_alert>;
>   cooling-device =
>   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
>   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>, @@ -478,6 +478,126 @@
>   };
>   };
>   };
> +
> + ddr-cluster5 {
> + polling-delay-passive = <1000>;
> + polling-delay = <5000>;
> + thermal-sensors = < 1>;
> +
> + trips {
> + ddr-cluster5-alert {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + ddr-cluster5-crit {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + wriop {
> + polling-delay-passive = <1000>;
> + polling-delay = <5000>;
> + thermal-sensors = < 2>;
> +
> + trips {
> + wriop-alert {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + wriop-crit {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + dce-qbman-hsio2 {
> + polling-delay-passive = <1000>;
> + polling-delay = <5000>;
> + thermal-sensors = < 

RE: [PATCH v2] thermal: qoriq: Update the settings for TMUv2

[Andy Tang]

PING.

BR,
Andy

> -Original Message-
> From: Yuantian Tang 
> Sent: 2020年4月16日 17:40
> To: rui.zh...@intel.com; edubez...@gmail.com; daniel.lezc...@linaro.org
> Cc: linux...@vger.kernel.org; linux-kernel@vger.kernel.org; Andy Tang
> 
> Subject: [PATCH v2] thermal: qoriq: Update the settings for TMUv2
> 
> For TMU v2, TMSAR registers need to be set properly to get the accurate
> temperature values.
> Also temperature reading needs to convert to degree Celsius since it is in
> degrees Kelvin.
> 
> Signed-off-by: Yuantian Tang 
> ---
> v2:
>   - change the temp in millicelsius
> 
>  drivers/thermal/qoriq_thermal.c | 15 ++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/thermal/qoriq_thermal.c
> b/drivers/thermal/qoriq_thermal.c index 028a6bbf75dc..f6371127f707
> 100644
> --- a/drivers/thermal/qoriq_thermal.c
> +++ b/drivers/thermal/qoriq_thermal.c
> @@ -23,6 +23,7 @@
>  #define TMTMIR_DEFAULT   0x000f
>  #define TIER_DISABLE 0x0
>  #define TEUMR0_V20x51009c00
> +#define TMSARA_V20xe
>  #define TMU_VER1 0x1
>  #define TMU_VER2 0x2
> 
> @@ -50,6 +51,9 @@
>   * Site Register
>   */
>  #define TRITSR_V BIT(31)
> +#define REGS_V2_TMSAR(n) (0x304 + 16 * (n))  /* TMU monitoring
> + * site adjustment register
> + */
>  #define REGS_TTRnCR(n)   (0xf10 + 4 * (n)) /* Temperature Range n
>  * Control Register
>  */
> @@ -100,7 +104,11 @@ static int tmu_get_temp(void *p, int *temp)
>10 * USEC_PER_MSEC))
>   return -ENODATA;
> 
> - *temp = (val & 0xff) * 1000;
> + /* For TMUv2, temperature reading in degrees Kelvin */
> + if (qdata->ver == TMU_VER1)
> + *temp = (val & 0xff) * 1000;
> + else
> + *temp = ((val & 0x1ff) - 273) * 1000;
> 
>   return 0;
>  }
> @@ -192,6 +200,8 @@ static int qoriq_tmu_calibration(struct device *dev,
> 
>  static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)  {
> + int i;
> +
>   /* Disable interrupt, using polling instead */
>   regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);
> 
> @@ -202,6 +212,8 @@ static void qoriq_tmu_init_device(struct
> qoriq_tmu_data *data)
>   } else {
>   regmap_write(data->regmap, REGS_V2_TMTMIR,
> TMTMIR_DEFAULT);
>   regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
> + for (i = 0; i < 7; i++)
> + regmap_write(data->regmap, REGS_V2_TMSAR(i),
> TMSARA_V2);
>   }
> 
>   /* Disable monitoring */
> @@ -212,6 +224,7 @@ static const struct regmap_range qoriq_yes_ranges[]
> = {
>   regmap_reg_range(REGS_TMR, REGS_TSCFGR),
>   regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(3)),
>   regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
> + regmap_reg_range(REGS_V2_TMSAR(0), REGS_V2_TMSAR(15)),
>   regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
>   /* Read only registers below */
>   regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
> --
> 2.17.1

RE: [EXT] Re: [PATCH v3] thermal: qoriq: add thermal monitor unit version 2 support

[Andy Tang]

Thanks Daniel for your help..

BR,
Andy

> -Original Message-
> From: Daniel Lezcano 
> Sent: 2019年10月11日 22:32
> To: Andy Tang ; edubez...@gmail.com;
> rui.zh...@intel.com; Anson Huang 
> Cc: Leo Li ; linux...@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: [EXT] Re: [PATCH v3] thermal: qoriq: add thermal monitor unit
> version 2 support
> 
> Caution: EXT Email
> 
> On 11/10/2019 04:05, Yuantian Tang wrote:
> > Thermal Monitor Unit v2 is introduced on new Layscape SoC.
> > Compared to v1, TMUv2 has a little different register layout and
> > digital output is fairly linear.
> >
> > Signed-off-by: Yuantian Tang 
> > Reviewed-by: Anson Huang 
> 
> Hi Yuantian,
> 
> I've applied the patch to the 'testing' branch [1]. If everything is fine, it 
> should
> be applied to thermal/next branch by Eduardo/Rui.
> 
> Thanks
> 
>   -- Daniel
> 
> [1]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.ker
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> 
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RE: [PATCH v2] thermal: qoriq: add thermal monitor unit version 2 support

[Andy Tang]

Hi Edubezval, Rui,

I had addressed Anson's comments and got his Reviewed-by.
Could you please merge it if you don't have other comments?

BR,
Andy

> -Original Message-
> From: Anson Huang
> Sent: 2019年9月24日 14:15
> To: Andy Tang ; edubez...@gmail.com;
> rui.zh...@intel.com
> Cc: daniel.lezc...@linaro.org; Leo Li ;
> linux...@vger.kernel.org; linux-kernel@vger.kernel.org; Andy Tang
> 
> Subject: RE: [PATCH v2] thermal: qoriq: add thermal monitor unit version 2
> support
> 
> 
> 
> > -Original Message-
> > From: Yuantian Tang 
> > Sent: Tuesday, September 24, 2019 11:17 AM
> > To: edubez...@gmail.com; rui.zh...@intel.com; Anson Huang
> > 
> > Cc: daniel.lezc...@linaro.org; Leo Li ; linux-
> > p...@vger.kernel.org; linux-kernel@vger.kernel.org; Andy Tang
> > 
> > Subject: [PATCH v2] thermal: qoriq: add thermal monitor unit version 2
> > support
> >
> > Thermal Monitor Unit v2 is introduced on new Layscape SoC.
> > Compared to v1, TMUv2 has a little different register layout and
> > digital output is fairly linear.
> >
> > Signed-off-by: Yuantian Tang 
> 
> Reviewed-by: Anson Huang 
> 
> > ---
> > v2:
> > - refine the code: remove redundant variable, rename variable etc.
> >
> >  drivers/thermal/qoriq_thermal.c | 121
> > +---
> >  1 file changed, 97 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/thermal/qoriq_thermal.c
> > b/drivers/thermal/qoriq_thermal.c index 7b364933bfb1..43617e53554b
> > 100644
> > --- a/drivers/thermal/qoriq_thermal.c
> > +++ b/drivers/thermal/qoriq_thermal.c
> > @@ -12,7 +12,16 @@
> >
> >  #include "thermal_core.h"
> >
> > -#define SITES_MAX  16
> > +#define SITES_MAX  16
> > +#define TMR_DISABLE0x0
> > +#define TMR_ME 0x8000
> > +#define TMR_ALPF   0x0c00
> > +#define TMR_ALPF_V20x0300
> > +#define TMTMIR_DEFAULT 0x000f
> > +#define TIER_DISABLE   0x0
> > +#define TEUMR0_V2  0x51009c00
> > +#define TMU_VER1   0x1
> > +#define TMU_VER2   0x2
> >
> >  /*
> >   * QorIQ TMU Registers
> > @@ -23,17 +32,55 @@ struct qoriq_tmu_site_regs {
> > u8 res0[0x8];
> >  };
> >
> > -struct qoriq_tmu_regs {
> > +struct qoriq_tmu_regs_v2 {
> > +   u32 tmr;/* Mode Register */
> > +   u32 tsr;/* Status Register */
> > +   u32 tmsr;   /* monitor site register */
> > +   u32 tmtmir; /* Temperature measurement interval
> > Register */
> > +   u8 res0[0x10];
> > +   u32 tier;   /* Interrupt Enable Register */
> > +   u32 tidr;   /* Interrupt Detect Register */
> > +   u8 res1[0x8];
> > +   u32 tiiscr; /* interrupt immediate site capture register
> > */
> > +   u32 tiascr; /* interrupt average site capture register */
> > +   u32 ticscr; /* Interrupt Critical Site Capture Register */
> > +   u32 res2;
> > +   u32 tmhtcr; /* monitor high temperature capture register
> > */
> > +   u32 tmltcr; /* monitor low temperature capture register
> > */
> > +   u32 tmrtrcr;/* monitor rising temperature rate capture register
> > */
> > +   u32 tmftrcr;/* monitor falling temperature rate capture register
> > */
> > +   u32 tmhtitr;/* High Temperature Immediate Threshold */
> > +   u32 tmhtatr;/* High Temperature Average Threshold */
> > +   u32 tmhtactr;   /* High Temperature Average Crit Threshold */
> > +   u32 res3;
> > +   u32 tmltitr;/* monitor low temperature immediate threshold */
> > +   u32 tmltatr;/* monitor low temperature average threshold
> > register */
> > +   u32 tmltactr;   /* monitor low temperature average critical
> > threshold */
> > +   u32 res4;
> > +   u32 tmrtrctr;   /* monitor rising temperature rate critical threshold
> > */
> > +   u32 tmftrctr;   /* monitor falling temperature rate critical
> > threshold*/
> > +   u8 res5[0x8];
> > +   u32 ttcfgr; /* Temperature Configuration Register */
> > +   u32 tscfgr; /* Sensor Configuration Register */
> > +   u8 res6[0x78];
> > +   struct qoriq_tmu_site_regs site[SITES_MAX];
> > +   u8 res7[0x9f8];
> > +   u32 ipbrr0; /* IP Block Revision Register 0 */
> > +   u32 ipbrr1; /* IP Block Revision Register 1 */
> > +   u8 res8[0x300];
> > + 

RE: [PATCH] thermal: qoriq: add thermal monitor unit version 2 support

[Andy Tang]

Hi Anson,

Points are taken. Will send out the next version.

Thanks,
Andy

> -Original Message-
> From: Anson Huang
> Sent: 2019年9月24日 10:11
> To: Andy Tang ; Zhang Rui ;
> edubez...@gmail.com
> Cc: daniel.lezc...@linaro.org; Leo Li ;
> linux...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: RE: [PATCH] thermal: qoriq: add thermal monitor unit version 2
> support
> 
> Hi, Andy
> 
> > Subject: RE: [PATCH] thermal: qoriq: add thermal monitor unit version
> > 2 support
> >
> > Hi Anson,
> >
> > Thanks for your review. Please see my reply inline.
> >
> > > -Original Message-----
> > > From: Anson Huang
> > > Sent: 2019年9月24日 9:17
> > > To: Zhang Rui ; Andy Tang ;
> > > edubez...@gmail.com
> > > Cc: daniel.lezc...@linaro.org; Leo Li ;
> > > linux...@vger.kernel.org; linux-kernel@vger.kernel.org
> > > Subject: RE: [PATCH] thermal: qoriq: add thermal monitor unit
> > > version
> > > 2 support
> > >
> > > Hi, Andy
> > >
> > >
> > > > On Mon, 2019-09-23 at 09:24 +, Andy Tang wrote:
> > > > > Hi Rui, Edubezval,
> > > > >
> > > > > Would you please review this patch?
> > > > >
> > > > CC Anson Huang.
> > > > I'd prefer all the qoriq thermal patches go through his review first.
> > > >
> > > > thanks,
> > > > rui
> > > >
> > > > > BR,
> > > > > Andy
> > > > >
> > > > > > -Original Message-
> > > > > > From: Andy Tang
> > > > > > Sent: 2019年8月29日 16:38
> > > > > > To: 'edubez...@gmail.com' ;
> > > > > > 'rui.zh...@intel.com'
> > > > > > 
> > > > > > Cc: 'daniel.lezc...@linaro.org' ;
> > > > > > Leo Li ; 'linux...@vger.kernel.org'
> > > > > > ; 'linux-kernel@vger.kernel.org'
> > > > > > 
> > > > > > Subject: RE: [PATCH] thermal: qoriq: add thermal monitor unit
> > > > > > version 2 support
> > > > > >
> > > > > > Hi Rui, Edubezval,
> > > > > >
> > > > > > Almost three monthes passed, I have not got your comments from
> > you.
> > > > > > Could you please take a look at this patch?
> > > > > >
> > > > > > BR,
> > > > > > Andy
> > > > > >
> > > > > > > -Original Message-
> > > > > > > From: Andy Tang
> > > > > > > Sent: 2019年8月6日 10:57
> > > > > > > To: edubez...@gmail.com; rui.zh...@intel.com
> > > > > > > Cc: daniel.lezc...@linaro.org; Leo Li ;
> > > > > > > linux...@vger.kernel.org; linux-kernel@vger.kernel.org
> > > > > > > Subject: RE: [PATCH] thermal: qoriq: add thermal monitor
> > > > > > > unit version
> > > > > > > 2 support
> > > > > > >
> > > > > > > Any comments?
> > > > > > >
> > > > > > > BR,
> > > > > > > Andy
> > > > > > >
> > > > > > > > -Original Message-
> > > > > > > > From: Yuantian Tang 
> > > > > > > > Sent: 2019年6月4日 10:51
> > > > > > > > To: edubez...@gmail.com; rui.zh...@intel.com
> > > > > > > > Cc: daniel.lezc...@linaro.org; Leo Li
> > > > > > > > ; linux...@vger.kernel.org;
> > > > > > > > linux-kernel@vger.kernel.org; Andy Tang
> > > > > > > > 
> > > > > > > > Subject: [PATCH] thermal: qoriq: add thermal monitor unit
> > > > > > > > version 2 support
> > > > > > > >
> > > > > > > > Thermal Monitor Unit v2 is introduced on new Layscape SoC.
> > > > > > > > Compared to v1, TMUv2 has a little different register
> > > > > > > > layout and digital output is fairly linear.
> > > > > > > >
> > > > > > > > Signed-off-by: Yuantian Tang 
> > > > > > > > ---
> > > > > > > >  drivers/thermal/qoriq_thermal.c | 122
> > > > > > > > +---
> > > > > > > >  1 file changed, 98 ins

RE: [PATCH] thermal: qoriq: add thermal monitor unit version 2 support

[Andy Tang]

Hi Anson,

Thanks for your review. Please see my reply inline.

> -Original Message-
> From: Anson Huang
> Sent: 2019年9月24日 9:17
> To: Zhang Rui ; Andy Tang ;
> edubez...@gmail.com
> Cc: daniel.lezc...@linaro.org; Leo Li ;
> linux...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: RE: [PATCH] thermal: qoriq: add thermal monitor unit version 2
> support
> 
> Hi, Andy
> 
> 
> > On Mon, 2019-09-23 at 09:24 +, Andy Tang wrote:
> > > Hi Rui, Edubezval,
> > >
> > > Would you please review this patch?
> > >
> > CC Anson Huang.
> > I'd prefer all the qoriq thermal patches go through his review first.
> >
> > thanks,
> > rui
> >
> > > BR,
> > > Andy
> > >
> > > > -Original Message-
> > > > From: Andy Tang
> > > > Sent: 2019年8月29日 16:38
> > > > To: 'edubez...@gmail.com' ;
> > > > 'rui.zh...@intel.com'
> > > > 
> > > > Cc: 'daniel.lezc...@linaro.org' ; Leo
> > > > Li ; 'linux...@vger.kernel.org'
> > > > ; 'linux-kernel@vger.kernel.org'
> > > > 
> > > > Subject: RE: [PATCH] thermal: qoriq: add thermal monitor unit
> > > > version 2 support
> > > >
> > > > Hi Rui, Edubezval,
> > > >
> > > > Almost three monthes passed, I have not got your comments from you.
> > > > Could you please take a look at this patch?
> > > >
> > > > BR,
> > > > Andy
> > > >
> > > > > -Original Message-
> > > > > From: Andy Tang
> > > > > Sent: 2019年8月6日 10:57
> > > > > To: edubez...@gmail.com; rui.zh...@intel.com
> > > > > Cc: daniel.lezc...@linaro.org; Leo Li ;
> > > > > linux...@vger.kernel.org; linux-kernel@vger.kernel.org
> > > > > Subject: RE: [PATCH] thermal: qoriq: add thermal monitor unit
> > > > > version
> > > > > 2 support
> > > > >
> > > > > Any comments?
> > > > >
> > > > > BR,
> > > > > Andy
> > > > >
> > > > > > -Original Message-
> > > > > > From: Yuantian Tang 
> > > > > > Sent: 2019年6月4日 10:51
> > > > > > To: edubez...@gmail.com; rui.zh...@intel.com
> > > > > > Cc: daniel.lezc...@linaro.org; Leo Li ;
> > > > > > linux...@vger.kernel.org; linux-kernel@vger.kernel.org; Andy
> > > > > > Tang 
> > > > > > Subject: [PATCH] thermal: qoriq: add thermal monitor unit
> > > > > > version 2 support
> > > > > >
> > > > > > Thermal Monitor Unit v2 is introduced on new Layscape SoC.
> > > > > > Compared to v1, TMUv2 has a little different register layout
> > > > > > and digital output is fairly linear.
> > > > > >
> > > > > > Signed-off-by: Yuantian Tang 
> > > > > > ---
> > > > > >  drivers/thermal/qoriq_thermal.c | 122
> > > > > > +---
> > > > > >  1 file changed, 98 insertions(+), 24 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/thermal/qoriq_thermal.c
> > > > > > b/drivers/thermal/qoriq_thermal.c index
> > > > > > 3b5f5b3fb1bc..0df6dfddf804
> > > > > > 100644
> > > > > > --- a/drivers/thermal/qoriq_thermal.c
> > > > > > +++ b/drivers/thermal/qoriq_thermal.c
> > > > > > @@ -13,6 +13,15 @@
> > > > > >  #include "thermal_core.h"
> > > > > >
> > > > > >  #define SITES_MAX  16
> > > > > > +#define TMR_DISABLE0x0
> > > > > > +#define TMR_ME 0x8000
> > > > > > +#define TMR_ALPF   0x0c00
> > > > > > +#define TMR_ALPF_V20x0300
> > > > > > +#define TMTMIR_DEFAULT 0x000f
> > > > > > +#define TIER_DISABLE   0x0
> > > > > > +#define TEUMR0_V2  0x51009C00
> 
> Better to use either lower case or capital letter for all macro definitions,
> some are lower case and some are capital letter look like NOT aligned.
I always use capital letter to define a macro. 
Did I use lower letter somewhere?

> 
> > > > > > +#define TMU_VER1   0x1
> > > > > > +#define TMU_VER2   0x2
> > > > > >
>

RE: [PATCH] thermal: qoriq: add thermal monitor unit version 2 support

[Andy Tang]

Hi Rui, Edubezval,

Would you please review this patch?

BR,
Andy

> -Original Message-
> From: Andy Tang
> Sent: 2019年8月29日 16:38
> To: 'edubez...@gmail.com' ; 'rui.zh...@intel.com'
> 
> Cc: 'daniel.lezc...@linaro.org' ; Leo Li
> ; 'linux...@vger.kernel.org'
> ; 'linux-kernel@vger.kernel.org'
> 
> Subject: RE: [PATCH] thermal: qoriq: add thermal monitor unit version 2
> support
> 
> Hi Rui, Edubezval,
> 
> Almost three monthes passed, I have not got your comments from you.
> Could you please take a look at this patch?
> 
> BR,
> Andy
> 
> > -Original Message-
> > From: Andy Tang
> > Sent: 2019年8月6日 10:57
> > To: edubez...@gmail.com; rui.zh...@intel.com
> > Cc: daniel.lezc...@linaro.org; Leo Li ;
> > linux...@vger.kernel.org; linux-kernel@vger.kernel.org
> > Subject: RE: [PATCH] thermal: qoriq: add thermal monitor unit version
> > 2 support
> >
> > Any comments?
> >
> > BR,
> > Andy
> >
> > > -Original Message-
> > > From: Yuantian Tang 
> > > Sent: 2019年6月4日 10:51
> > > To: edubez...@gmail.com; rui.zh...@intel.com
> > > Cc: daniel.lezc...@linaro.org; Leo Li ;
> > > linux...@vger.kernel.org; linux-kernel@vger.kernel.org; Andy Tang
> > > 
> > > Subject: [PATCH] thermal: qoriq: add thermal monitor unit version 2
> > > support
> > >
> > > Thermal Monitor Unit v2 is introduced on new Layscape SoC.
> > > Compared to v1, TMUv2 has a little different register layout and
> > > digital output is fairly linear.
> > >
> > > Signed-off-by: Yuantian Tang 
> > > ---
> > >  drivers/thermal/qoriq_thermal.c | 122
> > > +---
> > >  1 file changed, 98 insertions(+), 24 deletions(-)
> > >
> > > diff --git a/drivers/thermal/qoriq_thermal.c
> > > b/drivers/thermal/qoriq_thermal.c index 3b5f5b3fb1bc..0df6dfddf804
> > > 100644
> > > --- a/drivers/thermal/qoriq_thermal.c
> > > +++ b/drivers/thermal/qoriq_thermal.c
> > > @@ -13,6 +13,15 @@
> > >  #include "thermal_core.h"
> > >
> > >  #define SITES_MAX16
> > > +#define TMR_DISABLE  0x0
> > > +#define TMR_ME   0x8000
> > > +#define TMR_ALPF 0x0c00
> > > +#define TMR_ALPF_V2  0x0300
> > > +#define TMTMIR_DEFAULT   0x000f
> > > +#define TIER_DISABLE 0x0
> > > +#define TEUMR0_V20x51009C00
> > > +#define TMU_VER1 0x1
> > > +#define TMU_VER2 0x2
> > >
> > >  /*
> > >   * QorIQ TMU Registers
> > > @@ -23,17 +32,55 @@ struct qoriq_tmu_site_regs {
> > >   u8 res0[0x8];
> > >  };
> > >
> > > -struct qoriq_tmu_regs {
> > > +struct qoriq_tmu_regs_v2 {
> > > + u32 tmr;/* Mode Register */
> > > + u32 tsr;/* Status Register */
> > > + u32 tmsr;   /* monitor site register */
> > > + u32 tmtmir; /* Temperature measurement interval Register
> */
> > > + u8 res0[0x10];
> > > + u32 tier;   /* Interrupt Enable Register */
> > > + u32 tidr;   /* Interrupt Detect Register */
> > > + u8 res1[0x8];
> > > + u32 tiiscr; /* interrupt immediate site capture register */
> > > + u32 tiascr; /* interrupt average site capture register */
> > > + u32 ticscr; /* Interrupt Critical Site Capture Register */
> > > + u32 res2;
> > > + u32 tmhtcr; /* monitor high temperature capture register */
> > > + u32 tmltcr; /* monitor low temperature capture register */
> > > + u32 tmrtrcr;/* monitor rising temperature rate capture register
> */
> > > + u32 tmftrcr;/* monitor falling temperature rate capture register
> */
> > > + u32 tmhtitr;/* High Temperature Immediate Threshold */
> > > + u32 tmhtatr;/* High Temperature Average Threshold */
> > > + u32 tmhtactr;   /* High Temperature Average Crit Threshold */
> > > + u32 res3;
> > > + u32 tmltitr;/* monitor low temperature immediate threshold */
> > > + u32 tmltatr;/* monitor low temperature average threshold
> register */
> > > + u32 tmltactr;   /* monitor low temperature average critical
> threshold */
> > > + u32 res4;
> > > + u32 tmrtrctr;   /* monitor rising temperature rate critical threshold
> */
> > > + u32 tmftrctr;   /* monitor falling temperature rate critical
> threshold*/
> 

RE: [PATCH] thermal: qoriq: add thermal monitor unit version 2 support

[Andy Tang]

Hi Rui, Edubezval,

Almost three monthes passed, I have not got your comments from you.
Could you please take a look at this patch?

BR,
Andy

> -Original Message-
> From: Andy Tang
> Sent: 2019年8月6日 10:57
> To: edubez...@gmail.com; rui.zh...@intel.com
> Cc: daniel.lezc...@linaro.org; Leo Li ;
> linux...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: RE: [PATCH] thermal: qoriq: add thermal monitor unit version 2
> support
> 
> Any comments?
> 
> BR,
> Andy
> 
> > -Original Message-
> > From: Yuantian Tang 
> > Sent: 2019年6月4日 10:51
> > To: edubez...@gmail.com; rui.zh...@intel.com
> > Cc: daniel.lezc...@linaro.org; Leo Li ;
> > linux...@vger.kernel.org; linux-kernel@vger.kernel.org; Andy Tang
> > 
> > Subject: [PATCH] thermal: qoriq: add thermal monitor unit version 2
> > support
> >
> > Thermal Monitor Unit v2 is introduced on new Layscape SoC.
> > Compared to v1, TMUv2 has a little different register layout and
> > digital output is fairly linear.
> >
> > Signed-off-by: Yuantian Tang 
> > ---
> >  drivers/thermal/qoriq_thermal.c | 122
> > +---
> >  1 file changed, 98 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/thermal/qoriq_thermal.c
> > b/drivers/thermal/qoriq_thermal.c index 3b5f5b3fb1bc..0df6dfddf804
> > 100644
> > --- a/drivers/thermal/qoriq_thermal.c
> > +++ b/drivers/thermal/qoriq_thermal.c
> > @@ -13,6 +13,15 @@
> >  #include "thermal_core.h"
> >
> >  #define SITES_MAX  16
> > +#define TMR_DISABLE0x0
> > +#define TMR_ME 0x8000
> > +#define TMR_ALPF   0x0c00
> > +#define TMR_ALPF_V20x0300
> > +#define TMTMIR_DEFAULT 0x000f
> > +#define TIER_DISABLE   0x0
> > +#define TEUMR0_V2  0x51009C00
> > +#define TMU_VER1   0x1
> > +#define TMU_VER2   0x2
> >
> >  /*
> >   * QorIQ TMU Registers
> > @@ -23,17 +32,55 @@ struct qoriq_tmu_site_regs {
> > u8 res0[0x8];
> >  };
> >
> > -struct qoriq_tmu_regs {
> > +struct qoriq_tmu_regs_v2 {
> > +   u32 tmr;/* Mode Register */
> > +   u32 tsr;/* Status Register */
> > +   u32 tmsr;   /* monitor site register */
> > +   u32 tmtmir; /* Temperature measurement interval Register */
> > +   u8 res0[0x10];
> > +   u32 tier;   /* Interrupt Enable Register */
> > +   u32 tidr;   /* Interrupt Detect Register */
> > +   u8 res1[0x8];
> > +   u32 tiiscr; /* interrupt immediate site capture register */
> > +   u32 tiascr; /* interrupt average site capture register */
> > +   u32 ticscr; /* Interrupt Critical Site Capture Register */
> > +   u32 res2;
> > +   u32 tmhtcr; /* monitor high temperature capture register */
> > +   u32 tmltcr; /* monitor low temperature capture register */
> > +   u32 tmrtrcr;/* monitor rising temperature rate capture register */
> > +   u32 tmftrcr;/* monitor falling temperature rate capture register */
> > +   u32 tmhtitr;/* High Temperature Immediate Threshold */
> > +   u32 tmhtatr;/* High Temperature Average Threshold */
> > +   u32 tmhtactr;   /* High Temperature Average Crit Threshold */
> > +   u32 res3;
> > +   u32 tmltitr;/* monitor low temperature immediate threshold */
> > +   u32 tmltatr;/* monitor low temperature average threshold register */
> > +   u32 tmltactr;   /* monitor low temperature average critical threshold */
> > +   u32 res4;
> > +   u32 tmrtrctr;   /* monitor rising temperature rate critical threshold */
> > +   u32 tmftrctr;   /* monitor falling temperature rate critical threshold*/
> > +   u8 res5[0x8];
> > +   u32 ttcfgr; /* Temperature Configuration Register */
> > +   u32 tscfgr; /* Sensor Configuration Register */
> > +   u8 res6[0x78];
> > +   struct qoriq_tmu_site_regs site[SITES_MAX];
> > +   u8 res7[0x9f8];
> > +   u32 ipbrr0; /* IP Block Revision Register 0 */
> > +   u32 ipbrr1; /* IP Block Revision Register 1 */
> > +   u8 res8[0x300];
> > +   u32 teumr0;
> > +   u32 teumr1;
> > +   u32 teumr2;
> > +   u32 res9;
> > +   u32 ttrcr[4];   /* Temperature Range Control Register */
> > +};
> > +
> > +struct qoriq_tmu_regs_v1 {
> > u32 tmr;/* Mode Register */
> > -#define TMR_DISABLE0x0
> > -#define TMR_ME 0x8000
> > -#define TMR_ALPF   0x0c00
> &

RE: [PATCH v3] arm64: dts: ls1028a: Add temperature sensor node

[Andy Tang]

Please ignore this email. Sorry for sending the wrong patch.

BR,
Andy



> -Original Message-
> From: Yuantian Tang 
> Sent: 2019年8月6日 13:30
> To: shawn...@kernel.org
> Cc: Leo Li ; robh...@kernel.org;
> mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Andy Tang
> 
> Subject: [PATCH v3] arm64: dts: ls1028a: Add temperature sensor node
> 
> Add nxp sa56004 chip node for temperature monitor.
> 
> Signed-off-by: Yuantian Tang 
> ---
> v3:
>   - sort the node in i2c address
> v2:
>   - change the node name and add vcc-supply
>  arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts |   15
> +++
>  arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts |   15
> +++
>  2 files changed, 30 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> index b359068..960daf2 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> @@ -47,6 +47,15 @@
>   regulator-always-on;
>   };
> 
> + sb_3v3: regulator-sb3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "3v3_vbus";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
>   sound {
>   compatible = "simple-audio-card";
>   simple-audio-card,format = "i2s";
> @@ -117,6 +126,12 @@
>   #size-cells = <0>;
>   reg = <0x3>;
> 
> + temperature-sensor@4c {
> + compatible = "nxp,sa56004";
> + reg = <0x4c>;
> + vcc-supply = <_3v3>;
> + };
> +
>   rtc@51 {
>   compatible = "nxp,pcf2129";
>   reg = <0x51>;
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> index f9c272f..6a22423 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> @@ -43,6 +43,15 @@
>   regulator-always-on;
>   };
> 
> + sb_3v3: regulator-sb3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "3v3_vbus";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
>   sound {
>   compatible = "simple-audio-card";
>   simple-audio-card,format = "i2s";
> @@ -115,6 +124,12 @@
>   #size-cells = <0>;
>   reg = <0x3>;
> 
> + temperature-sensor@4c {
> + compatible = "nxp,sa56004";
> + reg = <0x4c>;
> + vcc-supply = <_3v3>;
> + };
> +
>   rtc@51 {
>   compatible = "nxp,pcf2129";
>   reg = <0x51>;
> --
> 1.7.1

RE: [PATCH] thermal: qoriq: add thermal monitor unit version 2 support

[Andy Tang]

Any comments?

BR,
Andy

> -Original Message-
> From: Yuantian Tang 
> Sent: 2019年6月4日 10:51
> To: edubez...@gmail.com; rui.zh...@intel.com
> Cc: daniel.lezc...@linaro.org; Leo Li ;
> linux...@vger.kernel.org; linux-kernel@vger.kernel.org; Andy Tang
> 
> Subject: [PATCH] thermal: qoriq: add thermal monitor unit version 2 support
> 
> Thermal Monitor Unit v2 is introduced on new Layscape SoC.
> Compared to v1, TMUv2 has a little different register layout and digital
> output is fairly linear.
> 
> Signed-off-by: Yuantian Tang 
> ---
>  drivers/thermal/qoriq_thermal.c | 122 +---
>  1 file changed, 98 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/thermal/qoriq_thermal.c
> b/drivers/thermal/qoriq_thermal.c index 3b5f5b3fb1bc..0df6dfddf804 100644
> --- a/drivers/thermal/qoriq_thermal.c
> +++ b/drivers/thermal/qoriq_thermal.c
> @@ -13,6 +13,15 @@
>  #include "thermal_core.h"
> 
>  #define SITES_MAX16
> +#define TMR_DISABLE  0x0
> +#define TMR_ME   0x8000
> +#define TMR_ALPF 0x0c00
> +#define TMR_ALPF_V2  0x0300
> +#define TMTMIR_DEFAULT   0x000f
> +#define TIER_DISABLE 0x0
> +#define TEUMR0_V20x51009C00
> +#define TMU_VER1 0x1
> +#define TMU_VER2 0x2
> 
>  /*
>   * QorIQ TMU Registers
> @@ -23,17 +32,55 @@ struct qoriq_tmu_site_regs {
>   u8 res0[0x8];
>  };
> 
> -struct qoriq_tmu_regs {
> +struct qoriq_tmu_regs_v2 {
> + u32 tmr;/* Mode Register */
> + u32 tsr;/* Status Register */
> + u32 tmsr;   /* monitor site register */
> + u32 tmtmir; /* Temperature measurement interval Register */
> + u8 res0[0x10];
> + u32 tier;   /* Interrupt Enable Register */
> + u32 tidr;   /* Interrupt Detect Register */
> + u8 res1[0x8];
> + u32 tiiscr; /* interrupt immediate site capture register */
> + u32 tiascr; /* interrupt average site capture register */
> + u32 ticscr; /* Interrupt Critical Site Capture Register */
> + u32 res2;
> + u32 tmhtcr; /* monitor high temperature capture register */
> + u32 tmltcr; /* monitor low temperature capture register */
> + u32 tmrtrcr;/* monitor rising temperature rate capture register */
> + u32 tmftrcr;/* monitor falling temperature rate capture register */
> + u32 tmhtitr;/* High Temperature Immediate Threshold */
> + u32 tmhtatr;/* High Temperature Average Threshold */
> + u32 tmhtactr;   /* High Temperature Average Crit Threshold */
> + u32 res3;
> + u32 tmltitr;/* monitor low temperature immediate threshold */
> + u32 tmltatr;/* monitor low temperature average threshold register */
> + u32 tmltactr;   /* monitor low temperature average critical threshold */
> + u32 res4;
> + u32 tmrtrctr;   /* monitor rising temperature rate critical threshold */
> + u32 tmftrctr;   /* monitor falling temperature rate critical threshold*/
> + u8 res5[0x8];
> + u32 ttcfgr; /* Temperature Configuration Register */
> + u32 tscfgr; /* Sensor Configuration Register */
> + u8 res6[0x78];
> + struct qoriq_tmu_site_regs site[SITES_MAX];
> + u8 res7[0x9f8];
> + u32 ipbrr0; /* IP Block Revision Register 0 */
> + u32 ipbrr1; /* IP Block Revision Register 1 */
> + u8 res8[0x300];
> + u32 teumr0;
> + u32 teumr1;
> + u32 teumr2;
> + u32 res9;
> + u32 ttrcr[4];   /* Temperature Range Control Register */
> +};
> +
> +struct qoriq_tmu_regs_v1 {
>   u32 tmr;/* Mode Register */
> -#define TMR_DISABLE  0x0
> -#define TMR_ME   0x8000
> -#define TMR_ALPF 0x0c00
>   u32 tsr;/* Status Register */
>   u32 tmtmir; /* Temperature measurement interval Register */
> -#define TMTMIR_DEFAULT   0x000f
>   u8 res0[0x14];
>   u32 tier;   /* Interrupt Enable Register */
> -#define TIER_DISABLE 0x0
>   u32 tidr;   /* Interrupt Detect Register */
>   u32 tiscr;  /* Interrupt Site Capture Register */
>   u32 ticscr; /* Interrupt Critical Site Capture Register */
> @@ -53,10 +100,7 @@ struct qoriq_tmu_regs {
>   u32 ipbrr0; /* IP Block Revision Register 0 */
>   u32 ipbrr1; /* IP Block Revision Register 1 */
>   u8 res6[0x310];
> - u32 ttr0cr; /* Temperature Range 0 Control Register */
> - u32 ttr1cr; /* Temperature Range 1 Control R

RE: [EXT] Re: [PATCH] dt-bindings: thermal: Make cooling-maps property optional

[Andy Tang]

Hi Edubezval, Rui,

Are you going to pick up this patch?

BR,
Andy

> -Original Message-
> From: Daniel Lezcano 
> Sent: 2019年6月4日 14:04
> To: Andy Tang ; rui.zh...@intel.com;
> edubez...@gmail.com
> Cc: robh...@kernel.org; mark.rutl...@arm.com; linux...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [EXT] Re: [PATCH] dt-bindings: thermal: Make cooling-maps property
> optional
> 
> Caution: EXT Email
> 
> On 04/06/2019 07:56, Andy Tang wrote:
> > Hi Edubezval, Rui,
> >
> > Any further comments?
> 
> From my POV, this patch makes sense. We may be interested to show up the
> thermal zones in sysfs and optionally mitigate them via an userspace
> governor.
> 
> Acked-by: Daniel Lezcano 
> 
> >> -Original Message-
> >> From: Yuantian Tang 
> >> Sent: 2019年5月15日 17:37
> >> To: rui.zh...@intel.com; edubez...@gmail.com
> >> Cc: robh...@kernel.org; daniel.lezc...@linaro.org;
> >> mark.rutl...@arm.com; linux...@vger.kernel.org;
> >> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Andy Tang
> >> 
> >> Subject: [PATCH] dt-bindings: thermal: Make cooling-maps property
> >> optional
> >>
> >> There may be no cooling device on system, or there are no enough
> >> cooling devices for each thermal zone in multiple thermal zone cases
> >> since cooling devices can't be shared.
> >> So make this property optional to remove such limitations.
> >>
> >> Signed-off-by: Yuantian Tang 
> >> ---
> >>  .../devicetree/bindings/thermal/thermal.txt|4 ++--
> >>  1 files changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/thermal/thermal.txt
> >> b/Documentation/devicetree/bindings/thermal/thermal.txt
> >> index ca14ba9..694e834 100644
> >> --- a/Documentation/devicetree/bindings/thermal/thermal.txt
> >> +++ b/Documentation/devicetree/bindings/thermal/thermal.txt
> >> @@ -142,11 +142,11 @@ Required properties:
> >>  - trips:A sub-node which is a container of only trip point
> nodes
> >>Type: sub-noderequired to describe the thermal zone.
> >>
> >> +
> >> +Optional property:
> >>  - cooling-maps: A sub-node which is a container of only
> cooling device
> >>Type: sub-nodemap nodes, used to describe the relation
> between
> >> trips
> >>  and cooling devices.
> >> -
> >> -Optional property:
> >>  - coefficients: An array of integers (one signed cell)
> containing
> >>Type: array   coefficients to compose a linear relation
> between
> >>Elem size: one cell   the sensors listed in the thermal-sensors
> property.
> >> --
> >> 1.7.1
> >
> 
> 
> --
> 
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RE: [PATCH v4] clk: qoriq: add support for lx2160a

[Andy Tang]

Hi Stephen, Mturquette,

Who will apply this patch? https://patchwork.kernel.org/patch/10918407/
All the comments are addressed and got acked by:
Acked-by: Scott Wood 
Acked-by: Stephen Boyd 
Acked-by: Viresh Kumar 

Could you please apply it?

BR,
Andy


> -Original Message-
> From: Vabhav Sharma
> Sent: 2019年5月23日 22:05
> To: linux-kernel@vger.kernel.org; linux-...@vger.kernel.org;
> mturque...@baylibre.com; sb...@kernel.org
> Cc: mturque...@baylibre.com; sb...@kernel.org; Andy Tang
> ; Yogesh Narayan Gaur
> 
> Subject: RE: [PATCH v4] clk: qoriq: add support for lx2160a
> 
> > -Original Message-
> > From: Vabhav Sharma
> > Sent: Tuesday, May 21, 2019 11:14 AM
> > To: linux-kernel@vger.kernel.org; linux-...@vger.kernel.org;
> > sb...@kernel.org
> > Cc: mturque...@baylibre.com; Andy Tang ; Yogesh
> > Narayan Gaur 
> > Subject: RE: [PATCH v4] clk: qoriq: add support for lx2160a
> >
> > Hello Stephen,
> > I have incorporated review comments from
> > https://patchwork.kernel.org/patch/10917171/
> Hello Maintainers,
> All the comments are addressed, Can you please take the patch?
> Please see this is essential for new hardware support.
> 
> Regards,
> Vabhav
> >
> > A gentle reminder to apply the patch
> > https://patchwork.kernel.org/patch/10918407/.
> >
> > Regards,
> > Vabhav
> >
> > > -Original Message-
> > > From: Vabhav Sharma 
> > > Sent: Friday, April 26, 2019 12:24 PM
> > > To: linux-kernel@vger.kernel.org; linux-...@vger.kernel.org
> > > Cc: sb...@kernel.org; mturque...@baylibre.com; Vabhav Sharma
> > > ; Andy Tang ; Yogesh
> > Narayan
> > > Gaur 
> > > Subject: [PATCH v4] clk: qoriq: add support for lx2160a
> > >
> > > Add clockgen support and configuration for NXP SoC lx2160a with
> > > compatible property as "fsl,lx2160a-clockgen".
> > >
> > > Signed-off-by: Tang Yuantian 
> > > Signed-off-by: Yogesh Gaur 
> > > Signed-off-by: Vabhav Sharma 
> > > Acked-by: Scott Wood 
> > > Acked-by: Stephen Boyd 
> > > Acked-by: Viresh Kumar 
> > > ---
> > > Changes for v4:
> > > - Incorporated review comments from Stephen Boyd
> > >
> > > Changes for v3:
> > > - Incorporated review comments of Rafael J. Wysocki
> > > - Updated commit message
> > >
> > > Changes for v2:
> > > - Subject line updated
> > >
> > >  drivers/clk/clk-qoriq.c | 12 
> > >  1 file changed, 12 insertions(+)
> > >
> > > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> > > 3d51d7c..1a15201 100644
> > > --- a/drivers/clk/clk-qoriq.c
> > > +++ b/drivers/clk/clk-qoriq.c
> > > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] =
> {
> > >   .flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > >   },
> > >   {
> > > + .compat = "fsl,lx2160a-clockgen",
> > > + .cmux_groups = {
> > > + _cmux_cga12, _cmux_cgb
> > > + },
> > > + .cmux_to_group = {
> > > + 0, 0, 0, 0, 1, 1, 1, 1, -1
> > > + },
> > > + .pll_mask = 0x37,
> > > + .flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > + },
> > > + {
> > >   .compat = "fsl,p2041-clockgen",
> > >   .guts_compat = "fsl,qoriq-device-config-1.0",
> > >   .init_periph = p2041_init_periph, @@ -1427,6 +1438,7 @@
> > > CLK_OF_DECLARE(qoriq_clockgen_ls1043a,
> > > "fsl,ls1043a-clockgen", clockgen_init);
> > > CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen",
> > > clockgen_init);  CLK_OF_DECLARE(qoriq_clockgen_ls1088a,
> > > "fsl,ls1088a- clockgen", clockgen_init);
> > > CLK_OF_DECLARE(qoriq_clockgen_ls2080a,
> > > "fsl,ls2080a-clockgen", clockgen_init);
> > > +CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen",
> > > +clockgen_init);
> > >  CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen",
> > > clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_p3041,
> > > "fsl,p3041-clockgen", clockgen_init);
> > > CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen",
> > > clockgen_init);
> > > --
> > > 2.7.4

RE: [PATCH] dt-bindings: thermal: Make cooling-maps property optional

[Andy Tang]

Hi Edubezval, Rui,

Any further comments?

BR,
Andy

> -Original Message-
> From: Yuantian Tang 
> Sent: 2019年5月15日 17:37
> To: rui.zh...@intel.com; edubez...@gmail.com
> Cc: robh...@kernel.org; daniel.lezc...@linaro.org; mark.rutl...@arm.com;
> linux...@vger.kernel.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Andy Tang 
> Subject: [PATCH] dt-bindings: thermal: Make cooling-maps property optional
> 
> There may be no cooling device on system, or there are no enough cooling
> devices for each thermal zone in multiple thermal zone cases since cooling
> devices can't be shared.
> So make this property optional to remove such limitations.
> 
> Signed-off-by: Yuantian Tang 
> ---
>  .../devicetree/bindings/thermal/thermal.txt|4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/thermal/thermal.txt
> b/Documentation/devicetree/bindings/thermal/thermal.txt
> index ca14ba9..694e834 100644
> --- a/Documentation/devicetree/bindings/thermal/thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/thermal.txt
> @@ -142,11 +142,11 @@ Required properties:
>  - trips: A sub-node which is a container of only trip point nodes
>Type: sub-node required to describe the thermal zone.
> 
> +
> +Optional property:
>  - cooling-maps:  A sub-node which is a container of only cooling 
> device
>Type: sub-node map nodes, used to describe the relation between
> trips
>   and cooling devices.
> -
> -Optional property:
>  - coefficients:  An array of integers (one signed cell) 
> containing
>Type: arraycoefficients to compose a linear relation 
> between
>Elem size: one cellthe sensors listed in the thermal-sensors 
> property.
> --
> 1.7.1

RE: [EXT] Re: [PATCH] arm64: dts: ls1028a: Add Thermal Monitor Unit node

[Andy Tang]

> -Original Message-
> From: Eduardo Valentin 
> Sent: 2019年5月29日 10:54
> To: Andy Tang 
> Cc: shawn...@kernel.org; Leo Li ;
> robh...@kernel.org; mark.rutl...@arm.com;
> linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux...@vger.kernel.org;
> daniel.lezc...@linaro.org; rui.zh...@intel.com
> Subject: [EXT] Re: [PATCH] arm64: dts: ls1028a: Add Thermal Monitor Unit
> node
> 
> Caution: EXT Email
> 
> On Thu, Apr 25, 2019 at 04:26:40PM +0800, Yuantian Tang wrote:
> > The Thermal Monitoring Unit (TMU) monitors and reports the temperature
> > from 2 remote temperature measurement sites located on ls1028a chip.
> > Add TMU dts node to enable this feature.
> >
> > Signed-off-by: Yuantian Tang 
> 
> I dont see anything wrong from a thermal standpoint.
> 
> Acked-by: Eduardo Valentin 
> 
> Please get this via your arch tree maintainer to avoid merge conflicts.
Thanks for your review. 
The only concern for arch tree maintainer is that "cooling-maps" is a required 
property.
So I have to add cooling-maps for each zone. 
Since there are two thermal zones but only one cooling device, which is 
cpufreq, I have to
use CPUFREQ as cooling device twice which may cause cooling decision conflict.
The case will get worse when we have 7 thermal zones.
This makes me think "maybe we need to change cooling-maps to an optional 
property".
In this way, we can put the cooling devices to specific thermal zones and leave 
the zones without
Cooling devices to do the default action which is reset or poweroff soc.
What's your opinion about this?

BR,
Andy

> 
> > ---
> >  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi |  114
> > 
> >  1 files changed, 114 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index b045812..a25f5fc 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -29,6 +29,7 @@
> >   clocks = < 1 0>;
> >   next-level-cache = <>;
> >   cpu-idle-states = <_PH20>;
> > + #cooling-cells = <2>;
> >   };
> >
> >   cpu1: cpu@1 {
> > @@ -39,6 +40,7 @@
> >   clocks = < 1 0>;
> >   next-level-cache = <>;
> >   cpu-idle-states = <_PH20>;
> > + #cooling-cells = <2>;
> >   };
> >
> >   l2: l2-cache {
> > @@ -398,6 +400,118 @@
> >   status = "disabled";
> >   };
> >
> > + tmu: tmu@1f0 {
> > + compatible = "fsl,qoriq-tmu";
> > + reg = <0x0 0x1f8 0x0 0x1>;
> > + interrupts = <0 23 0x4>;
> > + fsl,tmu-range = <0xb 0xa0026 0x80048
> 0x70061>;
> > + fsl,tmu-calibration = <0x 0x0024
> > +0x0001
> 0x002b
> > +0x0002
> 0x0031
> > +0x0003
> 0x0038
> > +0x0004
> 0x003f
> > +0x0005
> 0x0045
> > +0x0006
> 0x004c
> > +0x0007
> 0x0053
> > +0x0008
> 0x0059
> > +0x0009
> 0x0060
> > +0x000a
> 0x0066
> > +0x000b
> 0x006d
> > +
> > +0x0001
> 0x001c
> > +0x00010001
> 0x0024
> > +0x00010002
> 0x002c
> > +0x00010003
> 0x0035
> > +0x00010004
> 0x003d
> > +0x00010005
> 0x0045
> > +0x00010006
> 0x00

RE: [EXT] Re: [PATCH] arm64: dts: ls1028a: Add temperature sensor node

[Andy Tang]

Hi Leo,

> -Original Message-
> From: Li Yang 
> Sent: 2019年5月25日 6:32
> To: Andy Tang 
> Cc: Shawn Guo ; Rob Herring ;
> Mark Rutland ; moderated list:ARM/FREESCALE
> IMX / MXC ARM ARCHITECTURE ;
> open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> ; lkml 
> Subject: [EXT] Re: [PATCH] arm64: dts: ls1028a: Add temperature sensor
> node
> 
> Caution: EXT Email
> 
> On Thu, May 23, 2019 at 8:30 PM Yuantian Tang 
> wrote:
> >
> > Add nxp sa56004 chip node for temperature monitor.
> >
> > Signed-off-by: Yuantian Tang 
> > ---
> >  arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 5 +
> > arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 5 +
> >  2 files changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > index b359068d9605..31fd626dd344 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > @@ -131,6 +131,11 @@
> > compatible = "atmel,24c512";
> > reg = <0x57>;
> > };
> > +
> > +   temp@4c {
> 
> The recommended name for temperature senor in dts spec is
> temperature-sensor.
I didn't find the spec for this recommendation. Could you please provide the 
link?
I like to update it to temp-sensor though.

> 
> > +   compatible = "nxp,sa56004";
> 
> The binding says the following property is required.  If it is not the case,
> probably we should update the binding.
> - vcc-supply: vcc regulator for the supply voltage.
I will add the vcc-supply to comply this requirement.

Thanks,
Andy
> 
> > +   reg = <0x4c>;
> > +   };
> > };
> >
> > i2c@5 {
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > index f9c272fb0738..012b3f8696b7 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > @@ -119,6 +119,11 @@
> > compatible = "nxp,pcf2129";
> > reg = <0x51>;
> > };
> > +
> > +   temp@4c {
> > +   compatible = "nxp,sa56004";
> > +   reg = <0x4c>;
> > +   };
> > };
> > };
> >  };
> > --
> > 2.17.1
> >

RE: [EXT] Re: [PATCH] dt-bindings: thermal: Make cooling-maps property optional

[Andy Tang]

> -Original Message-
> From: Eduardo Valentin 
> Sent: 2019年5月24日 10:50
> To: Andy Tang 
> Cc: rui.zh...@intel.com; robh...@kernel.org; daniel.lezc...@linaro.org;
> mark.rutl...@arm.com; linux...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [EXT] Re: [PATCH] dt-bindings: thermal: Make cooling-maps property
> optional
> 
> Caution: EXT Email
> 
> On Wed, May 15, 2019 at 05:36:47PM +0800, Yuantian Tang wrote:
> > There may be no cooling device on system, or there are no enough
> > cooling devices for each thermal zone in multiple thermal zone cases
> > since cooling devices can't be shared.
> > So make this property optional to remove such limitations.
> 
> Yeah, I am  not sure that is enough reason to make this property optional.
> Let me maybe ask you why do you care creating a thermal zone if your control
> has no actions? Or rather, why bothering setting up a control that has no
> actuators?
No cooling-device map doesn't mean NO ACTIONS. There could be critic trips that 
trigger CPU reset or shutdown.
The root cause for it here is: there is no enough cooling device for each zone 
when multiple zone exist.
For example, for our ls2088a platform, there are 7 thermal zones, but we have 
only one cooling device which is cpufreq.
Due to this option limitation, multiple zones can't be supported.
I believe on most platform, there are only two type of cooling devices, cpufreq 
and fan. So how many cooling devices it could be?
So making the property optional is reasonable. We can assign cooling devices to 
certain thermal zones and leave the thermal zone with no cooling device taking 
default actions.

BR,
Andy
> 
> >
> > Signed-off-by: Yuantian Tang 
> > ---
> >  .../devicetree/bindings/thermal/thermal.txt|4 ++--
> >  1 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/thermal/thermal.txt
> > b/Documentation/devicetree/bindings/thermal/thermal.txt
> > index ca14ba9..694e834 100644
> > --- a/Documentation/devicetree/bindings/thermal/thermal.txt
> > +++ b/Documentation/devicetree/bindings/thermal/thermal.txt
> > @@ -142,11 +142,11 @@ Required properties:
> >  - trips: A sub-node which is a container of only trip point
> nodes
> >Type: sub-node required to describe the thermal zone.
> >
> > +
> > +Optional property:
> >  - cooling-maps:  A sub-node which is a container of only
> cooling device
> >Type: sub-node map nodes, used to describe the relation
> between trips
> >   and cooling devices.
> > -
> > -Optional property:
> >  - coefficients:  An array of integers (one signed cell)
> containing
> >Type: arraycoefficients to compose a linear relation
> between
> >Elem size: one cellthe sensors listed in the thermal-sensors
> property.
> > --
> > 1.7.1
> >

RE: [EXT] Re: [PATCH v6] arm64: dts: ls1088a: add one more thermal zone node

[Andy Tang]

Thanks Viresh for your explanation.

BR,
Andy
> -Original Message-
> From: Viresh Kumar 
> Sent: 2019年5月10日 18:12
> To: Andy Tang 
> Cc: Daniel Lezcano ; Shawn Guo
> ; Leo Li ; robh...@kernel.org;
> mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux...@vger.kernel.org; rui.zh...@intel.com; edubez...@gmail.com
> Subject: Re: [EXT] Re: [PATCH v6] arm64: dts: ls1088a: add one more thermal
> zone node
> 
> Caution: EXT Email
> 
> On 10-05-19, 08:47, Andy Tang wrote:
> > + Viresh for help.
> >
> > > -Original Message-
> > > From: Daniel Lezcano 
> > > Sent: 2019年5月10日 15:17
> > > To: Andy Tang ; Shawn Guo
> 
> > > Cc: Leo Li ; robh...@kernel.org;
> > > mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
> > > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > linux...@vger.kernel.org; rui.zh...@intel.com; edubez...@gmail.com
> > > Subject: Re: [EXT] Re: [PATCH v6] arm64: dts: ls1088a: add one more
> > > thermal zone node
> > >
> > > Caution: EXT Email
> > >
> > > On 10/05/2019 05:40, Andy Tang wrote:
> > > >> -Original Message-
> > > >> From: Shawn Guo 
> > > >> Sent: 2019年5月10日 11:14
> > > >> To: Andy Tang 
> > > >> Cc: Leo Li ; robh...@kernel.org;
> > > >> mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
> > > >> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > >> linux...@vger.kernel.org; daniel.lezc...@linaro.org;
> > > >> rui.zh...@intel.com; edubez...@gmail.com
> > > >> Subject: [EXT] Re: [PATCH v6] arm64: dts: ls1088a: add one more
> > > >> thermal zone node
> > > >>
> > > >> Caution: EXT Email
> > > >>
> > > >> On Tue, Apr 23, 2019 at 10:25:07AM +0800, Yuantian Tang wrote:
> > > >>> Ls1088a has 2 thermal sensors, core cluster and SoC platform.
> > > >>> Core cluster sensor is used to monitor the temperature of core
> > > >>> and SoC platform is for platform. The current dts only support the 
> > > >>> first
> sensor.
> > > >>> This patch adds the second sensor node to dts to enable it.
> > > >>>
> > > >>> Signed-off-by: Yuantian Tang 
> > > >>> ---
> > > >>> v6:
> > > >>> - add cooling device map to cpu0-7 in platform node.
> > > > I like to explain a little. I think it makes sense that multiple
> > > > thermal zone
> > > map to same cooling device.
> > > > In this way, no matter which thermal zone raises a temp alarm, it
> > > > can call
> > > cooling device to chill out.
> > > > I also asked cpufreq maintainer about the cooling map issue, he
> > > > think it
> > > would be fine.
> 
> Yes, you asked me and I said it should be okay.
> 
> > > > I have tested and no issue found.
> > > >
> > > > Daniel, what's your thought?
> > >
> > > If there are multiple thermal zones, they will be managed by
> > > different instances of a thermal governor. Each instances will act
> > > on the shared cooling device and will collide in their decisions:
> > >
> > >  - If the sensors are closed, their behavior will be similar
> > > regarding the temperature. The governors may take the same decision
> > > for the cooling device. But in such case having just one thermal zone
> managed is enough.
> > >
> > >  - If the sensors are not closed, their behavior will be different
> > > regarding the temperature. The governors will take different
> > > decision regarding the cooling device (one will decrease the freq, other
> will increase the freq).
> > >
> > > As the thermal governors are not able to manage several thermal
> > > zones and there is one cooling device (the cpu cooling device), this
> > > setup won't work as expected IMO.
> > >
> > > The setup making sense is having a thermal zone per 'cluster' and a
> > > cooling device per 'cluster'. That means the platform has one clock line
> per 'cluster'.
> > > The thermal management happens in a self-contained thermal zone (one
> > > cooling device - one governor - one thermal zone).
> > >
> > > In the case of HMP, other combinations are possible to be optimal.
> 
> But not sure how I missed the obvious, though I do remember thinking about
> this.
> 
> So the problem is that the cpu_cooling driver will get requests in parallel to
> set different max frequencies and the last call will always win and may result
> in undesired outcome.
> 
> Sorry about creating the confusion.
> 
> --
> viresh

RE: [EXT] Re: [PATCH v6] arm64: dts: ls1088a: add one more thermal zone node

[Andy Tang]

+ Viresh for help.

> -Original Message-
> From: Daniel Lezcano 
> Sent: 2019年5月10日 15:17
> To: Andy Tang ; Shawn Guo 
> Cc: Leo Li ; robh...@kernel.org;
> mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux...@vger.kernel.org; rui.zh...@intel.com; edubez...@gmail.com
> Subject: Re: [EXT] Re: [PATCH v6] arm64: dts: ls1088a: add one more thermal
> zone node
> 
> Caution: EXT Email
> 
> On 10/05/2019 05:40, Andy Tang wrote:
> >> -Original Message-
> >> From: Shawn Guo 
> >> Sent: 2019年5月10日 11:14
> >> To: Andy Tang 
> >> Cc: Leo Li ; robh...@kernel.org;
> >> mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
> >> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> >> linux...@vger.kernel.org; daniel.lezc...@linaro.org;
> >> rui.zh...@intel.com; edubez...@gmail.com
> >> Subject: [EXT] Re: [PATCH v6] arm64: dts: ls1088a: add one more
> >> thermal zone node
> >>
> >> Caution: EXT Email
> >>
> >> On Tue, Apr 23, 2019 at 10:25:07AM +0800, Yuantian Tang wrote:
> >>> Ls1088a has 2 thermal sensors, core cluster and SoC platform. Core
> >>> cluster sensor is used to monitor the temperature of core and SoC
> >>> platform is for platform. The current dts only support the first sensor.
> >>> This patch adds the second sensor node to dts to enable it.
> >>>
> >>> Signed-off-by: Yuantian Tang 
> >>> ---
> >>> v6:
> >>> - add cooling device map to cpu0-7 in platform node.
> > I like to explain a little. I think it makes sense that multiple thermal 
> > zone
> map to same cooling device.
> > In this way, no matter which thermal zone raises a temp alarm, it can call
> cooling device to chill out.
> > I also asked cpufreq maintainer about the cooling map issue, he think it
> would be fine.
> > I have tested and no issue found.
> >
> > Daniel, what's your thought?
> 
> If there are multiple thermal zones, they will be managed by different
> instances of a thermal governor. Each instances will act on the shared cooling
> device and will collide in their decisions:
> 
>  - If the sensors are closed, their behavior will be similar regarding the
> temperature. The governors may take the same decision for the cooling
> device. But in such case having just one thermal zone managed is enough.
> 
>  - If the sensors are not closed, their behavior will be different regarding 
> the
> temperature. The governors will take different decision regarding the cooling
> device (one will decrease the freq, other will increase the freq).
> 
> As the thermal governors are not able to manage several thermal zones and
> there is one cooling device (the cpu cooling device), this setup won't work as
> expected IMO.
> 
> The setup making sense is having a thermal zone per 'cluster' and a cooling
> device per 'cluster'. That means the platform has one clock line per 
> 'cluster'.
> The thermal management happens in a self-contained thermal zone (one
> cooling device - one governor - one thermal zone).
> 
> In the case of HMP, other combinations are possible to be optimal.
Hi Viresh,

I want to map multiple thermal zones to the same cooling device. The above is 
the discussion about it.
It seems reasonable. But I am not expert on this. Could you please provide some 
thoughts? Thanks.

BR,
Andy
> 
> 
> 
> --
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RE: [EXT] Re: [PATCH v6] arm64: dts: ls1088a: add one more thermal zone node

[Andy Tang]

> -Original Message-
> From: Shawn Guo 
> Sent: 2019年5月10日 11:14
> To: Andy Tang 
> Cc: Leo Li ; robh...@kernel.org;
> mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux...@vger.kernel.org; daniel.lezc...@linaro.org; rui.zh...@intel.com;
> edubez...@gmail.com
> Subject: [EXT] Re: [PATCH v6] arm64: dts: ls1088a: add one more thermal
> zone node
> 
> Caution: EXT Email
> 
> On Tue, Apr 23, 2019 at 10:25:07AM +0800, Yuantian Tang wrote:
> > Ls1088a has 2 thermal sensors, core cluster and SoC platform. Core
> > cluster sensor is used to monitor the temperature of core and SoC
> > platform is for platform. The current dts only support the first sensor.
> > This patch adds the second sensor node to dts to enable it.
> >
> > Signed-off-by: Yuantian Tang 
> > ---
> > v6:
> > - add cooling device map to cpu0-7 in platform node.
I like to explain a little. I think it makes sense that multiple thermal zone 
map to same cooling device. 
In this way, no matter which thermal zone raises a temp alarm, it can call 
cooling device to chill out.
I also asked cpufreq maintainer about the cooling map issue, he think it would 
be fine.
I have tested and no issue found. 

Daniel, what's your thought?

Thanks,
Andy
> 
> @Daniel, are you fine with this version?
> 
> Shawn
--- Begin Message ---
WARNING: This email was created outside of NXP. DO NOT CLICK links or 
attachments unless you recognize the sender and know the content is safe.



On 22-04-19, 07:09, Andy Tang wrote:
> Hi Viresh,
>
> Sorry to bother you. I have a question, hope I can get you help.
> Here it is:
>
> I want to add multiple "Thermal Zone" support in dts ( driver is ready).
> The final dts looks like below:
>
> thermal-zones {
> cpu_thermal: cpu-thermal {
> polling-delay-passive = <1000>;
> polling-delay = <5000>;
> thermal-sensors = < 0>;
>
> trips {
> ccu_alert: ccu-alert {
> temperature = <85000>;
> hysteresis = <2000>;
> type = "passive";
> };
> ccu_crit: ccu-crit {
> temperature = <95000>;
> hysteresis = <2000>;
> type = "critical";
> cooling-maps {
> map0 {
> trip = <_alert>;
> cooling-device =
> < THERMAL_NO_LIMIT 
> THERMAL_NO_LIMIT>,
> < THERMAL_NO_LIMIT 
> THERMAL_NO_LIMIT>,
> < THERMAL_NO_LIMIT 
> THERMAL_NO_LIMIT>,
> < THERMAL_NO_LIMIT 
> THERMAL_NO_LIMIT>,
> < THERMAL_NO_LIMIT 
> THERMAL_NO_LIMIT>,
> < THERMAL_NO_LIMIT 
> THERMAL_NO_LIMIT>,
> < THERMAL_NO_LIMIT 
> THERMAL_NO_LIMIT>,
> < THERMAL_NO_LIMIT 
> THERMAL_NO_LIMIT>;
> };
> };
> };
> platform {
> polling-delay-passive = <1000>;
> polling-delay = <5000>;
> thermal-sensors = < 1>;
> trips {
> plt_alert: plt-alert {
> temperature = <85000>;
> hysteresis = <2000>;
> type = "passive";
> };
> plt_crit: plt-crit {
> temperature = <95000>;
> hysteresis = <2000>;
> type = "critical";
> };
> };
> cooling-maps {
> 

RE: [EXT] Re: [PATCH v2] clk: qoriq: Add clockgen support for lx2160a

[Andy Tang]

> -Original Message-
> From: Rafael J. Wysocki 
> Sent: 2019年4月25日 18:04
> To: Vabhav Sharma 
> Cc: linux-kernel@vger.kernel.org; linux-...@vger.kernel.org;
> linux...@vger.kernel.org; sb...@kernel.org; mturque...@baylibre.com;
> r...@rjwysocki.net; viresh.ku...@linaro.org; Yogesh Narayan Gaur
> ; Andy Tang 
> Subject: [EXT] Re: [PATCH v2] clk: qoriq: Add clockgen support for lx2160a
> 
> Caution: EXT Email
> 
> On Thu, Apr 25, 2019 at 11:48 AM Vabhav Sharma 
> wrote:
> >
> > From: Yogesh Gaur 
> >
> > Add clockgen support for lx2160a.
> > Added entry for compat 'fsl,lx2160a-clockgen'.
> 
> Well, if I'm expected to apply this, the above is a bit terse.
> 
> It looks like the patch makes the qoriq-cpufreq driver handle some new
> hardware, but the changelog doesn't say much about that.
> 
> I'm guessing that the clockgen support added here makes it possible for
> qoriq-cpufreq to handle this chip, is that correct?
Yes, your guess is correct. The cpufreq feature is based on clock driver.
It should had been separated to two patches and reduced the confuse.
Do I need to update the commit message or you just take it?

BR,
Andy
> 
> > Signed-off-by: Tang Yuantian 
> > Signed-off-by: Yogesh Gaur 
> > Signed-off-by: Vabhav Sharma 
> > Acked-by: Scott Wood 
> > Acked-by: Stephen Boyd 
> > Acked-by: Viresh Kumar 
> > ---
> > Changes for v2:
> > - Subject line updated
> >
> >  drivers/clk/clk-qoriq.c | 12 
> >  drivers/cpufreq/qoriq-cpufreq.c |  1 +
> >  2 files changed, 13 insertions(+)
> >
> > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> > 3d51d7c..1a15201 100644
> > --- a/drivers/clk/clk-qoriq.c
> > +++ b/drivers/clk/clk-qoriq.c
> > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
> > .flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > },
> > {
> > +   .compat = "fsl,lx2160a-clockgen",
> > +   .cmux_groups = {
> > +   _cmux_cga12, _cmux_cgb
> > +   },
> > +   .cmux_to_group = {
> > +   0, 0, 0, 0, 1, 1, 1, 1, -1
> > +   },
> > +   .pll_mask = 0x37,
> > +   .flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > +   },
> > +   {
> > .compat = "fsl,p2041-clockgen",
> > .guts_compat = "fsl,qoriq-device-config-1.0",
> > .init_periph = p2041_init_periph, @@ -1427,6 +1438,7
> > @@ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen",
> > clockgen_init);  CLK_OF_DECLARE(qoriq_clockgen_ls1046a,
> > "fsl,ls1046a-clockgen", clockgen_init);
> > CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen",
> > clockgen_init);  CLK_OF_DECLARE(qoriq_clockgen_ls2080a,
> > "fsl,ls2080a-clockgen", clockgen_init);
> > +CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen",
> > +clockgen_init);
> >  CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen",
> > clockgen_init);  CLK_OF_DECLARE(qoriq_clockgen_p3041,
> > "fsl,p3041-clockgen", clockgen_init);
> > CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen",
> > clockgen_init); diff --git a/drivers/cpufreq/qoriq-cpufreq.c
> > b/drivers/cpufreq/qoriq-cpufreq.c index 4295e54..81f0288 100644
> > --- a/drivers/cpufreq/qoriq-cpufreq.c
> > +++ b/drivers/cpufreq/qoriq-cpufreq.c
> > @@ -284,6 +284,7 @@ static const struct of_device_id node_matches[]
> __initconst = {
> > { .compatible = "fsl,ls1046a-clockgen", },
> > { .compatible = "fsl,ls1088a-clockgen", },
> > { .compatible = "fsl,ls2080a-clockgen", },
> > +   { .compatible = "fsl,lx2160a-clockgen", },
> > { .compatible = "fsl,p4080-clockgen", },
> > { .compatible = "fsl,qoriq-clockgen-1.0", },
> > { .compatible = "fsl,qoriq-clockgen-2.0", },
> > --
> > 2.7.4
> >

[PATCH] cpufreq: qoriq: Add ls1028a chip support

[andy . tang]

From: Yuantian Tang 

Enable cpufreq feature on ls1028a chip by adding its compatible
string.

Signed-off-by: Yuantian Tang 
---
 drivers/cpufreq/qoriq-cpufreq.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index 4295e54..d308c4d 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -280,6 +280,7 @@ static int qoriq_cpufreq_target(struct cpufreq_policy 
*policy,
 
{ .compatible = "fsl,ls1012a-clockgen", },
{ .compatible = "fsl,ls1021a-clockgen", },
+   { .compatible = "fsl,ls1028a-clockgen", },
{ .compatible = "fsl,ls1043a-clockgen", },
{ .compatible = "fsl,ls1046a-clockgen", },
{ .compatible = "fsl,ls1088a-clockgen", },
-- 
1.7.1

[PATCH] dt-bindings: qoriq-clock: Add ls1028a chip compatible string

[andy . tang]

From: Yuantian Tang 

Add ls1028a chip compatible string in binding document.

Signed-off-by: Yuantian Tang 
---
 .../devicetree/bindings/clock/qoriq-clock.txt  |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt 
b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index c655f28..9cf4a07 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -39,6 +39,7 @@ Required properties:
* "fsl,b4860-clockgen"
* "fsl,ls1012a-clockgen"
* "fsl,ls1021a-clockgen"
+   * "fsl,ls1028a-clockgen"
* "fsl,ls1043a-clockgen"
* "fsl,ls1046a-clockgen"
* "fsl,ls1088a-clockgen"
-- 
1.7.1

[PATCH] clk: qoriq: Add ls1028a clock configuration

[andy . tang]

From: Yuantian Tang 

Enable clock driver by adding clock configuration for ls1028a chip.

Signed-off-by: Yuantian Tang 
---
 drivers/clk/clk-qoriq.c |   68 +++
 1 files changed, 68 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 1212a9b..8b0cb0b 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -245,6 +245,58 @@ static u32 cg_in(struct clockgen *cg, u32 __iomem *reg)
},
 };
 
+static const struct clockgen_muxinfo ls1028a_hwa1 = {
+   {
+   { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
+   { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
+   { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
+   { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
+   { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
+   {},
+   { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
+   { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
+   },
+};
+
+static const struct clockgen_muxinfo ls1028a_hwa2 = {
+   {
+   { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
+   { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
+   { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
+   { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
+   { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
+   {},
+   { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
+   { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
+   },
+};
+
+static const struct clockgen_muxinfo ls1028a_hwa3 = {
+   {
+   { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
+   { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
+   { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
+   { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
+   { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
+   {},
+   { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
+   { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
+   },
+};
+
+static const struct clockgen_muxinfo ls1028a_hwa4 = {
+   {
+   { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
+   { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
+   { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
+   { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
+   { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
+   {},
+   { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
+   { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
+   },
+};
+
 static const struct clockgen_muxinfo ls1043a_hwa1 = {
{
{},
@@ -508,6 +560,21 @@ static void __init t4240_init_periph(struct clockgen *cg)
.pll_mask = 0x03,
},
{
+   .compat = "fsl,ls1028a-clockgen",
+   .cmux_groups = {
+   _cmux_cga12
+   },
+   .hwaccel = {
+   _hwa1, _hwa2,
+   _hwa3, _hwa4
+   },
+   .cmux_to_group = {
+   0, 0, 0, 0, -1
+   },
+   .pll_mask = 0x07,
+   .flags = CG_VER3 | CG_LITTLE_ENDIAN,
+   },
+   {
.compat = "fsl,ls1043a-clockgen",
.init_periph = t2080_init_periph,
.cmux_groups = {
@@ -1423,6 +1490,7 @@ static void __init clockgen_init(struct device_node *np)
 CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
-- 
1.7.1

[PATCH 2/2] clk: qoriq: add more PLL divider clocks support

[andy . tang]

From: Yuantian Tang 

More PLL divider clocks are needed by clock consumer IP. So enlarge
the PLL divider array to accommodate more divider clocks.

Signed-off-by: Yuantian Tang 
---
 drivers/clk/clk-qoriq.c |5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 1212a9b..5e2b3ac 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -34,6 +34,7 @@
 #define CGA_PLL4   4   /* only on clockgen-1.0, which lacks CGB */
 #define CGB_PLL1   4
 #define CGB_PLL2   5
+#define MAX_PLL_DIV16
 
 struct clockgen_pll_div {
struct clk *clk;
@@ -41,7 +42,7 @@ struct clockgen_pll_div {
 };
 
 struct clockgen_pll {
-   struct clockgen_pll_div div[8];
+   struct clockgen_pll_div div[MAX_PLL_DIV];
 };
 
 #define CLKSEL_VALID   1
@@ -1128,7 +1129,7 @@ static void __init create_one_pll(struct clockgen *cg, 
int idx)
int ret;
 
/*
-* For platform PLL, there are 8 divider clocks.
+* For platform PLL, there are MAX_PLL_DIV divider clocks.
 * For core PLL, there are 4 divider clocks at most.
 */
if (idx != PLATFORM_PLL && i >= 4)
-- 
1.7.1

[PATCH 1/2] dt-bindings: qoriq-clock: add more PLL divider clocks support

[andy . tang]

From: Yuantian Tang 

More PLL divider clocks are needed by clock consumer IP. So update
the PLL divider description to make it more general.

Signed-off-by: Yuantian Tang 
---
 .../devicetree/bindings/clock/qoriq-clock.txt  |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt 
b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index c655f28..27aeed0 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -83,8 +83,8 @@ second cell is the clock index for the specified type.
1   cmuxindex (n in CLKCnCSR)
2   hwaccel index (n in CLKCGnHWACSR)
3   fman0 for fm1, 1 for fm2
-   4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
-   4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8
+   4   platform plln=pll/(n+1). For example, when n=1,
+   that means output_freq=PLL_freq/2.
5   coreclk must be 0
 
 3. Example
-- 
1.7.1

RE: [EXT] Re: [PATCH v5] arm64: dts: ls1088a: add one more thermal zone node

[Andy Tang]

> -Original Message-
> From: Daniel Lezcano 
> Sent: 2019年4月12日 20:19
> To: Andy Tang ; shawn...@kernel.org
> Cc: Leo Li ; robh...@kernel.org; mark.rutl...@arm.com;
> linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux...@vger.kernel.org; rui.zh...@intel.com;
> edubez...@gmail.com
> Subject: Re: [EXT] Re: [PATCH v5] arm64: dts: ls1088a: add one more thermal
> zone node
> 
> WARNING: This email was created outside of NXP. DO NOT CLICK links or
> attachments unless you recognize the sender and know the content is safe.
> 
> 
> 
> On 12/04/2019 09:47, Andy Tang wrote:
> >
> >> -Original Message-----
> >> From: Daniel Lezcano 
> >> Sent: 2019年4月12日 3:15
> >> To: Andy Tang ; shawn...@kernel.org
> >> Cc: Leo Li ; robh...@kernel.org;
> >> mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
> >> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> >> linux...@vger.kernel.org; rui.zh...@intel.com; edubez...@gmail.com
> >> Subject: [EXT] Re: [PATCH v5] arm64: dts: ls1088a: add one more
> >> thermal zone node
> >>
> >> WARNING: This email was created outside of NXP. DO NOT CLICK links or
> >> attachments unless you recognize the sender and know the content is safe.
> >>
> >>
> >>
> >> On 11/04/2019 10:32, Yuantian Tang wrote:
> >>> Ls1088a has 2 thermal sensors, core cluster and SoC platform. Core
> >>> cluster sensor is used to monitor the temperature of core and SoC
> >>> platform is for platform. The current dts only support the first sensor.
> >>> This patch adds the second sensor node to dts to enable it.
> >>>
> >>> Signed-off-by: Yuantian Tang 
> >>> ---
> >>> v5:
> >>>   - update the thermal zone name due to the length limitation
> >>>   - remove cooling map in platform zone
> >>> v4:
> >>>   - use hyphen instead of underscore in node name
> >>> v3:
> >>>   - use more descriptive name for each zone
> >>> v2:
> >>>   - Add more information about sensors to description
> >>>  arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   28
> >> ---
> >>>  1 files changed, 24 insertions(+), 4 deletions(-)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> >>> b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> >>> index de93b42..de39672 100644
> >>> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> >>> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> >>> @@ -129,19 +129,19 @@
> >>>   };
> >>>
> >>>   thermal-zones {
> >>> - cpu_thermal: cpu-thermal {
> >>> + core-cluster {
> >>>   polling-delay-passive = <1000>;
> >>>   polling-delay = <5000>;
> >>>   thermal-sensors = < 0>;
> >>>
> >>>   trips {
> >>> - cpu_alert: cpu-alert {
> >>> + core_cluster_alert: core-cluster-alert
> >>> + {
> >>>   temperature = <85000>;
> >>>   hysteresis = <2000>;
> >>>   type = "passive";
> >>>   };
> >>>
> >>> - cpu_crit: cpu-crit {
> >>> + core_cluster_crit: core-cluster-crit {
> >>>   temperature = <95000>;
> >>>   hysteresis = <2000>;
> >>>   type = "critical"; @@ -150,7
> >>> +150,7 @@
> >>>
> >>>   cooling-maps {
> >>>   map0 {
> >>> - trip = <_alert>;
> >>> + trip = <_cluster_alert>;
> >>>   cooling-device =
> >>>   <
> >> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> >>>   

RE: [EXT] Re: [PATCH v5] arm64: dts: ls1088a: add one more thermal zone node

[Andy Tang]

> -Original Message-
> From: Daniel Lezcano 
> Sent: 2019年4月12日 3:15
> To: Andy Tang ; shawn...@kernel.org
> Cc: Leo Li ; robh...@kernel.org; mark.rutl...@arm.com;
> linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux...@vger.kernel.org; rui.zh...@intel.com;
> edubez...@gmail.com
> Subject: [EXT] Re: [PATCH v5] arm64: dts: ls1088a: add one more thermal zone
> node
> 
> WARNING: This email was created outside of NXP. DO NOT CLICK links or
> attachments unless you recognize the sender and know the content is safe.
> 
> 
> 
> On 11/04/2019 10:32, Yuantian Tang wrote:
> > Ls1088a has 2 thermal sensors, core cluster and SoC platform. Core
> > cluster sensor is used to monitor the temperature of core and SoC
> > platform is for platform. The current dts only support the first sensor.
> > This patch adds the second sensor node to dts to enable it.
> >
> > Signed-off-by: Yuantian Tang 
> > ---
> > v5:
> >   - update the thermal zone name due to the length limitation
> >   - remove cooling map in platform zone
> > v4:
> >   - use hyphen instead of underscore in node name
> > v3:
> >   - use more descriptive name for each zone
> > v2:
> >   - Add more information about sensors to description
> >  arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   28
> ---
> >  1 files changed, 24 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > index de93b42..de39672 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > @@ -129,19 +129,19 @@
> >   };
> >
> >   thermal-zones {
> > - cpu_thermal: cpu-thermal {
> > + core-cluster {
> >   polling-delay-passive = <1000>;
> >   polling-delay = <5000>;
> >   thermal-sensors = < 0>;
> >
> >   trips {
> > - cpu_alert: cpu-alert {
> > + core_cluster_alert: core-cluster-alert {
> >   temperature = <85000>;
> >   hysteresis = <2000>;
> >   type = "passive";
> >   };
> >
> > - cpu_crit: cpu-crit {
> > + core_cluster_crit: core-cluster-crit {
> >   temperature = <95000>;
> >   hysteresis = <2000>;
> >   type = "critical"; @@ -150,7
> > +150,7 @@
> >
> >   cooling-maps {
> >   map0 {
> > - trip = <_alert>;
> > + trip = <_cluster_alert>;
> >   cooling-device =
> >   <
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> >   <
> THERMAL_NO_LIMIT
> > THERMAL_NO_LIMIT>, @@ -163,6 +163,26 @@
> >   };
> >   };
> >   };
> > +
> > + platform {
> > + polling-delay-passive = <1000>;
> > + polling-delay = <5000>;
> > + thermal-sensors = < 1>;
> > +
> > + trips {
> > + platform-alert {
> > + temperature = <85000>;
> > + hysteresis = <2000>;
> > + type = "passive";
> > + };
> > +
> > + platform-crit {
> > + temperature = <95000>;
> > + hysteresis = <2000>;
> > + type = "critical";
> > + };
> > + };
> > + };
> 
> 
> Unfortunately, the documentation says the thermal zone node must contain a
> "cooling-maps" entry.
That's a question.
If I add "cool

RE: [PATCH v4] arm64: dts: ls1088a: add one more thermal zone node

[Andy Tang]

Hi Daniel,


> -Original Message-
> From: Daniel Lezcano 
> Sent: 2019年4月4日 10:35
> To: Andy Tang ; shawn...@kernel.org
> Cc: Leo Li ; robh...@kernel.org; mark.rutl...@arm.com;
> linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux...@vger.kernel.org; rui.zh...@intel.com;
> edubez...@gmail.com
> Subject: Re: [PATCH v4] arm64: dts: ls1088a: add one more thermal zone node
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>;
> > +   };
> 
> Does it make sense to assign the same cooling devices to two different thermal
> zones running different instances of governor ?
Even though I didn't find any error when test, I do think it is inappropriate.

BR,
Andy
> 
> > +   };
> > +   };
> > +
> > +   platform-thermal {
> > +   polling-delay-passive = <1000>;
> > +   polling-delay = <5000>;
> > +   thermal-sensors = < 1>;
> > +
> > +   trips {
> > +   platform_alert: platform-alert {
> > +   temperature = <85000>;
> > +   hysteresis = <2000>;
> > +   type = "passive";
> > +   };
> > +
> > +   platform_crit: platform-crit {
> > +   temperature = <95000>;
> > +   hysteresis = <2000>;
> > +   type = "critical";
> > +   };
> > +   };
> > +
> > +   cooling-maps {
> > +   map0 {
> > +   trip = <_alert>;
> > cooling-device =
> > < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> >
> 
> 
> --
> 
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RE: [PATCH v2] arm64: dts: ls1088a: add one more thermal zone node

[Andy Tang]

> -Original Message-
> From: Shawn Guo 
> Sent: 2019年3月20日 22:49
> To: Andy Tang 
> Cc: Daniel Lezcano ; mark.rutl...@arm.com;
> devicet...@vger.kernel.org; linux...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Leo Li ;
> edubez...@gmail.com; robh...@kernel.org; rui.zh...@intel.com;
> linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v2] arm64: dts: ls1088a: add one more thermal zone node
> 
> On Wed, Mar 20, 2019 at 08:44:18AM +, Andy Tang wrote:
> > > > Sensor ID   placement
> > > > 1   DDR controller 1
> > > > 2   DDR controller 2
> > > > 3   DDR controller 3
> > > > 4   core cluster 1
> > > > 5   core cluster 2
> > > > 6   core cluster 3
> > > > 7   core cluster 4
> > > >
> > > > Apparently using CPU or CPU-cluster is not appropriate. Core-cluster is
> better.
> > >
> > > So using CPU is appropriate for me, less confusing, more consistent
> > > with other platforms.
> > What about core cluster? We can't name it cpu0, cpu1 etc I think.
> 
> Hmm, yes, that would be even more confusing.  What about cpu-thermal-1,
> cpu-thermal-2 ...?
Cpu-thermal-x can't change anything better than cpuX. It can't reflect the 
concept of CLUSTER.
I prefer to use core-cluster. It is a wild accepted term in ARM ecosystem.

BR,
Andy
> 
> Shawn

RE: [PATCH v2] arm64: dts: ls1088a: add one more thermal zone node

[Andy Tang]

Hi Shawn,

> -Original Message-
> From: Shawn Guo 
> Sent: 2019年3月20日 16:19
> To: Andy Tang 
> Cc: Daniel Lezcano ; mark.rutl...@arm.com;
> devicet...@vger.kernel.org; linux...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Leo Li ;
> edubez...@gmail.com; robh...@kernel.org; rui.zh...@intel.com;
> linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v2] arm64: dts: ls1088a: add one more thermal zone node
> 
> On Fri, Mar 08, 2019 at 09:57:09AM +, Andy Tang wrote:
> >
> >
> > > -Original Message-
> > > From: Daniel Lezcano 
> > > Sent: 2019年3月8日 17:28
> > > To: Andy Tang ; Shawn Guo 
> > > Cc: Leo Li ; robh...@kernel.org;
> > > mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
> > > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > linux...@vger.kernel.org; rui.zh...@intel.com; edubez...@gmail.com
> > > Subject: Re: [PATCH v2] arm64: dts: ls1088a: add one more thermal
> > > zone node
> > >
> > > On 08/03/2019 03:07, Andy Tang wrote:
> > > >
> > > >
> > > >> -Original Message-
> > > >> From: Daniel Lezcano 
> > > >> Sent: 2019年3月7日 17:15
> > > >> To: Andy Tang ; Shawn Guo
> > > >> 
> > > >> Cc: Leo Li ; robh...@kernel.org;
> > > >> mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
> > > >> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > >> linux...@vger.kernel.org; rui.zh...@intel.com;
> > > >> edubez...@gmail.com
> > > >> Subject: Re: [PATCH v2] arm64: dts: ls1088a: add one more thermal
> > > >> zone node
> > > >>
> > > >>>>> PS: In order to keep consistency to the first thermal-zone
> > > >>>>> node, there will be "WARNING: line over 80 characters" warnings.
> > > >>>>>
> > > >>>>>  arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   43
> > > >>>> +--
> > > >>>>>  1 files changed, 39 insertions(+), 4 deletions(-)
> > > >>>>>
> > > >>>>> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > >>>>> b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > >>>>> index 661137f..9f52bc9 100644
> > > >>>>> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > >>>>> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > >>>>> @@ -129,19 +129,19 @@
> > > >>>>> };
> > > >>>>>
> > > >>>>> thermal-zones {
> > > >>>>> -   cpu_thermal: cpu-thermal {
> > > >>>>> +   ccu {
> > > >>>>
> > > >>>> Is this change really necessary?  What does 'ccu' stand for?
> > > >>> I think so. ccu stands for core cluster unit. cpu is too general.
> > > >>> On some platforms, there are more than one core clusters.
> > > >>> At least we should change it to "core cluster" if short form is
> > > >>> not
> > > appropriate.
> > > >>
> > > >> If the sensor is a the cluster level, 'cluster' is enough. IMHO,
> > > >> no need to give a description of what contains the cluster,
> > > >> otherwise you will end up with a 'core-gpu-cluster-l2' name.
> > > > If cluster is specific to core, we can use cluster instead. But I don't 
> > > > think
> so.
> > > > Cluster may refer to "core cluster", "GPU cluster" etc.
> > > > So, I think "core-cluster" is ok.
> > > > If core was divided to several clusters, we can name it as
> > > > "core-cluster1",
> > > "core-cluster2" etc.
> > > > If GPU was divided to several clusters we can name it as
> > > > "gpu-cluster1",
> > > "gpu-cluster2" etc.
> > >
> > >
> > > Hi Andy,
> > >
> > > I think there is a confusion around the 'cpu' term and 'cluster'.
> > >
> > > ARM would like to see the 'cluster' word to disappear, so whenever
> > > possible we should avoid it.
> > >
> > > From the hardware side, 'CPU' is usually used to describe the
> > > physical chip containing the cores+cache.
> > >
> >

RE: [PATCH v2] arm64: dts: ls1088a: add one more thermal zone node

[Andy Tang]

> -Original Message-
> From: Daniel Lezcano 
> Sent: 2019年3月8日 17:28
> To: Andy Tang ; Shawn Guo 
> Cc: Leo Li ; robh...@kernel.org; mark.rutl...@arm.com;
> linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux...@vger.kernel.org; rui.zh...@intel.com;
> edubez...@gmail.com
> Subject: Re: [PATCH v2] arm64: dts: ls1088a: add one more thermal zone node
> 
> On 08/03/2019 03:07, Andy Tang wrote:
> >
> >
> >> -Original Message-
> >> From: Daniel Lezcano 
> >> Sent: 2019年3月7日 17:15
> >> To: Andy Tang ; Shawn Guo 
> >> Cc: Leo Li ; robh...@kernel.org;
> >> mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
> >> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> >> linux...@vger.kernel.org; rui.zh...@intel.com; edubez...@gmail.com
> >> Subject: Re: [PATCH v2] arm64: dts: ls1088a: add one more thermal
> >> zone node
> >>
> >>>>> PS: In order to keep consistency to the first thermal-zone node,
> >>>>> there will be "WARNING: line over 80 characters" warnings.
> >>>>>
> >>>>>  arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   43
> >>>> +--
> >>>>>  1 files changed, 39 insertions(+), 4 deletions(-)
> >>>>>
> >>>>> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> >>>>> b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> >>>>> index 661137f..9f52bc9 100644
> >>>>> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> >>>>> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> >>>>> @@ -129,19 +129,19 @@
> >>>>> };
> >>>>>
> >>>>> thermal-zones {
> >>>>> -   cpu_thermal: cpu-thermal {
> >>>>> +   ccu {
> >>>>
> >>>> Is this change really necessary?  What does 'ccu' stand for?
> >>> I think so. ccu stands for core cluster unit. cpu is too general.
> >>> On some platforms, there are more than one core clusters.
> >>> At least we should change it to "core cluster" if short form is not
> appropriate.
> >>
> >> If the sensor is a the cluster level, 'cluster' is enough. IMHO, no
> >> need to give a description of what contains the cluster, otherwise
> >> you will end up with a 'core-gpu-cluster-l2' name.
> > If cluster is specific to core, we can use cluster instead. But I don't 
> > think so.
> > Cluster may refer to "core cluster", "GPU cluster" etc.
> > So, I think "core-cluster" is ok.
> > If core was divided to several clusters, we can name it as "core-cluster1",
> "core-cluster2" etc.
> > If GPU was divided to several clusters we can name it as "gpu-cluster1",
> "gpu-cluster2" etc.
> 
> 
> Hi Andy,
> 
> I think there is a confusion around the 'cpu' term and 'cluster'.
> 
> ARM would like to see the 'cluster' word to disappear, so whenever possible we
> should avoid it.
> 
> From the hardware side, 'CPU' is usually used to describe the physical chip
> containing the cores+cache.
> 
> From the software side, 'CPU' is usually used to describe the logical process
> unit, aka a core or a hyper-thread.
> 
> As we are in the DT, so describing the hardware, the CPU refers to the group
> cores+caches.
> 
> From my POV, using 'cpu' for the group of cores and 'gpu' for the graphic
> sounds ok, and so far that is what is used for the other platforms.
> 
> If you change the name, that may give the feeling there is something special
> with those thermal zones.

Thanks Daniel for your detailed explanations.

But as you said 'CPU' is usually used to describe the physical chip.
So if we name it as CPU, it sounds like this temperature sensor is monitoring 
the whole chip.
That's not true in our case.

Take ls2088a for example:
In ls2088a SoC, there are 7 temperature sensors. Please note that they are all 
located in SoC.
The placement of the temperature sensors are showed below:

Sensor ID   placement
1   DDR controller 1
2   DDR controller 2
3   DDR controller 3
4   core cluster 1
5   core cluster 2
6   core cluster 3
7   core cluster 4

Apparently using CPU or CPU-cluster is not appropriate. Core-cluster is better.

What do you think?

BR,
Andy
> 
> 
> 
> 

RE: [PATCH v2] arm64: dts: ls1088a: add one more thermal zone node

[Andy Tang]

> -Original Message-
> From: Daniel Lezcano 
> Sent: 2019年3月7日 17:15
> To: Andy Tang ; Shawn Guo 
> Cc: Leo Li ; robh...@kernel.org; mark.rutl...@arm.com;
> linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux...@vger.kernel.org; rui.zh...@intel.com;
> edubez...@gmail.com
> Subject: Re: [PATCH v2] arm64: dts: ls1088a: add one more thermal zone node
> 
> >>> PS: In order to keep consistency to the first thermal-zone node,
> >>> there will be "WARNING: line over 80 characters" warnings.
> >>>
> >>>  arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   43
> >> +--
> >>>  1 files changed, 39 insertions(+), 4 deletions(-)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> >>> b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> >>> index 661137f..9f52bc9 100644
> >>> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> >>> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> >>> @@ -129,19 +129,19 @@
> >>>   };
> >>>
> >>>   thermal-zones {
> >>> - cpu_thermal: cpu-thermal {
> >>> + ccu {
> >>
> >> Is this change really necessary?  What does 'ccu' stand for?
> > I think so. ccu stands for core cluster unit. cpu is too general.
> > On some platforms, there are more than one core clusters.
> > At least we should change it to "core cluster" if short form is not 
> > appropriate.
> 
> If the sensor is a the cluster level, 'cluster' is enough. IMHO, no need to 
> give a
> description of what contains the cluster, otherwise you will end up with a
> 'core-gpu-cluster-l2' name.
If cluster is specific to core, we can use cluster instead. But I don't think 
so.
Cluster may refer to "core cluster", "GPU cluster" etc.
So, I think "core-cluster" is ok.
If core was divided to several clusters, we can name it as "core-cluster1", 
"core-cluster2" etc.
If GPU was divided to several clusters we can name it as "gpu-cluster1", 
"gpu-cluster2" etc. 

BR,
Andy
> 
> >>
> >>>   polling-delay-passive = <1000>;
> >>>   polling-delay = <5000>;
> >>>   thermal-sensors = < 0>;
> >>>
> >>>   trips {
> >>> - cpu_alert: cpu-alert {
> >>> + ccu_alert: ccu-alert {
> >>>   temperature = <85000>;
> >>>   hysteresis = <2000>;
> >>>   type = "passive";
> >>>   };
> >>>
> >>> - cpu_crit: cpu-crit {
> >>> + ccu_crit: ccu-crit {
> >>>   temperature = <95000>;
> >>>   hysteresis = <2000>;
> >>>   type = "critical";
> >>> @@ -150,7 +150,42 @@
> >>>
> >>>   cooling-maps {
> >>>   map0 {
> >>> - trip = <_alert>;
> >>> + trip = <_alert>;
> >>> + cooling-device =
> >>> + < THERMAL_NO_LIMIT
> >> THERMAL_NO_LIMIT>,
> >>> + < THERMAL_NO_LIMIT
> >> THERMAL_NO_LIMIT>,
> >>> + < THERMAL_NO_LIMIT
> >> THERMAL_NO_LIMIT>,
> >>> + < THERMAL_NO_LIMIT
> >> THERMAL_NO_LIMIT>,
> >>> + < THERMAL_NO_LIMIT
> >> THERMAL_NO_LIMIT>,
> >>> + < THERMAL_NO_LIMIT
> >> THERMAL_NO_LIMIT>,
> >>> + < THERMAL_NO_LIMIT
> >> THERMAL_NO_LIMIT>,
> >>> + < THERMAL_NO_LIMIT
> >> THERMAL_NO_LIMIT>;
> >>> + };
> >>> + };
> >>> + };
> >>> +
> >>> + plt {
>

RE: [PATCH v2] arm64: dts: ls1088a: add one more thermal zone node

[Andy Tang]

> -Original Message-
> From: Shawn Guo 
> Sent: 2019年3月4日 14:21
> To: Andy Tang 
> Cc: Leo Li ; robh...@kernel.org; mark.rutl...@arm.com;
> linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux...@vger.kernel.org;
> daniel.lezc...@linaro.org; rui.zh...@intel.com; edubez...@gmail.com
> Subject: Re: [PATCH v2] arm64: dts: ls1088a: add one more thermal zone node
> 
> On Mon, Mar 04, 2019 at 11:21:11AM +0800, Yuantian Tang wrote:
> > Ls1088a has 2 thermal sensors, core cluster and SoC platform. Core
> > cluster sensor is used to monitor the temperature of core and SoC
> > platform is for platform. The current dts only support the first sensor.
> > This patch adds the second sensor node to dts to enable it.
> >
> > Signed-off-by: Yuantian Tang 
> > ---
> > v2:
> > - Add more information about sensors to description
> > PS: In order to keep consistency to the first thermal-zone node, there
> > will be "WARNING: line over 80 characters" warnings.
> >
> >  arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   43
> +--
> >  1 files changed, 39 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > index 661137f..9f52bc9 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > @@ -129,19 +129,19 @@
> > };
> >
> > thermal-zones {
> > -   cpu_thermal: cpu-thermal {
> > +   ccu {
> 
> Is this change really necessary?  What does 'ccu' stand for?
I think so. ccu stands for core cluster unit. cpu is too general.
On some platforms, there are more than one core clusters.
At least we should change it to "core cluster" if short form is not appropriate.

> 
> > polling-delay-passive = <1000>;
> > polling-delay = <5000>;
> > thermal-sensors = < 0>;
> >
> > trips {
> > -   cpu_alert: cpu-alert {
> > +   ccu_alert: ccu-alert {
> > temperature = <85000>;
> > hysteresis = <2000>;
> > type = "passive";
> > };
> >
> > -   cpu_crit: cpu-crit {
> > +   ccu_crit: ccu-crit {
> > temperature = <95000>;
> > hysteresis = <2000>;
> > type = "critical";
> > @@ -150,7 +150,42 @@
> >
> > cooling-maps {
> > map0 {
> > -   trip = <_alert>;
> > +   trip = <_alert>;
> > +   cooling-device =
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>;
> > +   };
> > +   };
> > +   };
> > +
> > +   plt {
> 
> What about 'platform-thermal' for node name, platform-alert and platform-crit
> for trip nodes below?
OK, will use long name form.

BR,
Andy
> 
> Shawn
> 
> > +   polling-delay-passive = <1000>;
> > +   polling-delay = <5000>;
> > +   thermal-sensors = < 1>;
> > +
> > +   trips {
> > +   plt_alert: plt-alert {
> > +   temperature = <85000>;
> > +   hysteresis = <2000&

RE: [PATCH] arm64: dts: ls1088a: add one more thermal zone node

[Andy Tang]

> -Original Message-
> From: Shawn Guo 
> Sent: 2019年3月1日 21:38
> To: Andy Tang 
> Cc: Leo Li ; robh...@kernel.org; mark.rutl...@arm.com;
> linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux...@vger.kernel.org;
> daniel.lezc...@linaro.org; rui.zh...@intel.com; edubez...@gmail.com
> Subject: Re: [PATCH] arm64: dts: ls1088a: add one more thermal zone node
> 
> On Mon, Feb 25, 2019 at 11:00:49AM +0800, Yuantian Tang wrote:
> > Ls1088a has 2 thermal sensors. This patch adds the second node to dts
> > to enable it.
> 
> Can you elaborate on these 2 thermal sensors/zones, ccu and plt?
> 
OK, thanks.

BR,
Andy  

> Shawn
> 
> >
> > Signed-off-by: Yuantian Tang 
> > ---
> >  arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   43
> +--
> >  1 files changed, 39 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > index 661137f..9f52bc9 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > @@ -129,19 +129,19 @@
> > };
> >
> > thermal-zones {
> > -   cpu_thermal: cpu-thermal {
> > +   ccu {
> > polling-delay-passive = <1000>;
> > polling-delay = <5000>;
> > thermal-sensors = < 0>;
> >
> > trips {
> > -   cpu_alert: cpu-alert {
> > +   ccu_alert: ccu-alert {
> > temperature = <85000>;
> > hysteresis = <2000>;
> > type = "passive";
> > };
> >
> > -   cpu_crit: cpu-crit {
> > +   ccu_crit: ccu-crit {
> > temperature = <95000>;
> > hysteresis = <2000>;
> > type = "critical";
> > @@ -150,7 +150,42 @@
> >
> > cooling-maps {
> > map0 {
> > -   trip = <_alert>;
> > +   trip = <_alert>;
> > +   cooling-device =
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > +   < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>;
> > +   };
> > +   };
> > +   };
> > +
> > +   plt {
> > +   polling-delay-passive = <1000>;
> > +   polling-delay = <5000>;
> > +   thermal-sensors = < 1>;
> > +
> > +   trips {
> > +   plt_alert: plt-alert {
> > +   temperature = <85000>;
> > +   hysteresis = <2000>;
> > +   type = "passive";
> > +   };
> > +
> > +   plt_crit: plt-crit {
> > +   temperature = <95000>;
> > +   hysteresis = <2000>;
> > +   type = "critical";
> > +   };
> > +   };
> > +
> > +   cooling-maps {
> > +   map0 {
> > +   trip = <_alert>;
> > cooling-device =
> > < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > < THERMAL_NO_LIMIT
> THERMAL_NO_LIMIT>,
> > --
> > 1.7.1
> >

[PATCH v2] thermal: qoriq: add multiple sensors support

[andy . tang]

From: Yuantian Tang 

The QorIQ Layerscape SoC has several thermal sensors but the current
driver only supports one.

Massage the code to be sensor oriented and allow the support for
multiple sensors.

Signed-off-by: Yuantian Tang 
Reviewed-by: Daniel Lezcano 
---
v2:
- rebase to evalenti's tree

 drivers/thermal/qoriq_thermal.c |  104 +-
 1 files changed, 47 insertions(+), 57 deletions(-)

diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
index 18c711b..3b5f5b3 100644
--- a/drivers/thermal/qoriq_thermal.c
+++ b/drivers/thermal/qoriq_thermal.c
@@ -59,14 +59,21 @@ struct qoriq_tmu_regs {
u32 ttr3cr; /* Temperature Range 3 Control Register */
 };
 
+struct qoriq_tmu_data;
+
 /*
  * Thermal zone data
  */
+struct qoriq_sensor {
+   struct thermal_zone_device  *tzd;
+   struct qoriq_tmu_data   *qdata;
+   int id;
+};
+
 struct qoriq_tmu_data {
-   struct thermal_zone_device *tz;
struct qoriq_tmu_regs __iomem *regs;
-   int sensor_id;
bool little_endian;
+   struct qoriq_sensor *sensor[SITES_MAX];
 };
 
 static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr)
@@ -87,48 +94,50 @@ static u32 tmu_read(struct qoriq_tmu_data *p, void __iomem 
*addr)
 
 static int tmu_get_temp(void *p, int *temp)
 {
+   struct qoriq_sensor *qsensor = p;
+   struct qoriq_tmu_data *qdata = qsensor->qdata;
u32 val;
-   struct qoriq_tmu_data *data = p;
 
-   val = tmu_read(data, >regs->site[data->sensor_id].tritsr);
+   val = tmu_read(qdata, >regs->site[qsensor->id].tritsr);
*temp = (val & 0xff) * 1000;
 
return 0;
 }
 
-static int qoriq_tmu_get_sensor_id(void)
-{
-   int ret, id;
-   struct of_phandle_args sensor_specs;
-   struct device_node *np, *sensor_np;
-
-   np = of_find_node_by_name(NULL, "thermal-zones");
-   if (!np)
-   return -ENODEV;
-
-   sensor_np = of_get_next_child(np, NULL);
-   ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
-   "#thermal-sensor-cells",
-   0, _specs);
-   if (ret) {
-   of_node_put(np);
-   of_node_put(sensor_np);
-   return ret;
-   }
+static const struct thermal_zone_of_device_ops tmu_tz_ops = {
+   .get_temp = tmu_get_temp,
+};
 
-   if (sensor_specs.args_count >= 1) {
-   id = sensor_specs.args[0];
-   WARN(sensor_specs.args_count > 1,
-   "%pOFn: too many cells in sensor specifier 
%d\n",
-   sensor_specs.np, sensor_specs.args_count);
-   } else {
-   id = 0;
+static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
+{
+   struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
+   int id, sites = 0;
+
+   for (id = 0; id < SITES_MAX; id++) {
+   qdata->sensor[id] = devm_kzalloc(>dev,
+   sizeof(struct qoriq_sensor), GFP_KERNEL);
+   if (!qdata->sensor[id])
+   return -ENOMEM;
+
+   qdata->sensor[id]->id = id;
+   qdata->sensor[id]->qdata = qdata;
+   qdata->sensor[id]->tzd = devm_thermal_zone_of_sensor_register(
+   >dev, id, qdata->sensor[id], _tz_ops);
+   if (IS_ERR(qdata->sensor[id]->tzd)) {
+   if (PTR_ERR(qdata->sensor[id]->tzd) == -ENODEV)
+   continue;
+   else
+   return PTR_ERR(qdata->sensor[id]->tzd);
+   }
+
+   sites |= 0x1 << (15 - id);
}
 
-   of_node_put(np);
-   of_node_put(sensor_np);
+   /* Enable monitoring */
+   if (sites != 0)
+   tmu_write(qdata, sites | TMR_ME | TMR_ALPF, >regs->tmr);
 
-   return id;
+   return 0;
 }
 
 static int qoriq_tmu_calibration(struct platform_device *pdev)
@@ -178,16 +187,11 @@ static void qoriq_tmu_init_device(struct qoriq_tmu_data 
*data)
tmu_write(data, TMR_DISABLE, >regs->tmr);
 }
 
-static const struct thermal_zone_of_device_ops tmu_tz_ops = {
-   .get_temp = tmu_get_temp,
-};
-
 static int qoriq_tmu_probe(struct platform_device *pdev)
 {
int ret;
struct qoriq_tmu_data *data;
struct device_node *np = pdev->dev.of_node;
-   u32 site;
 
if (!np) {
dev_err(>dev, "Device OF-Node is NULL");
@@ -203,13 +207,6 @@ static int qoriq_tmu_probe(struct platform_device *pdev)
 
data->little_endian = of_property_read_bool(np, "little-endian");
 
-   data->sensor_id = qoriq_tmu_get_sensor_id();
-   if (data->sensor_id < 0) {
-   dev_err(>dev, "Failed to get sensor id\n");
-   ret = -ENODEV;
-   goto err_iomap;
-   }
-

RE: [PATCH] arm64: dts: nxp: ls208xa: add more thermal zone support

[Andy Tang]

> -Original Message-
> From: Shawn Guo 
> Sent: 2018年12月19日 12:08
> To: Andy Tang 
> Cc: mark.rutl...@arm.com; devicet...@vger.kernel.org;
> daniel.lezc...@linaro.org; linux-kernel@vger.kernel.org; Leo Li
> ; robh...@kernel.org; rui.zh...@intel.com;
> linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH] arm64: dts: nxp: ls208xa: add more thermal zone support
> 
> On Tue, Dec 18, 2018 at 07:01:32AM +, Andy Tang wrote:
> > Hi,
> >
> > PING.
> >
> > BR,
> > Andy
> >
> > > -Original Message-
> > > From: Yuantian Tang 
> > > Sent: 2018年10月31日 12:48
> > > To: shawn...@kernel.org
> > > Cc: Leo Li ; robh...@kernel.org;
> > > mark.rutl...@arm.com; linux-arm-ker...@lists.infradead.org;
> > > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > rui.zh...@intel.com; daniel.lezc...@linaro.org; Andy Tang
> > > 
> > > Subject: [PATCH] arm64: dts: nxp: ls208xa: add more thermal zone
> > > support
> > >
> > > Ls208xa has several thermal sensors. Add all the sensor id to dts to
> > > enable them.
> > >
> > > To make the dts cleaner, re-organize the nodes to split out the
> > > common part so that it can be shared with other SoCs.
> > >
> > > Signed-off-by: Yuantian Tang 
> 
> Please take a look at patch below.
> 
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch
> work.kernel.org%2Fpatch%2F10685815%2Fdata=02%7C01%7Candy.tang
> %40nxp.com%7C440d607feede45068dc608d66567c978%7C686ea1d3bc2b4c6fa
> 92cd99c5c301635%7C0%7C0%7C636807893765936983sdata=QC%2By9f
> mvI42t9eS3LS4YGD23Kqq6EUD0EpIGnDEDhrA%3Dreserved=0
> 
Thanks, will rebase my patch.

BR,
Andy
> Shawn

RE: [PATCH] arm64: dts: nxp: ls208xa: add more thermal zone support

[Andy Tang]

Hi,

PING.

BR,
Andy

> -Original Message-
> From: Yuantian Tang 
> Sent: 2018年10月31日 12:48
> To: shawn...@kernel.org
> Cc: Leo Li ; robh...@kernel.org; mark.rutl...@arm.com;
> linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; rui.zh...@intel.com; daniel.lezc...@linaro.org;
> Andy Tang 
> Subject: [PATCH] arm64: dts: nxp: ls208xa: add more thermal zone support
> 
> Ls208xa has several thermal sensors. Add all the sensor id to dts to enable
> them.
> 
> To make the dts cleaner, re-organize the nodes to split out the common part so
> that it can be shared with other SoCs.
> 
> Signed-off-by: Yuantian Tang 
> ---
>  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi  |8 +-
>  arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi  |8 +-
>  arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi  |   83 +++-
>  arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi |   99 +
>  arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi |   99 +
>  arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi |   99 +
>  arch/arm64/boot/dts/freescale/fsl-tmu.dtsi  |  251
> +++
>  7 files changed, 591 insertions(+), 56 deletions(-)  create mode 100644
> arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi
>  create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi
>  create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi
>  create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu.dtsi
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> index f9c1d30..8f9788c 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> @@ -12,7 +12,7 @@
>  #include "fsl-ls208xa.dtsi"
> 
>   {
> - cpu0: cpu@0 {
> + cooling_map0: cpu0: cpu@0 {
>   device_type = "cpu";
>   compatible = "arm,cortex-a57";
>   reg = <0x0>;
> @@ -32,7 +32,7 @@
>   #cooling-cells = <2>;
>   };
> 
> - cpu2: cpu@100 {
> + cooling_map1: cpu2: cpu@100 {
>   device_type = "cpu";
>   compatible = "arm,cortex-a57";
>   reg = <0x100>;
> @@ -52,7 +52,7 @@
>   #cooling-cells = <2>;
>   };
> 
> - cpu4: cpu@200 {
> + cooling_map2: cpu4: cpu@200 {
>   device_type = "cpu";
>   compatible = "arm,cortex-a57";
>   reg = <0x200>;
> @@ -72,7 +72,7 @@
>   #cooling-cells = <2>;
>   };
> 
> - cpu6: cpu@300 {
> + cooling_map3: cpu6: cpu@300 {
>   device_type = "cpu";
>   compatible = "arm,cortex-a57";
>   reg = <0x300>;
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> index 7c882da..013fe16 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> @@ -12,7 +12,7 @@
>  #include "fsl-ls208xa.dtsi"
> 
>   {
> - cpu0: cpu@0 {
> + cooling_map0: cpu0: cpu@0 {
>   device_type = "cpu";
>   compatible = "arm,cortex-a72";
>   reg = <0x0>;
> @@ -32,7 +32,7 @@
>   #cooling-cells = <2>;
>   };
> 
> - cpu2: cpu@100 {
> + cooling_map1: cpu2: cpu@100 {
>   device_type = "cpu";
>   compatible = "arm,cortex-a72";
>   reg = <0x100>;
> @@ -52,7 +52,7 @@
>   #cooling-cells = <2>;
>   };
> 
> - cpu4: cpu@200 {
> + cooling_map2: cpu4: cpu@200 {
>   device_type = "cpu";
>   compatible = "arm,cortex-a72";
>   reg = <0x200>;
> @@ -72,7 +72,7 @@
>   #cooling-cells = <2>;
>   };
> 
> - cpu6: cpu@300 {
> + cooling_map3: cpu6: cpu@300 {
>   device_type = "cpu";
>   compatible = "arm,cortex-a72";
>   reg = <0x300>;
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> index 8cb78dd..4102317 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> @@ -75,54 +75,7 @@
>   mask = <0x2>;
>   };
> 
> - thermal-zones {
> - cpu_thermal: cpu-the

RE: [PATCH v3] thermal: qoriq: add multiple sensors support

[Andy Tang]

> -Original Message-
> From: Eduardo Valentin 
> Sent: 2018年11月30日 1:21
> To: Daniel Lezcano 
> Cc: Andy Tang ; rui.zh...@intel.com;
> linux...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v3] thermal: qoriq: add multiple sensors support
> 
> On Wed, Nov 21, 2018 at 10:41:36AM +0100, Daniel Lezcano wrote:
> > On 21/11/2018 10:16, Andy Tang wrote:
> > > Hi Daniel,
> > >
> > > Thanks for your explanation. The problem is these two trees are not synced
> well.
> > > Let's take our driver(qoriq_thermal.c) for example.
> > >
> > > Git log on Rui's tree next branch:
> > > 2dfef65 thermal: qoriq: Switch to SPDX identifier
> > > 1a893a5 thermal: qoriq: Simplify the 'site' variable assignment
> > > f1506a6 thermal: qoriq: Use devm_thermal_zone_of_sensor_register()
> > > c30d5d5 thermal: qoriq: constify thermal_zone_of_device_ops
> > > structures
> > > 0e77488 thermal: qoriq: remove useless call for
> > > of_thermal_get_trip_points()
> > > 4352844 thermal: qoriq: Add thermal management support
> > >
> > > Git log on linux-soc-thermal tree branch next:
> > > 6017e2a thermal: qoriq: add i.mx8mq support
> > > 9b96566 thermal: Convert to using %pOFn instead of device_node.name
> > > c30d5d5 thermal: qoriq: constify thermal_zone_of_device_ops
> > > structures
> > > 0e77488 thermal: qoriq: remove useless call for
> > > of_thermal_get_trip_points()
> > > 4352844 thermal: qoriq: Add thermal management support
> > >
> > > You can see that the first 2-3 commits on these two tress are different.
> > >
> > > The strange thing is they seems sync well on Linus' tree:
> > > 0ef7791 Merge branch 'linus' of
> > > git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-the
> > > rmal 6017e2a thermal: qoriq: add i.mx8mq support
> > > 9b96566 thermal: Convert to using %pOFn instead of device_node.name
> > > 2dfef65 thermal: qoriq: Switch to SPDX identifier
> > > 1a893a5 thermal: qoriq: Simplify the 'site' variable assignment
> > > f1506a6 thermal: qoriq: Use devm_thermal_zone_of_sensor_register()
> > > c30d5d5 thermal: qoriq: constify thermal_zone_of_device_ops
> > > structures
> > > 0e77488 thermal: qoriq: remove useless call for
> > > of_thermal_get_trip_points()
> > > 4352844 thermal: qoriq: Add thermal management support
> > >
> > > Currently my patch was created based on Run's tree, probably I should
> rebase it to soc tree.
> > > But whichever tree I use, it can't be merged to Linus' tree without 
> > > conflict.
> > >
> > > Something I missed?
> >
> > No.
> >
> > Eduardo, Rui,
> >
> > why not create a 'thermal' group ala 'tip' group with a single tree
> > and two branches:
> >
> > thermal/next
> > thermal/fixes
> >
> >  - Rui takes the core changes.
> >  - Eduardo takes the SoC changes.
> >
> >  - Both commit to thermal/next
> >  - Both commit to thermal/fixes
> >  - Both merge thermal/fixes into thermal/core as often as possible.
> >
> > That will help to have a more up to date branch, simplify the patch
> > submission path and reduce the latency for the merge windows.
> >
> > If you need help, I can take care of applying the fixes only and merge
> > them to thermal/next.
> >
> > That is how the tip subsystem works, Peter Ziljstra, Ingo Molnar,
> > Thomas Gleixner, have all permissions to commit in the tip tree but
> > they take care of their subsystems. If one is away for vacations or
> > whatever, someone else can take over during the absence.
> >
> 
> Yeah, that is a setup people have been following. It does not necessarily mean
> it will work for all cases though.
> 
> I believe regardless of process and tree setup what we are lacking here is a
> documentation of how things are being done.
> 
> As I mentioned, I will work on writing something up to document at least what
> we have today before any change in process gets in place.
> 
[Andy] Besides the document, what about this patch? Could it be merged before 
the document is ready?

BR,
Andy
> >
> >
> >
> >
> > >> -Original Message-
> > >> From: Daniel Lezcano 
> > >> Sent: 2018年11月21日 16:44
> > >> To: Andy Tang ; rui.zh...@intel.com;
> > >> edubez...@gmail.com
> > >> Cc: linux...@vger.kernel.org; linux-kernel@vger.kernel.org
> > >> Subject: Re: [PATCH v3] thermal: qoriq: add m

RE: [PATCH 1/2 v3] powerpc/fsl: Use new clockgen binding

[Andy Tang]

> -Original Message-
> From: Scott Wood 
> Sent: 2018年11月26日 9:19
> To: Andy Tang 
> Cc: mturque...@baylibre.com; sb...@kernel.org; robh...@kernel.org;
> mark.rutl...@arm.com; b...@kernel.crashing.org; pau...@samba.org;
> m...@ellerman.id.au; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> linuxppc-...@lists.ozlabs.org
> Subject: Re: [PATCH 1/2 v3] powerpc/fsl: Use new clockgen binding
> 
> On Wed, 2018-10-31 at 14:57 +0800, Yuantian Tang wrote:
> > From: Scott Wood 
> >
> > The driver retains compatibility with old device trees, but we don't
> > want the old nodes lying around to be copied, or used as a reference
> > (some of the mux options are incorrect), or even just being clutter.
> >
> >
> > +sysclk: sysclk {
> > +   compatible = "fixed-clock";
> > +   #clock-cells = <0>;
> > +   clock-frequency = <1>;
> > +   clock-output-names = "sysclk";
> > +};
> > +
> >  clockgen: global-utilities@e1000 {
> 
> The U-Boot fixup won't work with this.  U-Boot patches the frequency
> directly into the clockgen node (BTW, this is another reason to preserve
> the generic
> 1.0/2.0 compatible string).  The new binding does not require an input
> clock node when it is provided as clock-frequency directly in the clockgen
> node -- and the sysclk node was not in my original patch (nor did you note
> that you made changes from that original).  Why did you add it?
> 
> I would just remove it when applying, but I'm concerned that this indicates
> a lack of testing (and I don't have the hardware access to test it myself,
> except on t4240) -- unless the 100 MHz sysclk just happened to be correct
> on the machines you tested (which would also be a test coverage
> problem)?
[Andy] You are right. Sysclk may not be useful anymore. 
Uboot will fixup the clockgen node correctly. Please apply this patch without 
sysclk. We will
test it and catch the error if the clock is not fixed correctly.

BTW, which git tree are you going to apply it on? This one?
https://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git/log/?h=next

BR,
Andy
> 
> -Scott
> 

RE: [PATCH v3] thermal: qoriq: add multiple sensors support

[Andy Tang]

Hi Daniel,

Thanks for your explanation. The problem is these two trees are not synced well.
Let's take our driver(qoriq_thermal.c) for example.

Git log on Rui's tree next branch:
2dfef65 thermal: qoriq: Switch to SPDX identifier
1a893a5 thermal: qoriq: Simplify the 'site' variable assignment
f1506a6 thermal: qoriq: Use devm_thermal_zone_of_sensor_register()
c30d5d5 thermal: qoriq: constify thermal_zone_of_device_ops structures
0e77488 thermal: qoriq: remove useless call for of_thermal_get_trip_points()
4352844 thermal: qoriq: Add thermal management support

Git log on linux-soc-thermal tree branch next:
6017e2a thermal: qoriq: add i.mx8mq support
9b96566 thermal: Convert to using %pOFn instead of device_node.name
c30d5d5 thermal: qoriq: constify thermal_zone_of_device_ops structures
0e77488 thermal: qoriq: remove useless call for of_thermal_get_trip_points()
4352844 thermal: qoriq: Add thermal management support

You can see that the first 2-3 commits on these two tress are different.

The strange thing is they seems sync well on Linus' tree:
0ef7791 Merge branch 'linus' of 
git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal
6017e2a thermal: qoriq: add i.mx8mq support
9b96566 thermal: Convert to using %pOFn instead of device_node.name
2dfef65 thermal: qoriq: Switch to SPDX identifier
1a893a5 thermal: qoriq: Simplify the 'site' variable assignment
f1506a6 thermal: qoriq: Use devm_thermal_zone_of_sensor_register()
c30d5d5 thermal: qoriq: constify thermal_zone_of_device_ops structures
0e77488 thermal: qoriq: remove useless call for of_thermal_get_trip_points()
4352844 thermal: qoriq: Add thermal management support

Currently my patch was created based on Run's tree, probably I should rebase it 
to soc tree.
But whichever tree I use, it can't be merged to Linus' tree without conflict.

Something I missed?

BR,
Andy
> -Original Message-
> From: Daniel Lezcano 
> Sent: 2018年11月21日 16:44
> To: Andy Tang ; rui.zh...@intel.com;
> edubez...@gmail.com
> Cc: linux...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v3] thermal: qoriq: add multiple sensors support
> 
> On 21/11/2018 02:34, Andy Tang wrote:
> > Hi all,
> >
> > Do you have any comments on this patch?
> >
> > I found for our thermal driver(qoriq_thermal.c) there are different
> between the following two git trees:
> > git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux.git
> > branch: next
> >
> git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.gi
> t.
> > branch: next
> >
> > Could you please clarify which git tree/branch should I use?
> 
> SoC changes are submitted against linux-soc-thermal.git.
> 
> Generic thermal framework are sent against Zhang Rui's tree but it
> happens sometimes Eduardo pick them also when the changes are related
> to SoC behavior.
> 
> However, I agree that can be confusing :)
> 
> Eduardo, Rui,
> 
> how about to add a section in the maintainer handbook for the thermal to
> clarify the expectations and the flow?
> 
> >> -Original Message-
> >> From: Andy Tang
> >> Sent: 2018年11月14日 15:29
> >> To: rui.zh...@intel.com; daniel.lezc...@linaro.org
> >> Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> >> linux-kernel@vger.kernel.org
> >> Subject: RE: [PATCH v3] thermal: qoriq: add multiple sensors support
> >>
> >> PING.
> >>
> >> BR,
> >> Andy
> >>
> >>> -Original Message-
> >>> From: andy.t...@nxp.com 
> >>> Sent: 2018年10月30日 9:00
> >>> To: rui.zh...@intel.com; daniel.lezc...@linaro.org
> >>> Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> >>> linux-kernel@vger.kernel.org; Andy Tang 
> >>> Subject: [PATCH v3] thermal: qoriq: add multiple sensors support
> >>>
> >>> From: Yuantian Tang 
> >>>
> >>> The QorIQ Layerscape SoC has several thermal sensors but the
> current
> >>> driver only supports one.
> >>>
> >>> Massage the code to be sensor oriented and allow the support for
> >>> multiple sensors.
> >>>
> >>> Signed-off-by: Yuantian Tang 
> >>> Reviewed-by: Daniel Lezcano 
> >>> ---
> >>> v3:
> >>>   - add Reviewed-by
> >>> v2:
> >>>   - update the commit message
> >>>   - refine the qoriq_tmu_register_tmu_zone()
> >>>
> >>>  drivers/thermal/qoriq_thermal.c |  100
> >>> ++-
> >>>  1 files changed, 46 insertions(+), 54 deletions(-)
> >>>
> >>> diff --git a/drivers/thermal/qoriq_th

RE: [PATCH v3] thermal: qoriq: add multiple sensors support

[Andy Tang]

Hi Daniel,

Thanks for your explanation. The problem is these two trees are not synced well.
Let's take our driver(qoriq_thermal.c) for example.

Git log on Rui's tree next branch:
2dfef65 thermal: qoriq: Switch to SPDX identifier
1a893a5 thermal: qoriq: Simplify the 'site' variable assignment
f1506a6 thermal: qoriq: Use devm_thermal_zone_of_sensor_register()
c30d5d5 thermal: qoriq: constify thermal_zone_of_device_ops structures
0e77488 thermal: qoriq: remove useless call for of_thermal_get_trip_points()
4352844 thermal: qoriq: Add thermal management support

Git log on linux-soc-thermal tree branch next:
6017e2a thermal: qoriq: add i.mx8mq support
9b96566 thermal: Convert to using %pOFn instead of device_node.name
c30d5d5 thermal: qoriq: constify thermal_zone_of_device_ops structures
0e77488 thermal: qoriq: remove useless call for of_thermal_get_trip_points()
4352844 thermal: qoriq: Add thermal management support

You can see that the first 2-3 commits on these two tress are different.

The strange thing is they seems sync well on Linus' tree:
0ef7791 Merge branch 'linus' of 
git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal
6017e2a thermal: qoriq: add i.mx8mq support
9b96566 thermal: Convert to using %pOFn instead of device_node.name
2dfef65 thermal: qoriq: Switch to SPDX identifier
1a893a5 thermal: qoriq: Simplify the 'site' variable assignment
f1506a6 thermal: qoriq: Use devm_thermal_zone_of_sensor_register()
c30d5d5 thermal: qoriq: constify thermal_zone_of_device_ops structures
0e77488 thermal: qoriq: remove useless call for of_thermal_get_trip_points()
4352844 thermal: qoriq: Add thermal management support

Currently my patch was created based on Run's tree, probably I should rebase it 
to soc tree.
But whichever tree I use, it can't be merged to Linus' tree without conflict.

Something I missed?

BR,
Andy
> -Original Message-
> From: Daniel Lezcano 
> Sent: 2018年11月21日 16:44
> To: Andy Tang ; rui.zh...@intel.com;
> edubez...@gmail.com
> Cc: linux...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v3] thermal: qoriq: add multiple sensors support
> 
> On 21/11/2018 02:34, Andy Tang wrote:
> > Hi all,
> >
> > Do you have any comments on this patch?
> >
> > I found for our thermal driver(qoriq_thermal.c) there are different
> between the following two git trees:
> > git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux.git
> > branch: next
> >
> git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.gi
> t.
> > branch: next
> >
> > Could you please clarify which git tree/branch should I use?
> 
> SoC changes are submitted against linux-soc-thermal.git.
> 
> Generic thermal framework are sent against Zhang Rui's tree but it
> happens sometimes Eduardo pick them also when the changes are related
> to SoC behavior.
> 
> However, I agree that can be confusing :)
> 
> Eduardo, Rui,
> 
> how about to add a section in the maintainer handbook for the thermal to
> clarify the expectations and the flow?
> 
> >> -Original Message-
> >> From: Andy Tang
> >> Sent: 2018年11月14日 15:29
> >> To: rui.zh...@intel.com; daniel.lezc...@linaro.org
> >> Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> >> linux-kernel@vger.kernel.org
> >> Subject: RE: [PATCH v3] thermal: qoriq: add multiple sensors support
> >>
> >> PING.
> >>
> >> BR,
> >> Andy
> >>
> >>> -Original Message-
> >>> From: andy.t...@nxp.com 
> >>> Sent: 2018年10月30日 9:00
> >>> To: rui.zh...@intel.com; daniel.lezc...@linaro.org
> >>> Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> >>> linux-kernel@vger.kernel.org; Andy Tang 
> >>> Subject: [PATCH v3] thermal: qoriq: add multiple sensors support
> >>>
> >>> From: Yuantian Tang 
> >>>
> >>> The QorIQ Layerscape SoC has several thermal sensors but the
> current
> >>> driver only supports one.
> >>>
> >>> Massage the code to be sensor oriented and allow the support for
> >>> multiple sensors.
> >>>
> >>> Signed-off-by: Yuantian Tang 
> >>> Reviewed-by: Daniel Lezcano 
> >>> ---
> >>> v3:
> >>>   - add Reviewed-by
> >>> v2:
> >>>   - update the commit message
> >>>   - refine the qoriq_tmu_register_tmu_zone()
> >>>
> >>>  drivers/thermal/qoriq_thermal.c |  100
> >>> ++-
> >>>  1 files changed, 46 insertions(+), 54 deletions(-)
> >>>
> >>> diff --git a/drivers/thermal/qoriq_th

RE: [PATCH v3] thermal: qoriq: add multiple sensors support

[Andy Tang]

Hi all,

Do you have any comments on this patch?

I found for our thermal driver(qoriq_thermal.c) there are different between the 
following two git trees:
git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux.git 
branch: next  
git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git.
branch: next

Could you please clarify which git tree/branch should I use?

BR,
Andy 

> -Original Message-
> From: Andy Tang
> Sent: 2018年11月14日 15:29
> To: rui.zh...@intel.com; daniel.lezc...@linaro.org
> Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: RE: [PATCH v3] thermal: qoriq: add multiple sensors support
> 
> PING.
> 
> BR,
> Andy
> 
> > -Original Message-
> > From: andy.t...@nxp.com 
> > Sent: 2018年10月30日 9:00
> > To: rui.zh...@intel.com; daniel.lezc...@linaro.org
> > Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> > linux-kernel@vger.kernel.org; Andy Tang 
> > Subject: [PATCH v3] thermal: qoriq: add multiple sensors support
> >
> > From: Yuantian Tang 
> >
> > The QorIQ Layerscape SoC has several thermal sensors but the current
> > driver only supports one.
> >
> > Massage the code to be sensor oriented and allow the support for
> > multiple sensors.
> >
> > Signed-off-by: Yuantian Tang 
> > Reviewed-by: Daniel Lezcano 
> > ---
> > v3:
> >   - add Reviewed-by
> > v2:
> >   - update the commit message
> >   - refine the qoriq_tmu_register_tmu_zone()
> >
> >  drivers/thermal/qoriq_thermal.c |  100
> > ++-
> >  1 files changed, 46 insertions(+), 54 deletions(-)
> >
> > diff --git a/drivers/thermal/qoriq_thermal.c
> > b/drivers/thermal/qoriq_thermal.c index 450ed66..8beb344 100644
> > --- a/drivers/thermal/qoriq_thermal.c
> > +++ b/drivers/thermal/qoriq_thermal.c
> > @@ -59,14 +59,21 @@ struct qoriq_tmu_regs {
> > u32 ttr3cr; /* Temperature Range 3 Control Register */
> >  };
> >
> > +struct qoriq_tmu_data;
> > +
> >  /*
> >   * Thermal zone data
> >   */
> > +struct qoriq_sensor {
> > +   struct thermal_zone_device  *tzd;
> > +   struct qoriq_tmu_data   *qdata;
> > +   int id;
> > +};
> > +
> >  struct qoriq_tmu_data {
> > -   struct thermal_zone_device *tz;
> > struct qoriq_tmu_regs __iomem *regs;
> > -   int sensor_id;
> > bool little_endian;
> > +   struct qoriq_sensor *sensor[SITES_MAX];
> >  };
> >
> >  static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem
> > *addr) @@ -87,48 +94,51 @@ static u32 tmu_read(struct
> qoriq_tmu_data
> > *p, void __iomem *addr)
> >
> >  static int tmu_get_temp(void *p, int *temp)  {
> > +   struct qoriq_sensor *qsensor = p;
> > +   struct qoriq_tmu_data *qdata = qsensor->qdata;
> > u32 val;
> > -   struct qoriq_tmu_data *data = p;
> >
> > -   val = tmu_read(data, >regs->site[data->sensor_id].tritsr);
> > +   val = tmu_read(qdata, >regs->site[qsensor->id].tritsr);
> > *temp = (val & 0xff) * 1000;
> >
> > return 0;
> >  }
> >
> > -static int qoriq_tmu_get_sensor_id(void)
> > +static const struct thermal_zone_of_device_ops tmu_tz_ops = {
> > +   .get_temp = tmu_get_temp,
> > +};
> > +
> > +static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
> >  {
> > -   int ret, id;
> > -   struct of_phandle_args sensor_specs;
> > -   struct device_node *np, *sensor_np;
> > +   struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
> > +   int id, sites = 0;
> >
> > -   np = of_find_node_by_name(NULL, "thermal-zones");
> > -   if (!np)
> > -   return -ENODEV;
> > +   for (id = 0; id < SITES_MAX; id++) {
> > +   qdata->sensor[id] = devm_kzalloc(>dev,
> > +   sizeof(struct qoriq_sensor), GFP_KERNEL);
> > +   if (!qdata->sensor[id])
> > +   return -ENOMEM;
> >
> > -   sensor_np = of_get_next_child(np, NULL);
> > -   ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
> > -   "#thermal-sensor-cells",
> > -   0, _specs);
> > -   if (ret) {
> > -   of_node_put(np);
> > -   of_node_put(sensor_np);
> > -   return ret;
> > -   }
> > +   qdata->sensor[id]->id = id;
> &g

RE: [PATCH v3] thermal: qoriq: add multiple sensors support

[Andy Tang]

Hi all,

Do you have any comments on this patch?

I found for our thermal driver(qoriq_thermal.c) there are different between the 
following two git trees:
git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux.git 
branch: next  
git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git.
branch: next

Could you please clarify which git tree/branch should I use?

BR,
Andy 

> -Original Message-
> From: Andy Tang
> Sent: 2018年11月14日 15:29
> To: rui.zh...@intel.com; daniel.lezc...@linaro.org
> Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: RE: [PATCH v3] thermal: qoriq: add multiple sensors support
> 
> PING.
> 
> BR,
> Andy
> 
> > -Original Message-
> > From: andy.t...@nxp.com 
> > Sent: 2018年10月30日 9:00
> > To: rui.zh...@intel.com; daniel.lezc...@linaro.org
> > Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> > linux-kernel@vger.kernel.org; Andy Tang 
> > Subject: [PATCH v3] thermal: qoriq: add multiple sensors support
> >
> > From: Yuantian Tang 
> >
> > The QorIQ Layerscape SoC has several thermal sensors but the current
> > driver only supports one.
> >
> > Massage the code to be sensor oriented and allow the support for
> > multiple sensors.
> >
> > Signed-off-by: Yuantian Tang 
> > Reviewed-by: Daniel Lezcano 
> > ---
> > v3:
> >   - add Reviewed-by
> > v2:
> >   - update the commit message
> >   - refine the qoriq_tmu_register_tmu_zone()
> >
> >  drivers/thermal/qoriq_thermal.c |  100
> > ++-
> >  1 files changed, 46 insertions(+), 54 deletions(-)
> >
> > diff --git a/drivers/thermal/qoriq_thermal.c
> > b/drivers/thermal/qoriq_thermal.c index 450ed66..8beb344 100644
> > --- a/drivers/thermal/qoriq_thermal.c
> > +++ b/drivers/thermal/qoriq_thermal.c
> > @@ -59,14 +59,21 @@ struct qoriq_tmu_regs {
> > u32 ttr3cr; /* Temperature Range 3 Control Register */
> >  };
> >
> > +struct qoriq_tmu_data;
> > +
> >  /*
> >   * Thermal zone data
> >   */
> > +struct qoriq_sensor {
> > +   struct thermal_zone_device  *tzd;
> > +   struct qoriq_tmu_data   *qdata;
> > +   int id;
> > +};
> > +
> >  struct qoriq_tmu_data {
> > -   struct thermal_zone_device *tz;
> > struct qoriq_tmu_regs __iomem *regs;
> > -   int sensor_id;
> > bool little_endian;
> > +   struct qoriq_sensor *sensor[SITES_MAX];
> >  };
> >
> >  static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem
> > *addr) @@ -87,48 +94,51 @@ static u32 tmu_read(struct
> qoriq_tmu_data
> > *p, void __iomem *addr)
> >
> >  static int tmu_get_temp(void *p, int *temp)  {
> > +   struct qoriq_sensor *qsensor = p;
> > +   struct qoriq_tmu_data *qdata = qsensor->qdata;
> > u32 val;
> > -   struct qoriq_tmu_data *data = p;
> >
> > -   val = tmu_read(data, >regs->site[data->sensor_id].tritsr);
> > +   val = tmu_read(qdata, >regs->site[qsensor->id].tritsr);
> > *temp = (val & 0xff) * 1000;
> >
> > return 0;
> >  }
> >
> > -static int qoriq_tmu_get_sensor_id(void)
> > +static const struct thermal_zone_of_device_ops tmu_tz_ops = {
> > +   .get_temp = tmu_get_temp,
> > +};
> > +
> > +static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
> >  {
> > -   int ret, id;
> > -   struct of_phandle_args sensor_specs;
> > -   struct device_node *np, *sensor_np;
> > +   struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
> > +   int id, sites = 0;
> >
> > -   np = of_find_node_by_name(NULL, "thermal-zones");
> > -   if (!np)
> > -   return -ENODEV;
> > +   for (id = 0; id < SITES_MAX; id++) {
> > +   qdata->sensor[id] = devm_kzalloc(>dev,
> > +   sizeof(struct qoriq_sensor), GFP_KERNEL);
> > +   if (!qdata->sensor[id])
> > +   return -ENOMEM;
> >
> > -   sensor_np = of_get_next_child(np, NULL);
> > -   ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
> > -   "#thermal-sensor-cells",
> > -   0, _specs);
> > -   if (ret) {
> > -   of_node_put(np);
> > -   of_node_put(sensor_np);
> > -   return ret;
> > -   }
> > +   qdata->sensor[id]->id = id;
> &g

RE: [PATCH v3] thermal: qoriq: add multiple sensors support

[Andy Tang]

PING.

BR,
Andy

> -Original Message-
> From: andy.t...@nxp.com 
> Sent: 2018年10月30日 9:00
> To: rui.zh...@intel.com; daniel.lezc...@linaro.org
> Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Andy Tang 
> Subject: [PATCH v3] thermal: qoriq: add multiple sensors support
> 
> From: Yuantian Tang 
> 
> The QorIQ Layerscape SoC has several thermal sensors but the current
> driver only supports one.
> 
> Massage the code to be sensor oriented and allow the support for
> multiple sensors.
> 
> Signed-off-by: Yuantian Tang 
> Reviewed-by: Daniel Lezcano 
> ---
> v3:
>   - add Reviewed-by
> v2:
>   - update the commit message
>   - refine the qoriq_tmu_register_tmu_zone()
> 
>  drivers/thermal/qoriq_thermal.c |  100
> ++-
>  1 files changed, 46 insertions(+), 54 deletions(-)
> 
> diff --git a/drivers/thermal/qoriq_thermal.c
> b/drivers/thermal/qoriq_thermal.c index 450ed66..8beb344 100644
> --- a/drivers/thermal/qoriq_thermal.c
> +++ b/drivers/thermal/qoriq_thermal.c
> @@ -59,14 +59,21 @@ struct qoriq_tmu_regs {
>   u32 ttr3cr; /* Temperature Range 3 Control Register */
>  };
> 
> +struct qoriq_tmu_data;
> +
>  /*
>   * Thermal zone data
>   */
> +struct qoriq_sensor {
> + struct thermal_zone_device  *tzd;
> + struct qoriq_tmu_data   *qdata;
> + int id;
> +};
> +
>  struct qoriq_tmu_data {
> - struct thermal_zone_device *tz;
>   struct qoriq_tmu_regs __iomem *regs;
> - int sensor_id;
>   bool little_endian;
> + struct qoriq_sensor *sensor[SITES_MAX];
>  };
> 
>  static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem
> *addr) @@ -87,48 +94,51 @@ static u32 tmu_read(struct
> qoriq_tmu_data *p, void __iomem *addr)
> 
>  static int tmu_get_temp(void *p, int *temp)  {
> + struct qoriq_sensor *qsensor = p;
> + struct qoriq_tmu_data *qdata = qsensor->qdata;
>   u32 val;
> - struct qoriq_tmu_data *data = p;
> 
> - val = tmu_read(data, >regs->site[data->sensor_id].tritsr);
> + val = tmu_read(qdata, >regs->site[qsensor->id].tritsr);
>   *temp = (val & 0xff) * 1000;
> 
>   return 0;
>  }
> 
> -static int qoriq_tmu_get_sensor_id(void)
> +static const struct thermal_zone_of_device_ops tmu_tz_ops = {
> + .get_temp = tmu_get_temp,
> +};
> +
> +static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
>  {
> - int ret, id;
> - struct of_phandle_args sensor_specs;
> - struct device_node *np, *sensor_np;
> + struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
> + int id, sites = 0;
> 
> - np = of_find_node_by_name(NULL, "thermal-zones");
> - if (!np)
> - return -ENODEV;
> + for (id = 0; id < SITES_MAX; id++) {
> + qdata->sensor[id] = devm_kzalloc(>dev,
> + sizeof(struct qoriq_sensor), GFP_KERNEL);
> + if (!qdata->sensor[id])
> + return -ENOMEM;
> 
> - sensor_np = of_get_next_child(np, NULL);
> - ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
> - "#thermal-sensor-cells",
> - 0, _specs);
> - if (ret) {
> - of_node_put(np);
> - of_node_put(sensor_np);
> - return ret;
> - }
> + qdata->sensor[id]->id = id;
> + qdata->sensor[id]->qdata = qdata;
> 
> - if (sensor_specs.args_count >= 1) {
> - id = sensor_specs.args[0];
> - WARN(sensor_specs.args_count > 1,
> - "%s: too many cells in sensor specifier %d\n",
> - sensor_specs.np->name, sensor_specs.args_count);
> - } else {
> - id = 0;
> - }
> + qdata->sensor[id]->tzd =
> devm_thermal_zone_of_sensor_register(
> + >dev, id, qdata->sensor[id], _tz_ops);
> + if (IS_ERR(qdata->sensor[id]->tzd)) {
> + if (PTR_ERR(qdata->sensor[id]->tzd) == -ENODEV)
> + continue;
> + else
> + return PTR_ERR(qdata->sensor[id]->tzd);
> 
> - of_node_put(np);
> - of_node_put(sensor_np);
> + }
> +
> + sites |= 0x1 << (15 - id);
> + }
> + /* Enable monitoring */
> + if (sites != 0)
> + tmu_write(qdata, sites | 

RE: [PATCH v3] thermal: qoriq: add multiple sensors support

[Andy Tang]

PING.

BR,
Andy

> -Original Message-
> From: andy.t...@nxp.com 
> Sent: 2018年10月30日 9:00
> To: rui.zh...@intel.com; daniel.lezc...@linaro.org
> Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Andy Tang 
> Subject: [PATCH v3] thermal: qoriq: add multiple sensors support
> 
> From: Yuantian Tang 
> 
> The QorIQ Layerscape SoC has several thermal sensors but the current
> driver only supports one.
> 
> Massage the code to be sensor oriented and allow the support for
> multiple sensors.
> 
> Signed-off-by: Yuantian Tang 
> Reviewed-by: Daniel Lezcano 
> ---
> v3:
>   - add Reviewed-by
> v2:
>   - update the commit message
>   - refine the qoriq_tmu_register_tmu_zone()
> 
>  drivers/thermal/qoriq_thermal.c |  100
> ++-
>  1 files changed, 46 insertions(+), 54 deletions(-)
> 
> diff --git a/drivers/thermal/qoriq_thermal.c
> b/drivers/thermal/qoriq_thermal.c index 450ed66..8beb344 100644
> --- a/drivers/thermal/qoriq_thermal.c
> +++ b/drivers/thermal/qoriq_thermal.c
> @@ -59,14 +59,21 @@ struct qoriq_tmu_regs {
>   u32 ttr3cr; /* Temperature Range 3 Control Register */
>  };
> 
> +struct qoriq_tmu_data;
> +
>  /*
>   * Thermal zone data
>   */
> +struct qoriq_sensor {
> + struct thermal_zone_device  *tzd;
> + struct qoriq_tmu_data   *qdata;
> + int id;
> +};
> +
>  struct qoriq_tmu_data {
> - struct thermal_zone_device *tz;
>   struct qoriq_tmu_regs __iomem *regs;
> - int sensor_id;
>   bool little_endian;
> + struct qoriq_sensor *sensor[SITES_MAX];
>  };
> 
>  static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem
> *addr) @@ -87,48 +94,51 @@ static u32 tmu_read(struct
> qoriq_tmu_data *p, void __iomem *addr)
> 
>  static int tmu_get_temp(void *p, int *temp)  {
> + struct qoriq_sensor *qsensor = p;
> + struct qoriq_tmu_data *qdata = qsensor->qdata;
>   u32 val;
> - struct qoriq_tmu_data *data = p;
> 
> - val = tmu_read(data, >regs->site[data->sensor_id].tritsr);
> + val = tmu_read(qdata, >regs->site[qsensor->id].tritsr);
>   *temp = (val & 0xff) * 1000;
> 
>   return 0;
>  }
> 
> -static int qoriq_tmu_get_sensor_id(void)
> +static const struct thermal_zone_of_device_ops tmu_tz_ops = {
> + .get_temp = tmu_get_temp,
> +};
> +
> +static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
>  {
> - int ret, id;
> - struct of_phandle_args sensor_specs;
> - struct device_node *np, *sensor_np;
> + struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
> + int id, sites = 0;
> 
> - np = of_find_node_by_name(NULL, "thermal-zones");
> - if (!np)
> - return -ENODEV;
> + for (id = 0; id < SITES_MAX; id++) {
> + qdata->sensor[id] = devm_kzalloc(>dev,
> + sizeof(struct qoriq_sensor), GFP_KERNEL);
> + if (!qdata->sensor[id])
> + return -ENOMEM;
> 
> - sensor_np = of_get_next_child(np, NULL);
> - ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
> - "#thermal-sensor-cells",
> - 0, _specs);
> - if (ret) {
> - of_node_put(np);
> - of_node_put(sensor_np);
> - return ret;
> - }
> + qdata->sensor[id]->id = id;
> + qdata->sensor[id]->qdata = qdata;
> 
> - if (sensor_specs.args_count >= 1) {
> - id = sensor_specs.args[0];
> - WARN(sensor_specs.args_count > 1,
> - "%s: too many cells in sensor specifier %d\n",
> - sensor_specs.np->name, sensor_specs.args_count);
> - } else {
> - id = 0;
> - }
> + qdata->sensor[id]->tzd =
> devm_thermal_zone_of_sensor_register(
> + >dev, id, qdata->sensor[id], _tz_ops);
> + if (IS_ERR(qdata->sensor[id]->tzd)) {
> + if (PTR_ERR(qdata->sensor[id]->tzd) == -ENODEV)
> + continue;
> + else
> + return PTR_ERR(qdata->sensor[id]->tzd);
> 
> - of_node_put(np);
> - of_node_put(sensor_np);
> + }
> +
> + sites |= 0x1 << (15 - id);
> + }
> + /* Enable monitoring */
> + if (sites != 0)
> + tmu_write(qdata, sites | 

RE: [PATCH v3] clk: qoriq: add more chips support

[Andy Tang]

Hi Stephen,

> -Original Message-
> From: Stephen Boyd 
> Sent: 2018年11月7日 1:25
> To: Andy Tang ; mturque...@baylibre.com
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Andy Tang
> 
> Subject: Re: [PATCH v3] clk: qoriq: add more chips support
> 
> Quoting Yuantian Tang (2018-10-31 00:46:16)
> > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> > 4c30b6e..5baa9e0 100644
> > --- a/drivers/clk/clk-qoriq.c
> > +++ b/drivers/clk/clk-qoriq.c
> > @@ -1418,12 +1418,23 @@ static void __init clockgen_init(struct
> > device_node *np)
> >
> >  CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0",
> > clockgen_init);  CLK_OF_DECLARE(qoriq_clockgen_2,
> > "fsl,qoriq-clockgen-2.0", clockgen_init);
> > +CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen",
> > +clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_b4860,
> > +"fsl,b4860-clockgen", clockgen_init);
> >  CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen",
> > clockgen_init);  CLK_OF_DECLARE(qoriq_clockgen_ls1021a,
> > "fsl,ls1021a-clockgen", clockgen_init);
> > CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen",
> > clockgen_init);  CLK_OF_DECLARE(qoriq_clockgen_ls1046a,
> > "fsl,ls1046a-clockgen", clockgen_init);
> > CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen",
> > clockgen_init);  CLK_OF_DECLARE(qoriq_clockgen_ls2080a,
> > "fsl,ls2080a-clockgen", clockgen_init);
> > +CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen",
> > +clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_p3041,
> > +"fsl,p3041-clockgen", clockgen_init);
> > +CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen",
> > +clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_p5020,
> > +"fsl,p5020-clockgen", clockgen_init);
> > +CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen",
> > +clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_t1023,
> > +"fsl,t1023-clockgen", clockgen_init);
> > +CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen",
> > +clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_t2080,
> > +"fsl,t2080-clockgen", clockgen_init);
> > +CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen",
> > +clockgen_init);
> 
> Some of these compatibles aren't documented. What happened to the
> binding patch to add more compatible strings?
Nothing happened. Binding patch will be merged to PowerPC tree soon. But it 
will take time to
get to mainline tree or your tree.

BR,
Andy

RE: [PATCH v3] clk: qoriq: add more chips support

[Andy Tang]

Hi Stephen,

> -Original Message-
> From: Stephen Boyd 
> Sent: 2018年11月7日 1:25
> To: Andy Tang ; mturque...@baylibre.com
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Andy Tang
> 
> Subject: Re: [PATCH v3] clk: qoriq: add more chips support
> 
> Quoting Yuantian Tang (2018-10-31 00:46:16)
> > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> > 4c30b6e..5baa9e0 100644
> > --- a/drivers/clk/clk-qoriq.c
> > +++ b/drivers/clk/clk-qoriq.c
> > @@ -1418,12 +1418,23 @@ static void __init clockgen_init(struct
> > device_node *np)
> >
> >  CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0",
> > clockgen_init);  CLK_OF_DECLARE(qoriq_clockgen_2,
> > "fsl,qoriq-clockgen-2.0", clockgen_init);
> > +CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen",
> > +clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_b4860,
> > +"fsl,b4860-clockgen", clockgen_init);
> >  CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen",
> > clockgen_init);  CLK_OF_DECLARE(qoriq_clockgen_ls1021a,
> > "fsl,ls1021a-clockgen", clockgen_init);
> > CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen",
> > clockgen_init);  CLK_OF_DECLARE(qoriq_clockgen_ls1046a,
> > "fsl,ls1046a-clockgen", clockgen_init);
> > CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen",
> > clockgen_init);  CLK_OF_DECLARE(qoriq_clockgen_ls2080a,
> > "fsl,ls2080a-clockgen", clockgen_init);
> > +CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen",
> > +clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_p3041,
> > +"fsl,p3041-clockgen", clockgen_init);
> > +CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen",
> > +clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_p5020,
> > +"fsl,p5020-clockgen", clockgen_init);
> > +CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen",
> > +clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_t1023,
> > +"fsl,t1023-clockgen", clockgen_init);
> > +CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen",
> > +clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_t2080,
> > +"fsl,t2080-clockgen", clockgen_init);
> > +CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen",
> > +clockgen_init);
> 
> Some of these compatibles aren't documented. What happened to the
> binding patch to add more compatible strings?
Nothing happened. Binding patch will be merged to PowerPC tree soon. But it 
will take time to
get to mainline tree or your tree.

BR,
Andy

[PATCH v3] thermal: qoriq: add multiple sensors support

[andy . tang]

From: Yuantian Tang 

The QorIQ Layerscape SoC has several thermal sensors but the current
driver only supports one.

Massage the code to be sensor oriented and allow the support for
multiple sensors.

Signed-off-by: Yuantian Tang 
Reviewed-by: Daniel Lezcano 
---
v3:
  - add Reviewed-by
v2:
  - update the commit message
  - refine the qoriq_tmu_register_tmu_zone()

 drivers/thermal/qoriq_thermal.c |  100 ++-
 1 files changed, 46 insertions(+), 54 deletions(-)

diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
index 450ed66..8beb344 100644
--- a/drivers/thermal/qoriq_thermal.c
+++ b/drivers/thermal/qoriq_thermal.c
@@ -59,14 +59,21 @@ struct qoriq_tmu_regs {
u32 ttr3cr; /* Temperature Range 3 Control Register */
 };
 
+struct qoriq_tmu_data;
+
 /*
  * Thermal zone data
  */
+struct qoriq_sensor {
+   struct thermal_zone_device  *tzd;
+   struct qoriq_tmu_data   *qdata;
+   int id;
+};
+
 struct qoriq_tmu_data {
-   struct thermal_zone_device *tz;
struct qoriq_tmu_regs __iomem *regs;
-   int sensor_id;
bool little_endian;
+   struct qoriq_sensor *sensor[SITES_MAX];
 };
 
 static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr)
@@ -87,48 +94,51 @@ static u32 tmu_read(struct qoriq_tmu_data *p, void __iomem 
*addr)
 
 static int tmu_get_temp(void *p, int *temp)
 {
+   struct qoriq_sensor *qsensor = p;
+   struct qoriq_tmu_data *qdata = qsensor->qdata;
u32 val;
-   struct qoriq_tmu_data *data = p;
 
-   val = tmu_read(data, >regs->site[data->sensor_id].tritsr);
+   val = tmu_read(qdata, >regs->site[qsensor->id].tritsr);
*temp = (val & 0xff) * 1000;
 
return 0;
 }
 
-static int qoriq_tmu_get_sensor_id(void)
+static const struct thermal_zone_of_device_ops tmu_tz_ops = {
+   .get_temp = tmu_get_temp,
+};
+
+static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
 {
-   int ret, id;
-   struct of_phandle_args sensor_specs;
-   struct device_node *np, *sensor_np;
+   struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
+   int id, sites = 0;
 
-   np = of_find_node_by_name(NULL, "thermal-zones");
-   if (!np)
-   return -ENODEV;
+   for (id = 0; id < SITES_MAX; id++) {
+   qdata->sensor[id] = devm_kzalloc(>dev,
+   sizeof(struct qoriq_sensor), GFP_KERNEL);
+   if (!qdata->sensor[id])
+   return -ENOMEM;
 
-   sensor_np = of_get_next_child(np, NULL);
-   ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
-   "#thermal-sensor-cells",
-   0, _specs);
-   if (ret) {
-   of_node_put(np);
-   of_node_put(sensor_np);
-   return ret;
-   }
+   qdata->sensor[id]->id = id;
+   qdata->sensor[id]->qdata = qdata;
 
-   if (sensor_specs.args_count >= 1) {
-   id = sensor_specs.args[0];
-   WARN(sensor_specs.args_count > 1,
-   "%s: too many cells in sensor specifier %d\n",
-   sensor_specs.np->name, sensor_specs.args_count);
-   } else {
-   id = 0;
-   }
+   qdata->sensor[id]->tzd = devm_thermal_zone_of_sensor_register(
+   >dev, id, qdata->sensor[id], _tz_ops);
+   if (IS_ERR(qdata->sensor[id]->tzd)) {
+   if (PTR_ERR(qdata->sensor[id]->tzd) == -ENODEV)
+   continue;
+   else
+   return PTR_ERR(qdata->sensor[id]->tzd);
 
-   of_node_put(np);
-   of_node_put(sensor_np);
+   }
+
+   sites |= 0x1 << (15 - id);
+   }
+   /* Enable monitoring */
+   if (sites != 0)
+   tmu_write(qdata, sites | TMR_ME | TMR_ALPF, >regs->tmr);
 
-   return id;
+   return 0;
 }
 
 static int qoriq_tmu_calibration(struct platform_device *pdev)
@@ -178,16 +188,11 @@ static void qoriq_tmu_init_device(struct qoriq_tmu_data 
*data)
tmu_write(data, TMR_DISABLE, >regs->tmr);
 }
 
-static const struct thermal_zone_of_device_ops tmu_tz_ops = {
-   .get_temp = tmu_get_temp,
-};
-
 static int qoriq_tmu_probe(struct platform_device *pdev)
 {
int ret;
struct qoriq_tmu_data *data;
struct device_node *np = pdev->dev.of_node;
-   u32 site;
 
if (!np) {
dev_err(>dev, "Device OF-Node is NULL");
@@ -203,13 +208,6 @@ static int qoriq_tmu_probe(struct platform_device *pdev)
 
data->little_endian = of_property_read_bool(np, "little-endian");
 
-   data->sensor_id = qoriq_tmu_get_sensor_id();
-   if (data->sensor_id < 0) {
-   dev_err(>dev, "Failed to get sensor id\n");
- 

[PATCH v3] thermal: qoriq: add multiple sensors support

[andy . tang]

From: Yuantian Tang 

The QorIQ Layerscape SoC has several thermal sensors but the current
driver only supports one.

Massage the code to be sensor oriented and allow the support for
multiple sensors.

Signed-off-by: Yuantian Tang 
Reviewed-by: Daniel Lezcano 
---
v3:
  - add Reviewed-by
v2:
  - update the commit message
  - refine the qoriq_tmu_register_tmu_zone()

 drivers/thermal/qoriq_thermal.c |  100 ++-
 1 files changed, 46 insertions(+), 54 deletions(-)

diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
index 450ed66..8beb344 100644
--- a/drivers/thermal/qoriq_thermal.c
+++ b/drivers/thermal/qoriq_thermal.c
@@ -59,14 +59,21 @@ struct qoriq_tmu_regs {
u32 ttr3cr; /* Temperature Range 3 Control Register */
 };
 
+struct qoriq_tmu_data;
+
 /*
  * Thermal zone data
  */
+struct qoriq_sensor {
+   struct thermal_zone_device  *tzd;
+   struct qoriq_tmu_data   *qdata;
+   int id;
+};
+
 struct qoriq_tmu_data {
-   struct thermal_zone_device *tz;
struct qoriq_tmu_regs __iomem *regs;
-   int sensor_id;
bool little_endian;
+   struct qoriq_sensor *sensor[SITES_MAX];
 };
 
 static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr)
@@ -87,48 +94,51 @@ static u32 tmu_read(struct qoriq_tmu_data *p, void __iomem 
*addr)
 
 static int tmu_get_temp(void *p, int *temp)
 {
+   struct qoriq_sensor *qsensor = p;
+   struct qoriq_tmu_data *qdata = qsensor->qdata;
u32 val;
-   struct qoriq_tmu_data *data = p;
 
-   val = tmu_read(data, >regs->site[data->sensor_id].tritsr);
+   val = tmu_read(qdata, >regs->site[qsensor->id].tritsr);
*temp = (val & 0xff) * 1000;
 
return 0;
 }
 
-static int qoriq_tmu_get_sensor_id(void)
+static const struct thermal_zone_of_device_ops tmu_tz_ops = {
+   .get_temp = tmu_get_temp,
+};
+
+static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
 {
-   int ret, id;
-   struct of_phandle_args sensor_specs;
-   struct device_node *np, *sensor_np;
+   struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
+   int id, sites = 0;
 
-   np = of_find_node_by_name(NULL, "thermal-zones");
-   if (!np)
-   return -ENODEV;
+   for (id = 0; id < SITES_MAX; id++) {
+   qdata->sensor[id] = devm_kzalloc(>dev,
+   sizeof(struct qoriq_sensor), GFP_KERNEL);
+   if (!qdata->sensor[id])
+   return -ENOMEM;
 
-   sensor_np = of_get_next_child(np, NULL);
-   ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
-   "#thermal-sensor-cells",
-   0, _specs);
-   if (ret) {
-   of_node_put(np);
-   of_node_put(sensor_np);
-   return ret;
-   }
+   qdata->sensor[id]->id = id;
+   qdata->sensor[id]->qdata = qdata;
 
-   if (sensor_specs.args_count >= 1) {
-   id = sensor_specs.args[0];
-   WARN(sensor_specs.args_count > 1,
-   "%s: too many cells in sensor specifier %d\n",
-   sensor_specs.np->name, sensor_specs.args_count);
-   } else {
-   id = 0;
-   }
+   qdata->sensor[id]->tzd = devm_thermal_zone_of_sensor_register(
+   >dev, id, qdata->sensor[id], _tz_ops);
+   if (IS_ERR(qdata->sensor[id]->tzd)) {
+   if (PTR_ERR(qdata->sensor[id]->tzd) == -ENODEV)
+   continue;
+   else
+   return PTR_ERR(qdata->sensor[id]->tzd);
 
-   of_node_put(np);
-   of_node_put(sensor_np);
+   }
+
+   sites |= 0x1 << (15 - id);
+   }
+   /* Enable monitoring */
+   if (sites != 0)
+   tmu_write(qdata, sites | TMR_ME | TMR_ALPF, >regs->tmr);
 
-   return id;
+   return 0;
 }
 
 static int qoriq_tmu_calibration(struct platform_device *pdev)
@@ -178,16 +188,11 @@ static void qoriq_tmu_init_device(struct qoriq_tmu_data 
*data)
tmu_write(data, TMR_DISABLE, >regs->tmr);
 }
 
-static const struct thermal_zone_of_device_ops tmu_tz_ops = {
-   .get_temp = tmu_get_temp,
-};
-
 static int qoriq_tmu_probe(struct platform_device *pdev)
 {
int ret;
struct qoriq_tmu_data *data;
struct device_node *np = pdev->dev.of_node;
-   u32 site;
 
if (!np) {
dev_err(>dev, "Device OF-Node is NULL");
@@ -203,13 +208,6 @@ static int qoriq_tmu_probe(struct platform_device *pdev)
 
data->little_endian = of_property_read_bool(np, "little-endian");
 
-   data->sensor_id = qoriq_tmu_get_sensor_id();
-   if (data->sensor_id < 0) {
-   dev_err(>dev, "Failed to get sensor id\n");
- 

[PATCH v2] thermal: qoriq: add multiple sensors support

[andy . tang]

From: Yuantian Tang 

The QorIQ Layerscape SoC has several thermal sensors but the current
driver only supports one.

Massage the code to be sensor oriented and allow the support for
multiple sensors.

Signed-off-by: Yuantian Tang 
---
v2:
  - update the commit message
  - refine the qoriq_tmu_register_tmu_zone()

 drivers/thermal/qoriq_thermal.c |  100 ++-
 1 files changed, 46 insertions(+), 54 deletions(-)

diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
index 450ed66..8beb344 100644
--- a/drivers/thermal/qoriq_thermal.c
+++ b/drivers/thermal/qoriq_thermal.c
@@ -59,14 +59,21 @@ struct qoriq_tmu_regs {
u32 ttr3cr; /* Temperature Range 3 Control Register */
 };
 
+struct qoriq_tmu_data;
+
 /*
  * Thermal zone data
  */
+struct qoriq_sensor {
+   struct thermal_zone_device  *tzd;
+   struct qoriq_tmu_data   *qdata;
+   int id;
+};
+
 struct qoriq_tmu_data {
-   struct thermal_zone_device *tz;
struct qoriq_tmu_regs __iomem *regs;
-   int sensor_id;
bool little_endian;
+   struct qoriq_sensor *sensor[SITES_MAX];
 };
 
 static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr)
@@ -87,48 +94,51 @@ static u32 tmu_read(struct qoriq_tmu_data *p, void __iomem 
*addr)
 
 static int tmu_get_temp(void *p, int *temp)
 {
+   struct qoriq_sensor *qsensor = p;
+   struct qoriq_tmu_data *qdata = qsensor->qdata;
u32 val;
-   struct qoriq_tmu_data *data = p;
 
-   val = tmu_read(data, >regs->site[data->sensor_id].tritsr);
+   val = tmu_read(qdata, >regs->site[qsensor->id].tritsr);
*temp = (val & 0xff) * 1000;
 
return 0;
 }
 
-static int qoriq_tmu_get_sensor_id(void)
+static const struct thermal_zone_of_device_ops tmu_tz_ops = {
+   .get_temp = tmu_get_temp,
+};
+
+static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
 {
-   int ret, id;
-   struct of_phandle_args sensor_specs;
-   struct device_node *np, *sensor_np;
+   struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
+   int id, sites = 0;
 
-   np = of_find_node_by_name(NULL, "thermal-zones");
-   if (!np)
-   return -ENODEV;
+   for (id = 0; id < SITES_MAX; id++) {
+   qdata->sensor[id] = devm_kzalloc(>dev,
+   sizeof(struct qoriq_sensor), GFP_KERNEL);
+   if (!qdata->sensor[id])
+   return -ENOMEM;
 
-   sensor_np = of_get_next_child(np, NULL);
-   ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
-   "#thermal-sensor-cells",
-   0, _specs);
-   if (ret) {
-   of_node_put(np);
-   of_node_put(sensor_np);
-   return ret;
-   }
+   qdata->sensor[id]->id = id;
+   qdata->sensor[id]->qdata = qdata;
 
-   if (sensor_specs.args_count >= 1) {
-   id = sensor_specs.args[0];
-   WARN(sensor_specs.args_count > 1,
-   "%s: too many cells in sensor specifier %d\n",
-   sensor_specs.np->name, sensor_specs.args_count);
-   } else {
-   id = 0;
-   }
+   qdata->sensor[id]->tzd = devm_thermal_zone_of_sensor_register(
+   >dev, id, qdata->sensor[id], _tz_ops);
+   if (IS_ERR(qdata->sensor[id]->tzd)) {
+   if (PTR_ERR(qdata->sensor[id]->tzd) == -ENODEV)
+   continue;
+   else
+   return PTR_ERR(qdata->sensor[id]->tzd);
 
-   of_node_put(np);
-   of_node_put(sensor_np);
+   }
+
+   sites |= 0x1 << (15 - id);
+   }
+   /* Enable monitoring */
+   if (sites != 0)
+   tmu_write(qdata, sites | TMR_ME | TMR_ALPF, >regs->tmr);
 
-   return id;
+   return 0;
 }
 
 static int qoriq_tmu_calibration(struct platform_device *pdev)
@@ -178,16 +188,11 @@ static void qoriq_tmu_init_device(struct qoriq_tmu_data 
*data)
tmu_write(data, TMR_DISABLE, >regs->tmr);
 }
 
-static const struct thermal_zone_of_device_ops tmu_tz_ops = {
-   .get_temp = tmu_get_temp,
-};
-
 static int qoriq_tmu_probe(struct platform_device *pdev)
 {
int ret;
struct qoriq_tmu_data *data;
struct device_node *np = pdev->dev.of_node;
-   u32 site;
 
if (!np) {
dev_err(>dev, "Device OF-Node is NULL");
@@ -203,13 +208,6 @@ static int qoriq_tmu_probe(struct platform_device *pdev)
 
data->little_endian = of_property_read_bool(np, "little-endian");
 
-   data->sensor_id = qoriq_tmu_get_sensor_id();
-   if (data->sensor_id < 0) {
-   dev_err(>dev, "Failed to get sensor id\n");
-   ret = -ENODEV;
-   goto err_iomap;
-   

[PATCH v2] thermal: qoriq: add multiple sensors support

[andy . tang]

From: Yuantian Tang 

The QorIQ Layerscape SoC has several thermal sensors but the current
driver only supports one.

Massage the code to be sensor oriented and allow the support for
multiple sensors.

Signed-off-by: Yuantian Tang 
---
v2:
  - update the commit message
  - refine the qoriq_tmu_register_tmu_zone()

 drivers/thermal/qoriq_thermal.c |  100 ++-
 1 files changed, 46 insertions(+), 54 deletions(-)

diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
index 450ed66..8beb344 100644
--- a/drivers/thermal/qoriq_thermal.c
+++ b/drivers/thermal/qoriq_thermal.c
@@ -59,14 +59,21 @@ struct qoriq_tmu_regs {
u32 ttr3cr; /* Temperature Range 3 Control Register */
 };
 
+struct qoriq_tmu_data;
+
 /*
  * Thermal zone data
  */
+struct qoriq_sensor {
+   struct thermal_zone_device  *tzd;
+   struct qoriq_tmu_data   *qdata;
+   int id;
+};
+
 struct qoriq_tmu_data {
-   struct thermal_zone_device *tz;
struct qoriq_tmu_regs __iomem *regs;
-   int sensor_id;
bool little_endian;
+   struct qoriq_sensor *sensor[SITES_MAX];
 };
 
 static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr)
@@ -87,48 +94,51 @@ static u32 tmu_read(struct qoriq_tmu_data *p, void __iomem 
*addr)
 
 static int tmu_get_temp(void *p, int *temp)
 {
+   struct qoriq_sensor *qsensor = p;
+   struct qoriq_tmu_data *qdata = qsensor->qdata;
u32 val;
-   struct qoriq_tmu_data *data = p;
 
-   val = tmu_read(data, >regs->site[data->sensor_id].tritsr);
+   val = tmu_read(qdata, >regs->site[qsensor->id].tritsr);
*temp = (val & 0xff) * 1000;
 
return 0;
 }
 
-static int qoriq_tmu_get_sensor_id(void)
+static const struct thermal_zone_of_device_ops tmu_tz_ops = {
+   .get_temp = tmu_get_temp,
+};
+
+static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
 {
-   int ret, id;
-   struct of_phandle_args sensor_specs;
-   struct device_node *np, *sensor_np;
+   struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
+   int id, sites = 0;
 
-   np = of_find_node_by_name(NULL, "thermal-zones");
-   if (!np)
-   return -ENODEV;
+   for (id = 0; id < SITES_MAX; id++) {
+   qdata->sensor[id] = devm_kzalloc(>dev,
+   sizeof(struct qoriq_sensor), GFP_KERNEL);
+   if (!qdata->sensor[id])
+   return -ENOMEM;
 
-   sensor_np = of_get_next_child(np, NULL);
-   ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
-   "#thermal-sensor-cells",
-   0, _specs);
-   if (ret) {
-   of_node_put(np);
-   of_node_put(sensor_np);
-   return ret;
-   }
+   qdata->sensor[id]->id = id;
+   qdata->sensor[id]->qdata = qdata;
 
-   if (sensor_specs.args_count >= 1) {
-   id = sensor_specs.args[0];
-   WARN(sensor_specs.args_count > 1,
-   "%s: too many cells in sensor specifier %d\n",
-   sensor_specs.np->name, sensor_specs.args_count);
-   } else {
-   id = 0;
-   }
+   qdata->sensor[id]->tzd = devm_thermal_zone_of_sensor_register(
+   >dev, id, qdata->sensor[id], _tz_ops);
+   if (IS_ERR(qdata->sensor[id]->tzd)) {
+   if (PTR_ERR(qdata->sensor[id]->tzd) == -ENODEV)
+   continue;
+   else
+   return PTR_ERR(qdata->sensor[id]->tzd);
 
-   of_node_put(np);
-   of_node_put(sensor_np);
+   }
+
+   sites |= 0x1 << (15 - id);
+   }
+   /* Enable monitoring */
+   if (sites != 0)
+   tmu_write(qdata, sites | TMR_ME | TMR_ALPF, >regs->tmr);
 
-   return id;
+   return 0;
 }
 
 static int qoriq_tmu_calibration(struct platform_device *pdev)
@@ -178,16 +188,11 @@ static void qoriq_tmu_init_device(struct qoriq_tmu_data 
*data)
tmu_write(data, TMR_DISABLE, >regs->tmr);
 }
 
-static const struct thermal_zone_of_device_ops tmu_tz_ops = {
-   .get_temp = tmu_get_temp,
-};
-
 static int qoriq_tmu_probe(struct platform_device *pdev)
 {
int ret;
struct qoriq_tmu_data *data;
struct device_node *np = pdev->dev.of_node;
-   u32 site;
 
if (!np) {
dev_err(>dev, "Device OF-Node is NULL");
@@ -203,13 +208,6 @@ static int qoriq_tmu_probe(struct platform_device *pdev)
 
data->little_endian = of_property_read_bool(np, "little-endian");
 
-   data->sensor_id = qoriq_tmu_get_sensor_id();
-   if (data->sensor_id < 0) {
-   dev_err(>dev, "Failed to get sensor id\n");
-   ret = -ENODEV;
-   goto err_iomap;
-   

RE: [PATCH] thermal: qoriq: add multiple sensors support

[Andy Tang]

Hi Daniel,

> -Original Message-
> From: Daniel Lezcano 
> Sent: 2018年10月16日 19:21
> To: Andy Tang ; rui.zh...@intel.com
> Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Rob Herring 
> Subject: Re: [PATCH] thermal: qoriq: add multiple sensors support
> 
> >>>> The current code is reading the DT in order to get the sensor id
> >>>> and initialize it. IOW, the DT gives the sensors to use.
> >>>>
> >>>> IMO, it would be more self contained if the driver initializes all
> >>>> the sensors without taking care of the DT and let the of- code to
> >>>> do the binding when the thermal zone, no ?
> >>> [Andy] could you please explain more about this way? I am not sure
> >>> how
> >> to implement it.
> >>> But one thing is for sure: we must get the sensor IDs explicitly so
> >>> that we can enable them by the following command:
> tmu_write(qdata,
> >>> sites | TMR_ME | TMR_ALPF, >regs->tmr);
> >>
> >> What I meant is about code separation between the driver itself and
> >> the of-thermal code.
> >>
> >> The code above re-inspect the DT to find out the sensor ids in order
> >> to enable them and somehow this is not wrong but breaks the self
> >> encapsulation of the driver. I was suggesting if it isn't possible to
> >> enable all the sensors without taking care of digging into the DT.
> >
> > [Andy] I don't want to re-parse the DT here too. But I have to.
> > This driver will be used by all our SOCs with different sensor IDs and
> number.
> > For example: there are 2 sensors on ls1088a platform with ID 0 and 1.
> > While on ls1043a there are 6 sensors with ID 0, 1, 2, 3, 4, 5.
> > If we don't scan the DT we would not know how many sensors it is and
> > what are the sensor's IDs, unless we hardcode it in driver.
> 
> Yes, you are not the only one in this situation IMO and the drivers
> supporting multiple sensors are increasing, so this will repeat again and
> again.
> 
> That could be hardcoded in the driver by using the compatible string but it
> will be nicer if we can fix that in the DT.
> 
> [Cc'ing Rob]
> 
> What is missing is a description of the sensors id in the temperature
> device node. We have the  with 0 or 1 telling if
> there is one or several sensors but we can't specify which sensor ids we
> have. The only alternative is to parse the thermal zones to found out which
> sensors are in use and use them to initialize the driver, an approach which
> breaks the self-encapsulation: the of-thermal framework is the one in
> charge of doing the link between the thermal zone and a sensor id.
> 
> Is it acceptable to add the list of the sensors id in the temp device node, so
> the driver can initialize these sensors without parsing the thermal zone in
> the DT ?
> 
Have you got any conclusion yet?
When can I send the next version of this patch?

BR,
Andy
> 
> 
> 
> --
> 
> <https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> www.linaro.org%2Fdata=02%7C01%7Candy.tang%40nxp.com%7Cf6
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RE: [PATCH] thermal: qoriq: add multiple sensors support

[Andy Tang]

Hi Daniel,

> -Original Message-
> From: Daniel Lezcano 
> Sent: 2018年10月16日 19:21
> To: Andy Tang ; rui.zh...@intel.com
> Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Rob Herring 
> Subject: Re: [PATCH] thermal: qoriq: add multiple sensors support
> 
> >>>> The current code is reading the DT in order to get the sensor id
> >>>> and initialize it. IOW, the DT gives the sensors to use.
> >>>>
> >>>> IMO, it would be more self contained if the driver initializes all
> >>>> the sensors without taking care of the DT and let the of- code to
> >>>> do the binding when the thermal zone, no ?
> >>> [Andy] could you please explain more about this way? I am not sure
> >>> how
> >> to implement it.
> >>> But one thing is for sure: we must get the sensor IDs explicitly so
> >>> that we can enable them by the following command:
> tmu_write(qdata,
> >>> sites | TMR_ME | TMR_ALPF, >regs->tmr);
> >>
> >> What I meant is about code separation between the driver itself and
> >> the of-thermal code.
> >>
> >> The code above re-inspect the DT to find out the sensor ids in order
> >> to enable them and somehow this is not wrong but breaks the self
> >> encapsulation of the driver. I was suggesting if it isn't possible to
> >> enable all the sensors without taking care of digging into the DT.
> >
> > [Andy] I don't want to re-parse the DT here too. But I have to.
> > This driver will be used by all our SOCs with different sensor IDs and
> number.
> > For example: there are 2 sensors on ls1088a platform with ID 0 and 1.
> > While on ls1043a there are 6 sensors with ID 0, 1, 2, 3, 4, 5.
> > If we don't scan the DT we would not know how many sensors it is and
> > what are the sensor's IDs, unless we hardcode it in driver.
> 
> Yes, you are not the only one in this situation IMO and the drivers
> supporting multiple sensors are increasing, so this will repeat again and
> again.
> 
> That could be hardcoded in the driver by using the compatible string but it
> will be nicer if we can fix that in the DT.
> 
> [Cc'ing Rob]
> 
> What is missing is a description of the sensors id in the temperature
> device node. We have the  with 0 or 1 telling if
> there is one or several sensors but we can't specify which sensor ids we
> have. The only alternative is to parse the thermal zones to found out which
> sensors are in use and use them to initialize the driver, an approach which
> breaks the self-encapsulation: the of-thermal framework is the one in
> charge of doing the link between the thermal zone and a sensor id.
> 
> Is it acceptable to add the list of the sensors id in the temp device node, so
> the driver can initialize these sensors without parsing the thermal zone in
> the DT ?
> 
Have you got any conclusion yet?
When can I send the next version of this patch?

BR,
Andy
> 
> 
> 
> --
> 
> <https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> www.linaro.org%2Fdata=02%7C01%7Candy.tang%40nxp.com%7Cf6
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> 8lmevq%2FwJe9sosvNRFxhvPAb8TT3FWQ%3Dreserved=0>
> Linaro.org │ Open source software for ARM SoCs
> 
> Follow Linaro:
> <https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
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> g%40nxp.com%7Cf6343bd28e0643833fa108d6335973ca%7C686ea1d3b
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> fa92cd99c5c301635%7C0%7C0%7C636752856644006568sdata=h
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> 0> Blog

RE: [PATCH] thermal: qoriq: add multiple sensors support

[Andy Tang]

Hi Daniel,

Please see my reply inline.

> -Original Message-
> From: Daniel Lezcano 
> Sent: 2018年10月15日 16:56
> To: Andy Tang ; rui.zh...@intel.com
> Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] thermal: qoriq: add multiple sensors support
> > >
> >>
> >>> Signed-off-by: Tang Yuantian 
> >>> ---
> >>>  drivers/thermal/qoriq_thermal.c |  117
> >>> +++
> >>>  1 files changed, 70 insertions(+), 47 deletions(-)
> >>>
> >>> diff --git a/drivers/thermal/qoriq_thermal.c
> >>> b/drivers/thermal/qoriq_thermal.c index c866cc1..7c1e88a 100644
> >>> --- a/drivers/thermal/qoriq_thermal.c
> >>> +++ b/drivers/thermal/qoriq_thermal.c
> >>> @@ -69,14 +69,21 @@ struct qoriq_tmu_regs {
> >>>   u32 ttr3cr; /* Temperature Range 3 Control Register */
> >>>  };
> >>>
> >>> +struct qoriq_tmu_data;
> >>> +
> >>>  /*
> >>>   * Thermal zone data
> >>>   */
> >>> +struct qoriq_sensor {
> >>> + struct thermal_zone_device  *tzd;
> >>> + struct qoriq_tmu_data   *qdata;
> >>> + int id;
> >>> +};
> >>
> >> Can you move the qoriq_tmu_site_regs structure content inside the
> >> qoriq_sensor structure and kill the 'sites' field in the
> >> qoriq_tmu_regs structure ? Otherwise we end up with a SITES_MAX
> array
> >> in the qoriq_tmu_data structure and another one in the
> qoriq_tmu_regs
> >> structure.
> > [Andy] I am afraid I can't.
> > qoriq_tmu_site_regs structure is to define the registers. After iomap,
> TMU can be accessed.
> > qoriq_sensor structure is used for each sensor. It DONOT include the
> register defines.
> > qoriq_tmu_data structure is used for global TMU date.
> > So there is no any duplicated or redundant data here.
> 
> It is not about duplicate but just code reorg.
> 
> This patch changes the structure as:
> 
> struct qoriq_tmu_data {
> - struct thermal_zone_device *tz;
>   struct qoriq_tmu_regs __iomem *regs;
> - int sensor_id;
>   bool little_endian;
> + struct qoriq_sensor *sensor[SITES_MAX];
>  };
> 
> 
> So we have:
> 
> struct qoriq_tmu_data
>   => struct qoriq_sensor[SITES_MAX]
>   => struct qoriq_tmu_regs
>  => struct qoriq_tmu_site_regs[SITES_MAX]
> 
> I'm proposing to move struct qoriq_tmu_site_regs inside the struct
> qoriq_sensor.
> 
> 
> We end up with:
> 
> struct qoriq_sensor {
>struct thermal_zone_device *tzd;
>struct struct qoriq_tmu_site_regs *regs;
>struct qoriq_tmu_data *qdata;
>int id;
> };
[Andy] I see your point. If I add a *regs member to qoriq_sensor struct, then I 
can speed up the access to the register.
But I don't think it is better. Currently I can access sensor register by: 
qdata->regs->site[qsensor->id].
The whole point here is we can't MOVE struct qoriq_tmu_site_regs to the struct 
qoriq_sensor. We can only COPY
it to struct qoriq_sensor. 

This is the TMU module memory map:
struct qoriq_tmu_regs {
..
u32 tscfgr; /* Sensor Configuration Register */
u8 res4[0x78];
struct qoriq_tmu_site_regs site[SITES_MAX];
u8 res5[0x9f8];
u32 ipbrr0; /* IP Block Revision Register 0 */
u32 ipbrr1; /* IP Block Revision Register 1 */
...}
struct qoriq_tmu_site_regs site[SITES_MAX] is part of the memory map. It can't 
be removed or we have to define a similar struct to fill it up.


> 
> 
> >>> - if (sensor_specs.args_count >= 1) {
> >>> - id = sensor_specs.args[0];
> >>> - WARN(sensor_specs.args_count > 1,
> >>> - "%s: too many cells in sensor specifier %d\n",
> >>> - sensor_specs.np->name,
> sensor_specs.args_count);
> >>> - } else {
> >>> - id = 0;
> >>> + if (id > SITES_MAX)
> >>> + return -EINVAL;
> >>> +
> >>> + qdata->sensor[id] = devm_kzalloc(>dev,
> >>> + sizeof(struct qoriq_sensor), GFP_KERNEL);
> >>> + if (!qdata->sensor[id])
> >>> + return -ENOMEM;
> >>> +
> >>> + qdata->sensor[id]->id = id;
> >>> + qdata->sensor[id]->qdata = qdata;
> >>> +
> &

RE: [PATCH] thermal: qoriq: add multiple sensors support

[Andy Tang]

Hi Daniel,

Please see my reply inline.

> -Original Message-
> From: Daniel Lezcano 
> Sent: 2018年10月15日 16:56
> To: Andy Tang ; rui.zh...@intel.com
> Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] thermal: qoriq: add multiple sensors support
> > >
> >>
> >>> Signed-off-by: Tang Yuantian 
> >>> ---
> >>>  drivers/thermal/qoriq_thermal.c |  117
> >>> +++
> >>>  1 files changed, 70 insertions(+), 47 deletions(-)
> >>>
> >>> diff --git a/drivers/thermal/qoriq_thermal.c
> >>> b/drivers/thermal/qoriq_thermal.c index c866cc1..7c1e88a 100644
> >>> --- a/drivers/thermal/qoriq_thermal.c
> >>> +++ b/drivers/thermal/qoriq_thermal.c
> >>> @@ -69,14 +69,21 @@ struct qoriq_tmu_regs {
> >>>   u32 ttr3cr; /* Temperature Range 3 Control Register */
> >>>  };
> >>>
> >>> +struct qoriq_tmu_data;
> >>> +
> >>>  /*
> >>>   * Thermal zone data
> >>>   */
> >>> +struct qoriq_sensor {
> >>> + struct thermal_zone_device  *tzd;
> >>> + struct qoriq_tmu_data   *qdata;
> >>> + int id;
> >>> +};
> >>
> >> Can you move the qoriq_tmu_site_regs structure content inside the
> >> qoriq_sensor structure and kill the 'sites' field in the
> >> qoriq_tmu_regs structure ? Otherwise we end up with a SITES_MAX
> array
> >> in the qoriq_tmu_data structure and another one in the
> qoriq_tmu_regs
> >> structure.
> > [Andy] I am afraid I can't.
> > qoriq_tmu_site_regs structure is to define the registers. After iomap,
> TMU can be accessed.
> > qoriq_sensor structure is used for each sensor. It DONOT include the
> register defines.
> > qoriq_tmu_data structure is used for global TMU date.
> > So there is no any duplicated or redundant data here.
> 
> It is not about duplicate but just code reorg.
> 
> This patch changes the structure as:
> 
> struct qoriq_tmu_data {
> - struct thermal_zone_device *tz;
>   struct qoriq_tmu_regs __iomem *regs;
> - int sensor_id;
>   bool little_endian;
> + struct qoriq_sensor *sensor[SITES_MAX];
>  };
> 
> 
> So we have:
> 
> struct qoriq_tmu_data
>   => struct qoriq_sensor[SITES_MAX]
>   => struct qoriq_tmu_regs
>  => struct qoriq_tmu_site_regs[SITES_MAX]
> 
> I'm proposing to move struct qoriq_tmu_site_regs inside the struct
> qoriq_sensor.
> 
> 
> We end up with:
> 
> struct qoriq_sensor {
>struct thermal_zone_device *tzd;
>struct struct qoriq_tmu_site_regs *regs;
>struct qoriq_tmu_data *qdata;
>int id;
> };
[Andy] I see your point. If I add a *regs member to qoriq_sensor struct, then I 
can speed up the access to the register.
But I don't think it is better. Currently I can access sensor register by: 
qdata->regs->site[qsensor->id].
The whole point here is we can't MOVE struct qoriq_tmu_site_regs to the struct 
qoriq_sensor. We can only COPY
it to struct qoriq_sensor. 

This is the TMU module memory map:
struct qoriq_tmu_regs {
..
u32 tscfgr; /* Sensor Configuration Register */
u8 res4[0x78];
struct qoriq_tmu_site_regs site[SITES_MAX];
u8 res5[0x9f8];
u32 ipbrr0; /* IP Block Revision Register 0 */
u32 ipbrr1; /* IP Block Revision Register 1 */
...}
struct qoriq_tmu_site_regs site[SITES_MAX] is part of the memory map. It can't 
be removed or we have to define a similar struct to fill it up.


> 
> 
> >>> - if (sensor_specs.args_count >= 1) {
> >>> - id = sensor_specs.args[0];
> >>> - WARN(sensor_specs.args_count > 1,
> >>> - "%s: too many cells in sensor specifier %d\n",
> >>> - sensor_specs.np->name,
> sensor_specs.args_count);
> >>> - } else {
> >>> - id = 0;
> >>> + if (id > SITES_MAX)
> >>> + return -EINVAL;
> >>> +
> >>> + qdata->sensor[id] = devm_kzalloc(>dev,
> >>> + sizeof(struct qoriq_sensor), GFP_KERNEL);
> >>> + if (!qdata->sensor[id])
> >>> + return -ENOMEM;
> >>> +
> >>> + qdata->sensor[id]->id = id;
> >>> + qdata->sensor[id]->qdata = qdata;
> >>> +
> &

RE: [PATCH] thermal: qoriq: add multiple sensors support

[Andy Tang]

Thanks Daniel,

Please see my reply inline.

> -Original Message-
> From: Daniel Lezcano 
> Sent: 2018年10月14日 4:43
> To: Andy Tang ; rui.zh...@intel.com
> Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] thermal: qoriq: add multiple sensors support
> 
> 
> Hi Yuantian,
> 
> 
> On 27/09/2018 04:42, andy.t...@nxp.com wrote:
> > From: Yuantian Tang 
> >
> > There is only one sensor supported in current driver.
> > Multiple sensors are existing on Layscape socs. To support them,
> > covert this driver to support multiple sensors.
> 
> s/covert/convert/
> 
> What about the following changelog ?
> 
> "
> The QorIQ Layerscape SoC has several thermal sensors but the current
> driver only supports one.
> 
> Massage the code to be sensor oriented and allow the support for
> multiple sensors.
> "
[Andy]  Thanks, will update

> 
> > Signed-off-by: Tang Yuantian 
> > ---
> >  drivers/thermal/qoriq_thermal.c |  117
> > +++
> >  1 files changed, 70 insertions(+), 47 deletions(-)
> >
> > diff --git a/drivers/thermal/qoriq_thermal.c
> > b/drivers/thermal/qoriq_thermal.c index c866cc1..7c1e88a 100644
> > --- a/drivers/thermal/qoriq_thermal.c
> > +++ b/drivers/thermal/qoriq_thermal.c
> > @@ -69,14 +69,21 @@ struct qoriq_tmu_regs {
> > u32 ttr3cr; /* Temperature Range 3 Control Register */
> >  };
> >
> > +struct qoriq_tmu_data;
> > +
> >  /*
> >   * Thermal zone data
> >   */
> > +struct qoriq_sensor {
> > +   struct thermal_zone_device  *tzd;
> > +   struct qoriq_tmu_data   *qdata;
> > +   int id;
> > +};
> 
> Can you move the qoriq_tmu_site_regs structure content inside the
> qoriq_sensor structure and kill the 'sites' field in the qoriq_tmu_regs
> structure ? Otherwise we end up with a SITES_MAX array in the
> qoriq_tmu_data structure and another one in the qoriq_tmu_regs
> structure.
[Andy] I am afraid I can't.
qoriq_tmu_site_regs structure is to define the registers. After iomap, TMU can 
be accessed.
qoriq_sensor structure is used for each sensor. It DONOT include the register 
defines.
qoriq_tmu_data structure is used for global TMU date.
So there is no any duplicated or redundant data here.

> > -   if (sensor_specs.args_count >= 1) {
> > -   id = sensor_specs.args[0];
> > -   WARN(sensor_specs.args_count > 1,
> > -   "%s: too many cells in sensor specifier %d\n",
> > -   sensor_specs.np->name, sensor_specs.args_count);
> > -   } else {
> > -   id = 0;
> > +   if (id > SITES_MAX)
> > +   return -EINVAL;
> > +
> > +   qdata->sensor[id] = devm_kzalloc(>dev,
> > +   sizeof(struct qoriq_sensor), GFP_KERNEL);
> > +   if (!qdata->sensor[id])
> > +   return -ENOMEM;
> > +
> > +   qdata->sensor[id]->id = id;
> > +   qdata->sensor[id]->qdata = qdata;
> > +
> > +   qdata->sensor[id]->tzd =
> devm_thermal_zone_of_sensor_register(
> > +   >dev, id, qdata->sensor[id], _tz_ops);
> > +
> > +   if (IS_ERR(qdata->sensor[id]->tzd)) {
> > +   ret = PTR_ERR(qdata->sensor[id]->tzd);
> > +   dev_err(>dev,
> > +   "Failed to register thermal zone device.\n");
> > +   return -ENODEV;
> > +   }
> > +
> > +   sites |= 0x1 << (15 - id);
> 
> The current code is reading the DT in order to get the sensor id and
> initialize it. IOW, the DT gives the sensors to use.
> 
> IMO, it would be more self contained if the driver initializes all the sensors
> without taking care of the DT and let the of- code to do the binding when
> the thermal zone, no ?
[Andy] could you please explain more about this way? I am not sure how to 
implement it.
But one thing is for sure: we must get the sensor IDs explicitly so that we can 
enable them by
the following command:  tmu_write(qdata, sites | TMR_ME | TMR_ALPF, 
>regs->tmr);

BR,
Andy  

> 
> > }
> >
> > -   of_node_put(np);
> > -   of_node_put(sensor_np);
> > +   /* Enable monitoring */
> > +   if (sites != 0)
> > +   tmu_write(qdata, sites | TMR_ME | TMR_ALPF,
> >regs->tmr);
> >
> > -   return id;
> > +   return 0;
> &

RE: [PATCH] thermal: qoriq: add multiple sensors support

[Andy Tang]

Thanks Daniel,

Please see my reply inline.

> -Original Message-
> From: Daniel Lezcano 
> Sent: 2018年10月14日 4:43
> To: Andy Tang ; rui.zh...@intel.com
> Cc: edubez...@gmail.com; linux...@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] thermal: qoriq: add multiple sensors support
> 
> 
> Hi Yuantian,
> 
> 
> On 27/09/2018 04:42, andy.t...@nxp.com wrote:
> > From: Yuantian Tang 
> >
> > There is only one sensor supported in current driver.
> > Multiple sensors are existing on Layscape socs. To support them,
> > covert this driver to support multiple sensors.
> 
> s/covert/convert/
> 
> What about the following changelog ?
> 
> "
> The QorIQ Layerscape SoC has several thermal sensors but the current
> driver only supports one.
> 
> Massage the code to be sensor oriented and allow the support for
> multiple sensors.
> "
[Andy]  Thanks, will update

> 
> > Signed-off-by: Tang Yuantian 
> > ---
> >  drivers/thermal/qoriq_thermal.c |  117
> > +++
> >  1 files changed, 70 insertions(+), 47 deletions(-)
> >
> > diff --git a/drivers/thermal/qoriq_thermal.c
> > b/drivers/thermal/qoriq_thermal.c index c866cc1..7c1e88a 100644
> > --- a/drivers/thermal/qoriq_thermal.c
> > +++ b/drivers/thermal/qoriq_thermal.c
> > @@ -69,14 +69,21 @@ struct qoriq_tmu_regs {
> > u32 ttr3cr; /* Temperature Range 3 Control Register */
> >  };
> >
> > +struct qoriq_tmu_data;
> > +
> >  /*
> >   * Thermal zone data
> >   */
> > +struct qoriq_sensor {
> > +   struct thermal_zone_device  *tzd;
> > +   struct qoriq_tmu_data   *qdata;
> > +   int id;
> > +};
> 
> Can you move the qoriq_tmu_site_regs structure content inside the
> qoriq_sensor structure and kill the 'sites' field in the qoriq_tmu_regs
> structure ? Otherwise we end up with a SITES_MAX array in the
> qoriq_tmu_data structure and another one in the qoriq_tmu_regs
> structure.
[Andy] I am afraid I can't.
qoriq_tmu_site_regs structure is to define the registers. After iomap, TMU can 
be accessed.
qoriq_sensor structure is used for each sensor. It DONOT include the register 
defines.
qoriq_tmu_data structure is used for global TMU date.
So there is no any duplicated or redundant data here.

> > -   if (sensor_specs.args_count >= 1) {
> > -   id = sensor_specs.args[0];
> > -   WARN(sensor_specs.args_count > 1,
> > -   "%s: too many cells in sensor specifier %d\n",
> > -   sensor_specs.np->name, sensor_specs.args_count);
> > -   } else {
> > -   id = 0;
> > +   if (id > SITES_MAX)
> > +   return -EINVAL;
> > +
> > +   qdata->sensor[id] = devm_kzalloc(>dev,
> > +   sizeof(struct qoriq_sensor), GFP_KERNEL);
> > +   if (!qdata->sensor[id])
> > +   return -ENOMEM;
> > +
> > +   qdata->sensor[id]->id = id;
> > +   qdata->sensor[id]->qdata = qdata;
> > +
> > +   qdata->sensor[id]->tzd =
> devm_thermal_zone_of_sensor_register(
> > +   >dev, id, qdata->sensor[id], _tz_ops);
> > +
> > +   if (IS_ERR(qdata->sensor[id]->tzd)) {
> > +   ret = PTR_ERR(qdata->sensor[id]->tzd);
> > +   dev_err(>dev,
> > +   "Failed to register thermal zone device.\n");
> > +   return -ENODEV;
> > +   }
> > +
> > +   sites |= 0x1 << (15 - id);
> 
> The current code is reading the DT in order to get the sensor id and
> initialize it. IOW, the DT gives the sensors to use.
> 
> IMO, it would be more self contained if the driver initializes all the sensors
> without taking care of the DT and let the of- code to do the binding when
> the thermal zone, no ?
[Andy] could you please explain more about this way? I am not sure how to 
implement it.
But one thing is for sure: we must get the sensor IDs explicitly so that we can 
enable them by
the following command:  tmu_write(qdata, sites | TMR_ME | TMR_ALPF, 
>regs->tmr);

BR,
Andy  

> 
> > }
> >
> > -   of_node_put(np);
> > -   of_node_put(sensor_np);
> > +   /* Enable monitoring */
> > +   if (sites != 0)
> > +   tmu_write(qdata, sites | TMR_ME | TMR_ALPF,
> >regs->tmr);
> >
> > -   return id;
> > +   return 0;
> &

RE: [PATCH] thermal: qoriq: add multiple sensors support

[Andy Tang]

Hi Rui,

Appreciate if you can give it a review.

BR,
Andy

> -Original Message-
> From: andy.t...@nxp.com 
> Sent: 2018年9月27日 10:42
> To: rui.zh...@intel.com
> Cc: edubez...@gmail.com; daniel.lezc...@linaro.org;
> linux...@vger.kernel.org; linux-kernel@vger.kernel.org; Andy Tang
> 
> Subject: [PATCH] thermal: qoriq: add multiple sensors support
> 
> From: Yuantian Tang 
> 
> There is only one sensor supported in current driver.
> Multiple sensors are existing on Layscape socs. To support them, covert
> this driver to support multiple sensors.
> 
> Signed-off-by: Tang Yuantian 
> ---
>  drivers/thermal/qoriq_thermal.c |  117
> +++
>  1 files changed, 70 insertions(+), 47 deletions(-)
> 
> diff --git a/drivers/thermal/qoriq_thermal.c
> b/drivers/thermal/qoriq_thermal.c index c866cc1..7c1e88a 100644
> --- a/drivers/thermal/qoriq_thermal.c
> +++ b/drivers/thermal/qoriq_thermal.c
> @@ -69,14 +69,21 @@ struct qoriq_tmu_regs {
>   u32 ttr3cr; /* Temperature Range 3 Control Register */
>  };
> 
> +struct qoriq_tmu_data;
> +
>  /*
>   * Thermal zone data
>   */
> +struct qoriq_sensor {
> + struct thermal_zone_device  *tzd;
> + struct qoriq_tmu_data   *qdata;
> + int id;
> +};
> +
>  struct qoriq_tmu_data {
> - struct thermal_zone_device *tz;
>   struct qoriq_tmu_regs __iomem *regs;
> - int sensor_id;
>   bool little_endian;
> + struct qoriq_sensor *sensor[SITES_MAX];
>  };
> 
>  static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem
> *addr) @@ -97,48 +104,83 @@ static u32 tmu_read(struct
> qoriq_tmu_data *p, void __iomem *addr)
> 
>  static int tmu_get_temp(void *p, int *temp)  {
> + struct qoriq_sensor *qsensor = p;
> + struct qoriq_tmu_data *qdata = qsensor->qdata;
>   u32 val;
> - struct qoriq_tmu_data *data = p;
> 
> - val = tmu_read(data, >regs->site[data->sensor_id].tritsr);
> + val = tmu_read(qdata, >regs->site[qsensor->id].tritsr);
>   *temp = (val & 0xff) * 1000;
> 
>   return 0;
>  }
> 
> -static int qoriq_tmu_get_sensor_id(void)
> +static const struct thermal_zone_of_device_ops tmu_tz_ops = {
> + .get_temp = tmu_get_temp,
> +};
> +
> +static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
>  {
> - int ret, id;
> + struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
>   struct of_phandle_args sensor_specs;
>   struct device_node *np, *sensor_np;
> + int ret, id, sites = 0;
> 
>   np = of_find_node_by_name(NULL, "thermal-zones");
>   if (!np)
>   return -ENODEV;
> 
> - sensor_np = of_get_next_child(np, NULL);
> - ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
> - "#thermal-sensor-cells",
> - 0, _specs);
> - if (ret) {
> + for_each_available_child_of_node(np, sensor_np) {
> + ret = of_parse_phandle_with_args(sensor_np,
> "thermal-sensors",
> + "#thermal-sensor-cells",
> + 0, _specs);
> + if (ret) {
> + of_node_put(np);
> + of_node_put(sensor_np);
> + return ret;
> + }
> +
> + if (sensor_specs.args_count >= 1) {
> + id = sensor_specs.args[0];
> + WARN(sensor_specs.args_count > 1,
> + "%s: too many cells in sensor specifier 
> %d\n",
> + sensor_specs.np->name,
> + sensor_specs.args_count);
> + } else {
> + id = 0;
> + }
> +
>   of_node_put(np);
>   of_node_put(sensor_np);
> - return ret;
> - }
> 
> - if (sensor_specs.args_count >= 1) {
> - id = sensor_specs.args[0];
> - WARN(sensor_specs.args_count > 1,
> - "%s: too many cells in sensor specifier %d\n",
> - sensor_specs.np->name, sensor_specs.args_count);
> - } else {
> - id = 0;
> + if (id > SITES_MAX)
> + return -EINVAL;
> +
> + qdata->sensor[id] = devm_kzalloc(>dev,
> + sizeof(struct qoriq_sensor), GFP_KERNEL);
> + if (!qdata->sensor[id])
> +   

RE: [PATCH] thermal: qoriq: add multiple sensors support

[Andy Tang]

Hi Rui,

Appreciate if you can give it a review.

BR,
Andy

> -Original Message-
> From: andy.t...@nxp.com 
> Sent: 2018年9月27日 10:42
> To: rui.zh...@intel.com
> Cc: edubez...@gmail.com; daniel.lezc...@linaro.org;
> linux...@vger.kernel.org; linux-kernel@vger.kernel.org; Andy Tang
> 
> Subject: [PATCH] thermal: qoriq: add multiple sensors support
> 
> From: Yuantian Tang 
> 
> There is only one sensor supported in current driver.
> Multiple sensors are existing on Layscape socs. To support them, covert
> this driver to support multiple sensors.
> 
> Signed-off-by: Tang Yuantian 
> ---
>  drivers/thermal/qoriq_thermal.c |  117
> +++
>  1 files changed, 70 insertions(+), 47 deletions(-)
> 
> diff --git a/drivers/thermal/qoriq_thermal.c
> b/drivers/thermal/qoriq_thermal.c index c866cc1..7c1e88a 100644
> --- a/drivers/thermal/qoriq_thermal.c
> +++ b/drivers/thermal/qoriq_thermal.c
> @@ -69,14 +69,21 @@ struct qoriq_tmu_regs {
>   u32 ttr3cr; /* Temperature Range 3 Control Register */
>  };
> 
> +struct qoriq_tmu_data;
> +
>  /*
>   * Thermal zone data
>   */
> +struct qoriq_sensor {
> + struct thermal_zone_device  *tzd;
> + struct qoriq_tmu_data   *qdata;
> + int id;
> +};
> +
>  struct qoriq_tmu_data {
> - struct thermal_zone_device *tz;
>   struct qoriq_tmu_regs __iomem *regs;
> - int sensor_id;
>   bool little_endian;
> + struct qoriq_sensor *sensor[SITES_MAX];
>  };
> 
>  static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem
> *addr) @@ -97,48 +104,83 @@ static u32 tmu_read(struct
> qoriq_tmu_data *p, void __iomem *addr)
> 
>  static int tmu_get_temp(void *p, int *temp)  {
> + struct qoriq_sensor *qsensor = p;
> + struct qoriq_tmu_data *qdata = qsensor->qdata;
>   u32 val;
> - struct qoriq_tmu_data *data = p;
> 
> - val = tmu_read(data, >regs->site[data->sensor_id].tritsr);
> + val = tmu_read(qdata, >regs->site[qsensor->id].tritsr);
>   *temp = (val & 0xff) * 1000;
> 
>   return 0;
>  }
> 
> -static int qoriq_tmu_get_sensor_id(void)
> +static const struct thermal_zone_of_device_ops tmu_tz_ops = {
> + .get_temp = tmu_get_temp,
> +};
> +
> +static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
>  {
> - int ret, id;
> + struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
>   struct of_phandle_args sensor_specs;
>   struct device_node *np, *sensor_np;
> + int ret, id, sites = 0;
> 
>   np = of_find_node_by_name(NULL, "thermal-zones");
>   if (!np)
>   return -ENODEV;
> 
> - sensor_np = of_get_next_child(np, NULL);
> - ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
> - "#thermal-sensor-cells",
> - 0, _specs);
> - if (ret) {
> + for_each_available_child_of_node(np, sensor_np) {
> + ret = of_parse_phandle_with_args(sensor_np,
> "thermal-sensors",
> + "#thermal-sensor-cells",
> + 0, _specs);
> + if (ret) {
> + of_node_put(np);
> + of_node_put(sensor_np);
> + return ret;
> + }
> +
> + if (sensor_specs.args_count >= 1) {
> + id = sensor_specs.args[0];
> + WARN(sensor_specs.args_count > 1,
> + "%s: too many cells in sensor specifier 
> %d\n",
> + sensor_specs.np->name,
> + sensor_specs.args_count);
> + } else {
> + id = 0;
> + }
> +
>   of_node_put(np);
>   of_node_put(sensor_np);
> - return ret;
> - }
> 
> - if (sensor_specs.args_count >= 1) {
> - id = sensor_specs.args[0];
> - WARN(sensor_specs.args_count > 1,
> - "%s: too many cells in sensor specifier %d\n",
> - sensor_specs.np->name, sensor_specs.args_count);
> - } else {
> - id = 0;
> + if (id > SITES_MAX)
> + return -EINVAL;
> +
> + qdata->sensor[id] = devm_kzalloc(>dev,
> + sizeof(struct qoriq_sensor), GFP_KERNEL);
> + if (!qdata->sensor[id])
> +   

[PATCH] thermal: qoriq: add multiple sensors support

[andy . tang]

From: Yuantian Tang 

There is only one sensor supported in current driver.
Multiple sensors are existing on Layscape socs. To support them,
covert this driver to support multiple sensors.

Signed-off-by: Tang Yuantian 
---
 drivers/thermal/qoriq_thermal.c |  117 +++
 1 files changed, 70 insertions(+), 47 deletions(-)

diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
index c866cc1..7c1e88a 100644
--- a/drivers/thermal/qoriq_thermal.c
+++ b/drivers/thermal/qoriq_thermal.c
@@ -69,14 +69,21 @@ struct qoriq_tmu_regs {
u32 ttr3cr; /* Temperature Range 3 Control Register */
 };
 
+struct qoriq_tmu_data;
+
 /*
  * Thermal zone data
  */
+struct qoriq_sensor {
+   struct thermal_zone_device  *tzd;
+   struct qoriq_tmu_data   *qdata;
+   int id;
+};
+
 struct qoriq_tmu_data {
-   struct thermal_zone_device *tz;
struct qoriq_tmu_regs __iomem *regs;
-   int sensor_id;
bool little_endian;
+   struct qoriq_sensor *sensor[SITES_MAX];
 };
 
 static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr)
@@ -97,48 +104,83 @@ static u32 tmu_read(struct qoriq_tmu_data *p, void __iomem 
*addr)
 
 static int tmu_get_temp(void *p, int *temp)
 {
+   struct qoriq_sensor *qsensor = p;
+   struct qoriq_tmu_data *qdata = qsensor->qdata;
u32 val;
-   struct qoriq_tmu_data *data = p;
 
-   val = tmu_read(data, >regs->site[data->sensor_id].tritsr);
+   val = tmu_read(qdata, >regs->site[qsensor->id].tritsr);
*temp = (val & 0xff) * 1000;
 
return 0;
 }
 
-static int qoriq_tmu_get_sensor_id(void)
+static const struct thermal_zone_of_device_ops tmu_tz_ops = {
+   .get_temp = tmu_get_temp,
+};
+
+static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
 {
-   int ret, id;
+   struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
struct of_phandle_args sensor_specs;
struct device_node *np, *sensor_np;
+   int ret, id, sites = 0;
 
np = of_find_node_by_name(NULL, "thermal-zones");
if (!np)
return -ENODEV;
 
-   sensor_np = of_get_next_child(np, NULL);
-   ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
-   "#thermal-sensor-cells",
-   0, _specs);
-   if (ret) {
+   for_each_available_child_of_node(np, sensor_np) {
+   ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
+   "#thermal-sensor-cells",
+   0, _specs);
+   if (ret) {
+   of_node_put(np);
+   of_node_put(sensor_np);
+   return ret;
+   }
+
+   if (sensor_specs.args_count >= 1) {
+   id = sensor_specs.args[0];
+   WARN(sensor_specs.args_count > 1,
+   "%s: too many cells in sensor specifier 
%d\n",
+   sensor_specs.np->name,
+   sensor_specs.args_count);
+   } else {
+   id = 0;
+   }
+
of_node_put(np);
of_node_put(sensor_np);
-   return ret;
-   }
 
-   if (sensor_specs.args_count >= 1) {
-   id = sensor_specs.args[0];
-   WARN(sensor_specs.args_count > 1,
-   "%s: too many cells in sensor specifier %d\n",
-   sensor_specs.np->name, sensor_specs.args_count);
-   } else {
-   id = 0;
+   if (id > SITES_MAX)
+   return -EINVAL;
+
+   qdata->sensor[id] = devm_kzalloc(>dev,
+   sizeof(struct qoriq_sensor), GFP_KERNEL);
+   if (!qdata->sensor[id])
+   return -ENOMEM;
+
+   qdata->sensor[id]->id = id;
+   qdata->sensor[id]->qdata = qdata;
+
+   qdata->sensor[id]->tzd = devm_thermal_zone_of_sensor_register(
+   >dev, id, qdata->sensor[id], _tz_ops);
+
+   if (IS_ERR(qdata->sensor[id]->tzd)) {
+   ret = PTR_ERR(qdata->sensor[id]->tzd);
+   dev_err(>dev,
+   "Failed to register thermal zone device.\n");
+   return -ENODEV;
+   }
+
+   sites |= 0x1 << (15 - id);
}
 
-   of_node_put(np);
-   of_node_put(sensor_np);
+   /* Enable monitoring */
+   if (sites != 0)
+   tmu_write(qdata, sites | TMR_ME | TMR_ALPF, >regs->tmr);
 
-   return id;
+   return 0;
 }
 
 static int qoriq_tmu_calibration(struct platform_device *pdev)
@@ -188,16 +230,11 @@ static void qoriq_tmu_init_device(struct 

[PATCH] thermal: qoriq: add multiple sensors support

[andy . tang]

From: Yuantian Tang 

There is only one sensor supported in current driver.
Multiple sensors are existing on Layscape socs. To support them,
covert this driver to support multiple sensors.

Signed-off-by: Tang Yuantian 
---
 drivers/thermal/qoriq_thermal.c |  117 +++
 1 files changed, 70 insertions(+), 47 deletions(-)

diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
index c866cc1..7c1e88a 100644
--- a/drivers/thermal/qoriq_thermal.c
+++ b/drivers/thermal/qoriq_thermal.c
@@ -69,14 +69,21 @@ struct qoriq_tmu_regs {
u32 ttr3cr; /* Temperature Range 3 Control Register */
 };
 
+struct qoriq_tmu_data;
+
 /*
  * Thermal zone data
  */
+struct qoriq_sensor {
+   struct thermal_zone_device  *tzd;
+   struct qoriq_tmu_data   *qdata;
+   int id;
+};
+
 struct qoriq_tmu_data {
-   struct thermal_zone_device *tz;
struct qoriq_tmu_regs __iomem *regs;
-   int sensor_id;
bool little_endian;
+   struct qoriq_sensor *sensor[SITES_MAX];
 };
 
 static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr)
@@ -97,48 +104,83 @@ static u32 tmu_read(struct qoriq_tmu_data *p, void __iomem 
*addr)
 
 static int tmu_get_temp(void *p, int *temp)
 {
+   struct qoriq_sensor *qsensor = p;
+   struct qoriq_tmu_data *qdata = qsensor->qdata;
u32 val;
-   struct qoriq_tmu_data *data = p;
 
-   val = tmu_read(data, >regs->site[data->sensor_id].tritsr);
+   val = tmu_read(qdata, >regs->site[qsensor->id].tritsr);
*temp = (val & 0xff) * 1000;
 
return 0;
 }
 
-static int qoriq_tmu_get_sensor_id(void)
+static const struct thermal_zone_of_device_ops tmu_tz_ops = {
+   .get_temp = tmu_get_temp,
+};
+
+static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
 {
-   int ret, id;
+   struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
struct of_phandle_args sensor_specs;
struct device_node *np, *sensor_np;
+   int ret, id, sites = 0;
 
np = of_find_node_by_name(NULL, "thermal-zones");
if (!np)
return -ENODEV;
 
-   sensor_np = of_get_next_child(np, NULL);
-   ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
-   "#thermal-sensor-cells",
-   0, _specs);
-   if (ret) {
+   for_each_available_child_of_node(np, sensor_np) {
+   ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
+   "#thermal-sensor-cells",
+   0, _specs);
+   if (ret) {
+   of_node_put(np);
+   of_node_put(sensor_np);
+   return ret;
+   }
+
+   if (sensor_specs.args_count >= 1) {
+   id = sensor_specs.args[0];
+   WARN(sensor_specs.args_count > 1,
+   "%s: too many cells in sensor specifier 
%d\n",
+   sensor_specs.np->name,
+   sensor_specs.args_count);
+   } else {
+   id = 0;
+   }
+
of_node_put(np);
of_node_put(sensor_np);
-   return ret;
-   }
 
-   if (sensor_specs.args_count >= 1) {
-   id = sensor_specs.args[0];
-   WARN(sensor_specs.args_count > 1,
-   "%s: too many cells in sensor specifier %d\n",
-   sensor_specs.np->name, sensor_specs.args_count);
-   } else {
-   id = 0;
+   if (id > SITES_MAX)
+   return -EINVAL;
+
+   qdata->sensor[id] = devm_kzalloc(>dev,
+   sizeof(struct qoriq_sensor), GFP_KERNEL);
+   if (!qdata->sensor[id])
+   return -ENOMEM;
+
+   qdata->sensor[id]->id = id;
+   qdata->sensor[id]->qdata = qdata;
+
+   qdata->sensor[id]->tzd = devm_thermal_zone_of_sensor_register(
+   >dev, id, qdata->sensor[id], _tz_ops);
+
+   if (IS_ERR(qdata->sensor[id]->tzd)) {
+   ret = PTR_ERR(qdata->sensor[id]->tzd);
+   dev_err(>dev,
+   "Failed to register thermal zone device.\n");
+   return -ENODEV;
+   }
+
+   sites |= 0x1 << (15 - id);
}
 
-   of_node_put(np);
-   of_node_put(sensor_np);
+   /* Enable monitoring */
+   if (sites != 0)
+   tmu_write(qdata, sites | TMR_ME | TMR_ALPF, >regs->tmr);
 
-   return id;
+   return 0;
 }
 
 static int qoriq_tmu_calibration(struct platform_device *pdev)
@@ -188,16 +230,11 @@ static void qoriq_tmu_init_device(struct 

RE: [PATCH 2/2] arm64: dts: ls2088a: add cpu idle support

[Andy Tang]

Hi Shawn,

Please see my explanation inline.

> -Original Message-
> From: Shawn Guo [mailto:shawn...@kernel.org]
> Sent: Thursday, August 03, 2017 9:40 AM
> To: Andy Tang <andy.t...@nxp.com>
> Cc: mark.rutl...@arm.com; devicet...@vger.kernel.org;
> catalin.mari...@arm.com; will.dea...@arm.com; linux-
> ker...@vger.kernel.org; robh...@kernel.org; linux-arm-
> ker...@lists.infradead.org
> Subject: Re: [PATCH 2/2] arm64: dts: ls2088a: add cpu idle support
> 
> On Wed, Jul 26, 2017 at 03:24:53PM +0800, andy.t...@nxp.com wrote:
> > From: Yuantian Tang <andy.t...@nxp.com>
> >
> > ls2088a supports another cpu idle state which is pw20 which saves more
> > power when cpu is idle.
> > It was implemented through psci firmware.
> >
> > Signed-off-by: Tang Yuantian <andy.t...@nxp.com>
> 
> Can you explain a bit in the commit log why psci node is being added in fsl-
> ls208xa.dtsi while you are only adding idle state for ls2088a?  Does that mean
> ls2088a and ls2080a gets different idle implementation?
> 
IDLE implementation is same on both ls2080a and ls2088a.  it is just there is 
no 
Requirement for ls2080a though. Still it is better to update both.

I will resend the patch adding ls2080a supports.

Regards,
Andy

> Shawn
> 
> > ---
> >  arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 17 +
> > arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi |  5 +
> >  2 files changed, 22 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > index 5c695c6..6aa319d 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > @@ -53,6 +53,7 @@
> > compatible = "arm,cortex-a72";
> > reg = <0x0>;
> > clocks = < 1 0>;
> > +   cpu-idle-states = <_PW20>;
> > next-level-cache = <_l2>;
> > #cooling-cells = <2>;
> > };
> > @@ -62,6 +63,7 @@
> > compatible = "arm,cortex-a72";
> > reg = <0x1>;
> > clocks = < 1 0>;
> > +   cpu-idle-states = <_PW20>;
> > next-level-cache = <_l2>;
> > };
> >
> > @@ -70,6 +72,7 @@
> > compatible = "arm,cortex-a72";
> > reg = <0x100>;
> > clocks = < 1 1>;
> > +   cpu-idle-states = <_PW20>;
> > next-level-cache = <_l2>;
> > #cooling-cells = <2>;
> > };
> > @@ -79,6 +82,7 @@
> > compatible = "arm,cortex-a72";
> > reg = <0x101>;
> > clocks = < 1 1>;
> > +   cpu-idle-states = <_PW20>;
> > next-level-cache = <_l2>;
> > };
> >
> > @@ -88,6 +92,7 @@
> > reg = <0x200>;
> > clocks = < 1 2>;
> > next-level-cache = <_l2>;
> > +   cpu-idle-states = <_PW20>;
> > #cooling-cells = <2>;
> > };
> >
> > @@ -96,6 +101,7 @@
> > compatible = "arm,cortex-a72";
> > reg = <0x201>;
> > clocks = < 1 2>;
> > +   cpu-idle-states = <_PW20>;
> > next-level-cache = <_l2>;
> > };
> >
> > @@ -104,6 +110,7 @@
> > compatible = "arm,cortex-a72";
> > reg = <0x300>;
> > clocks = < 1 3>;
> > +   cpu-idle-states = <_PW20>;
> > next-level-cache = <_l2>;
> > #cooling-cells = <2>;
> > };
> > @@ -113,6 +120,7 @@
> > compatible = "arm,cortex-a72";
> > reg = <0x301>;
> > clocks = < 1 3>;
> > +   cpu-idle-states = <_PW20>;
> > next-level-cache = <_l2>;
> > };
> >
> > @@ -131,6 +139,15 @@
> > cluster3_l2: l2-cache3 {
> > compatible = "cache";
> > };
> > +
> > +   CPU_PW20: cpu-pw20 {
> > +   compatible = "arm,idle-state";
> > +   idle-state-name = "PW20";
> > +   arm,psci-suspend-param = <0x0001>;
> > +   entry-latency-us = <2000>;
> > +   exit-latency-us = <2000>;
> > +   min-residency-us = <6000>;
> > +   };
> >  };
> >
> >   {
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> > index 94cdd30..205b7f7 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> > @@ -118,6 +118,11 @@
> > interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
> > };
> >
> > +   psci {
> > +   compatible = "arm,psci-0.2";
> > +   method = "smc";
> > +   };
> > +
> > soc {
> > compatible = "simple-bus";
> > #address-cells = <2>;
> > --
> > 2.1.0.27.g96db324
> >
> >
> > ___
> > linux-arm-kernel mailing list
> > linux-arm-ker...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

RE: [PATCH 2/2] arm64: dts: ls2088a: add cpu idle support

[Andy Tang]

Hi Shawn,

Please see my explanation inline.

> -Original Message-
> From: Shawn Guo [mailto:shawn...@kernel.org]
> Sent: Thursday, August 03, 2017 9:40 AM
> To: Andy Tang 
> Cc: mark.rutl...@arm.com; devicet...@vger.kernel.org;
> catalin.mari...@arm.com; will.dea...@arm.com; linux-
> ker...@vger.kernel.org; robh...@kernel.org; linux-arm-
> ker...@lists.infradead.org
> Subject: Re: [PATCH 2/2] arm64: dts: ls2088a: add cpu idle support
> 
> On Wed, Jul 26, 2017 at 03:24:53PM +0800, andy.t...@nxp.com wrote:
> > From: Yuantian Tang 
> >
> > ls2088a supports another cpu idle state which is pw20 which saves more
> > power when cpu is idle.
> > It was implemented through psci firmware.
> >
> > Signed-off-by: Tang Yuantian 
> 
> Can you explain a bit in the commit log why psci node is being added in fsl-
> ls208xa.dtsi while you are only adding idle state for ls2088a?  Does that mean
> ls2088a and ls2080a gets different idle implementation?
> 
IDLE implementation is same on both ls2080a and ls2088a.  it is just there is 
no 
Requirement for ls2080a though. Still it is better to update both.

I will resend the patch adding ls2080a supports.

Regards,
Andy

> Shawn
> 
> > ---
> >  arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 17 +
> > arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi |  5 +
> >  2 files changed, 22 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > index 5c695c6..6aa319d 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > @@ -53,6 +53,7 @@
> > compatible = "arm,cortex-a72";
> > reg = <0x0>;
> > clocks = < 1 0>;
> > +   cpu-idle-states = <_PW20>;
> > next-level-cache = <_l2>;
> > #cooling-cells = <2>;
> > };
> > @@ -62,6 +63,7 @@
> > compatible = "arm,cortex-a72";
> > reg = <0x1>;
> > clocks = < 1 0>;
> > +   cpu-idle-states = <_PW20>;
> > next-level-cache = <_l2>;
> > };
> >
> > @@ -70,6 +72,7 @@
> > compatible = "arm,cortex-a72";
> > reg = <0x100>;
> > clocks = < 1 1>;
> > +   cpu-idle-states = <_PW20>;
> > next-level-cache = <_l2>;
> > #cooling-cells = <2>;
> > };
> > @@ -79,6 +82,7 @@
> > compatible = "arm,cortex-a72";
> > reg = <0x101>;
> > clocks = < 1 1>;
> > +   cpu-idle-states = <_PW20>;
> > next-level-cache = <_l2>;
> > };
> >
> > @@ -88,6 +92,7 @@
> > reg = <0x200>;
> > clocks = < 1 2>;
> > next-level-cache = <_l2>;
> > +   cpu-idle-states = <_PW20>;
> > #cooling-cells = <2>;
> > };
> >
> > @@ -96,6 +101,7 @@
> > compatible = "arm,cortex-a72";
> > reg = <0x201>;
> > clocks = < 1 2>;
> > +   cpu-idle-states = <_PW20>;
> > next-level-cache = <_l2>;
> > };
> >
> > @@ -104,6 +110,7 @@
> > compatible = "arm,cortex-a72";
> > reg = <0x300>;
> > clocks = < 1 3>;
> > +   cpu-idle-states = <_PW20>;
> > next-level-cache = <_l2>;
> > #cooling-cells = <2>;
> > };
> > @@ -113,6 +120,7 @@
> > compatible = "arm,cortex-a72";
> > reg = <0x301>;
> > clocks = < 1 3>;
> > +   cpu-idle-states = <_PW20>;
> > next-level-cache = <_l2>;
> > };
> >
> > @@ -131,6 +139,15 @@
> > cluster3_l2: l2-cache3 {
> > compatible = "cache";
> > };
> > +
> > +   CPU_PW20: cpu-pw20 {
> > +   compatible = "arm,idle-state";
> > +   idle-state-name = "PW20";
> > +   arm,psci-suspend-param = <0x0001>;
> > +   entry-latency-us = <2000>;
> > +   exit-latency-us = <2000>;
> > +   min-residency-us = <6000>;
> > +   };
> >  };
> >
> >   {
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> > index 94cdd30..205b7f7 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> > @@ -118,6 +118,11 @@
> > interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
> > };
> >
> > +   psci {
> > +   compatible = "arm,psci-0.2";
> > +   method = "smc";
> > +   };
> > +
> > soc {
> > compatible = "simple-bus";
> > #address-cells = <2>;
> > --
> > 2.1.0.27.g96db324
> >
> >
> > ___
> > linux-arm-kernel mailing list
> > linux-arm-ker...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

RE: [PATCH 1/2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

Hi,

> -Original Message-
> From: sb...@codeaurora.org [mailto:sb...@codeaurora.org]
> Sent: Saturday, July 22, 2017 6:03 AM
> To: Andy Tang <andy.t...@nxp.com>
> Cc: mturque...@baylibre.com; mark.rutl...@arm.com; linux-
> c...@vger.kernel.org; devicet...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott Wood
> <o...@buserror.net>; Rob Herring <r...@kernel.org>
> Subject: Re: [PATCH 1/2] dt-bindings: qoriq-clock: Add coreclk
> 
> On 03/09, Y.T. Tang wrote:
> > Hi Michael and Stephen,
> >
> > This patch set was acked by Rob Herring. Do you have any comments on
> them?
> >
> > BTW:  Scott should stay in author, do I need to resend them with author
> changed or you can change it when applying?
> >
> 
> Please resend these two patches.

Those two patches have been merged several months ago. No need to resend.
Thanks.

Regards,
Andy

> 
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
> Linux Foundation Collaborative Project

RE: [PATCH 1/2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

Hi,

> -Original Message-
> From: sb...@codeaurora.org [mailto:sb...@codeaurora.org]
> Sent: Saturday, July 22, 2017 6:03 AM
> To: Andy Tang 
> Cc: mturque...@baylibre.com; mark.rutl...@arm.com; linux-
> c...@vger.kernel.org; devicet...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott Wood
> ; Rob Herring 
> Subject: Re: [PATCH 1/2] dt-bindings: qoriq-clock: Add coreclk
> 
> On 03/09, Y.T. Tang wrote:
> > Hi Michael and Stephen,
> >
> > This patch set was acked by Rob Herring. Do you have any comments on
> them?
> >
> > BTW:  Scott should stay in author, do I need to resend them with author
> changed or you can change it when applying?
> >
> 
> Please resend these two patches.

Those two patches have been merged several months ago. No need to resend.
Thanks.

Regards,
Andy

> 
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
> Linux Foundation Collaborative Project

RE: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a

[Andy Tang]

Hi Stephen,

Thanks for your applying.

There are other two patches sent on April 6, 2017:
https://patchwork.kernel.org/patch/9665973/
https://patchwork.kernel.org/patch/9665977/

Hope they are in your review queue. Please give it a review.

Regards,
Andy

-Original Message-
From: Stephen Boyd [mailto:sb...@codeaurora.org] 
Sent: Thursday, June 01, 2017 4:28 PM
To: Andy Tang <andy.t...@nxp.com>
Cc: mturque...@baylibre.com; robh...@kernel.org; mark.rutl...@arm.com; 
linux-...@vger.kernel.org; devicet...@vger.kernel.org; 
linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott Wood 
<o...@buserror.net>
Subject: Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs 
on ls1012a

On 03/20, Yuantian Tang wrote:
> From: Scott Wood <o...@buserror.net>
> 
> ls1012a has separate input root clocks for core PLLs versus the 
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will 
> be used for the core PLLs.
> 
> Signed-off-by: Scott Wood <o...@buserror.net>
> Signed-off-by: Tang Yuantian <andy.t...@nxp.com>
> Acked-by: Rob Herring <r...@kernel.org>
> ---

Applied to clk-next

--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux 
Foundation Collaborative Project

RE: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a

[Andy Tang]

Hi Stephen,

Thanks for your applying.

There are other two patches sent on April 6, 2017:
https://patchwork.kernel.org/patch/9665973/
https://patchwork.kernel.org/patch/9665977/

Hope they are in your review queue. Please give it a review.

Regards,
Andy

-Original Message-
From: Stephen Boyd [mailto:sb...@codeaurora.org] 
Sent: Thursday, June 01, 2017 4:28 PM
To: Andy Tang 
Cc: mturque...@baylibre.com; robh...@kernel.org; mark.rutl...@arm.com; 
linux-...@vger.kernel.org; devicet...@vger.kernel.org; 
linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott Wood 

Subject: Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs 
on ls1012a

On 03/20, Yuantian Tang wrote:
> From: Scott Wood 
> 
> ls1012a has separate input root clocks for core PLLs versus the 
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will 
> be used for the core PLLs.
> 
> Signed-off-by: Scott Wood 
> Signed-off-by: Tang Yuantian 
> Acked-by: Rob Herring 
> ---

Applied to clk-next

--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux 
Foundation Collaborative Project

RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

Hi Stephen and Michael,

How many times do I need to push those patch get merged?

Regards,
Andy

-Original Message-
From: Andy Tang 
Sent: Monday, April 17, 2017 9:37 AM
To: 'mturque...@baylibre.com' <mturque...@baylibre.com>; 'sb...@codeaurora.org' 
<sb...@codeaurora.org>
Cc: 'robh...@kernel.org' <robh...@kernel.org>; 'mark.rutl...@arm.com' 
<mark.rutl...@arm.com>; 'linux-...@vger.kernel.org' 
<linux-...@vger.kernel.org>; 'devicet...@vger.kernel.org' 
<devicet...@vger.kernel.org>; 'linux-kernel@vger.kernel.org' 
<linux-kernel@vger.kernel.org>; 'linux-arm-ker...@lists.infradead.org' 
<linux-arm-ker...@lists.infradead.org>; 'Scott Wood' <o...@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

Hi Stephen and Michael,

This patch set has been pending for more than two months since it was first 
sent.
I have not received any response from you until now.

Could you give some comments on it?

Regards,
Andy

-Original Message-
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturque...@baylibre.com; sb...@codeaurora.org
Cc: robh...@kernel.org; mark.rutl...@arm.com; linux-...@vger.kernel.org; 
devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; 
linux-arm-ker...@lists.infradead.org; Scott Wood <o...@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

Hello 

Do you have any comments on this patch set which was acked by Rob?

Regards,
Andy

> -Original Message-
> From: Yuantian Tang [mailto:andy.t...@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturque...@baylibre.com
> Cc: sb...@codeaurora.org; robh...@kernel.org; mark.rutl...@arm.com; 
> linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux- 
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott 
> Wood <o...@buserror.net>; Andy Tang <andy.t...@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> From: Scott Wood <o...@buserror.net>
> 
> ls1012a has separate input root clocks for core PLLs versus the 
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named 
> "coreclk".  If present, this clock will be used for the core PLLs.
> 
> Signed-off-by: Scott Wood <o...@buserror.net>
> Signed-off-by: Tang Yuantian <andy.t...@nxp.com>
> Acked-by: Rob Herring <r...@kernel.org>
> ---
> v2:
>   -- change the author to Scott
>  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
>  - clocks: If clock-frequency is not specified, sysclk may be provided
>   as an input clock.  Either clock-frequency or clocks must be
>   provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present.  Valid names are
> + "sysclk" and "coreclk".
> 
>  2. Clock Provider
> 
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
>   2   hwaccel index (n in CLKCGnHWACSR)
>   3   fman0 for fm1, 1 for fm2
>   4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5   coreclk must be 0
> 
>  3. Example
> 
> --
> 2.1.0.27.g96db324

RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

Hi Stephen and Michael,

How many times do I need to push those patch get merged?

Regards,
Andy

-Original Message-
From: Andy Tang 
Sent: Monday, April 17, 2017 9:37 AM
To: 'mturque...@baylibre.com' ; 'sb...@codeaurora.org' 

Cc: 'robh...@kernel.org' ; 'mark.rutl...@arm.com' 
; 'linux-...@vger.kernel.org' 
; 'devicet...@vger.kernel.org' 
; 'linux-kernel@vger.kernel.org' 
; 'linux-arm-ker...@lists.infradead.org' 
; 'Scott Wood' 
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

Hi Stephen and Michael,

This patch set has been pending for more than two months since it was first 
sent.
I have not received any response from you until now.

Could you give some comments on it?

Regards,
Andy

-Original Message-
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturque...@baylibre.com; sb...@codeaurora.org
Cc: robh...@kernel.org; mark.rutl...@arm.com; linux-...@vger.kernel.org; 
devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; 
linux-arm-ker...@lists.infradead.org; Scott Wood 
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

Hello 

Do you have any comments on this patch set which was acked by Rob?

Regards,
Andy

> -Original Message-
> From: Yuantian Tang [mailto:andy.t...@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturque...@baylibre.com
> Cc: sb...@codeaurora.org; robh...@kernel.org; mark.rutl...@arm.com; 
> linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux- 
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott 
> Wood ; Andy Tang 
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> From: Scott Wood 
> 
> ls1012a has separate input root clocks for core PLLs versus the 
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named 
> "coreclk".  If present, this clock will be used for the core PLLs.
> 
> Signed-off-by: Scott Wood 
> Signed-off-by: Tang Yuantian 
> Acked-by: Rob Herring 
> ---
> v2:
>   -- change the author to Scott
>  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
>  - clocks: If clock-frequency is not specified, sysclk may be provided
>   as an input clock.  Either clock-frequency or clocks must be
>   provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present.  Valid names are
> + "sysclk" and "coreclk".
> 
>  2. Clock Provider
> 
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
>   2   hwaccel index (n in CLKCGnHWACSR)
>   3   fman0 for fm1, 1 for fm2
>   4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5   coreclk must be 0
> 
>  3. Example
> 
> --
> 2.1.0.27.g96db324

RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

Hi Robh,

Could you please take a look at this patch set? They are pending for a really 
long time.
Don't know why they have not been merged.

Patch links:
https://patchwork.kernel.org/patch/9633007/
https://patchwork.kernel.org/patch/9633009/

Regards,
Andy

> -Original Message-
> From: Andy Tang
> Sent: Monday, April 24, 2017 11:15 AM
> To: mturque...@baylibre.com; sb...@codeaurora.org
> Cc: robh...@kernel.org; mark.rutl...@arm.com; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; Scott Wood <o...@buserror.net>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> Does anyone give me a clue why this patch set can't be responded after so
> long time?
> 
> Thanks,
> Andy
> 
> -Original Message-
> From: Andy Tang
> Sent: Monday, April 17, 2017 9:37 AM
> To: 'mturque...@baylibre.com' <mturque...@baylibre.com>;
> 'sb...@codeaurora.org' <sb...@codeaurora.org>
> Cc: 'robh...@kernel.org' <robh...@kernel.org>; 'mark.rutl...@arm.com'
> <mark.rutl...@arm.com>; 'linux-...@vger.kernel.org'  c...@vger.kernel.org>; 'devicet...@vger.kernel.org'
> <devicet...@vger.kernel.org>; 'linux-kernel@vger.kernel.org'  ker...@vger.kernel.org>; 'linux-arm-ker...@lists.infradead.org'  ker...@lists.infradead.org>; 'Scott Wood' <o...@buserror.net>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> Hi Stephen and Michael,
> 
> This patch set has been pending for more than two months since it was first
> sent.
> I have not received any response from you until now.
> 
> Could you give some comments on it?
> 
> Regards,
> Andy
> 
> -Original Message-
> From: Andy Tang
> Sent: Wednesday, April 05, 2017 2:16 PM
> To: mturque...@baylibre.com; sb...@codeaurora.org
> Cc: robh...@kernel.org; mark.rutl...@arm.com; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; Scott Wood <o...@buserror.net>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> Hello
> 
> Do you have any comments on this patch set which was acked by Rob?
> 
> Regards,
> Andy
> 
> > -Original Message-
> > From: Yuantian Tang [mailto:andy.t...@nxp.com]
> > Sent: Monday, March 20, 2017 10:37 AM
> > To: mturque...@baylibre.com
> > Cc: sb...@codeaurora.org; robh...@kernel.org; mark.rutl...@arm.com;
> > linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux-
> > ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott
> > Wood <o...@buserror.net>; Andy Tang <andy.t...@nxp.com>
> > Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> >
> > From: Scott Wood <o...@buserror.net>
> >
> > ls1012a has separate input root clocks for core PLLs versus the
> > platform PLL, with the latter described as sysclk in the hw docs.
> > Update the qoriq-clock binding to allow a second input clock, named
> > "coreclk".  If present, this clock will be used for the core PLLs.
> >
> > Signed-off-by: Scott Wood <o...@buserror.net>
> > Signed-off-by: Tang Yuantian <andy.t...@nxp.com>
> > Acked-by: Rob Herring <r...@kernel.org>
> > ---
> > v2:
> > -- change the author to Scott
> >  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > index aa3526f..119cafd 100644
> > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > @@ -56,6 +56,11 @@ Optional properties:
> >  - clocks: If clock-frequency is not specified, sysclk may be provided
> > as an input clock.  Either clock-frequency or clocks must be
> > provided.
> > +   A second input clock, called "coreclk", may be provided if
> > +   core PLLs are based on a different input clock from the
> > +   platform PLL.
> > +- clock-names: Required if a coreclk is present.  Valid names are
> > +   "sysclk" and "coreclk".
> >
> >  2. Clock Provider
> >
> > @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> > 2   hwaccel index (n in CLKCGnHWACSR)
> > 3   fman0 for fm1, 1 for fm2
> > 4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> > +   5   coreclk must be 0
> >
> >  3. Example
> >
> > --
> > 2.1.0.27.g96db324

RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

Hi Robh,

Could you please take a look at this patch set? They are pending for a really 
long time.
Don't know why they have not been merged.

Patch links:
https://patchwork.kernel.org/patch/9633007/
https://patchwork.kernel.org/patch/9633009/

Regards,
Andy

> -Original Message-
> From: Andy Tang
> Sent: Monday, April 24, 2017 11:15 AM
> To: mturque...@baylibre.com; sb...@codeaurora.org
> Cc: robh...@kernel.org; mark.rutl...@arm.com; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; Scott Wood 
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> Does anyone give me a clue why this patch set can't be responded after so
> long time?
> 
> Thanks,
> Andy
> 
> -Original Message-
> From: Andy Tang
> Sent: Monday, April 17, 2017 9:37 AM
> To: 'mturque...@baylibre.com' ;
> 'sb...@codeaurora.org' 
> Cc: 'robh...@kernel.org' ; 'mark.rutl...@arm.com'
> ; 'linux-...@vger.kernel.org'  c...@vger.kernel.org>; 'devicet...@vger.kernel.org'
> ; 'linux-kernel@vger.kernel.org'  ker...@vger.kernel.org>; 'linux-arm-ker...@lists.infradead.org'  ker...@lists.infradead.org>; 'Scott Wood' 
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> Hi Stephen and Michael,
> 
> This patch set has been pending for more than two months since it was first
> sent.
> I have not received any response from you until now.
> 
> Could you give some comments on it?
> 
> Regards,
> Andy
> 
> -Original Message-
> From: Andy Tang
> Sent: Wednesday, April 05, 2017 2:16 PM
> To: mturque...@baylibre.com; sb...@codeaurora.org
> Cc: robh...@kernel.org; mark.rutl...@arm.com; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; Scott Wood 
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> Hello
> 
> Do you have any comments on this patch set which was acked by Rob?
> 
> Regards,
> Andy
> 
> > -Original Message-
> > From: Yuantian Tang [mailto:andy.t...@nxp.com]
> > Sent: Monday, March 20, 2017 10:37 AM
> > To: mturque...@baylibre.com
> > Cc: sb...@codeaurora.org; robh...@kernel.org; mark.rutl...@arm.com;
> > linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux-
> > ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott
> > Wood ; Andy Tang 
> > Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> >
> > From: Scott Wood 
> >
> > ls1012a has separate input root clocks for core PLLs versus the
> > platform PLL, with the latter described as sysclk in the hw docs.
> > Update the qoriq-clock binding to allow a second input clock, named
> > "coreclk".  If present, this clock will be used for the core PLLs.
> >
> > Signed-off-by: Scott Wood 
> > Signed-off-by: Tang Yuantian 
> > Acked-by: Rob Herring 
> > ---
> > v2:
> > -- change the author to Scott
> >  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > index aa3526f..119cafd 100644
> > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > @@ -56,6 +56,11 @@ Optional properties:
> >  - clocks: If clock-frequency is not specified, sysclk may be provided
> > as an input clock.  Either clock-frequency or clocks must be
> > provided.
> > +   A second input clock, called "coreclk", may be provided if
> > +   core PLLs are based on a different input clock from the
> > +   platform PLL.
> > +- clock-names: Required if a coreclk is present.  Valid names are
> > +   "sysclk" and "coreclk".
> >
> >  2. Clock Provider
> >
> > @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> > 2   hwaccel index (n in CLKCGnHWACSR)
> > 3   fman0 for fm1, 1 for fm2
> > 4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> > +   5   coreclk must be 0
> >
> >  3. Example
> >
> > --
> > 2.1.0.27.g96db324

RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

Does anyone give me a clue why this patch set can't be responded after so long 
time?

Thanks,
Andy

-Original Message-
From: Andy Tang 
Sent: Monday, April 17, 2017 9:37 AM
To: 'mturque...@baylibre.com' <mturque...@baylibre.com>; 'sb...@codeaurora.org' 
<sb...@codeaurora.org>
Cc: 'robh...@kernel.org' <robh...@kernel.org>; 'mark.rutl...@arm.com' 
<mark.rutl...@arm.com>; 'linux-...@vger.kernel.org' 
<linux-...@vger.kernel.org>; 'devicet...@vger.kernel.org' 
<devicet...@vger.kernel.org>; 'linux-kernel@vger.kernel.org' 
<linux-kernel@vger.kernel.org>; 'linux-arm-ker...@lists.infradead.org' 
<linux-arm-ker...@lists.infradead.org>; 'Scott Wood' <o...@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

Hi Stephen and Michael,

This patch set has been pending for more than two months since it was first 
sent.
I have not received any response from you until now.

Could you give some comments on it?

Regards,
Andy

-Original Message-
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturque...@baylibre.com; sb...@codeaurora.org
Cc: robh...@kernel.org; mark.rutl...@arm.com; linux-...@vger.kernel.org; 
devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; 
linux-arm-ker...@lists.infradead.org; Scott Wood <o...@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

Hello 

Do you have any comments on this patch set which was acked by Rob?

Regards,
Andy

> -Original Message-
> From: Yuantian Tang [mailto:andy.t...@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturque...@baylibre.com
> Cc: sb...@codeaurora.org; robh...@kernel.org; mark.rutl...@arm.com; 
> linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux- 
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott 
> Wood <o...@buserror.net>; Andy Tang <andy.t...@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> From: Scott Wood <o...@buserror.net>
> 
> ls1012a has separate input root clocks for core PLLs versus the 
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named 
> "coreclk".  If present, this clock will be used for the core PLLs.
> 
> Signed-off-by: Scott Wood <o...@buserror.net>
> Signed-off-by: Tang Yuantian <andy.t...@nxp.com>
> Acked-by: Rob Herring <r...@kernel.org>
> ---
> v2:
>   -- change the author to Scott
>  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
>  - clocks: If clock-frequency is not specified, sysclk may be provided
>   as an input clock.  Either clock-frequency or clocks must be
>   provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present.  Valid names are
> + "sysclk" and "coreclk".
> 
>  2. Clock Provider
> 
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
>   2   hwaccel index (n in CLKCGnHWACSR)
>   3   fman0 for fm1, 1 for fm2
>   4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5   coreclk must be 0
> 
>  3. Example
> 
> --
> 2.1.0.27.g96db324

RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

Does anyone give me a clue why this patch set can't be responded after so long 
time?

Thanks,
Andy

-Original Message-
From: Andy Tang 
Sent: Monday, April 17, 2017 9:37 AM
To: 'mturque...@baylibre.com' ; 'sb...@codeaurora.org' 

Cc: 'robh...@kernel.org' ; 'mark.rutl...@arm.com' 
; 'linux-...@vger.kernel.org' 
; 'devicet...@vger.kernel.org' 
; 'linux-kernel@vger.kernel.org' 
; 'linux-arm-ker...@lists.infradead.org' 
; 'Scott Wood' 
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

Hi Stephen and Michael,

This patch set has been pending for more than two months since it was first 
sent.
I have not received any response from you until now.

Could you give some comments on it?

Regards,
Andy

-Original Message-
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturque...@baylibre.com; sb...@codeaurora.org
Cc: robh...@kernel.org; mark.rutl...@arm.com; linux-...@vger.kernel.org; 
devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; 
linux-arm-ker...@lists.infradead.org; Scott Wood 
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

Hello 

Do you have any comments on this patch set which was acked by Rob?

Regards,
Andy

> -Original Message-
> From: Yuantian Tang [mailto:andy.t...@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturque...@baylibre.com
> Cc: sb...@codeaurora.org; robh...@kernel.org; mark.rutl...@arm.com; 
> linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux- 
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott 
> Wood ; Andy Tang 
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> From: Scott Wood 
> 
> ls1012a has separate input root clocks for core PLLs versus the 
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named 
> "coreclk".  If present, this clock will be used for the core PLLs.
> 
> Signed-off-by: Scott Wood 
> Signed-off-by: Tang Yuantian 
> Acked-by: Rob Herring 
> ---
> v2:
>   -- change the author to Scott
>  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
>  - clocks: If clock-frequency is not specified, sysclk may be provided
>   as an input clock.  Either clock-frequency or clocks must be
>   provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present.  Valid names are
> + "sysclk" and "coreclk".
> 
>  2. Clock Provider
> 
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
>   2   hwaccel index (n in CLKCGnHWACSR)
>   3   fman0 for fm1, 1 for fm2
>   4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5   coreclk must be 0
> 
>  3. Example
> 
> --
> 2.1.0.27.g96db324

RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

Hi Stephen and Michael,

This patch set has been pending for more than two months since it was first 
sent.
I have not received any response from you until now.

Could you give some comments on it?

Regards,
Andy

-Original Message-
From: Andy Tang 
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturque...@baylibre.com; sb...@codeaurora.org
Cc: robh...@kernel.org; mark.rutl...@arm.com; linux-...@vger.kernel.org; 
devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; 
linux-arm-ker...@lists.infradead.org; Scott Wood <o...@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

Hello 

Do you have any comments on this patch set which was acked by Rob?

Regards,
Andy

> -Original Message-
> From: Yuantian Tang [mailto:andy.t...@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturque...@baylibre.com
> Cc: sb...@codeaurora.org; robh...@kernel.org; mark.rutl...@arm.com; 
> linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux- 
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott 
> Wood <o...@buserror.net>; Andy Tang <andy.t...@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> From: Scott Wood <o...@buserror.net>
> 
> ls1012a has separate input root clocks for core PLLs versus the 
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named 
> "coreclk".  If present, this clock will be used for the core PLLs.
> 
> Signed-off-by: Scott Wood <o...@buserror.net>
> Signed-off-by: Tang Yuantian <andy.t...@nxp.com>
> Acked-by: Rob Herring <r...@kernel.org>
> ---
> v2:
>   -- change the author to Scott
>  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
>  - clocks: If clock-frequency is not specified, sysclk may be provided
>   as an input clock.  Either clock-frequency or clocks must be
>   provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present.  Valid names are
> + "sysclk" and "coreclk".
> 
>  2. Clock Provider
> 
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
>   2   hwaccel index (n in CLKCGnHWACSR)
>   3   fman0 for fm1, 1 for fm2
>   4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5   coreclk must be 0
> 
>  3. Example
> 
> --
> 2.1.0.27.g96db324

RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

Hi Stephen and Michael,

This patch set has been pending for more than two months since it was first 
sent.
I have not received any response from you until now.

Could you give some comments on it?

Regards,
Andy

-Original Message-
From: Andy Tang 
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturque...@baylibre.com; sb...@codeaurora.org
Cc: robh...@kernel.org; mark.rutl...@arm.com; linux-...@vger.kernel.org; 
devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; 
linux-arm-ker...@lists.infradead.org; Scott Wood 
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

Hello 

Do you have any comments on this patch set which was acked by Rob?

Regards,
Andy

> -Original Message-
> From: Yuantian Tang [mailto:andy.t...@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturque...@baylibre.com
> Cc: sb...@codeaurora.org; robh...@kernel.org; mark.rutl...@arm.com; 
> linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux- 
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott 
> Wood ; Andy Tang 
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> From: Scott Wood 
> 
> ls1012a has separate input root clocks for core PLLs versus the 
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named 
> "coreclk".  If present, this clock will be used for the core PLLs.
> 
> Signed-off-by: Scott Wood 
> Signed-off-by: Tang Yuantian 
> Acked-by: Rob Herring 
> ---
> v2:
>   -- change the author to Scott
>  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
>  - clocks: If clock-frequency is not specified, sysclk may be provided
>   as an input clock.  Either clock-frequency or clocks must be
>   provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present.  Valid names are
> + "sysclk" and "coreclk".
> 
>  2. Clock Provider
> 
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
>   2   hwaccel index (n in CLKCGnHWACSR)
>   3   fman0 for fm1, 1 for fm2
>   4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5   coreclk must be 0
> 
>  3. Example
> 
> --
> 2.1.0.27.g96db324

RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

Hello Stephen and Michael,

Do you have any comments on this patch set which was acked by Rob?

Regards,
Andy

> -Original Message-
> From: Yuantian Tang [mailto:andy.t...@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturque...@baylibre.com
> Cc: sb...@codeaurora.org; robh...@kernel.org; mark.rutl...@arm.com;
> linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott Wood
> <o...@buserror.net>; Andy Tang <andy.t...@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> From: Scott Wood <o...@buserror.net>
> 
> ls1012a has separate input root clocks for core PLLs versus the platform PLL,
> with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk".  If present, this clock will be used for the core PLLs.
> 
> Signed-off-by: Scott Wood <o...@buserror.net>
> Signed-off-by: Tang Yuantian <andy.t...@nxp.com>
> Acked-by: Rob Herring <r...@kernel.org>
> ---
> v2:
>   -- change the author to Scott
>  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
>  - clocks: If clock-frequency is not specified, sysclk may be provided
>   as an input clock.  Either clock-frequency or clocks must be
>   provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present.  Valid names are
> + "sysclk" and "coreclk".
> 
>  2. Clock Provider
> 
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
>   2   hwaccel index (n in CLKCGnHWACSR)
>   3   fman0 for fm1, 1 for fm2
>   4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5   coreclk must be 0
> 
>  3. Example
> 
> --
> 2.1.0.27.g96db324

RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

Hello Stephen and Michael,

Do you have any comments on this patch set which was acked by Rob?

Regards,
Andy

> -Original Message-
> From: Yuantian Tang [mailto:andy.t...@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturque...@baylibre.com
> Cc: sb...@codeaurora.org; robh...@kernel.org; mark.rutl...@arm.com;
> linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott Wood
> ; Andy Tang 
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> From: Scott Wood 
> 
> ls1012a has separate input root clocks for core PLLs versus the platform PLL,
> with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk".  If present, this clock will be used for the core PLLs.
> 
> Signed-off-by: Scott Wood 
> Signed-off-by: Tang Yuantian 
> Acked-by: Rob Herring 
> ---
> v2:
>   -- change the author to Scott
>  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
>  - clocks: If clock-frequency is not specified, sysclk may be provided
>   as an input clock.  Either clock-frequency or clocks must be
>   provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present.  Valid names are
> + "sysclk" and "coreclk".
> 
>  2. Clock Provider
> 
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
>   2   hwaccel index (n in CLKCGnHWACSR)
>   3   fman0 for fm1, 1 for fm2
>   4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5   coreclk must be 0
> 
>  3. Example
> 
> --
> 2.1.0.27.g96db324

RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

PING!

Regards,
Yuantian

> -Original Message-
> From: Yuantian Tang [mailto:andy.t...@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturque...@baylibre.com
> Cc: sb...@codeaurora.org; robh...@kernel.org; mark.rutl...@arm.com;
> linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott Wood;
> Andy Tang
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> From: Scott Wood <o...@buserror.net>
> 
> ls1012a has separate input root clocks for core PLLs versus the platform PLL,
> with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk".  If present, this clock will be used for the core PLLs.
> 
> Signed-off-by: Scott Wood <o...@buserror.net>
> Signed-off-by: Tang Yuantian <andy.t...@nxp.com>
> Acked-by: Rob Herring <r...@kernel.org>
> ---
> v2:
>   -- change the author to Scott
>  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
>  - clocks: If clock-frequency is not specified, sysclk may be provided
>   as an input clock.  Either clock-frequency or clocks must be
>   provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present.  Valid names are
> + "sysclk" and "coreclk".
> 
>  2. Clock Provider
> 
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
>   2   hwaccel index (n in CLKCGnHWACSR)
>   3   fman0 for fm1, 1 for fm2
>   4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5   coreclk must be 0
> 
>  3. Example
> 
> --
> 2.1.0.27.g96db324

RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Andy Tang]

PING!

Regards,
Yuantian

> -Original Message-
> From: Yuantian Tang [mailto:andy.t...@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturque...@baylibre.com
> Cc: sb...@codeaurora.org; robh...@kernel.org; mark.rutl...@arm.com;
> linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Scott Wood;
> Andy Tang
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> 
> From: Scott Wood 
> 
> ls1012a has separate input root clocks for core PLLs versus the platform PLL,
> with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk".  If present, this clock will be used for the core PLLs.
> 
> Signed-off-by: Scott Wood 
> Signed-off-by: Tang Yuantian 
> Acked-by: Rob Herring 
> ---
> v2:
>   -- change the author to Scott
>  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
>  - clocks: If clock-frequency is not specified, sysclk may be provided
>   as an input clock.  Either clock-frequency or clocks must be
>   provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present.  Valid names are
> + "sysclk" and "coreclk".
> 
>  2. Clock Provider
> 
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
>   2   hwaccel index (n in CLKCGnHWACSR)
>   3   fman0 for fm1, 1 for fm2
>   4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5   coreclk must be 0
> 
>  3. Example
> 
> --
> 2.1.0.27.g96db324

RE: [PATCH] cpufreq: qoriq: enhance bus frequency calculation

[Andy Tang]

Hi Viresh,

> -Original Message-
> From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
> Sent: Friday, March 10, 2017 6:05 PM
> To: Andy Tang
> Cc: r...@rjwysocki.net; linux...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH] cpufreq: qoriq: enhance bus frequency calculation
> 
> On 10-03-17, 01:44, Andy Tang wrote:
> > > Will this always work? If yes, then what about dropping the code
> > > parsing DT completely ? That is, just rely on clk_get_rate() in all cases.
> > >
> > We put all the clock tree configuration in driver, not in dts.
> > cg-pll0-div1 is hardcoded in driver since we don't depend on dts.
> > We kind of don't have other choices but use the hardcode clock name
> > here too.
> 
> Looks like you misread my comment. Let me try again. Will it be fine to write
> get_bus_freq() this way?
> 
> static u32 get_bus_freq(void)
> {
>   struct clk *pltclk;
> 
>   /* get platform freq by its clock name */
>   pltclk = clk_get(NULL, "cg-pll0-div1");
>   if (IS_ERR(pltclk)) {
>   pr_err("%s: can't get bus frequency %ld\n",
>  __func__, PTR_ERR(pltclk));
>   return PTR_ERR(pltclk);
>   }
> 
>   return clk_get_rate(pltclk);
> }
> 
Yes, we can. But for some legacy powerpc-based socs, this may not work.
powerpc-base socs are still  using legacy clock driver. For compatibility sake, 
we better be compatible with old ones. It would break any compatibility this 
way.

Regards,
Yuantian

> --
> viresh

RE: [PATCH] cpufreq: qoriq: enhance bus frequency calculation

[Andy Tang]

Hi Viresh,

> -Original Message-
> From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
> Sent: Friday, March 10, 2017 6:05 PM
> To: Andy Tang
> Cc: r...@rjwysocki.net; linux...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH] cpufreq: qoriq: enhance bus frequency calculation
> 
> On 10-03-17, 01:44, Andy Tang wrote:
> > > Will this always work? If yes, then what about dropping the code
> > > parsing DT completely ? That is, just rely on clk_get_rate() in all cases.
> > >
> > We put all the clock tree configuration in driver, not in dts.
> > cg-pll0-div1 is hardcoded in driver since we don't depend on dts.
> > We kind of don't have other choices but use the hardcode clock name
> > here too.
> 
> Looks like you misread my comment. Let me try again. Will it be fine to write
> get_bus_freq() this way?
> 
> static u32 get_bus_freq(void)
> {
>   struct clk *pltclk;
> 
>   /* get platform freq by its clock name */
>   pltclk = clk_get(NULL, "cg-pll0-div1");
>   if (IS_ERR(pltclk)) {
>   pr_err("%s: can't get bus frequency %ld\n",
>  __func__, PTR_ERR(pltclk));
>   return PTR_ERR(pltclk);
>   }
> 
>   return clk_get_rate(pltclk);
> }
> 
Yes, we can. But for some legacy powerpc-based socs, this may not work.
powerpc-base socs are still  using legacy clock driver. For compatibility sake, 
we better be compatible with old ones. It would break any compatibility this 
way.

Regards,
Yuantian

> --
> viresh

RE: [PATCH] cpufreq: qoriq: enhance bus frequency calculation

[Andy Tang]

Hi Viresh,

> -Original Message-
> From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
> Sent: Thursday, March 09, 2017 5:39 PM
> To: Y.T. Tang
> Cc: r...@rjwysocki.net; linux...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Y.T. Tang
> Subject: Re: [PATCH] cpufreq: qoriq: enhance bus frequency calculation
> 
> On 09-03-17, 16:15, YuanTian Tang wrote:
> > From: Tang Yuantian 
> >
> > On some platforms, property device-type may be missed in soc node in
> > dts which caused the bus-frequency can not be obtained correctly.
> >
> > This patch enhanced the bus-frequency calculation. When property
> > device-type is missed in dts, bus-frequency will be obtained by
> > looking up clock table to get platform clock and hence get its
> > frequency.
> >
> > Signed-off-by: Tang Yuantian 
> > ---
> >  drivers/cpufreq/qoriq-cpufreq.c | 24 +---
> >  1 file changed, 17 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/cpufreq/qoriq-cpufreq.c
> > b/drivers/cpufreq/qoriq-cpufreq.c index bfec1bc..0f22e40 100644
> > --- a/drivers/cpufreq/qoriq-cpufreq.c
> > +++ b/drivers/cpufreq/qoriq-cpufreq.c
> > @@ -52,17 +52,27 @@ static u32 get_bus_freq(void)  {
> > struct device_node *soc;
> > u32 sysfreq;
> > +   struct clk *pltclk;
> > +   int ret;
> >
> > +   /* get platform freq by searching bus-frequency property */
> > soc = of_find_node_by_type(NULL, "soc");
> > -   if (!soc)
> > -   return 0;
> > -
> > -   if (of_property_read_u32(soc, "bus-frequency", ))
> > -   sysfreq = 0;
> > +   if (soc) {
> > +   ret = of_property_read_u32(soc, "bus-frequency", );
> > +   of_node_put(soc);
> > +   if (!ret)
> > +   return sysfreq;
> > +   }
> >
> > -   of_node_put(soc);
> > +   /* get platform freq by its clock name */
> > +   pltclk = clk_get(NULL, "cg-pll0-div1");
> 
> Will this always work? If yes, then what about dropping the code parsing DT
> completely ? That is, just rely on clk_get_rate() in all cases.
> 
We put all the clock tree configuration in driver, not in dts.  cg-pll0-div1 is 
hardcoded in driver since we don't depend on dts.  We kind of don't have other 
choices but use the hardcode clock name here too.

> > +   if (IS_ERR(pltclk)) {
> > +   pr_err("%s: can't get bus frequency %ld\n",
> > +   __func__, PTR_ERR(pltclk));
> 
> You need to properly align this. Try running checkpatch over this patch or:
> 
> checkpatch --strict
> 
I did check it with checkpatch script, but without --strict parameter.
After applying --strict, script tell the alignment issue. :)

Regards,
Andy

> > +   return PTR_ERR(pltclk);
> > +   }
> >
> > -   return sysfreq;
> > +   return clk_get_rate(pltclk);
> >  }
> >
> >  static struct clk *cpu_to_clk(int cpu)
> > --
> > 2.1.0.27.g96db324
> 
> --
> viresh

RE: [PATCH] cpufreq: qoriq: enhance bus frequency calculation

[Andy Tang]

Hi Viresh,

> -Original Message-
> From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
> Sent: Thursday, March 09, 2017 5:39 PM
> To: Y.T. Tang
> Cc: r...@rjwysocki.net; linux...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Y.T. Tang
> Subject: Re: [PATCH] cpufreq: qoriq: enhance bus frequency calculation
> 
> On 09-03-17, 16:15, YuanTian Tang wrote:
> > From: Tang Yuantian 
> >
> > On some platforms, property device-type may be missed in soc node in
> > dts which caused the bus-frequency can not be obtained correctly.
> >
> > This patch enhanced the bus-frequency calculation. When property
> > device-type is missed in dts, bus-frequency will be obtained by
> > looking up clock table to get platform clock and hence get its
> > frequency.
> >
> > Signed-off-by: Tang Yuantian 
> > ---
> >  drivers/cpufreq/qoriq-cpufreq.c | 24 +---
> >  1 file changed, 17 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/cpufreq/qoriq-cpufreq.c
> > b/drivers/cpufreq/qoriq-cpufreq.c index bfec1bc..0f22e40 100644
> > --- a/drivers/cpufreq/qoriq-cpufreq.c
> > +++ b/drivers/cpufreq/qoriq-cpufreq.c
> > @@ -52,17 +52,27 @@ static u32 get_bus_freq(void)  {
> > struct device_node *soc;
> > u32 sysfreq;
> > +   struct clk *pltclk;
> > +   int ret;
> >
> > +   /* get platform freq by searching bus-frequency property */
> > soc = of_find_node_by_type(NULL, "soc");
> > -   if (!soc)
> > -   return 0;
> > -
> > -   if (of_property_read_u32(soc, "bus-frequency", ))
> > -   sysfreq = 0;
> > +   if (soc) {
> > +   ret = of_property_read_u32(soc, "bus-frequency", );
> > +   of_node_put(soc);
> > +   if (!ret)
> > +   return sysfreq;
> > +   }
> >
> > -   of_node_put(soc);
> > +   /* get platform freq by its clock name */
> > +   pltclk = clk_get(NULL, "cg-pll0-div1");
> 
> Will this always work? If yes, then what about dropping the code parsing DT
> completely ? That is, just rely on clk_get_rate() in all cases.
> 
We put all the clock tree configuration in driver, not in dts.  cg-pll0-div1 is 
hardcoded in driver since we don't depend on dts.  We kind of don't have other 
choices but use the hardcode clock name here too.

> > +   if (IS_ERR(pltclk)) {
> > +   pr_err("%s: can't get bus frequency %ld\n",
> > +   __func__, PTR_ERR(pltclk));
> 
> You need to properly align this. Try running checkpatch over this patch or:
> 
> checkpatch --strict
> 
I did check it with checkpatch script, but without --strict parameter.
After applying --strict, script tell the alignment issue. :)

Regards,
Andy

> > +   return PTR_ERR(pltclk);
> > +   }
> >
> > -   return sysfreq;
> > +   return clk_get_rate(pltclk);
> >  }
> >
> >  static struct clk *cpu_to_clk(int cpu)
> > --
> > 2.1.0.27.g96db324
> 
> --
> viresh