[linux-sunxi] [PATCH resend 0/6] ARM: sunxi: Add support for A10/A20 Video Engine clocks

[Chen-Yu Tsai]

Hi everyone,

(Series resent with linux-arm-kernel list added.)

This series adds support for the clocks used by the Video Engine (VPU /
video codec hardware) on the Allwinner A10/A20. The series purposely
excludes sun5i (A10s/A13/R8) to avoid any conflicts with Maxime's KMS
driver series, but adding it should be easy. VE clocks for the newer
generation of SoCs are the same, except the reset control is moved to
the common bus reset controls. These can be supported later on.

The series is meant to get platform stuff out of the way so people who
want to work on a proper driver for the VPU can do so.

The patches are pretty self-explanatory.

Regards
ChenYu

Chen-Yu Tsai (6):
  clk: sunxi: Add DRAM gates support for sun4i-a10
  clk: sunxi: Add VE (Video Engine) module clock driver for sun[457]i
  ARM: dts: sun4i: Add DRAM gates
  ARM: dts: sun4i: Add VE (Video Engine) module clock node
  ARM: dts: sun7i: Add DRAM gates
  ARM: dts: sun7i: Add VE (Video Engine) module clock node

 Documentation/devicetree/bindings/clock/sunxi.txt |   5 +
 arch/arm/boot/dts/sun4i-a10.dtsi  |  45 +-
 arch/arm/boot/dts/sun7i-a20.dtsi  |  41 +-
 drivers/clk/sunxi/Makefile|   1 +
 drivers/clk/sunxi/clk-a10-ve.c| 171 ++
 drivers/clk/sunxi/clk-simple-gates.c  |  12 ++
 6 files changed, 268 insertions(+), 7 deletions(-)
 create mode 100644 drivers/clk/sunxi/clk-a10-ve.c

-- 
2.6.2

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[linux-sunxi] [PATCH resend 3/6] ARM: dts: sun4i: Add DRAM gates

[Chen-Yu Tsai]

The DRAM gates controls direct memory access for some peripherals.
These peripherals include the display pipeline, so add the required
gates to the simplefb nodes as well.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 36 
 1 file changed, 32 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index aa90f319309b..849d0242ece8 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -66,7 +66,7 @@
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = < 1>, <_gates 36>, <_gates 43>,
-<_gates 44>;
+<_gates 44>, <_gates 26>;
status = "disabled";
};
 
@@ -75,7 +75,8 @@
 "simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
clocks = < 1>, <_gates 36>, <_gates 43>,
-<_gates 44>, <_gates 46>;
+<_gates 44>, <_gates 46>,
+<_gates 25>, <_gates 26>;
status = "disabled";
};
 
@@ -84,7 +85,8 @@
 "simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0";
clocks = < 1>, <_gates 36>, <_gates 44>,
-<_gates 46>;
+<_gates 46>, <_gates 25>,
+<_gates 26>;
status = "disabled";
};
 
@@ -93,7 +95,8 @@
 "simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
clocks = < 1>, <_gates 34>, <_gates 36>,
-<_gates 44>, <_gates 46>;
+<_gates 44>, <_gates 46>,
+<_gates 25>, <_gates 26>;
status = "disabled";
};
};
@@ -492,6 +495,31 @@
clock-output-names = "spi3";
};
 
+   dram_gates: clk@01c20100 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-dram-gates-clk";
+   reg = <0x01c20100 0x4>;
+   clocks = < 0>;
+   clock-indices = <0>,
+   <1>, <2>,
+   <3>,
+   <4>,
+   <5>, <6>,
+   <15>,
+   <24>, <25>,
+   <26>, <27>,
+   <28>, <29>;
+   clock-output-names = "dram_ve",
+"dram_csi0", "dram_csi1",
+"dram_ts",
+"dram_tvd",
+"dram_tve0", "dram_tve1",
+"dram_output",
+"dram_de_fe1", "dram_de_fe0",
+"dram_de_be0", "dram_de_be1",
+"dram_de_mp", "dram_ace";
+   };
+
codec_clk: clk@01c20140 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-codec-clk";
-- 
2.6.2

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[linux-sunxi] [PATCH resend 2/6] clk: sunxi: Add VE (Video Engine) module clock driver for sun[457]i

[Chen-Yu Tsai]

The video engine has its own special module clock, consisting of a clock
gate, configurable dividers, and a reset control.

On later (sun[68]i) families, the reset control is moved out of this
piece of hardware and grouped with reset controls of other peripherals.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |   4 +
 drivers/clk/sunxi/Makefile|   1 +
 drivers/clk/sunxi/clk-a10-ve.c| 171 ++
 3 files changed, 176 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-a10-ve.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index ef0b452806b1..14496056319f 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -74,6 +74,7 @@ Required properties:
"allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
+   "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
 
 Required properties for all clocks:
 - reg : shall be the control register address for the clock.
@@ -93,6 +94,9 @@ Required properties for all clocks:
 And "allwinner,*-usb-clk" clocks also require:
 - reset-cells : shall be set to 1
 
+The "allwinner,sun4i-a10-ve-clk" clock also requires:
+- reset-cells : shall be set to 0
+
 The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
 - #reset-cells : shall be set to 1
 - resets : shall be the reset control phandle for the mmc block.
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 103efab05ca8..78db91ad5af6 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -7,6 +7,7 @@ obj-y += clk-a10-codec.o
 obj-y += clk-a10-hosc.o
 obj-y += clk-a10-mod1.o
 obj-y += clk-a10-pll2.o
+obj-y += clk-a10-ve.o
 obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
diff --git a/drivers/clk/sunxi/clk-a10-ve.c b/drivers/clk/sunxi/clk-a10-ve.c
new file mode 100644
index ..de0fdb656150
--- /dev/null
+++ b/drivers/clk/sunxi/clk-a10-ve.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <w...@csie.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static DEFINE_SPINLOCK(ve_lock);
+
+#define SUN4I_VE_ENABLE31
+#define SUN4I_VE_DIVIDER_SHIFT 16
+#define SUN4I_VE_DIVIDER_WIDTH 3
+#define SUN4I_VE_RESET 0
+
+/**
+ * sunxi_ve_reset... - reset bit in ve clk registers handling
+ */
+
+struct ve_reset_data {
+   void __iomem*reg;
+   spinlock_t  *lock;
+   struct reset_controller_dev rcdev;
+};
+
+static int sunxi_ve_reset_assert(struct reset_controller_dev *rcdev,
+unsigned long id)
+{
+   struct ve_reset_data *data = container_of(rcdev,
+ struct ve_reset_data,
+ rcdev);
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(data->lock, flags);
+
+   reg = readl(data->reg);
+   writel(reg & ~BIT(SUN4I_VE_RESET), data->reg);
+
+   spin_unlock_irqrestore(data->lock, flags);
+
+   return 0;
+}
+
+static int sunxi_ve_reset_deassert(struct reset_controller_dev *rcdev,
+  unsigned long id)
+{
+   struct ve_reset_data *data = container_of(rcdev,
+ struct ve_reset_data,
+ rcdev);
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(data->lock, flags);
+
+   reg = readl(data->reg);
+   writel(reg | BIT(SUN4I_VE_RESET), data->reg);
+
+   spin_unlock_irqrestore(data->lock, flags);
+
+   return 0;
+}
+
+static int sunxi_ve_of_xlate(struct reset_controller_dev *rcdev,
+const struct of_phandle_args *reset_spec)
+{
+if (WARN_ON(reset_spec->args_count != 0))
+   return -EINVAL;
+
+return 0;
+}
+
+static struct reset_control_ops sunxi_ve_reset_ops = {
+   .assert = sunxi_ve_reset_assert,
+   .deassert   = sunx

[linux-sunxi] [PATCH resend 5/6] ARM: dts: sun7i: Add DRAM gates

[Chen-Yu Tsai]

The DRAM gates controls direct memory access for some peripherals.
These peripherals include the display pipeline, so add the required
gates to the simplefb nodes as well.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 32 +---
 1 file changed, 29 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index e02eb720c4fc..21169c0a6627 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -68,7 +68,7 @@
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = < 1>, <_gates 36>, <_gates 43>,
-<_gates 44>;
+<_gates 44>, <_gates 26>;
status = "disabled";
};
 
@@ -76,7 +76,8 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
-   clocks = < 1>, <_gates 36>, <_gates 44>;
+   clocks = < 1>, <_gates 36>, <_gates 44>,
+<_gates 26>;
status = "disabled";
};
 
@@ -85,7 +86,7 @@
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
clocks = < 1>, <_gates 34>, <_gates 36>,
-<_gates 44>;
+<_gates 44>, <_gates 26>;
status = "disabled";
};
};
@@ -501,6 +502,31 @@
clock-output-names = "spi3";
};
 
+   dram_gates: clk@01c20100 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-dram-gates-clk";
+   reg = <0x01c20100 0x4>;
+   clocks = < 0>;
+   clock-indices = <0>,
+   <1>, <2>,
+   <3>,
+   <4>,
+   <5>, <6>,
+   <15>,
+   <24>, <25>,
+   <26>, <27>,
+   <28>, <29>;
+   clock-output-names = "dram_ve",
+"dram_csi0", "dram_csi1",
+"dram_ts",
+"dram_tvd",
+"dram_tve0", "dram_tve1",
+"dram_output",
+"dram_de_fe1", "dram_de_fe0",
+"dram_de_be0", "dram_de_be1",
+"dram_de_mp", "dram_ace";
+   };
+
codec_clk: clk@01c20140 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-codec-clk";
-- 
2.6.2

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[linux-sunxi] [PATCH 6/6] ARM: dts: sun7i: Add VE (Video Engine) module clock node

[Chen-Yu Tsai]

The video engine has its own module clock, which also includes a
reset control for it.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 21169c0a6627..0940a788f824 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -527,6 +527,15 @@
 "dram_de_mp", "dram_ace";
};
 
+   ve_clk: clk@01c2013c {
+   #clock-cells = <0>;
+   #reset-cells = <0>;
+   compatible = "allwinner,sun4i-a10-ve-clk";
+   reg = <0x01c2013c 0x4>;
+   clocks = <>;
+   clock-output-names = "ve";
+   };
+
codec_clk: clk@01c20140 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-codec-clk";
-- 
2.6.2

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[linux-sunxi] [PATCH 3/6] ARM: dts: sun4i: Add DRAM gates

[Chen-Yu Tsai]

The DRAM gates controls direct memory access for some peripherals.
These peripherals include the display pipeline, so add the required
gates to the simplefb nodes as well.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 36 
 1 file changed, 32 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index aa90f319309b..849d0242ece8 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -66,7 +66,7 @@
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = < 1>, <_gates 36>, <_gates 43>,
-<_gates 44>;
+<_gates 44>, <_gates 26>;
status = "disabled";
};
 
@@ -75,7 +75,8 @@
 "simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
clocks = < 1>, <_gates 36>, <_gates 43>,
-<_gates 44>, <_gates 46>;
+<_gates 44>, <_gates 46>,
+<_gates 25>, <_gates 26>;
status = "disabled";
};
 
@@ -84,7 +85,8 @@
 "simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0";
clocks = < 1>, <_gates 36>, <_gates 44>,
-<_gates 46>;
+<_gates 46>, <_gates 25>,
+<_gates 26>;
status = "disabled";
};
 
@@ -93,7 +95,8 @@
 "simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
clocks = < 1>, <_gates 34>, <_gates 36>,
-<_gates 44>, <_gates 46>;
+<_gates 44>, <_gates 46>,
+<_gates 25>, <_gates 26>;
status = "disabled";
};
};
@@ -492,6 +495,31 @@
clock-output-names = "spi3";
};
 
+   dram_gates: clk@01c20100 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-dram-gates-clk";
+   reg = <0x01c20100 0x4>;
+   clocks = < 0>;
+   clock-indices = <0>,
+   <1>, <2>,
+   <3>,
+   <4>,
+   <5>, <6>,
+   <15>,
+   <24>, <25>,
+   <26>, <27>,
+   <28>, <29>;
+   clock-output-names = "dram_ve",
+"dram_csi0", "dram_csi1",
+"dram_ts",
+"dram_tvd",
+"dram_tve0", "dram_tve1",
+"dram_output",
+"dram_de_fe1", "dram_de_fe0",
+"dram_de_be0", "dram_de_be1",
+"dram_de_mp", "dram_ace";
+   };
+
codec_clk: clk@01c20140 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-codec-clk";
-- 
2.6.2

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[linux-sunxi] [PATCH 4/6] ARM: dts: sun4i: Add VE (Video Engine) module clock node

[Chen-Yu Tsai]

The video engine has its own module clock, which also includes a
reset control for it.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 849d0242ece8..2c8f5e6ad905 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -520,6 +520,15 @@
 "dram_de_mp", "dram_ace";
};
 
+   ve_clk: clk@01c2013c {
+   #clock-cells = <0>;
+   #reset-cells = <0>;
+   compatible = "allwinner,sun4i-a10-ve-clk";
+   reg = <0x01c2013c 0x4>;
+   clocks = <>;
+   clock-output-names = "ve";
+   };
+
codec_clk: clk@01c20140 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-codec-clk";
-- 
2.6.2

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[linux-sunxi] [PATCH 5/6] ARM: dts: sun7i: Add DRAM gates

[Chen-Yu Tsai]

The DRAM gates controls direct memory access for some peripherals.
These peripherals include the display pipeline, so add the required
gates to the simplefb nodes as well.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 32 +---
 1 file changed, 29 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index e02eb720c4fc..21169c0a6627 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -68,7 +68,7 @@
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = < 1>, <_gates 36>, <_gates 43>,
-<_gates 44>;
+<_gates 44>, <_gates 26>;
status = "disabled";
};
 
@@ -76,7 +76,8 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
-   clocks = < 1>, <_gates 36>, <_gates 44>;
+   clocks = < 1>, <_gates 36>, <_gates 44>,
+<_gates 26>;
status = "disabled";
};
 
@@ -85,7 +86,7 @@
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
clocks = < 1>, <_gates 34>, <_gates 36>,
-<_gates 44>;
+<_gates 44>, <_gates 26>;
status = "disabled";
};
};
@@ -501,6 +502,31 @@
clock-output-names = "spi3";
};
 
+   dram_gates: clk@01c20100 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-dram-gates-clk";
+   reg = <0x01c20100 0x4>;
+   clocks = < 0>;
+   clock-indices = <0>,
+   <1>, <2>,
+   <3>,
+   <4>,
+   <5>, <6>,
+   <15>,
+   <24>, <25>,
+   <26>, <27>,
+   <28>, <29>;
+   clock-output-names = "dram_ve",
+"dram_csi0", "dram_csi1",
+"dram_ts",
+"dram_tvd",
+"dram_tve0", "dram_tve1",
+"dram_output",
+"dram_de_fe1", "dram_de_fe0",
+"dram_de_be0", "dram_de_be1",
+"dram_de_mp", "dram_ace";
+   };
+
codec_clk: clk@01c20140 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-codec-clk";
-- 
2.6.2

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[linux-sunxi] [PATCH 2/6] clk: sunxi: Add VE (Video Engine) module clock driver for sun[457]i

[Chen-Yu Tsai]

The video engine has its own special module clock, consisting of a clock
gate, configurable dividers, and a reset control.

On later (sun[68]i) families, the reset control is moved out of this
piece of hardware and grouped with reset controls of other peripherals.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |   4 +
 drivers/clk/sunxi/Makefile|   1 +
 drivers/clk/sunxi/clk-a10-ve.c| 171 ++
 3 files changed, 176 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-a10-ve.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index ef0b452806b1..14496056319f 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -74,6 +74,7 @@ Required properties:
"allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
+   "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
 
 Required properties for all clocks:
 - reg : shall be the control register address for the clock.
@@ -93,6 +94,9 @@ Required properties for all clocks:
 And "allwinner,*-usb-clk" clocks also require:
 - reset-cells : shall be set to 1
 
+The "allwinner,sun4i-a10-ve-clk" clock also requires:
+- reset-cells : shall be set to 0
+
 The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
 - #reset-cells : shall be set to 1
 - resets : shall be the reset control phandle for the mmc block.
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 103efab05ca8..78db91ad5af6 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -7,6 +7,7 @@ obj-y += clk-a10-codec.o
 obj-y += clk-a10-hosc.o
 obj-y += clk-a10-mod1.o
 obj-y += clk-a10-pll2.o
+obj-y += clk-a10-ve.o
 obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
diff --git a/drivers/clk/sunxi/clk-a10-ve.c b/drivers/clk/sunxi/clk-a10-ve.c
new file mode 100644
index ..de0fdb656150
--- /dev/null
+++ b/drivers/clk/sunxi/clk-a10-ve.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <w...@csie.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static DEFINE_SPINLOCK(ve_lock);
+
+#define SUN4I_VE_ENABLE31
+#define SUN4I_VE_DIVIDER_SHIFT 16
+#define SUN4I_VE_DIVIDER_WIDTH 3
+#define SUN4I_VE_RESET 0
+
+/**
+ * sunxi_ve_reset... - reset bit in ve clk registers handling
+ */
+
+struct ve_reset_data {
+   void __iomem*reg;
+   spinlock_t  *lock;
+   struct reset_controller_dev rcdev;
+};
+
+static int sunxi_ve_reset_assert(struct reset_controller_dev *rcdev,
+unsigned long id)
+{
+   struct ve_reset_data *data = container_of(rcdev,
+ struct ve_reset_data,
+ rcdev);
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(data->lock, flags);
+
+   reg = readl(data->reg);
+   writel(reg & ~BIT(SUN4I_VE_RESET), data->reg);
+
+   spin_unlock_irqrestore(data->lock, flags);
+
+   return 0;
+}
+
+static int sunxi_ve_reset_deassert(struct reset_controller_dev *rcdev,
+  unsigned long id)
+{
+   struct ve_reset_data *data = container_of(rcdev,
+ struct ve_reset_data,
+ rcdev);
+   unsigned long flags;
+   u32 reg;
+
+   spin_lock_irqsave(data->lock, flags);
+
+   reg = readl(data->reg);
+   writel(reg | BIT(SUN4I_VE_RESET), data->reg);
+
+   spin_unlock_irqrestore(data->lock, flags);
+
+   return 0;
+}
+
+static int sunxi_ve_of_xlate(struct reset_controller_dev *rcdev,
+const struct of_phandle_args *reset_spec)
+{
+if (WARN_ON(reset_spec->args_count != 0))
+   return -EINVAL;
+
+return 0;
+}
+
+static struct reset_control_ops sunxi_ve_reset_ops = {
+   .assert = sunxi_ve_reset_assert,
+   .deassert   = sunx

[linux-sunxi] [PATCH 1/6] clk: sunxi: Add DRAM gates support for sun4i-a10

[Chen-Yu Tsai]

The A10/A20 share the same set of DRAM clock gates, which controls
direct memory access for some peripherals.

On the A10, bit 15 controls the system's DRAM clock output (possibly
to the DRAM chips), which we need to keep on.

On the A20 this has been moved to the DRAM controller, becoming a no-op.
However it is still listed in the user manual, so add it anyway.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-simple-gates.c  | 12 
 2 files changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 153ac72869e8..ef0b452806b1 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -57,6 +57,7 @@ Required properties:
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
+   "allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
diff --git a/drivers/clk/sunxi/clk-simple-gates.c 
b/drivers/clk/sunxi/clk-simple-gates.c
index c8acc0612c15..f4da52b5ca0e 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -160,3 +160,15 @@ CLK_OF_DECLARE(sun5i_a13_ahb, 
"allwinner,sun5i-a13-ahb-gates-clk",
   sun4i_a10_ahb_init);
 CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
   sun4i_a10_ahb_init);
+
+static const int sun4i_a10_dram_critical_clocks[] __initconst = {
+   15, /* dram_output */
+};
+
+static void __init sun4i_a10_dram_init(struct device_node *node)
+{
+   sunxi_simple_gates_setup(node, sun4i_a10_dram_critical_clocks,
+ARRAY_SIZE(sun4i_a10_dram_critical_clocks));
+}
+CLK_OF_DECLARE(sun4i_a10_dram, "allwinner,sun4i-a10-dram-gates-clk",
+  sun4i_a10_dram_init);
-- 
2.6.2

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[linux-sunxi] [PATCH 0/6] ARM: sunxi: Add support for A10/A20 Video Engine clocks

[Chen-Yu Tsai]

Hi everyone,

This series adds support for the clocks used by the Video Engine (VPU /
video codec hardware) on the Allwinner A10/A20. The series purposely
excludes sun5i (A10s/A13/R8) to avoid any conflicts with Maxime's KMS
driver series, but adding it should be easy. VE clocks for the newer
generation of SoCs are the same, except the reset control is moved to
the common bus reset controls. These can be supported later on.

The series is meant to get platform stuff out of the way so people who
want to work on a proper driver for the VPU can do so.

The patches are pretty self-explanatory.

Regards
ChenYu

Chen-Yu Tsai (6):
  clk: sunxi: Add DRAM gates support for sun4i-a10
  clk: sunxi: Add VE (Video Engine) module clock driver for sun[457]i
  ARM: dts: sun4i: Add DRAM gates
  ARM: dts: sun4i: Add VE (Video Engine) module clock node
  ARM: dts: sun7i: Add DRAM gates
  ARM: dts: sun7i: Add VE (Video Engine) module clock node

 Documentation/devicetree/bindings/clock/sunxi.txt |   5 +
 arch/arm/boot/dts/sun4i-a10.dtsi  |  45 +-
 arch/arm/boot/dts/sun7i-a20.dtsi  |  41 +-
 drivers/clk/sunxi/Makefile|   1 +
 drivers/clk/sunxi/clk-a10-ve.c| 171 ++
 drivers/clk/sunxi/clk-simple-gates.c  |  12 ++
 6 files changed, 268 insertions(+), 7 deletions(-)
 create mode 100644 drivers/clk/sunxi/clk-a10-ve.c

-- 
2.6.2

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[linux-sunxi] Requesting help with MMC2 DDR 52 mode clock delays

[Chen-Yu Tsai]

Hi,

I am working on DDR support for the MMC controllers.
Unfortunately none of my boards support signal voltage switching to 1.8V,
(and I suspect no boards do), so I cannot try out UHS-1 modes.

I have 4 boards that have eMMC chips connected to MMC2.
These are the A80 Optimus, Cubieboard4, Sinlinx SinA33, and SinA31s.
eMMC DDR 52 is working on all but the SinA31s. The delay values
from Allwinner kernel sources do not work.

Can Allwinner provide the delay values for A31/A31s MMC2 DDR50?

Ongoing work can be found here:

https://github.com/wens/linux/commits/sun9i-wip

If anyone knows of any boards that support SD card voltage switching,
please let me know.

Regards
ChenYu

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Re: [linux-sunxi] clk_out_a usage in mainline

[Chen-Yu Tsai]

On Fri, Dec 11, 2015 at 4:51 PM,   wrote:
> The most up to date documentation is the following
> https://github.com/allwinner-zh
>
>
> documents/A20/A20_User_Manual_v1.4_20150510.pdf
>
> Page 289 has no mention of the fact that to actually have clk_out_a you need
> to set the port to pullup mode

Well a lot of the manual is just register value dumps. Not much explaining how
things are supposed to work. Maybe if you had a contract with them things might
be different, but I wouldn't know.

Also if you think something is wrong or missing, you can raise an
issue with them
directly:

https://github.com/allwinner-zh/documents/issues

> Also, (unrelated but puzzling question) from pinctrl-sun71-a20.c
>
>  SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
>  SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
>
> Should MUX code for SUNXI_FUNCTION_IRQ be 0x6 as from manual page ?

The driver is probably wrong. Feel free to send a patch for it. :)

Regards
ChenYu

>
>>
>> What documentation are you referring to?
>>
>> ChenYu
>
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[linux-sunxi] [PATCH v6 4/9] mfd: axp20x: Split the driver into core and i2c bits

[Chen-Yu Tsai]

The axp20x driver assumes the device is i2c based. This is not the
case with later chips, which use a proprietary 2 wire serial bus
by Allwinner called "Reduced Serial Bus".

This patch follows the example of mfd/wm831x and splits it into
an interface independent core, and an i2c specific glue layer.
MFD_AXP20X and the new MFD_AXP20X_I2C are changed to tristate
symbols, allowing the driver to be built as modules.

Whitespace and other style errors in the moved i2c specific code
have been fixed. Included but unused header files are removed as
well.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/mfd/Kconfig|  14 ---
 drivers/mfd/Makefile   |   1 +
 drivers/mfd/axp20x-i2c.c   | 102 +
 drivers/mfd/axp20x.c   |  88 +++---
 include/linux/mfd/axp20x.h |  33 ++-
 5 files changed, 158 insertions(+), 80 deletions(-)
 create mode 100644 drivers/mfd/axp20x-i2c.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 4d92df6ef9fe..804cd3dcce32 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -91,14 +91,18 @@ config MFD_BCM590XX
  Support for the BCM590xx PMUs from Broadcom
 
 config MFD_AXP20X
-   bool "X-Powers AXP20X"
+   tristate
select MFD_CORE
-   select REGMAP_I2C
select REGMAP_IRQ
-   depends on I2C=y
+
+config MFD_AXP20X_I2C
+   tristate "X-Powers AXP series PMICs with I2C"
+   select MFD_AXP20X
+   select REGMAP_I2C
+   depends on I2C
help
- If you say Y here you get support for the X-Powers AXP202, AXP209 and
- AXP288 power management IC (PMIC).
+ If you say Y here you get support for the X-Powers AXP series power
+ management ICs (PMICs) controlled with I2C.
  This driver include only the core APIs. You have to select individual
  components like regulators or the PEK (Power Enable Key) under the
  corresponding menus.
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a8b76b81b467..a6913007d667 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -107,6 +107,7 @@ obj-$(CONFIG_PMIC_DA9052)   += da9052-core.o
 obj-$(CONFIG_MFD_DA9052_SPI)   += da9052-spi.o
 obj-$(CONFIG_MFD_DA9052_I2C)   += da9052-i2c.o
 obj-$(CONFIG_MFD_AXP20X)   += axp20x.o
+obj-$(CONFIG_MFD_AXP20X_I2C)   += axp20x-i2c.o
 
 obj-$(CONFIG_MFD_LP3943)   += lp3943.o
 obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c
new file mode 100644
index ..b54205677bb2
--- /dev/null
+++ b/drivers/mfd/axp20x-i2c.c
@@ -0,0 +1,102 @@
+/*
+ * axp20x-i2c.c - I2C driver for the X-Powers' Power Management ICs
+ *
+ * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK 
DC-DC
+ * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
+ * as well as configurable GPIOs.
+ *
+ * This driver supports the I2C variants.
+ *
+ * Author: Carlo Caione <ca...@caione.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int axp20x_i2c_probe(struct i2c_client *i2c,
+   const struct i2c_device_id *id)
+{
+   struct axp20x_dev *axp20x;
+   int ret;
+
+   axp20x = devm_kzalloc(>dev, sizeof(*axp20x), GFP_KERNEL);
+   if (!axp20x)
+   return -ENOMEM;
+
+   axp20x->dev = >dev;
+   axp20x->irq = i2c->irq;
+   dev_set_drvdata(axp20x->dev, axp20x);
+
+   ret = axp20x_match_device(axp20x);
+   if (ret)
+   return ret;
+
+   axp20x->regmap = devm_regmap_init_i2c(i2c, axp20x->regmap_cfg);
+   if (IS_ERR(axp20x->regmap)) {
+   ret = PTR_ERR(axp20x->regmap);
+   dev_err(>dev, "regmap init failed: %d\n", ret);
+   return ret;
+   }
+
+   return axp20x_device_probe(axp20x);
+}
+
+static int axp20x_i2c_remove(struct i2c_client *i2c)
+{
+   struct axp20x_dev *axp20x = i2c_get_clientdata(i2c);
+
+   return axp20x_device_remove(axp20x);
+}
+
+static const struct of_device_id axp20x_i2c_of_match[] = {
+   { .compatible = "x-powers,axp152", .data = (void *)AXP152_ID },
+   { .compatible = "x-powers,axp202", .data = (void *)AXP202_ID },
+   { .compatible = "x-powers,axp209", .data = (void *)AXP209_ID },
+   { .compatible = "x-powers,axp221", .data = (void *)AXP221_ID },
+   { },
+};
+MODULE_DEVICE_TABLE(of, axp20x_i2c_of_match);
+
+/*
+ * This is useless for OF-enabled devices, but it is needed by I2C subsystem
+ */
+static const struct i2c_device_id axp20x_i2c_id

[linux-sunxi] [PATCH v6 7/9] regulator: axp20x: Support new AXP223 PMIC

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Reviewed-by: Mark Brown <broo...@kernel.org>
---
 drivers/regulator/axp20x-regulator.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/regulator/axp20x-regulator.c 
b/drivers/regulator/axp20x-regulator.c
index 35de22fdb7a0..55cce8125716 100644
--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
@@ -244,6 +244,7 @@ static int axp20x_set_dcdc_freq(struct platform_device 
*pdev, u32 dcdcfreq)
step = 75;
break;
case AXP221_ID:
+   case AXP223_ID:
min = 1800;
max = 4050;
def = 3000;
@@ -322,6 +323,7 @@ static int axp20x_set_dcdc_workmode(struct regulator_dev 
*rdev, int id, u32 work
break;
 
case AXP221_ID:
+   case AXP223_ID:
if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
return -EINVAL;
 
@@ -360,6 +362,7 @@ static int axp20x_regulator_probe(struct platform_device 
*pdev)
nregulators = AXP20X_REG_ID_MAX;
break;
case AXP221_ID:
+   case AXP223_ID:
regulators = axp22x_regulators;
nregulators = AXP22X_REG_ID_MAX;
break;
-- 
2.6.4

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[linux-sunxi] [PATCH v6 5/9] mfd: axp20x: Whitespace, open parenthesis alignment code style fixes

[Chen-Yu Tsai]

This fixes some leftover code style issues in the axp20x core.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/mfd/axp20x.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 631ad64ddf69..54a00168da26 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -591,14 +591,14 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
dev_err(dev, "Unable to match OF ID\n");
return -ENODEV;
}
-   axp20x->variant = (long) of_id->data;
+   axp20x->variant = (long)of_id->data;
} else {
acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
if (!acpi_id || !acpi_id->driver_data) {
dev_err(dev, "Unable to match ACPI ID and data\n");
return -ENODEV;
}
-   axp20x->variant = (long) acpi_id->driver_data;
+   axp20x->variant = (long)acpi_id->driver_data;
}
 
switch (axp20x->variant) {
@@ -632,7 +632,7 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
return -EINVAL;
}
dev_info(dev, "AXP20x variant %s found\n",
-   axp20x_model_names[axp20x->variant]);
+axp20x_model_names[axp20x->variant]);
 
return 0;
 }
@@ -652,7 +652,7 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
}
 
ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
-   axp20x->nr_cells, NULL, 0, NULL);
+ axp20x->nr_cells, NULL, 0, NULL);
 
if (ret) {
dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
-- 
2.6.4

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[linux-sunxi] [PATCH v6 0/9] mfd: axp20x: Add support for RSB based AXP223

[Chen-Yu Tsai]

Hi everyone,

This is v6 of the AXP223 PMIC series. v6 fixes the address of the AXP223
in the DT. Hope this series makes it into 4.5, and we can then support
even more AXP PMICs in 4.6+.

Lee, can you take the first 7 patches. Once they're in, Maxime can take
the DTS patches.

Changes since v5:

  - Correct AXP223 address to 0x3a3.

Changes since v4:

  - Get rid of second parameter of axp20x_match_device() (new patch 2)

  - Match against dev->driver->of_match_table, so the entirety of
axp20x_match_device() can be kept in the core. (new patch 3)

  - Move *_device_id tables to bottom of the driver, right above driver
declaration. (patch 4 & 6)

  - Remove extra whitespaces while moving i2c specific code (patch 4)

  - Remove leftover whitespace and code style issues in axp20x core
(new patch 5)

  - Remove extra whitespaces in rsb specific code (patch 6)

Changes since v3:

  - Removed settings for axp223 reg_rtc_ldo from board dts files that
are already in axp22x.dtsi. The name is kept.

  - Dropped simplefb label and defconfig patches, as they are merged.

Changes since v2:

  - s/It's/Its/ for the commit messages of patches 5 and 7

  - Add Rob's Acked-by for patch 1

Changes since v1:

  - Dropped NMI interrupt controller dts patch (Merged)

  - Change MFD_AXP20X to represent the axp20x core, and drop MFD_AXP20X_CORE
  
  - Keep the axp20x core bits named axp20x.c

  - Add patch 7 to add AXP223 to sun8i-q8-common.dtsi

  - Add patch 8 & 9 to update defconfigs

  - Make axp20x drivers tristate and buildable as modules

  - Drop "_sunxi" substring from identifiers in axp20x-rsb driver


This series adds support for the Reduced Serial Bus based AXP223 PMIC.
The AXP223 is functionally identical to the AXP221, which we already
support. Only some default values for the regulators are different.
The defaults fit their recommended application, paired with different
SoCs.

Patch 1 adds AXP223 to the list of supported chips in the DT binding.

Patch 2 gets rid of the extra "struct device *" parameter from
axp20x_match_device().

Patch 3 makes axp20x_match_device() use dev->driver->of_match_table,
so the function can be library-ized without modification.

Patch 4 splits the axp20x mfd driver into 2 parts, a core library, and
an I2C driver.

Patch 5 cleans up some leftover whitespace issues in axp20x core.

Patch 6 adds an RSB based driver for the AXP223.

Patch 7 adds support for the AXP223 regulators

Patch 8 enables the AXP223 PMIC and its regulators for the Sinlinx
SinA33.

Patch 9 enables the AXP223 PMIC and its regulators for A23/A33 based
Q8 tablet devices.


Regards
ChenYu


Chen-Yu Tsai (9):
  mfd: axp20x: Add AXP223 to list of supported PMICs in DT bindings
  mfd: axp20x: Remove second struct device * parameter for
axp20x_match_device()
  mfd: axp20x: use dev->driver->of_match_table in axp20x_match_device()
  mfd: axp20x: Split the driver into core and i2c bits
  mfd: axp20x: Whitespace, open parenthesis alignment code style fixes
  mfd: axp20x: Add support for RSB based AXP223 PMIC
  regulator: axp20x: Support new AXP223 PMIC
  ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator
nodes
  ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes

 Documentation/devicetree/bindings/mfd/axp20x.txt |   7 +-
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts   |  76 -
 arch/arm/boot/dts/sun8i-q8-common.dtsi   |  83 +-
 drivers/mfd/Kconfig  |  25 --
 drivers/mfd/Makefile |   2 +
 drivers/mfd/axp20x-i2c.c | 102 +++
 drivers/mfd/axp20x-rsb.c |  78 +
 drivers/mfd/axp20x.c | 101 +-
 drivers/regulator/axp20x-regulator.c |   3 +
 include/linux/mfd/axp20x.h   |  34 +++-
 10 files changed, 418 insertions(+), 93 deletions(-)
 create mode 100644 drivers/mfd/axp20x-i2c.c
 create mode 100644 drivers/mfd/axp20x-rsb.c

-- 
2.6.4

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[linux-sunxi] [PATCH v6 9/9] ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes

[Chen-Yu Tsai]

A23/A33 Q8 tablets have an X-Powers AXP223 PMIC connected via RSB. Its
regulators provide power to various parts of the SoC and the board.

Also add lcd regulator supply for simplefb and update the existing
vmmc-supply for mmc0.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-q8-common.dtsi | 83 +-
 1 file changed, 81 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi 
b/arch/arm/boot/dts/sun8i-q8-common.dtsi
index 1a69231d2da5..9d2b7e2f5975 100644
--- a/arch/arm/boot/dts/sun8i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi
@@ -56,7 +56,6 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
enable-gpios = < 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
-   /* backlight is powered by AXP223 DC1SW */
};
 
chosen {
@@ -67,7 +66,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin_q8>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <4>;
cd-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
@@ -92,6 +91,82 @@
 
 _rsb {
status = "okay";
+
+   axp22x: pmic@3a3 {
+   compatible = "x-powers,axp223";
+   reg = <0x3a3>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   eldoin-supply = <_dcdc1>;
+   };
+};
+
+#include "axp22x.dtsi"
+
+_aldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-io";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <235>;
+   regulator-max-microvolt = <265>;
+   regulator-name = "vdd-dll";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <270>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_dc1sw {
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-lcd";
+};
+
+_dc5ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpus";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-3v0";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-sys";
+};
+
+_dcdc3 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpu";
+};
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram";
+};
+
+_rtc_ldo {
+   regulator-name = "vcc-rtc";
 };
 
 _uart {
@@ -99,3 +174,7 @@
pinctrl-0 = <_uart_pins_a>;
status = "okay";
 };
+
+_lcd {
+   vcc-lcd-supply = <_dc1sw>;
+};
-- 
2.6.4

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[linux-sunxi] [PATCH v6 8/9] ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator nodes

[Chen-Yu Tsai]

This board has a X-Powers AXP223 PMIC connected via RSB. Its regulators
provide power to various parts of the SoC and the board.

Also update the regulator supply phandles.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 76 +-
 1 file changed, 73 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts 
b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index 13ce68f06dd6..8af38a9719ca 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -68,7 +68,7 @@
 };
 
  {
-   vref-supply = <_vcc3v0>;
+   vref-supply = <_dcdc1>;
status = "okay";
 
button@200 {
@@ -96,7 +96,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin_sina33>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <4>;
cd-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
@@ -106,7 +106,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_8bit_pins>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <8>;
non-removable;
status = "okay";
@@ -132,6 +132,76 @@
 
 _rsb {
status = "okay";
+
+   axp22x: pmic@3a3 {
+   compatible = "x-powers,axp223";
+   reg = <0x3a3>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   eldoin-supply = <_dcdc1>;
+   };
+};
+
+#include "axp22x.dtsi"
+
+_aldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-io";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <235>;
+   regulator-max-microvolt = <265>;
+   regulator-name = "vdd-dll";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <270>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_dc5ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpus";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-3v0";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-sys";
+};
+
+_dcdc3 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpu";
+};
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram";
+};
+
+_rtc_ldo {
+   regulator-name = "vcc-rtc";
 };
 
  {
-- 
2.6.4

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[linux-sunxi] [PATCH v6 3/9] mfd: axp20x: use dev->driver->of_match_table in axp20x_match_device()

[Chen-Yu Tsai]

In axp20x_match_device(), match the of_device_id table bound to the
device driver instead of pointing to axp20x_of_match directly. This
will allow us to keep axp20x_match_device() unmodified when we expand
the axp20x driver into multiple ones covering different interface
types.

of_device_get_match_data() cannot be used here as we need to know if
it failed to get a match, or if the match data value just happened to
be 0, as it is for the AXP152.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/mfd/axp20x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 685a78614f83..3e186f2dcac3 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -613,7 +613,7 @@ static int axp20x_match_device(struct axp20x_dev *axp20x)
const struct of_device_id *of_id;
 
if (dev->of_node) {
-   of_id = of_match_device(axp20x_of_match, dev);
+   of_id = of_match_device(dev->driver->of_match_table, dev);
if (!of_id) {
dev_err(dev, "Unable to match OF ID\n");
return -ENODEV;
-- 
2.6.4

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[linux-sunxi] [PATCH v6 2/9] mfd: axp20x: Remove second struct device * parameter for axp20x_match_device()

[Chen-Yu Tsai]

The first argument passed to axp20x_match_device(), struct axp20x_dev *,
already contains a pointer to the device. By rearranging some code,
moving the assignment of the pointer before axp20x_match_device() is
called, we can eliminate the second parameter.

Suggested-by: Andy Shevchenko <andy.shevche...@gmail.com>
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/mfd/axp20x.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 9842199e2e6c..685a78614f83 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -606,8 +606,9 @@ static void axp20x_power_off(void)
 AXP20X_OFF);
 }
 
-static int axp20x_match_device(struct axp20x_dev *axp20x, struct device *dev)
+static int axp20x_match_device(struct axp20x_dev *axp20x)
 {
+   struct device *dev = axp20x->dev;
const struct acpi_device_id *acpi_id;
const struct of_device_id *of_id;
 
@@ -673,14 +674,14 @@ static int axp20x_i2c_probe(struct i2c_client *i2c,
if (!axp20x)
return -ENOMEM;
 
-   ret = axp20x_match_device(axp20x, >dev);
-   if (ret)
-   return ret;
-
axp20x->i2c_client = i2c;
axp20x->dev = >dev;
dev_set_drvdata(axp20x->dev, axp20x);
 
+   ret = axp20x_match_device(axp20x);
+   if (ret)
+   return ret;
+
axp20x->regmap = devm_regmap_init_i2c(i2c, axp20x->regmap_cfg);
if (IS_ERR(axp20x->regmap)) {
ret = PTR_ERR(axp20x->regmap);
-- 
2.6.4

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[linux-sunxi] [PATCH v6 6/9] mfd: axp20x: Add support for RSB based AXP223 PMIC

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/mfd/Kconfig| 11 +++
 drivers/mfd/Makefile   |  1 +
 drivers/mfd/axp20x-rsb.c   | 78 ++
 drivers/mfd/axp20x.c   |  2 ++
 include/linux/mfd/axp20x.h |  1 +
 5 files changed, 93 insertions(+)
 create mode 100644 drivers/mfd/axp20x-rsb.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 804cd3dcce32..13c565103e96 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -107,6 +107,17 @@ config MFD_AXP20X_I2C
  components like regulators or the PEK (Power Enable Key) under the
  corresponding menus.
 
+config MFD_AXP20X_RSB
+   tristate "X-Powers AXP series PMICs with RSB"
+   select MFD_AXP20X
+   depends on SUNXI_RSB
+   help
+ If you say Y here you get support for the X-Powers AXP series power
+ management ICs (PMICs) controlled with RSB.
+ This driver include only the core APIs. You have to select individual
+ components like regulators or the PEK (Power Enable Key) under the
+ corresponding menus.
+
 config MFD_CROS_EC
tristate "ChromeOS Embedded Controller"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a6913007d667..caea6637d5e8 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -108,6 +108,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)+= da9052-spi.o
 obj-$(CONFIG_MFD_DA9052_I2C)   += da9052-i2c.o
 obj-$(CONFIG_MFD_AXP20X)   += axp20x.o
 obj-$(CONFIG_MFD_AXP20X_I2C)   += axp20x-i2c.o
+obj-$(CONFIG_MFD_AXP20X_RSB)   += axp20x-rsb.o
 
 obj-$(CONFIG_MFD_LP3943)   += lp3943.o
 obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
diff --git a/drivers/mfd/axp20x-rsb.c b/drivers/mfd/axp20x-rsb.c
new file mode 100644
index ..76ff02b96df0
--- /dev/null
+++ b/drivers/mfd/axp20x-rsb.c
@@ -0,0 +1,78 @@
+/*
+ * axp20x-rsb.c - RSB driver for the X-Powers' Power Management ICs
+ *
+ * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK 
DC-DC
+ * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
+ * as well as configurable GPIOs.
+ *
+ * This driver supports the RSB variants.
+ *
+ * Author: Chen-Yu Tsai <w...@csie.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int axp20x_rsb_probe(struct sunxi_rsb_device *rdev)
+{
+   struct axp20x_dev *axp20x;
+   int ret;
+
+   axp20x = devm_kzalloc(>dev, sizeof(*axp20x), GFP_KERNEL);
+   if (!axp20x)
+   return -ENOMEM;
+
+   axp20x->dev = >dev;
+   axp20x->irq = rdev->irq;
+   sunxi_rsb_device_set_drvdata(rdev, axp20x);
+
+   ret = axp20x_match_device(axp20x);
+   if (ret)
+   return ret;
+
+   axp20x->regmap = devm_regmap_init_sunxi_rsb(rdev, axp20x->regmap_cfg);
+   if (IS_ERR(axp20x->regmap)) {
+   ret = PTR_ERR(axp20x->regmap);
+   dev_err(>dev, "regmap init failed: %d\n", ret);
+   return ret;
+   }
+
+   return axp20x_device_probe(axp20x);
+}
+
+static int axp20x_rsb_remove(struct sunxi_rsb_device *rdev)
+{
+   struct axp20x_dev *axp20x = sunxi_rsb_device_get_drvdata(rdev);
+
+   return axp20x_device_remove(axp20x);
+}
+
+static const struct of_device_id axp20x_rsb_of_match[] = {
+   { .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
+   { },
+};
+MODULE_DEVICE_TABLE(of, axp20x_rsb_of_match);
+
+static struct sunxi_rsb_driver axp20x_rsb_driver = {
+   .driver = {
+   .name   = "axp20x-rsb",
+   .of_match_table = of_match_ptr(axp20x_rsb_of_match),
+   },
+   .probe  = axp20x_rsb_probe,
+   .remove = axp20x_rsb_remove,
+};
+module_sunxi_rsb_driver(axp20x_rsb_driver);
+
+MODULE_DESCRIPTION("PMIC MFD sunXi RSB driver for AXP20X");
+MODULE_AUTHOR("Chen-Yu Tsai <w...@csie.org>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 54a00168da26..968d77fb95d8 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -33,6 +33,7 @@ static const char * const axp20x_model_names[] = {
"AXP202",
"AXP209",
"AXP221",
+   "AXP223",
"AXP288",
 };
 
@@ -616,6 +617,7 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
axp20x->regmap_irq_chip = _regmap_irq_c

[linux-sunxi] [PATCH v6 1/9] mfd: axp20x: Add AXP223 to list of supported PMICs in DT bindings

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Acked-by: Rob Herring <r...@kernel.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
 Documentation/devicetree/bindings/mfd/axp20x.txt | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt 
b/Documentation/devicetree/bindings/mfd/axp20x.txt
index a474359dd206..fd39fa54571b 100644
--- a/Documentation/devicetree/bindings/mfd/axp20x.txt
+++ b/Documentation/devicetree/bindings/mfd/axp20x.txt
@@ -5,11 +5,12 @@ axp152 (X-Powers)
 axp202 (X-Powers)
 axp209 (X-Powers)
 axp221 (X-Powers)
+axp223 (X-Powers)
 
 Required properties:
 - compatible: "x-powers,axp152", "x-powers,axp202", "x-powers,axp209",
- "x-powers,axp221"
-- reg: The I2C slave address for the AXP chip
+ "x-powers,axp221", "x-powers,axp223"
+- reg: The I2C slave address or RSB hardware address for the AXP chip
 - interrupt-parent: The parent interrupt controller
 - interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin
 - interrupt-controller: The PMIC has its own internal IRQs
@@ -51,7 +52,7 @@ LDO3  : LDO   : ldo3in-supply
 LDO4   : LDO   : ldo24in-supply: shared supply
 LDO5   : LDO   : ldo5in-supply
 
-AXP221 regulators, type, and corresponding input supply names:
+AXP221/AXP223 regulators, type, and corresponding input supply names:
 
 RegulatorTypeSupply Name Notes
 ---- -
-- 
2.6.4

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Re: [linux-sunxi] [PATCH v4] sun4i-codec: add inputs

[Chen-Yu Tsai]

Hi,

On Fri, Dec 11, 2015 at 2:57 AM, Danny Milosavljevic
 wrote:
> Hi Maxime,
>
>> There's no need to have two at the same time, they're mutually
>> exclusive.
>
> Hmmm. I don't understand it properly then...
> Let's say two different compatibles in two different device tree nodes
> match the same module on the same computer.
> Will that module's probe() function be entered and left twice in that case?
> If so, will the pdev differ?

In simplified terms, a pdev is created for each device node.

For each pdev that has a matching driver, the driver's probe function
is entered.
So yes, a drivers probe function can be run multiple times, which is often the
case for USB hosts, MMC controllers, any thing a system has multiple
instances of.

(Hence it is not a good idea to use global variables within a driver.)

Once a driver successfully probes (probe function returns 0), the driver core
considers the device "bound", and will not attempt to match other drivers.

>
> (I know that for our current hardware it's not possible for that to happen
>  in the first place, but I mean in general)
>
>> 2) make the "sun4i-codec" kernel module register two different codecs
>>with two different compatibles and two different "sun4i"_codec_widget
>>variables.
>> 4) Copy the structure in probe and modify the copied instance
>>
>> I guess 2 or 4 are the two valid way of doing things.
>
> Yeah, in v6 I did some combination of 2 and 4 (if you squint) which turned
> out quite nice.
> Please check whether it's safe that way (if you have the time).

If everything is known beforehand, having 2 separate read only tables is
probably better. No need for maintainers / reviewers to squint. :)


Regards
ChenYu

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Re: [linux-sunxi] clk_out_a usage in mainline

[Chen-Yu Tsai]

Hi,

On Fri, Dec 11, 2015 at 1:26 AM,   wrote:
> I am able to have a 32Khz signal output from PI12 if I add a pullup
> definition to
>
> clk_out_a_pins_a: clk_out_a@0 {
> allwinner,pins = "PI12";
> allwinner,function = "clk_out_a";
> allwinner,drive = ;
> /* allwinner,pull = ;  */
> allwinner,pull = ;
>
> in the file sun71-a20-dtsi
>
> Clearly the rising front is a capacitor charge slope, but it is at 32Khz,
> the falling front is correct

AFAIK board designs using this all have an external pull-up resistor.
Maybe this pin is open-drain by design?

Also, for higher clock rates you should increase the drive strength.

30 mA should be good enough for clock rates up to 50 MHz.


ChenYu

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[linux-sunxi] Re: [PATCH 3/3] ARM: dts: sunxi: allwinner,sun4i-a10-lradc-keys binding: typo fix

[Chen-Yu Tsai]

On Fri, Dec 11, 2015 at 11:54 AM, Chen-Yu Tsai <w...@csie.org> wrote:
> On Fri, Dec 11, 2015 at 11:45 AM, Rob Herring <r...@kernel.org> wrote:
>> On Thu, Dec 10, 2015 at 09:32:01PM +0100, Karsten Merker wrote:
>>> Trivial typo fix ("mut" -> "must") in the sunxi LRADC-keys binding
>>> documentation.
>>>
>>> Signed-off-by: Karsten Merker <mer...@debian.org>
>>
>> Acked-by: Rob Herring <r...@kernel.org>
>
> Acked-by: Chen-Yu Tsai <w...@csie.org>

You should send this patch to the input subsystem maintainer and input
mailing list (with all the acks gathered in this thread).

ChenYu

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[linux-sunxi] Re: [PATCH 1/3] ARM: dts: sun7i: Olimex A20-SOM-EVB: Add LRADC keys

[Chen-Yu Tsai]

On Fri, Dec 11, 2015 at 4:31 AM, Karsten Merker <mer...@debian.org> wrote:
> The Olimex A20-SOM-EVB is an evaluation board for the Olimex
> A20-SOM system-on-module.  It provides a set of android-style
> buttons (labeled "VOL+", "VOL-", "MENU", "SEARCH", "HOME", "ESC"
> and "ENTER") which are connected to a low-resolution ADC via a
> resistor network.
>
> This patch adds appropriate button definitions to the board
> dts. The voltages assigned to the keys are specified in the
> board schematics published by the manufacturer.
>
> Signed-off-by: Karsten Merker <mer...@debian.org>

Acked-by: Chen-Yu Tsai <w...@csie.org>

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[linux-sunxi] Re: [PATCH 3/3] ARM: dts: sunxi: allwinner,sun4i-a10-lradc-keys binding: typo fix

[Chen-Yu Tsai]

On Fri, Dec 11, 2015 at 11:45 AM, Rob Herring <r...@kernel.org> wrote:
> On Thu, Dec 10, 2015 at 09:32:01PM +0100, Karsten Merker wrote:
>> Trivial typo fix ("mut" -> "must") in the sunxi LRADC-keys binding
>> documentation.
>>
>> Signed-off-by: Karsten Merker <mer...@debian.org>
>
> Acked-by: Rob Herring <r...@kernel.org>

Acked-by: Chen-Yu Tsai <w...@csie.org>

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[linux-sunxi] [PATCH 1/3] ARM: dts: sun9i: cubieboard4: Enable LEDs

[Chen-Yu Tsai]

The Cubieboard4 has 2 controllable LEDs, 1 red and 1 green.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---

This is a resend of an old patch.

---
 arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts 
b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 6484dcf69873..8791d49bed2d 100644
--- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
@@ -62,9 +62,31 @@
stdout-path = "serial0:115200n8";
};
 
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_cubieboard4>;
+
+   green {
+   label = "cubieboard4:green:usr";
+   gpios = < 7 17 GPIO_ACTIVE_HIGH>; /* PH17 */
+   };
+
+   red {
+   label = "cubieboard4:red:usr";
+   gpios = < 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+   };
+   };
 };
 
  {
+   led_pins_cubieboard4: led-pins@0 {
+   allwinner,pins = "PH6", "PH17";
+   allwinner,function = "gpio_out";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+
mmc0_cd_pin_cubieboard4: mmc0_cd_pin@0 {
allwinner,pins = "PH18";
allwinner,function = "gpio_in";
-- 
2.6.2

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[linux-sunxi] [PATCH 2/3] ARM: dts: sun9i: cubieboard4: Enable consumer IR receiver

[Chen-Yu Tsai]

The Cubieboard4 has a consumer IR receiver. Enable it in the DT.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts 
b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 8791d49bed2d..8c26b556e82a 100644
--- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
@@ -114,6 +114,10 @@
status = "okay";
 };
 
+_ir {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-- 
2.6.2

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[linux-sunxi] [PATCH 0/3] ARM: dts: sun9i: cubieboard4: Enable misc. peripherals

[Chen-Yu Tsai]

Hi Maxime,

Here are some patches enabling some peripherals on the Cubieboard4.

Patch 1 enables the LEDs.

Patch 2 enables the IR receiver.

Patch 3 enables the RSB controller.


Regards
ChenYu

Chen-Yu Tsai (3):
  ARM: dts: sun9i: cubieboard4: Enable LEDs
  ARM: dts: sun9i: cubieboard4: Enable consumer IR receiver
  ARM: dts: sun9i: cubieboard4: Enable Reduced Serial Bus controller

 arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 30 +
 1 file changed, 30 insertions(+)

-- 
2.6.2

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Re: [linux-sunxi] clk_out_a usage in mainline

[Chen-Yu Tsai]

On Fri, Dec 11, 2015 at 4:03 PM,   wrote:
>> AFAIK board designs using this all have an external pull-up resistor.
>> Maybe this pin is open-drain by design?
>>
>> Also, for higher clock rates you should increase the drive strength.
>>
>> 30 mA should be good enough for clock rates up to 50 MHz.
>
>
> Assuming that what you write is accurate, then documentation for CPU and the
> corresponding Kernel dtsi should be changed
>
> Is this the case ?

What documentation are you referring to?

ChenYu

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Re: [linux-sunxi] Re: Requesting help with MMC2 DDR 52 mode clock delays

[Chen-Yu Tsai]

On Fri, Dec 11, 2015 at 10:41 AM, Sugar Wu <shugeli...@gmail.com> wrote:
> Hi ChenYu,
>
> I am sorry.
> We just run DDR8 40MHz on A31/A31s with MMC3.
> If you run it with MMC2, it not support DDR8 function.
> You should switch pinmux to MMC3.

Interesting. Is this a hardware difference between MMC2 and MMC3?
Or is it just signal routing problems?

Anyway I got DDR8 working on my A31s. Thanks!

> If you want to try DDR 50, you can improve IO voltage to 3v.
> And, you should set mod clock(in ccmu) and card clock(in mmc controller) in
> following different scenarios:
> a.  8 bit width:
> source clock must be double card clock, it mean  CCLK_DIV is 2.
> (Card Clock) = (MMC Module Clock) / 2

Yes. I noticed this from the SDK. With this already 8 bit works on A33 / A80.

I also noticed A33's "new timing mode", but I can make DDR work without it,
using old timing mode.


Regards
ChenYu

>
> b.  4 bit width:
> Card Clock = MMC Module Clock
>
> Best regards
>
> Sugar
>
> On Thursday, December 10, 2015 at 3:17:44 PM UTC+8, Chen-Yu Tsai wrote:
>>
>> Hi,
>>
>> I am working on DDR support for the MMC controllers.
>> Unfortunately none of my boards support signal voltage switching to 1.8V,
>> (and I suspect no boards do), so I cannot try out UHS-1 modes.
>>
>> I have 4 boards that have eMMC chips connected to MMC2.
>> These are the A80 Optimus, Cubieboard4, Sinlinx SinA33, and SinA31s.
>> eMMC DDR 52 is working on all but the SinA31s. The delay values
>> from Allwinner kernel sources do not work.
>>
>> Can Allwinner provide the delay values for A31/A31s MMC2 DDR50?
>>
>> Ongoing work can be found here:
>>
>> https://github.com/wens/linux/commits/sun9i-wip
>>
>> If anyone knows of any boards that support SD card voltage switching,
>> please let me know.
>>
>> Regards
>> ChenYu
>
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[linux-sunxi] Re: [PATCH v5 0/9] mfd: axp20x: Add support for RSB based AXP223

[Chen-Yu Tsai]

Hi Lee,

On Fri, Nov 27, 2015 at 2:43 PM, Chen-Yu Tsai <w...@csie.org> wrote:
> Hi everyone,
>
> This is v5 of the AXP223 PMIC series. v5 cleans up the code before and
> after the axp20x split, as suggested by Andy.

Any chance you could merge this series (patches 1~7) for 4.5?

The DTS patches can't be merged without the driver updates, and we'd
like to get both parts in.

> Changes since v4:
>
>   - Get rid of second parameter of axp20x_match_device() (new patch 2)
>
>   - Match against dev->driver->of_match_table, so the entirety of
> axp20x_match_device() can be kept in the core. (new patch 3)
>
>   - Move *_device_id tables to bottom of the driver, right above driver
> declaration. (patch 4 & 6)
>
>   - Remove extra whitespaces while moving i2c specific code (patch 4)
>
>   - Remove leftover whitespace and code style issues in axp20x core
> (new patch 5)
>
>   - Remove extra whitespaces in rsb specific code (patch 6)
>
> Changes since v3:
>
>   - Removed settings for axp223 reg_rtc_ldo from board dts files that
> are already in axp22x.dtsi. The name is kept.
>
>   - Dropped simplefb label and defconfig patches, as they are merged.
>
> Changes since v2:
>
>   - s/It's/Its/ for the commit messages of patches 5 and 7
>
>   - Add Rob's Acked-by for patch 1
>
> Changes since v1:
>
>   - Dropped NMI interrupt controller dts patch (Merged)
>
>   - Change MFD_AXP20X to represent the axp20x core, and drop MFD_AXP20X_CORE
>
>   - Keep the axp20x core bits named axp20x.c
>
>   - Add patch 7 to add AXP223 to sun8i-q8-common.dtsi
>
>   - Add patch 8 & 9 to update defconfigs
>
>   - Make axp20x drivers tristate and buildable as modules
>
>   - Drop "_sunxi" substring from identifiers in axp20x-rsb driver
>
>
> This series adds support for the Reduced Serial Bus based AXP223 PMIC.
> The AXP223 is functionally identical to the AXP221, which we already
> support. Only some default values for the regulators are different.
> The defaults fit their recommended application, paired with different
> SoCs.
>

Updated description:

Patch 1 adds AXP223 to the list of supported chips in the DT binding.

Patch 2 gets rid of the extra "struct device *" parameter from
axp20x_match_device().

Patch 3 makes axp20x_match_device() use dev->driver->of_match_table,
so the function can be library-ized without modification.

Patch 4 splits the axp20x mfd driver into 2 parts, a core library, and
an I2C driver.

Patch 5 cleans up some leftover whitespace issues in axp20x core.

Patch 6 adds an RSB based driver for the AXP223.

Patch 7 adds support for the AXP223 regulators

Patch 8 enables the AXP223 PMIC and its regulators for the Sinlinx
SinA33.

Patch 9 enables the AXP223 PMIC and its regulators for A23/A33 based
Q8 tablet devices.


Regards
ChenYu

>
> Chen-Yu Tsai (9):
>   mfd: axp20x: Add AXP223 to list of supported PMICs in DT bindings
>   mfd: axp20x: Remove second struct device * parameter for
> axp20x_match_device()
>   mfd: axp20x: use dev->driver->of_match_table in axp20x_match_device()
>   mfd: axp20x: Split the driver into core and i2c bits
>   mfd: axp20x: Whitespace, open parenthesis alignment code style fixes
>   mfd: axp20x: Add support for RSB based AXP223 PMIC
>   regulator: axp20x: Support new AXP223 PMIC
>   ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator
> nodes
>   ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes
>
>  Documentation/devicetree/bindings/mfd/axp20x.txt |   7 +-
>  arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts   |  76 -
>  arch/arm/boot/dts/sun8i-q8-common.dtsi   |  83 +-
>  drivers/mfd/Kconfig  |  25 --
>  drivers/mfd/Makefile |   2 +
>  drivers/mfd/axp20x-i2c.c | 102 
> +++
>  drivers/mfd/axp20x-rsb.c |  78 +
>  drivers/mfd/axp20x.c | 101 +-
>  drivers/regulator/axp20x-regulator.c |   3 +
>  include/linux/mfd/axp20x.h   |  34 +++-
>  10 files changed, 418 insertions(+), 93 deletions(-)
>  create mode 100644 drivers/mfd/axp20x-i2c.c
>  create mode 100644 drivers/mfd/axp20x-rsb.c
>
> --
> 2.6.2
>

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[linux-sunxi] Re: [PATCH v6 0/9] mfd: axp20x: Add support for RSB based AXP223

[Chen-Yu Tsai]

Hi Lee,

On Thu, Dec 17, 2015 at 12:32 AM, Chen-Yu Tsai <w...@csie.org> wrote:
> Hi everyone,
>
> This is v6 of the AXP223 PMIC series. v6 fixes the address of the AXP223
> in the DT. Hope this series makes it into 4.5, and we can then support
> even more AXP PMICs in 4.6+.
>
> Lee, can you take the first 7 patches. Once they're in, Maxime can take
> the DTS patches.

We're at -rc8. Any chance the first 7 patches make the next release?

Thanks

ChenYu

>
> Changes since v5:
>
>   - Correct AXP223 address to 0x3a3.
>
> Changes since v4:
>
>   - Get rid of second parameter of axp20x_match_device() (new patch 2)
>
>   - Match against dev->driver->of_match_table, so the entirety of
> axp20x_match_device() can be kept in the core. (new patch 3)
>
>   - Move *_device_id tables to bottom of the driver, right above driver
> declaration. (patch 4 & 6)
>
>   - Remove extra whitespaces while moving i2c specific code (patch 4)
>
>   - Remove leftover whitespace and code style issues in axp20x core
> (new patch 5)
>
>   - Remove extra whitespaces in rsb specific code (patch 6)
>
> Changes since v3:
>
>   - Removed settings for axp223 reg_rtc_ldo from board dts files that
> are already in axp22x.dtsi. The name is kept.
>
>   - Dropped simplefb label and defconfig patches, as they are merged.
>
> Changes since v2:
>
>   - s/It's/Its/ for the commit messages of patches 5 and 7
>
>   - Add Rob's Acked-by for patch 1
>
> Changes since v1:
>
>   - Dropped NMI interrupt controller dts patch (Merged)
>
>   - Change MFD_AXP20X to represent the axp20x core, and drop MFD_AXP20X_CORE
>
>   - Keep the axp20x core bits named axp20x.c
>
>   - Add patch 7 to add AXP223 to sun8i-q8-common.dtsi
>
>   - Add patch 8 & 9 to update defconfigs
>
>   - Make axp20x drivers tristate and buildable as modules
>
>   - Drop "_sunxi" substring from identifiers in axp20x-rsb driver
>
>
> This series adds support for the Reduced Serial Bus based AXP223 PMIC.
> The AXP223 is functionally identical to the AXP221, which we already
> support. Only some default values for the regulators are different.
> The defaults fit their recommended application, paired with different
> SoCs.
>
> Patch 1 adds AXP223 to the list of supported chips in the DT binding.
>
> Patch 2 gets rid of the extra "struct device *" parameter from
> axp20x_match_device().
>
> Patch 3 makes axp20x_match_device() use dev->driver->of_match_table,
> so the function can be library-ized without modification.
>
> Patch 4 splits the axp20x mfd driver into 2 parts, a core library, and
> an I2C driver.
>
> Patch 5 cleans up some leftover whitespace issues in axp20x core.
>
> Patch 6 adds an RSB based driver for the AXP223.
>
> Patch 7 adds support for the AXP223 regulators
>
> Patch 8 enables the AXP223 PMIC and its regulators for the Sinlinx
> SinA33.
>
> Patch 9 enables the AXP223 PMIC and its regulators for A23/A33 based
> Q8 tablet devices.
>
>
> Regards
> ChenYu
>
>
> Chen-Yu Tsai (9):
>   mfd: axp20x: Add AXP223 to list of supported PMICs in DT bindings
>   mfd: axp20x: Remove second struct device * parameter for
> axp20x_match_device()
>   mfd: axp20x: use dev->driver->of_match_table in axp20x_match_device()
>   mfd: axp20x: Split the driver into core and i2c bits
>   mfd: axp20x: Whitespace, open parenthesis alignment code style fixes
>   mfd: axp20x: Add support for RSB based AXP223 PMIC
>   regulator: axp20x: Support new AXP223 PMIC
>   ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator
> nodes
>   ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes
>
>  Documentation/devicetree/bindings/mfd/axp20x.txt |   7 +-
>  arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts   |  76 -
>  arch/arm/boot/dts/sun8i-q8-common.dtsi   |  83 +-
>  drivers/mfd/Kconfig  |  25 --
>  drivers/mfd/Makefile |   2 +
>  drivers/mfd/axp20x-i2c.c | 102 
> +++
>  drivers/mfd/axp20x-rsb.c |  78 +
>  drivers/mfd/axp20x.c | 101 +-
>  drivers/regulator/axp20x-regulator.c |   3 +
>  include/linux/mfd/axp20x.h   |  34 +++-
>  10 files changed, 418 insertions(+), 93 deletions(-)
>  create mode 100644 drivers/mfd/axp20x-i2c.c
>  create mode 100644 drivers/mfd/axp20x-rsb.c
>
> --
> 2.6.4
>

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Re: [linux-sunxi] Re: PSCI for H3

[Chen-Yu Tsai]

On Mon, Dec 28, 2015 at 1:16 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> On Wed, Dec 23, 2015 at 12:14:15PM +0200, Siarhei Siamashka wrote:
>> On Tue, 17 Nov 2015 15:32:30 +0100
>> Jens Kuske <jensku...@gmail.com> wrote:
>>
>> > On 16/11/15 07:26, Chen-Yu Tsai wrote:
>> > > Hi everyone,
>> > >
>> > > I got my Orange Pi PC booting U-boot now, using Hans' sunxi-wip branch 
>> > > that
>> > > includes Jens' patches.
>> > >
>> > > For PSCI and SMP, it seems the H3 follows the structure of previous 
>> > > sun8i SoCs.
>> > > The CPUCFG registers line up. The manual doesn't have the PRCM, so I'll 
>> > > have to
>> > > dig through the SDK.
>> > >
>> > > One other thing is the SMTA, or Secure Memory Touch Arbiter, which we 
>> > > last
>> > > encountered issues with on the A31s. This controls non-secure access to 
>> > > a whole
>> > > bunch of peripherals, which we'll need to enable for Linux to run 
>> > > non-secure.
>> >
>> > There is also register 0x2f0 in the CCU, it defaults to disabling
>> > non-secure access to all clock registers.
>> >
>> > Jens
>> >
>>
>> How about just enabling SMP on Allwinner H3 in an old unfashionable way
>> while all these non-secure access limiters are still being under
>> investigation?
>
> I'd really prefer not to.
>
> This ends up being dead code that no-one uses, but we can't really
> remove. Adding support for the H3 support would only delay that
> removal once again.
>
> What controller are you having issues accessing?

So I finished H3 PSCI support. For the moment everything seems to
work. Though given the limited number of peripherals supported and
used, that may not be complete.

For now the patches are available at

https://github.com/wens/u-boot-sunxi/tree/h3-psci

I'll find some time to post them.


Regards
ChenYu

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Re: [linux-sunxi] reason for Allwinner SoC specific pinctrl drivers?

[Chen-Yu Tsai]

On Mon, Jan 4, 2016 at 7:02 PM, Andre Przywara  wrote:
> Hi,
>
> while looking at the Allwinner A64 SoC support, I was wondering why we
> would actually need a pinctrl driver (file) for each and every Allwinner
> SoC that we support.
> Looking at both the A20 and the A64 doc I don't see any differences in
> the port controller implementation apart from the actual
> muxval <-> subsystem assignment, which is just data, right?
> Comparing the code files in drivers/pinctrl/sunxi seems to support this,
> as those drivers only consist of the table and some boilerplate code.
>
> Now I was wondering whether we could get away with one generic Allwinner
> pinctrl driver and put the SoC specific pin assignments in DT instead.
> It looks like adding an "allwinner,muxval" property in addition to the
> existing "allwinner,function" in the SoC's .dtsi would give us all the
> information we need. This could look like:
>
> uart0_pins_a: uart0@0 {
> allwinner,pins =   "PB22", "PB23";
> +   allwinner,muxval = <0x020x02>;
> allwinner,function = "uart0";
> allwinner,drive = ;
> allwinner,pull = ;
> };

Using a mux value over a string does not gain us much, other than
smaller driver code, since all the strings are gone, and smaller DT,
again no strings. However, if you want some sensible debug output
from the driver, you're going to keep the strings anyway.

The mux values would need to be macros defined in some header file,
instead of raw values which are hard to understand.

That's only half of it. The driver should know what pins are available
and which mux values can be used for them. So you'd still need a table
of some sort. That means it's unlikely you can have a generic driver.
Leaking the internals into the DT is not a good way either.

The current approach of a generic driver library and SoC specific
tables maybe isn't the best approach, but it is easy enough to add new
SoC support.


Regards
ChenYu

> Would it make sense that I sit down and prototype such a driver?
>
> We should keep compatibility with older DTs by keeping the existing
> drivers in (or maybe emulating the current behaviour by providing just
> those tables as a fallback) , but newer SoCs (like the A64?) would not
> need a SoC specific driver, but just go with that generic driver and
> appropriate DT properties.
>
> I appreciate any comments on this, especially if I missed something
> which would render this approach impossible or tedious.
>
> Cheers,
> Andre.
>
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[linux-sunxi] [PATCH 1/4] sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3

[Chen-Yu Tsai]

Secure Memory Touch Arbiter is the same thing as the TrustZone
Protection Controller found on A31/A31s.

Access to many peripherals on the H3 can be controlled by the SMTA,
and the settings default to secure access only.

This patch supports the new settings, and sets them to allow non-secure
access.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/cpu/armv7/sunxi/Makefile  |  1 +
 arch/arm/cpu/armv7/sunxi/tzpc.c| 11 ++-
 arch/arm/include/asm/arch-sunxi/tzpc.h | 13 -
 3 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index dfb0a3e..7a6a3cc 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_SUN8I)  += clock_sun6i.o
 endif
 obj-$(CONFIG_MACH_SUN9I)   += clock_sun9i.o
 obj-$(CONFIG_MACH_SUN6I)   += tzpc.o
+obj-$(CONFIG_MACH_SUN8I)   += tzpc.o
 
 obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c
index 5c9c69b..6c8a0fd 100644
--- a/arch/arm/cpu/armv7/sunxi/tzpc.c
+++ b/arch/arm/cpu/armv7/sunxi/tzpc.c
@@ -13,6 +13,15 @@ void tzpc_init(void)
 {
struct sunxi_tzpc *tzpc = (struct sunxi_tzpc *)SUNXI_TZPC_BASE;
 
+#ifdef CONFIG_MACH_SUN6I
/* Enable non-secure access to the RTC */
-   writel(SUNXI_TZPC_DECPORT0_RTC, >decport0_set);
+   writel(SUN6I_TZPC_DECPORT0_RTC, >decport0_set);
+#endif
+
+#ifdef CONFIG_MACH_SUN8I_H3
+   /* Enable non-secure access to all peripherals */
+   writel(SUN8I_H3_TZPC_DECPORT0_ALL, >decport0_set);
+   writel(SUN8I_H3_TZPC_DECPORT1_ALL, >decport1_set);
+   writel(SUN8I_H3_TZPC_DECPORT2_ALL, >decport2_set);
+#endif
 }
diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h 
b/arch/arm/include/asm/arch-sunxi/tzpc.h
index ba4d43b..95c55cd 100644
--- a/arch/arm/include/asm/arch-sunxi/tzpc.h
+++ b/arch/arm/include/asm/arch-sunxi/tzpc.h
@@ -13,10 +13,21 @@ struct sunxi_tzpc {
u32 decport0_status;/* 0x04 Status of decode protection port 0 */
u32 decport0_set;   /* 0x08 Set decode protection port 0 */
u32 decport0_clear; /* 0x0c Clear decode protection port 0 */
+   /* For A80 and later SoCs */
+   u32 decport1_status;/* 0x10 Status of decode protection port 1 */
+   u32 decport1_set;   /* 0x14 Set decode protection port 1 */
+   u32 decport1_clear; /* 0x18 Clear decode protection port 1 */
+   u32 decport2_status;/* 0x1c Status of decode protection port 2 */
+   u32 decport2_set;   /* 0x20 Set decode protection port 2 */
+   u32 decport2_clear; /* 0x24 Clear decode protection port 2 */
 };
 #endif
 
-#define SUNXI_TZPC_DECPORT0_RTC(1 << 1)
+#define SUN6I_TZPC_DECPORT0_RTC(1 << 1)
+
+#define SUN8I_H3_TZPC_DECPORT0_ALL  0xbe
+#define SUN8I_H3_TZPC_DECPORT1_ALL  0xff
+#define SUN8I_H3_TZPC_DECPORT2_ALL  0x7f
 
 void tzpc_init(void);
 
-- 
2.6.4

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[linux-sunxi] [PATCH 4/4] sunxi: Enable booting non-secure and virtualization for H3

[Chen-Yu Tsai]

Now that we support PSCI and various security switches, we can let
U-boot boot Linux into non-secure and HYP mode.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 board/sunxi/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 9d67847..28e6bb4 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -71,8 +71,11 @@ config MACH_SUN8I_A33
 config MACH_SUN8I_H3
bool "sun8i (Allwinner H3)"
select CPU_V7
+   select CPU_V7_HAS_NONSEC
+   select CPU_V7_HAS_VIRT
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+   select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config MACH_SUN8I_A83T
bool "sun8i (Allwinner A83T)"
-- 
2.6.4

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[linux-sunxi] [PATCH 3/4] sunxi: Support PSCI ops on Allwinner H3

[Chen-Yu Tsai]

H3 has the same power sequencing procedure as the A31/A31s, which
includes the power clamps.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 4ff46e4..90b5bfd 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -106,7 +106,7 @@ psci_fiq_enter:
str r10, [r8, #0x100]
timer_wait r10, ONE_MS
 
-#ifdef CONFIG_MACH_SUN6I
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
@ Activate power clamp
lsl r12, r9, #2 @ x4
add r12, r12, r8
@@ -170,7 +170,7 @@ psci_cpu_on:
movwr0, #(SUNXI_PRCM_BASE & 0x)
movtr0, #(SUNXI_PRCM_BASE >> 16)
 
-#ifdef CONFIG_MACH_SUN6I
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
@ Release power clamp
lsl r5, r1, #2  @ 1 register per CPU
add r5, r5, r0  @ PRCM
-- 
2.6.4

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[linux-sunxi] [PATCH 0/4] sunxi: PSCI support for H3

[Chen-Yu Tsai]

Hi everyone,

This series enables PSCI support for the H3. Like other Allwinner SoCs,
the implementation only supports PSCI 0.1, specifically only secondary
CPU boot/hotplug.

Patch 1 supports the SMTA (previously called TZPC) TrustZone hardware
on H3. This controls non-secure access to some important hardware blocks.

Patch 2 supports the security switch in H3's CCU. This is H3 only. No
other SoCs have this feature.

Patch 3 supports H3 using sun6i PSCI implementation. H3 uses the same
power sequence as sun6i, including the power clamps. This is shown in
Allwinner's SDK, and confirmed / tested by Siarhei.

Patch 4 enables PSCI support for the H3 in Kconfig.


I've only tested booting HYP/SMP on my Orange Pi PC. Hotplugging was not
tested, but should work.


Regards
ChenYu

Chen-Yu Tsai (4):
  sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3
  sunxi: Support H3 CCU security switches
  sunxi: Support PSCI ops on Allwinner H3
  sunxi: Enable booting non-secure and virtualization for H3

 arch/arm/cpu/armv7/sunxi/Makefile |  1 +
 arch/arm/cpu/armv7/sunxi/clock.c  |  5 +
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c| 13 +
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S |  4 ++--
 arch/arm/cpu/armv7/sunxi/tzpc.c   | 11 ++-
 arch/arm/include/asm/arch-sunxi/clock.h   |  1 +
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h |  7 +++
 arch/arm/include/asm/arch-sunxi/tzpc.h| 13 -
 board/sunxi/Kconfig   |  3 +++
 9 files changed, 54 insertions(+), 4 deletions(-)

-- 
2.6.4

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[linux-sunxi] [PATCH 2/4] sunxi: Support H3 CCU security switches

[Chen-Yu Tsai]

H3's CCU includes some switches which disable non-secure access to some
of the more critical clock controls, such as MBUS, PLLs, and main
platform busses.

Configure them to enable non-secure access.

For now the only SoC that has this feature is the H3. For other
platforms just use a default (weak) empty function so things do
not break.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/cpu/armv7/sunxi/clock.c  |  5 +
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c| 13 +
 arch/arm/include/asm/arch-sunxi/clock.h   |  1 +
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h |  7 +++
 4 files changed, 26 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index 47fb70f..5cc5d25 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -14,12 +14,17 @@
 #include 
 #include 
 
+__weak void clock_init_sec(void)
+{
+}
+
 int clock_init(void)
 {
 #ifdef CONFIG_SPL_BUILD
clock_init_safe();
 #endif
clock_init_uart();
+   clock_init_sec();
 
return 0;
 }
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c 
b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 4501884..d0085e8 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -45,6 +45,19 @@ void clock_init_safe(void)
 }
 #endif
 
+void clock_init_sec(void)
+{
+   struct sunxi_ccm_reg * const ccm =
+   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+#ifdef CONFIG_MACH_SUN8I_H3
+   setbits_le32(>ccu_sec_switch,
+CCM_SEC_SWITCH_MBUS_NONSEC |
+CCM_SEC_SWITCH_BUS_NONSEC |
+CCM_SEC_SWITCH_PLL_NONSEC);
+#endif
+}
+
 void clock_init_uart(void)
 {
 #if CONFIG_CONS_INDEX < 5
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h 
b/arch/arm/include/asm/arch-sunxi/clock.h
index 8ca58ae..6c0573f 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -30,6 +30,7 @@ int clock_init(void);
 int clock_twi_onoff(int port, int state);
 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);
 void clock_init_safe(void);
+void clock_init_sec(void);
 void clock_init_uart(void);
 #endif
 
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 5c76275..554d858 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -137,6 +137,8 @@ struct sunxi_ccm_reg {
u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */
u32 reserved24;
u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
+   u32 reserved25[5];
+   u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */
 };
 
 /* apb2 bit field */
@@ -375,6 +377,11 @@ struct sunxi_ccm_reg {
 #define CCM_DE_CTRL_PLL10  (5 << 24)
 #define CCM_DE_CTRL_GATE   (1 << 31)
 
+/* CCU security switch, H3 only */
+#define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2)
+#define CCM_SEC_SWITCH_BUS_NONSEC  (1 << 1)
+#define CCM_SEC_SWITCH_PLL_NONSEC  (1 << 0)
+
 #ifndef __ASSEMBLY__
 void clock_set_pll1(unsigned int hz);
 void clock_set_pll3(unsigned int hz);
-- 
2.6.4

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[linux-sunxi] Re: [PATCH 3/5] ARM: dts: sun4i: Add touchscreen node to inet97fv2 dts file

[Chen-Yu Tsai]

On Sun, Dec 20, 2015 at 7:43 PM, Hans de Goede  wrote:
> Add a node describing the focaltech ft5306de4 touchscreen found on
> inet97fv2 tablets.
>
> Signed-off-by: Hans de Goede 
> ---
>  arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 11 +++
>  1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts 
> b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
> index 77c31da..74dd458 100644
> --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
> @@ -48,6 +48,7 @@
>
>  #include 
>  #include 
> +#include 
>
>  / {
> model = "INet-97F Rev 02";
> @@ -93,6 +94,16 @@
> pinctrl-names = "default";
> pinctrl-0 = <_pins_a>;
> status = "okay";
> +
> +   ft5406ee8: touchscreen@38 {
> +   compatible = "edt,edt-ft5406";
> +   reg = <0x38>;
> +   interrupt-parent = <>;
> +   interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
> +   pinctrl-names = "default";

Name only and no references?

ChenYu

> +   touchscreen-size-x = <800>;
> +   touchscreen-size-y = <480>;
> +   };
>  };
>
>   {
> --
> 2.5.0
>

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[linux-sunxi] Re: [PATCH 4/5] ARM: dts: sun5i: Add dts file for the Empire Electronix D709 tablet

[Chen-Yu Tsai]

Hi,

On Sun, Dec 20, 2015 at 7:43 PM, Hans de Goede  wrote:
> The Empire Electronix D709 tablet is a fairly standard 7" A13 tablet,
> featuring usb-wifi, a micro-sd slot, micro-usb otg and headphone jack.
>
> Empire Electronix is written on the back of the tablet, the D709 model
> info can be found in the about tablet menu in android.
>
> The PCB has no markings to speak of.
>
> This dts file does not add support for the ft5x touchscreen found at
> i2c bus 1, addr 0x38, irq PG11, because it does not work out of the box.
> It seems it has been flashed with the wrong firmware and needs to have
> alternative firmware uploaded at boot to make the touchscreen work
> properly, when hot-booting from android into an upstream kernel the
> touchscreen does work.
>
> The Memsic MXC622X accelerometer at i2c bus 1, addr 0x15 also is not
> enabled as there is no driver for it.
>
> Signed-off-by: Hans de Goede 
> ---
>  arch/arm/boot/dts/Makefile |   1 +
>  .../boot/dts/sun5i-a13-empire-electronix-d709.dts  | 241 
> +

The contents seem the same as sun5i-q8-common.dtsi and sun5i-a13-q8-tablet.dts.
Any chance you could use those instead?

On the side, any thoughts on how to handle the differences between various "Q8"
tablets, like different I2C-based sensors and WiFi chips?

I'm asking because with Maxime's couple-regulator we should be able to get the
RTL8723BS on the Q8 A23/33 v1.5 working.

Regards
ChenYu

>  2 files changed, 242 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts

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Re: [linux-sunxi][PATCH v2 2/5] ARM: dts: sun7i: Add Itead A20 Core support

[Chen-Yu Tsai]

On Sat, Dec 19, 2015 at 11:05 PM,  <codekip...@gmail.com> wrote:
> From: Marcus Cooper <codekip...@gmail.com>
>
> The A20 Itead Core module comes with 4GB NAND and 1GB DDR RAM. All of the
> I/O interfaces are exposed via 4 groups of 2*30 1mm pitched female headers.
>
> Signed-off-by: Marcus Cooper <codekip...@gmail.com>

Acked-by: Chen-Yu Tsai <w...@csie.org>

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[linux-sunxi] Re: [PATCH 5/5] ARM: dts: sun7i: Enable gmac on Wits Pro A20 DKT

[Chen-Yu Tsai]

On Sun, Dec 20, 2015 at 7:43 PM, Hans de Goede <hdego...@redhat.com> wrote:
> The Wits Pro A20 DKT has a gbit ethernet port, enable it.
>
> Signed-off-by: Hans de Goede <hdego...@redhat.com>

Acked-by: Chen-Yu Tsai <w...@csie.org>

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[linux-sunxi] Re: [PATCH 2/5] ARM: dts: sun4i: Add touchscreen node to chuwi-v7 dts file

[Chen-Yu Tsai]

On Sun, Dec 20, 2015 at 7:42 PM, Hans de Goede  wrote:
> Add a node describing the focaltech ft5306de4 touchscreen found on
> chuwi-v7-cw0825 tablets.
>
> Signed-off-by: Hans de Goede 
> ---
>  arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts | 11 +++
>  1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts 
> b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
> index 5366089..c71b654 100644
> --- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
> @@ -45,6 +45,7 @@
>  #include "sunxi-common-regulators.dtsi"
>  #include 
>  #include 
> +#include 
>
>  / {
> model = "Chuwi V7 CW0825";
> @@ -88,6 +89,16 @@
> pinctrl-names = "default";
> pinctrl-0 = <_pins_a>;
> status = "okay";
> +
> +   ft5306de4: touchscreen@38 {
> +   compatible = "edt,edt-ft5406";
> +   reg = <0x38>;
> +   interrupt-parent = <>;
> +   interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
> +   pinctrl-names = "default";

Only a name and no references?

ChenYu

> +   touchscreen-size-x = <1024>;
> +   touchscreen-size-y = <768>;
> +   };
>  };
>
>   {
> --
> 2.5.0
>

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Re: [linux-sunxi][PATCH v2 1/5] ARM: dts: sunxi: Add sunxi-itead-core-common.dtsi

[Chen-Yu Tsai]

Hi,

On Sat, Dec 19, 2015 at 11:05 PM,  <codekip...@gmail.com> wrote:
> From: Marcus Cooper <codekip...@gmail.com>
>
> Itead have a core module board that can be populated with either
> an Allwinner A10 or A20 SoC. This patch creates a common dtsi
> which these boards can use.
>
> Signed-off-by: Marcus Cooper <codekip...@gmail.com>
> ---
>  arch/arm/boot/dts/sunxi-itead-core-common.dtsi | 114 
> +
>  1 file changed, 114 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sunxi-itead-core-common.dtsi
>
> diff --git a/arch/arm/boot/dts/sunxi-itead-core-common.dtsi 
> b/arch/arm/boot/dts/sunxi-itead-core-common.dtsi
> new file mode 100644
> index 000..41449fa
> --- /dev/null
> +++ b/arch/arm/boot/dts/sunxi-itead-core-common.dtsi
> @@ -0,0 +1,114 @@
> +/*
> + * Copyright 2015 - Marcus Cooper <codekip...@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "sunxi-common-regulators.dtsi"
> +
> +#include 
> +#include 
> +#include 
> +
> +/ {
> +   aliases {
> +   serial0 = 
> +   };
> +
> +   chosen {
> +   stdout-path = "serial0:115200n8";
> +   };
> +};
> +
> + {
> +   target-supply = <_ahci_5v>;
> +   status = "okay";
> +};
> +
> + {
> +   status = "okay";
> +};
> +
> + {
> +   status = "okay";
> +};
> +
> + {
> +   status = "okay";
> +};
> +
> + {
> +   pinctrl-names = "default";
> +   pinctrl-0 = <_pins_a>;
> +   status = "okay";
> +};
> +
> + {
> +   status = "okay";
> +};
> +
> + {
> +   status = "okay";
> +};
> +
> +_ahci_5v {
> +   pinctrl-0 = <_pwr_pin_a>;
> +   gpio = < 1 8 GPIO_ACTIVE_HIGH>;

These 2 lines are in sunxi-common-regulators.dtsi. No need to repeat them here.

Otherwise,

Acked-by: Chen-Yu Tsai <w...@csie.org>

> +   status = "okay";
> +};
> +
> +_usb1_vbus {
> +   status = "okay";
> +};
> +
> +_usb2_vbus {
> +   status = "okay";
> +};
> +
> + {
> +   pinctrl-names = "default";
> +   pinctrl-0 = <_pins_a>;
> +   status = "okay";
> +};
> +
> + {
> +   usb1_vbus-supply = <_usb1_vbus>;
> +   usb2_vbus-supply = <_usb2_vbus>;
> +   status = "okay";
> +};
> --
> 1.9.1
>
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Re: [linux-sunxi] Re: PSCI for H3

[Chen-Yu Tsai]

On Wed, Dec 23, 2015 at 6:14 PM, Siarhei Siamashka
<siarhei.siamas...@gmail.com> wrote:
> On Tue, 17 Nov 2015 15:32:30 +0100
> Jens Kuske <jensku...@gmail.com> wrote:
>
>> On 16/11/15 07:26, Chen-Yu Tsai wrote:
>> > Hi everyone,
>> >
>> > I got my Orange Pi PC booting U-boot now, using Hans' sunxi-wip branch that
>> > includes Jens' patches.
>> >
>> > For PSCI and SMP, it seems the H3 follows the structure of previous sun8i 
>> > SoCs.
>> > The CPUCFG registers line up. The manual doesn't have the PRCM, so I'll 
>> > have to
>> > dig through the SDK.
>> >
>> > One other thing is the SMTA, or Secure Memory Touch Arbiter, which we last
>> > encountered issues with on the A31s. This controls non-secure access to a 
>> > whole
>> > bunch of peripherals, which we'll need to enable for Linux to run 
>> > non-secure.
>>
>> There is also register 0x2f0 in the CCU, it defaults to disabling
>> non-secure access to all clock registers.
>>
>> Jens
>>
>
> How about just enabling SMP on Allwinner H3 in an old unfashionable way
> while all these non-secure access limiters are still being under
> investigation?

I'm not against it, though I was considering removing the SMP code.

BTW, without docs on the PRCM, do we know if the H3 has the same power clamps
as the A31? FYI the A23 SMP code is the same as A31, just without the power
clamps.

Thanks
ChenYu

> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 0faa38a..d23ed84 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -51,6 +51,7 @@
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> +   enable-method = "allwinner,sun6i-a31";
>
> cpu@0 {
> compatible = "arm,cortex-a7";
> @@ -591,5 +592,15 @@
> interrupts = ,
>  ;
> };
> +
> +   prcm@01f01400 {
> +   compatible = "allwinner,sun8i-h3-prcm";
> +   reg = <0x01f01400 0x200>;
> +   };
> +
> +   cpucfg@01f01c00 {
> +   compatible = "allwinner,sun8i-h3-cpuconfig";
> +   reg = <0x01f01c00 0x300>;
> +   };
> };
>  };
> diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
> index e8483ec..8ca4064 100644
> --- a/arch/arm/mach-sunxi/platsmp.c
> +++ b/arch/arm/mach-sunxi/platsmp.c
> @@ -44,6 +44,9 @@ static void __init sun6i_smp_prepare_cpus(unsigned int 
> max_cpus)
> struct device_node *node;
>
> node = of_find_compatible_node(NULL, NULL, 
> "allwinner,sun6i-a31-prcm");
> +   if (!node)
> +   node = of_find_compatible_node(NULL, NULL,
> +  "allwinner,sun8i-h3-prcm");
> if (!node) {
> pr_err("Missing A31 PRCM node in the device tree\n");
> return;
> @@ -57,6 +60,9 @@ static void __init sun6i_smp_prepare_cpus(unsigned int 
> max_cpus)
>
> node = of_find_compatible_node(NULL, NULL,
>"allwinner,sun6i-a31-cpuconfig");
> +   if (!node)
> +   node = of_find_compatible_node(NULL, NULL,
> +  
> "allwinner,sun8i-h3-cpuconfig");
> if (!node) {
> pr_err("Missing A31 CPU config node in the device tree\n");
> return;
> --
> 2.4.10
>
>
> --
> Best regards,
> Siarhei Siamashka

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Re: [linux-sunxi][PATCH v2 1/5] ARM: dts: sunxi: Add sunxi-itead-core-common.dtsi

[Chen-Yu Tsai]

On Mon, Dec 21, 2015 at 2:18 PM, Chen-Yu Tsai <w...@csie.org> wrote:
> Hi,
>
> On Sat, Dec 19, 2015 at 11:05 PM,  <codekip...@gmail.com> wrote:
>> From: Marcus Cooper <codekip...@gmail.com>
>>
>> Itead have a core module board that can be populated with either
>> an Allwinner A10 or A20 SoC. This patch creates a common dtsi
>> which these boards can use.
>>
>> Signed-off-by: Marcus Cooper <codekip...@gmail.com>
>> ---
>>  arch/arm/boot/dts/sunxi-itead-core-common.dtsi | 114 
>> +
>>  1 file changed, 114 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/sunxi-itead-core-common.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sunxi-itead-core-common.dtsi 
>> b/arch/arm/boot/dts/sunxi-itead-core-common.dtsi
>> new file mode 100644
>> index 000..41449fa
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sunxi-itead-core-common.dtsi
>> @@ -0,0 +1,114 @@
>> +/*
>> + * Copyright 2015 - Marcus Cooper <codekip...@gmail.com>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include "sunxi-common-regulators.dtsi"
>> +
>> +#include 
>> +#include 
>> +#include 
>> +
>> +/ {
>> +   aliases {
>> +   serial0 = 
>> +   };
>> +
>> +   chosen {
>> +   stdout-path = "serial0:115200n8";
>> +   };
>> +};
>> +
>> + {
>> +   target-supply = <_ahci_5v>;
>> +   status = "okay";
>> +};
>> +
>> + {
>> +   status = "okay";
>> +};
>> +
>> + {
>> +   status = "okay";
>> +};
>> +
>> + {
>> +   status = "okay";
>> +};
>> +
>> + {
>> +   pinctrl-names = "default";
>> +   pinctrl-0 = <_pins_a>;
>> +   status = "okay";
>> +};
>> +
>> + {
>> +   status = "okay";
>> +};
>> +
>> + {
>> +   status = "okay";
>> +};
>> +
>> +_ahci_5v {
>> +   pinctrl-0 = <_pwr_pin_a>;
>> +   gpio = < 1 8 GPIO_ACTIVE_HIGH>;
>
> These 2 lines are in sunxi-common-regulators.dtsi. No need to repeat them 
> here.
>
> Otherwise,
>
> Acked-by: Chen-Yu Tsai <w...@csie.org>

On second thought: What happens when you have a base board that doesn't support
all the peripherals you enabled 

Re: [linux-sunxi][PATCH v2 3/5] ARM: dts: sun7i: Add Itead Ibox support

[Chen-Yu Tsai]

On Sat, Dec 19, 2015 at 11:05 PM,  <codekip...@gmail.com> wrote:
> From: Marcus Cooper <codekip...@gmail.com>
>
> The Itead Ibox is a multi board device based on the Allwinner A20 SoC.
> It contains the A20 Itead Core module and a base board for the external
> interfaces.
>
> The core module comes with 4GB NAND and 1GB DDR RAM.
>
> The base board to which the core board is connected provides 3 USB 2.0 Host
> ports, 1 USB 2.0 OTG, 1 uSD slot, 10/100 Ethernet port, HDMI, IR receiver,
> SPDIF and a 32-pin GPIO header. This header expands the features of core
> board by exposing the VGA pins, audio In/Out pins, SATA, SPI, I2C, UARTS,
> USB-OTG and power.
>
> Signed-off-by: Marcus Cooper <codekip...@gmail.com>

Acked-by: Chen-Yu Tsai <w...@csie.org>

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Re: [linux-sunxi] Re: [PATCH 4/5] ARM: dts: sun5i: Add dts file for the Empire Electronix D709 tablet

[Chen-Yu Tsai]

On Tue, Dec 22, 2015 at 3:36 AM, Hans de Goede  wrote:
> Hi,
>
> On 21-12-15 17:11, Maxime Ripard wrote:
>>
>> Hi,x
>>
>> On Mon, Dec 21, 2015 at 11:46:18AM +0100, Hans de Goede wrote:

 On the side, any thoughts on how to handle the differences between
 various "Q8"
 tablets, like different I2C-based sensors and WiFi chips?
>>>
>>>
>>> For i2c based sensors the plan is to use devicetree overlays + an in
>>> kernel
>>> overlay manager which probes the i2c bus (checking known touchscreen /
>>> accelerometer
>>> addresses) and then picks the right touchscreen + accelerometer overlays.
>>>
>>> Wifi is somewhat more tricky I must admit, esp. since there seem to be q8
>>> a23 based
>>> tablet variants with usb wifi and others with sdio wifi. Since both
>>> busses are
>>> discoverable I'm tempted to just enable both in devicetree, and let the
>>> kernel probe
>>> and see what is actually there. This assume that the way the wifichip is
>>> powered
>>> is the same on all boards, or at least that it is safe to enable the
>>> necessary
>>> regulators on all boards ...
>>>
 I'm asking because with Maxime's couple-regulator we should be able to
 get the
 RTL8723BS on the Q8 A23/33 v1.5 working.
>>>
>>>
>>> So this means enabled the sdio controller (should be safe on all boards?)
>>> and
>>> enabling 2 regulators to power the wifi-chip. I think it will be safe to
>>> do this
>>> even on boards where those regulators are not used, what do you think ?
>>
>>
>> Wouldn't that introduce some useless power drain on those boards?
>
>
> If nothing is attached to those regulators (which I expect to be the case
> when
> they are not used to power wifi) then I would expect the drain to be
> minimal,
> my biggest worry is some board having tied these to ground, but I don't
> think
> that is very likely.

AFAIK the AXP datasheets mention that unused DCDC outputs should be left
floating. Not sure if this applies to LDO outputs as well. But any used
outputs would have a bypass capacitor.

>From the board designs I've seen, this seems to be the common case.
I'm not an electrical engineer, but I think we're covered here.

Another thing we need to deal with is the different power sequencing
requirements for the different SDIO chips.

Regards
ChenYu

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[linux-sunxi] Re: [PATCH v3 2/3] ARM: dts: sun8i: Add Allwinner A83T dtsi

[Chen-Yu Tsai]

On Sat, Dec 19, 2015 at 5:41 AM, Maxime Ripard
 wrote:
> Hi,
>
> On Fri, Dec 18, 2015 at 09:30:50PM +0800, Vishnu Patekar wrote:
>> Allwinner A83T is new octa-core cortex-a7 SOC.
>> This adds the basic dtsi, the clocks differs from
>> earlier sun8i SOCs.
>>
>> Signed-off-by: Vishnu Patekar 
>> ---
>>  arch/arm/boot/dts/sun8i-a83t.dtsi | 206 
>> ++
>>  1 file changed, 206 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
>> b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> new file mode 100644
>> index 000..e577c64
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> @@ -0,0 +1,206 @@
>> +/*
>> + * Copyright 2015 Vishnu Patekar
>> + *
>> + * Vishnu Patekar 
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> +
>> + */
>> +
>> +#include "skeleton.dtsi"
>> +
>> +#include 
>> +
>> +#include 
>> +
>> +/ {
>> + interrupt-parent = <>;
>> +
>> + chosen {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0>;
>> + };
>> +
>> + cpu@1 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <1>;
>> + };
>> +
>> + cpu@2 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <2>;
>> + };
>> +
>> + cpu@3 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <3>;
>> + };
>
> A \n here please
>
>> + cpu@100 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0x100>;
>> + };
>> +
>> + cpu@101 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0x101>;
>> + };
>
> Ditto.
>
>> + cpu@102 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0x102>;
>> + };
>> +
>> + cpu@103 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0x103>;
>> + };
>> + };
>> +
>> + memory {
>> + reg = <0x4000 0x8000>;
>> + };
>
> Is mainline u-boot usable ? If so, you 

[linux-sunxi] Re: [PATCH 5/5] ARM: dts: sun5i: Add backlight node to sun5i-q8-common.dtsi

[Chen-Yu Tsai]

On Sat, Dec 19, 2015 at 6:54 PM,  <8001...@gmail.com> wrote:
>> + default-brightness-level = <8>;
>
>
> Why?
> Is not better 100% ?

It's just an arbitrary value. Plus having the backlight at 100% on battery
powered devices might eat up the battery quicker.

ChenYu

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Re: [linux-sunxi] Re: [PATCH] ARM: dts: sun4i: Use red1 LED for heartbeat indication on Marsboard A10

[Chen-Yu Tsai]

On Tue, Dec 29, 2015 at 8:33 PM, Hans de Goede  wrote:
> Hi,
>
> On 27-12-15 21:51, Maxime Ripard wrote:
>>
>> On Sat, Dec 26, 2015 at 12:57:59PM +0300, Aleksei Mamlin wrote:
>>>
>>> Marsboard A10 have four red LEDs, the first one can be used for
>>> heartbeat indication.
>>>
>>> Signed-off-by: Aleksei Mamlin 
>>
>>
>> I'm really not sure about this one.
>>
>> This is something that can easily be changed through sysfs, and it
>> will likely end up being a "war" on what trigger people want to use.
>>
>> Hans, Chen-Yu, What's your view on this?
>
>
> I would prefer to not set any (default) led triggers in the dts
> files for sunxi boards.

+1

ChenYu

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[linux-sunxi] [PATCH v5 3/9] mfd: axp20x: use dev->driver->of_match_table in axp20x_match_device()

[Chen-Yu Tsai]

In axp20x_match_device(), match the of_device_id table bound to the
device driver instead of pointing to axp20x_of_match directly. This
will allow us to keep axp20x_match_device() unmodified when we expand
the axp20x driver into multiple ones covering different interface
types.

of_device_get_match_data() cannot be used here as we need to know if
it failed to get a match, or if the match data value just happened to
be 0, as it is for the AXP152.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/mfd/axp20x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 685a78614f83..3e186f2dcac3 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -613,7 +613,7 @@ static int axp20x_match_device(struct axp20x_dev *axp20x)
const struct of_device_id *of_id;
 
if (dev->of_node) {
-   of_id = of_match_device(axp20x_of_match, dev);
+   of_id = of_match_device(dev->driver->of_match_table, dev);
if (!of_id) {
dev_err(dev, "Unable to match OF ID\n");
return -ENODEV;
-- 
2.6.2

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[linux-sunxi] [PATCH v5 9/9] ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes

[Chen-Yu Tsai]

A23/A33 Q8 tablets have an X-Powers AXP223 PMIC connected via RSB. Its
regulators provide power to various parts of the SoC and the board.

Also add lcd regulator supply for simplefb and update the existing
vmmc-supply for mmc0.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-q8-common.dtsi | 83 +-
 1 file changed, 81 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi 
b/arch/arm/boot/dts/sun8i-q8-common.dtsi
index 1a69231d2da5..1db0e8f77767 100644
--- a/arch/arm/boot/dts/sun8i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi
@@ -56,7 +56,6 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
enable-gpios = < 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
-   /* backlight is powered by AXP223 DC1SW */
};
 
chosen {
@@ -67,7 +66,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin_q8>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <4>;
cd-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
@@ -92,6 +91,82 @@
 
 _rsb {
status = "okay";
+
+   axp22x: pmic@3e3 {
+   compatible = "x-powers,axp223";
+   reg = <0x3e3>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   eldoin-supply = <_dcdc1>;
+   };
+};
+
+#include "axp22x.dtsi"
+
+_aldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-io";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <235>;
+   regulator-max-microvolt = <265>;
+   regulator-name = "vdd-dll";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <270>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_dc1sw {
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-lcd";
+};
+
+_dc5ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpus";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-3v0";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-sys";
+};
+
+_dcdc3 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpu";
+};
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram";
+};
+
+_rtc_ldo {
+   regulator-name = "vcc-rtc";
 };
 
 _uart {
@@ -99,3 +174,7 @@
pinctrl-0 = <_uart_pins_a>;
status = "okay";
 };
+
+_lcd {
+   vcc-lcd-supply = <_dc1sw>;
+};
-- 
2.6.2

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[linux-sunxi] [PATCH v5 4/9] mfd: axp20x: Split the driver into core and i2c bits

[Chen-Yu Tsai]

The axp20x driver assumes the device is i2c based. This is not the
case with later chips, which use a proprietary 2 wire serial bus
by Allwinner called "Reduced Serial Bus".

This patch follows the example of mfd/wm831x and splits it into
an interface independent core, and an i2c specific glue layer.
MFD_AXP20X and the new MFD_AXP20X_I2C are changed to tristate
symbols, allowing the driver to be built as modules.

Whitespace and other style errors in the moved i2c specific code
have been fixed. Included but unused header files are removed as
well.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/mfd/Kconfig|  14 ---
 drivers/mfd/Makefile   |   1 +
 drivers/mfd/axp20x-i2c.c   | 102 +
 drivers/mfd/axp20x.c   |  88 +++---
 include/linux/mfd/axp20x.h |  33 ++-
 5 files changed, 158 insertions(+), 80 deletions(-)
 create mode 100644 drivers/mfd/axp20x-i2c.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 4d92df6ef9fe..804cd3dcce32 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -91,14 +91,18 @@ config MFD_BCM590XX
  Support for the BCM590xx PMUs from Broadcom
 
 config MFD_AXP20X
-   bool "X-Powers AXP20X"
+   tristate
select MFD_CORE
-   select REGMAP_I2C
select REGMAP_IRQ
-   depends on I2C=y
+
+config MFD_AXP20X_I2C
+   tristate "X-Powers AXP series PMICs with I2C"
+   select MFD_AXP20X
+   select REGMAP_I2C
+   depends on I2C
help
- If you say Y here you get support for the X-Powers AXP202, AXP209 and
- AXP288 power management IC (PMIC).
+ If you say Y here you get support for the X-Powers AXP series power
+ management ICs (PMICs) controlled with I2C.
  This driver include only the core APIs. You have to select individual
  components like regulators or the PEK (Power Enable Key) under the
  corresponding menus.
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a8b76b81b467..a6913007d667 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -107,6 +107,7 @@ obj-$(CONFIG_PMIC_DA9052)   += da9052-core.o
 obj-$(CONFIG_MFD_DA9052_SPI)   += da9052-spi.o
 obj-$(CONFIG_MFD_DA9052_I2C)   += da9052-i2c.o
 obj-$(CONFIG_MFD_AXP20X)   += axp20x.o
+obj-$(CONFIG_MFD_AXP20X_I2C)   += axp20x-i2c.o
 
 obj-$(CONFIG_MFD_LP3943)   += lp3943.o
 obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c
new file mode 100644
index ..b54205677bb2
--- /dev/null
+++ b/drivers/mfd/axp20x-i2c.c
@@ -0,0 +1,102 @@
+/*
+ * axp20x-i2c.c - I2C driver for the X-Powers' Power Management ICs
+ *
+ * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK 
DC-DC
+ * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
+ * as well as configurable GPIOs.
+ *
+ * This driver supports the I2C variants.
+ *
+ * Author: Carlo Caione <ca...@caione.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int axp20x_i2c_probe(struct i2c_client *i2c,
+   const struct i2c_device_id *id)
+{
+   struct axp20x_dev *axp20x;
+   int ret;
+
+   axp20x = devm_kzalloc(>dev, sizeof(*axp20x), GFP_KERNEL);
+   if (!axp20x)
+   return -ENOMEM;
+
+   axp20x->dev = >dev;
+   axp20x->irq = i2c->irq;
+   dev_set_drvdata(axp20x->dev, axp20x);
+
+   ret = axp20x_match_device(axp20x);
+   if (ret)
+   return ret;
+
+   axp20x->regmap = devm_regmap_init_i2c(i2c, axp20x->regmap_cfg);
+   if (IS_ERR(axp20x->regmap)) {
+   ret = PTR_ERR(axp20x->regmap);
+   dev_err(>dev, "regmap init failed: %d\n", ret);
+   return ret;
+   }
+
+   return axp20x_device_probe(axp20x);
+}
+
+static int axp20x_i2c_remove(struct i2c_client *i2c)
+{
+   struct axp20x_dev *axp20x = i2c_get_clientdata(i2c);
+
+   return axp20x_device_remove(axp20x);
+}
+
+static const struct of_device_id axp20x_i2c_of_match[] = {
+   { .compatible = "x-powers,axp152", .data = (void *)AXP152_ID },
+   { .compatible = "x-powers,axp202", .data = (void *)AXP202_ID },
+   { .compatible = "x-powers,axp209", .data = (void *)AXP209_ID },
+   { .compatible = "x-powers,axp221", .data = (void *)AXP221_ID },
+   { },
+};
+MODULE_DEVICE_TABLE(of, axp20x_i2c_of_match);
+
+/*
+ * This is useless for OF-enabled devices, but it is needed by I2C subsystem
+ */
+static const struct i2c_device_id axp20x_i2c_id

[linux-sunxi] [PATCH v5 0/9] mfd: axp20x: Add support for RSB based AXP223

[Chen-Yu Tsai]

Hi everyone,

This is v5 of the AXP223 PMIC series. v5 cleans up the code before and
after the axp20x split, as suggested by Andy.

Changes since v4:

  - Get rid of second parameter of axp20x_match_device() (new patch 2)

  - Match against dev->driver->of_match_table, so the entirety of
axp20x_match_device() can be kept in the core. (new patch 3)

  - Move *_device_id tables to bottom of the driver, right above driver
declaration. (patch 4 & 6)

  - Remove extra whitespaces while moving i2c specific code (patch 4)

  - Remove leftover whitespace and code style issues in axp20x core
(new patch 5)

  - Remove extra whitespaces in rsb specific code (patch 6)

Changes since v3:

  - Removed settings for axp223 reg_rtc_ldo from board dts files that
are already in axp22x.dtsi. The name is kept.

  - Dropped simplefb label and defconfig patches, as they are merged.

Changes since v2:

  - s/It's/Its/ for the commit messages of patches 5 and 7

  - Add Rob's Acked-by for patch 1

Changes since v1:

  - Dropped NMI interrupt controller dts patch (Merged)

  - Change MFD_AXP20X to represent the axp20x core, and drop MFD_AXP20X_CORE
  
  - Keep the axp20x core bits named axp20x.c

  - Add patch 7 to add AXP223 to sun8i-q8-common.dtsi

  - Add patch 8 & 9 to update defconfigs

  - Make axp20x drivers tristate and buildable as modules

  - Drop "_sunxi" substring from identifiers in axp20x-rsb driver


This series adds support for the Reduced Serial Bus based AXP223 PMIC.
The AXP223 is functionally identical to the AXP221, which we already
support. Only some default values for the regulators are different.
The defaults fit their recommended application, paired with different
SoCs.

Patch 1 adds AXP223 to the list of supported chips in the DT binding.

Patch 2 splits the axp20x mfd driver into 2 parts, a core library, and
an I2C driver.

Patch 3 adds an RSB based driver for the AXP223.

Patch 4 adds support for the AXP223 regulators

Patch 5 enables the AXP223 PMIC and its regulators for the Sinlinx
SinA33.

Patch 6 enables the AXP223 PMIC and its regulators for A23/A33 based
Q8 devices.


Regards
ChenYu


Chen-Yu Tsai (9):
  mfd: axp20x: Add AXP223 to list of supported PMICs in DT bindings
  mfd: axp20x: Remove second struct device * parameter for
axp20x_match_device()
  mfd: axp20x: use dev->driver->of_match_table in axp20x_match_device()
  mfd: axp20x: Split the driver into core and i2c bits
  mfd: axp20x: Whitespace, open parenthesis alignment code style fixes
  mfd: axp20x: Add support for RSB based AXP223 PMIC
  regulator: axp20x: Support new AXP223 PMIC
  ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator
nodes
  ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes

 Documentation/devicetree/bindings/mfd/axp20x.txt |   7 +-
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts   |  76 -
 arch/arm/boot/dts/sun8i-q8-common.dtsi   |  83 +-
 drivers/mfd/Kconfig  |  25 --
 drivers/mfd/Makefile |   2 +
 drivers/mfd/axp20x-i2c.c | 102 +++
 drivers/mfd/axp20x-rsb.c |  78 +
 drivers/mfd/axp20x.c | 101 +-
 drivers/regulator/axp20x-regulator.c |   3 +
 include/linux/mfd/axp20x.h   |  34 +++-
 10 files changed, 418 insertions(+), 93 deletions(-)
 create mode 100644 drivers/mfd/axp20x-i2c.c
 create mode 100644 drivers/mfd/axp20x-rsb.c

-- 
2.6.2

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[linux-sunxi] [PATCH v5 6/9] mfd: axp20x: Add support for RSB based AXP223 PMIC

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/mfd/Kconfig| 11 +++
 drivers/mfd/Makefile   |  1 +
 drivers/mfd/axp20x-rsb.c   | 78 ++
 drivers/mfd/axp20x.c   |  2 ++
 include/linux/mfd/axp20x.h |  1 +
 5 files changed, 93 insertions(+)
 create mode 100644 drivers/mfd/axp20x-rsb.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 804cd3dcce32..13c565103e96 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -107,6 +107,17 @@ config MFD_AXP20X_I2C
  components like regulators or the PEK (Power Enable Key) under the
  corresponding menus.
 
+config MFD_AXP20X_RSB
+   tristate "X-Powers AXP series PMICs with RSB"
+   select MFD_AXP20X
+   depends on SUNXI_RSB
+   help
+ If you say Y here you get support for the X-Powers AXP series power
+ management ICs (PMICs) controlled with RSB.
+ This driver include only the core APIs. You have to select individual
+ components like regulators or the PEK (Power Enable Key) under the
+ corresponding menus.
+
 config MFD_CROS_EC
tristate "ChromeOS Embedded Controller"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a6913007d667..caea6637d5e8 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -108,6 +108,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)+= da9052-spi.o
 obj-$(CONFIG_MFD_DA9052_I2C)   += da9052-i2c.o
 obj-$(CONFIG_MFD_AXP20X)   += axp20x.o
 obj-$(CONFIG_MFD_AXP20X_I2C)   += axp20x-i2c.o
+obj-$(CONFIG_MFD_AXP20X_RSB)   += axp20x-rsb.o
 
 obj-$(CONFIG_MFD_LP3943)   += lp3943.o
 obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
diff --git a/drivers/mfd/axp20x-rsb.c b/drivers/mfd/axp20x-rsb.c
new file mode 100644
index ..76ff02b96df0
--- /dev/null
+++ b/drivers/mfd/axp20x-rsb.c
@@ -0,0 +1,78 @@
+/*
+ * axp20x-rsb.c - RSB driver for the X-Powers' Power Management ICs
+ *
+ * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK 
DC-DC
+ * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
+ * as well as configurable GPIOs.
+ *
+ * This driver supports the RSB variants.
+ *
+ * Author: Chen-Yu Tsai <w...@csie.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int axp20x_rsb_probe(struct sunxi_rsb_device *rdev)
+{
+   struct axp20x_dev *axp20x;
+   int ret;
+
+   axp20x = devm_kzalloc(>dev, sizeof(*axp20x), GFP_KERNEL);
+   if (!axp20x)
+   return -ENOMEM;
+
+   axp20x->dev = >dev;
+   axp20x->irq = rdev->irq;
+   sunxi_rsb_device_set_drvdata(rdev, axp20x);
+
+   ret = axp20x_match_device(axp20x);
+   if (ret)
+   return ret;
+
+   axp20x->regmap = devm_regmap_init_sunxi_rsb(rdev, axp20x->regmap_cfg);
+   if (IS_ERR(axp20x->regmap)) {
+   ret = PTR_ERR(axp20x->regmap);
+   dev_err(>dev, "regmap init failed: %d\n", ret);
+   return ret;
+   }
+
+   return axp20x_device_probe(axp20x);
+}
+
+static int axp20x_rsb_remove(struct sunxi_rsb_device *rdev)
+{
+   struct axp20x_dev *axp20x = sunxi_rsb_device_get_drvdata(rdev);
+
+   return axp20x_device_remove(axp20x);
+}
+
+static const struct of_device_id axp20x_rsb_of_match[] = {
+   { .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
+   { },
+};
+MODULE_DEVICE_TABLE(of, axp20x_rsb_of_match);
+
+static struct sunxi_rsb_driver axp20x_rsb_driver = {
+   .driver = {
+   .name   = "axp20x-rsb",
+   .of_match_table = of_match_ptr(axp20x_rsb_of_match),
+   },
+   .probe  = axp20x_rsb_probe,
+   .remove = axp20x_rsb_remove,
+};
+module_sunxi_rsb_driver(axp20x_rsb_driver);
+
+MODULE_DESCRIPTION("PMIC MFD sunXi RSB driver for AXP20X");
+MODULE_AUTHOR("Chen-Yu Tsai <w...@csie.org>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 54a00168da26..968d77fb95d8 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -33,6 +33,7 @@ static const char * const axp20x_model_names[] = {
"AXP202",
"AXP209",
"AXP221",
+   "AXP223",
"AXP288",
 };
 
@@ -616,6 +617,7 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
axp20x->regmap_irq_chip = _regmap_irq_c

[linux-sunxi] [PATCH v5 7/9] regulator: axp20x: Support new AXP223 PMIC

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Reviewed-by: Mark Brown <broo...@kernel.org>
---
 drivers/regulator/axp20x-regulator.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/regulator/axp20x-regulator.c 
b/drivers/regulator/axp20x-regulator.c
index 35de22fdb7a0..55cce8125716 100644
--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
@@ -244,6 +244,7 @@ static int axp20x_set_dcdc_freq(struct platform_device 
*pdev, u32 dcdcfreq)
step = 75;
break;
case AXP221_ID:
+   case AXP223_ID:
min = 1800;
max = 4050;
def = 3000;
@@ -322,6 +323,7 @@ static int axp20x_set_dcdc_workmode(struct regulator_dev 
*rdev, int id, u32 work
break;
 
case AXP221_ID:
+   case AXP223_ID:
if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
return -EINVAL;
 
@@ -360,6 +362,7 @@ static int axp20x_regulator_probe(struct platform_device 
*pdev)
nregulators = AXP20X_REG_ID_MAX;
break;
case AXP221_ID:
+   case AXP223_ID:
regulators = axp22x_regulators;
nregulators = AXP22X_REG_ID_MAX;
break;
-- 
2.6.2

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[linux-sunxi] [PATCH v5 8/9] ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator nodes

[Chen-Yu Tsai]

This board has a X-Powers AXP223 PMIC connected via RSB. Its regulators
provide power to various parts of the SoC and the board.

Also update the regulator supply phandles.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 76 +-
 1 file changed, 73 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts 
b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index 13ce68f06dd6..2809e079902e 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -68,7 +68,7 @@
 };
 
  {
-   vref-supply = <_vcc3v0>;
+   vref-supply = <_dcdc1>;
status = "okay";
 
button@200 {
@@ -96,7 +96,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin_sina33>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <4>;
cd-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
@@ -106,7 +106,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_8bit_pins>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <8>;
non-removable;
status = "okay";
@@ -132,6 +132,76 @@
 
 _rsb {
status = "okay";
+
+   axp22x: pmic@3e3 {
+   compatible = "x-powers,axp223";
+   reg = <0x3e3>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   eldoin-supply = <_dcdc1>;
+   };
+};
+
+#include "axp22x.dtsi"
+
+_aldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-io";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <235>;
+   regulator-max-microvolt = <265>;
+   regulator-name = "vdd-dll";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <270>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_dc5ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpus";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-3v0";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-sys";
+};
+
+_dcdc3 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpu";
+};
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram";
+};
+
+_rtc_ldo {
+   regulator-name = "vcc-rtc";
 };
 
  {
-- 
2.6.2

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[linux-sunxi] [PATCH v5 2/9] mfd: axp20x: Remove second struct device * parameter for axp20x_match_device()

[Chen-Yu Tsai]

The first argument passed to axp20x_match_device(), struct axp20x_dev *,
already contains a pointer to the device. By rearranging some code,
moving the assignment of the pointer before axp20x_match_device() is
called, we can eliminate the second parameter.

Suggested-by: Andy Shevchenko <andy.shevche...@gmail.com>
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/mfd/axp20x.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 9842199e2e6c..685a78614f83 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -606,8 +606,9 @@ static void axp20x_power_off(void)
 AXP20X_OFF);
 }
 
-static int axp20x_match_device(struct axp20x_dev *axp20x, struct device *dev)
+static int axp20x_match_device(struct axp20x_dev *axp20x)
 {
+   struct device *dev = axp20x->dev;
const struct acpi_device_id *acpi_id;
const struct of_device_id *of_id;
 
@@ -673,14 +674,14 @@ static int axp20x_i2c_probe(struct i2c_client *i2c,
if (!axp20x)
return -ENOMEM;
 
-   ret = axp20x_match_device(axp20x, >dev);
-   if (ret)
-   return ret;
-
axp20x->i2c_client = i2c;
axp20x->dev = >dev;
dev_set_drvdata(axp20x->dev, axp20x);
 
+   ret = axp20x_match_device(axp20x);
+   if (ret)
+   return ret;
+
axp20x->regmap = devm_regmap_init_i2c(i2c, axp20x->regmap_cfg);
if (IS_ERR(axp20x->regmap)) {
ret = PTR_ERR(axp20x->regmap);
-- 
2.6.2

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[linux-sunxi] [PATCH v5 1/9] mfd: axp20x: Add AXP223 to list of supported PMICs in DT bindings

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Acked-by: Rob Herring <r...@kernel.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
 Documentation/devicetree/bindings/mfd/axp20x.txt | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt 
b/Documentation/devicetree/bindings/mfd/axp20x.txt
index a474359dd206..fd39fa54571b 100644
--- a/Documentation/devicetree/bindings/mfd/axp20x.txt
+++ b/Documentation/devicetree/bindings/mfd/axp20x.txt
@@ -5,11 +5,12 @@ axp152 (X-Powers)
 axp202 (X-Powers)
 axp209 (X-Powers)
 axp221 (X-Powers)
+axp223 (X-Powers)
 
 Required properties:
 - compatible: "x-powers,axp152", "x-powers,axp202", "x-powers,axp209",
- "x-powers,axp221"
-- reg: The I2C slave address for the AXP chip
+ "x-powers,axp221", "x-powers,axp223"
+- reg: The I2C slave address or RSB hardware address for the AXP chip
 - interrupt-parent: The parent interrupt controller
 - interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin
 - interrupt-controller: The PMIC has its own internal IRQs
@@ -51,7 +52,7 @@ LDO3  : LDO   : ldo3in-supply
 LDO4   : LDO   : ldo24in-supply: shared supply
 LDO5   : LDO   : ldo5in-supply
 
-AXP221 regulators, type, and corresponding input supply names:
+AXP221/AXP223 regulators, type, and corresponding input supply names:
 
 RegulatorTypeSupply Name Notes
 ---- -
-- 
2.6.2

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[linux-sunxi] [PATCH v5 5/9] mfd: axp20x: Whitespace, open parenthesis alignment code style fixes

[Chen-Yu Tsai]

This fixes some leftover code style issues in the axp20x core.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/mfd/axp20x.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 631ad64ddf69..54a00168da26 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -591,14 +591,14 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
dev_err(dev, "Unable to match OF ID\n");
return -ENODEV;
}
-   axp20x->variant = (long) of_id->data;
+   axp20x->variant = (long)of_id->data;
} else {
acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
if (!acpi_id || !acpi_id->driver_data) {
dev_err(dev, "Unable to match ACPI ID and data\n");
return -ENODEV;
}
-   axp20x->variant = (long) acpi_id->driver_data;
+   axp20x->variant = (long)acpi_id->driver_data;
}
 
switch (axp20x->variant) {
@@ -632,7 +632,7 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
return -EINVAL;
}
dev_info(dev, "AXP20x variant %s found\n",
-   axp20x_model_names[axp20x->variant]);
+axp20x_model_names[axp20x->variant]);
 
return 0;
 }
@@ -652,7 +652,7 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
}
 
ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
-   axp20x->nr_cells, NULL, 0, NULL);
+ axp20x->nr_cells, NULL, 0, NULL);
 
if (ret) {
dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
-- 
2.6.2

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[linux-sunxi] Re: [PATCH v3 3/5] clk: sunxi: Add sun9i A80 cpus (cpu special) clock support

[Chen-Yu Tsai]

On Thu, Nov 26, 2015 at 1:32 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Tue, Nov 24, 2015 at 05:32:14PM +0800, Chen-Yu Tsai wrote:
>> The "cpus" clock is the clock for the embedded processor in the A80.
>> It is also part of the PRCM clock tree. This clock includes a pre-
>> divider on one of its inputs. For now we are using a custom clock
>> driver for it. In the future we may want to develop a generalized
>> driver for these types of clocks, which also includes the AHB clock
>> driver on sun[5678]i.
>>
>> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
>> ---
>>
>> Hi Maxime,
>>
>> I'll do the factors clock refactoring mentioned during the discussion
>> around v2 later on.
>
> I have no idea what you are talking about :)

Then I guess I have more time to figure something out. :)

>>
>> ---
>>  Documentation/devicetree/bindings/clock/sunxi.txt |   1 +
>>  drivers/clk/sunxi/Makefile|   1 +
>>  drivers/clk/sunxi/clk-sun9i-cpus.c| 240 
>> ++
>>  3 files changed, 242 insertions(+)
>>  create mode 100644 drivers/clk/sunxi/clk-sun9i-cpus.c
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
>> b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index b6859ed6913f..153ac72869e8 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -27,6 +27,7 @@ Required properties:
>>   "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
>>   "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
>>   "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
>> + "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
>>   "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
>>   "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
>>   "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
>> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
>> index 121333ce34ea..07d914c3f6d1 100644
>> --- a/drivers/clk/sunxi/Makefile
>> +++ b/drivers/clk/sunxi/Makefile
>> @@ -13,6 +13,7 @@ obj-y += clk-simple-gates.o
>>  obj-y += clk-sun8i-apb0.o
>>  obj-y += clk-sun8i-mbus.o
>>  obj-y += clk-sun9i-core.o
>> +obj-y += clk-sun9i-cpus.o
>
> Same thing here, if it's only used in the A80, just compile it when
> ARCH_SUN9I is compiled.

Sure. Should I add a patch changing the ones already in? sun9i-core
and sun9i-mmc that is.

Thanks
ChenYu

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[linux-sunxi] Re: [PATCH v3 1/2] phy-sun4i-usb: Use of_match_node to get model specific config data

[Chen-Yu Tsai]

On Thu, Nov 26, 2015 at 12:50 AM, Hans de Goede  wrote:
> Use of_match_node instead of calling of_device_is_compatible a ton of
> times to get model specific config data.
>
> Signed-off-by: Hans de Goede 
> ---
> Changes in v3:
> -New patch in v3 of this patch-set
> ---
>  drivers/phy/phy-sun4i-usb.c | 130 
> +---
>  1 file changed, 85 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> index b12964b..1d8f85d 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -88,12 +88,22 @@
>  #define DEBOUNCE_TIME  msecs_to_jiffies(50)
>  #define POLL_TIME  msecs_to_jiffies(250)
>
> +enum sun4i_usb_phy_type {
> +   sun4i_a10_phy,
> +   sun8i_a33_phy,
> +};
> +
> +struct sun4i_usb_phy_cfg {
> +   int num_phys;
> +   u32 disc_thresh;
> +   enum sun4i_usb_phy_type type;
> +   bool dedicated_clocks;
> +};
> +
>  struct sun4i_usb_phy_data {
> void __iomem *base;
> +   const struct sun4i_usb_phy_cfg *cfg;
> struct mutex mutex;
> -   int num_phys;
> -   u32 disc_thresh;
> -   bool has_a33_phyctl;
> struct sun4i_usb_phy {
> struct phy *phy;
> void __iomem *pmu;
> @@ -164,12 +174,15 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy 
> *phy, u32 addr, u32 data,
>
> mutex_lock(_data->mutex);
>
> -   if (phy_data->has_a33_phyctl) {
> +   switch (phy_data->cfg->type) {
> +   case sun4i_a10_phy:
> +   phyctl = phy_data->base + REG_PHYCTL_A10;

Any reason why this offset isn't incorporated into phy_data?

> +   break;
> +   case sun8i_a33_phy:
> phyctl = phy_data->base + REG_PHYCTL_A33;
> /* A33 needs us to set phyctl to 0 explicitly */
> writel(0, phyctl);
> -   } else {
> -   phyctl = phy_data->base + REG_PHYCTL_A10;
> +   break;
> }
>
> for (i = 0; i < len; i++) {
> @@ -249,7 +262,8 @@ static int sun4i_usb_phy_init(struct phy *_phy)
> sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
>
> /* Disconnect threshold adjustment */
> -   sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2);
> +   sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
> +   data->cfg->disc_thresh, 2);
>
> sun4i_usb_phy_passby(phy, 1);
>
> @@ -476,7 +490,7 @@ static struct phy *sun4i_usb_phy_xlate(struct device *dev,
>  {
> struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
>
> -   if (args->args[0] >= data->num_phys)
> +   if (args->args[0] >= data->cfg->num_phys)
> return ERR_PTR(-ENODEV);
>
> return data->phys[args->args[0]].phy;
> @@ -499,6 +513,59 @@ static int sun4i_usb_phy_remove(struct platform_device 
> *pdev)
> return 0;
>  }
>
> +static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
> +   .num_phys = 3,
> +   .disc_thresh = 3,
> +   .type = sun4i_a10_phy,
> +   .dedicated_clocks = false,
> +};
> +
> +static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
> +   .num_phys = 2,
> +   .disc_thresh = 2,
> +   .type = sun4i_a10_phy,
> +   .dedicated_clocks = false,
> +};
> +
> +static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
> +   .num_phys = 3,
> +   .disc_thresh = 3,
> +   .type = sun4i_a10_phy,
> +   .dedicated_clocks = true,
> +};
> +
> +static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
> +   .num_phys = 3,
> +   .disc_thresh = 2,
> +   .type = sun4i_a10_phy,
> +   .dedicated_clocks = false,
> +};
> +
> +static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
> +   .num_phys = 2,
> +   .disc_thresh = 3,
> +   .type = sun4i_a10_phy,
> +   .dedicated_clocks = true,
> +};
> +
> +static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
> +   .num_phys = 2,
> +   .disc_thresh = 3,
> +   .type = sun8i_a33_phy,
> +   .dedicated_clocks = true,
> +};
> +
> +static const struct of_device_id sun4i_usb_phy_of_match[] = {
> +   { .compatible = "allwinner,sun4i-a10-usb-phy", .data = _a10_cfg 
> },
> +   { .compatible = "allwinner,sun5i-a13-usb-phy", .data = _a13_cfg 
> },
> +   { .compatible = "allwinner,sun6i-a31-usb-phy", .data = _a31_cfg 
> },
> +   { .compatible = "allwinner,sun7i-a20-usb-phy", .data = _a20_cfg 
> },
> +   { .compatible = "allwinner,sun8i-a23-usb-phy", .data = _a23_cfg 
> },
> +   { .compatible = "allwinner,sun8i-a33-usb-phy", .data = _a33_cfg 
> },
> +   { },
> +};
> +MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
> +
>  static const unsigned int sun4i_usb_phy0_cable[] = {
> EXTCON_USB,
> EXTCON_USB_HOST,
> @@ -511,10 +578,16 @@ static int sun4i_usb_phy_probe(struct platform_device 
> *pdev)
> struct device *dev = >dev;

[linux-sunxi] [PATCH v4 1/5] clk: sunxi: Add CLK_OF_DECLARE support for sun8i-a23-apb0-clk driver

[Chen-Yu Tsai]

The APBS clock on sun9i is the same as the APB0 clock on sun8i. With
sun9i we are supporting the PRCM clocks by using CLK_OF_DECLARE,
instead of through a PRCM mfd device and subdevices for each clock
and reset control. As such we need a CLK_OF_DECLARE version of
the sun8i-a23-apb0-clk driver.

Also, build it for sun9i/A80, and not just for configurations with
MFD_SUN6I_PRCM enabled.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/clk/sunxi/Makefile |  5 +--
 drivers/clk/sunxi/clk-sun8i-apb0.c | 71 +++---
 2 files changed, 62 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index cb4c299214ce..c55d5cd1c0e5 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -15,6 +15,7 @@ obj-y += clk-sun9i-core.o
 obj-y += clk-sun9i-mmc.o
 obj-y += clk-usb.o
 
+obj-$(CONFIG_MACH_SUN9I) += clk-sun8i-apb0.o
+
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \
-   clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
-   clk-sun8i-apb0.o
+   clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o
diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c 
b/drivers/clk/sunxi/clk-sun8i-apb0.c
index 7ae5d2c2cde1..c1e2ac8f4b0d 100644
--- a/drivers/clk/sunxi/clk-sun8i-apb0.c
+++ b/drivers/clk/sunxi/clk-sun8i-apb0.c
@@ -17,13 +17,68 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
+static struct clk *sun8i_a23_apb0_register(struct device_node *node,
+  void __iomem *reg)
+{
+   const char *clk_name = node->name;
+   const char *clk_parent;
+   struct clk *clk;
+   int ret;
+
+   clk_parent = of_clk_get_parent_name(node, 0);
+   if (!clk_parent)
+   return ERR_PTR(-EINVAL);
+
+   of_property_read_string(node, "clock-output-names", _name);
+
+   /* The A23 APB0 clock is a standard 2 bit wide divider clock */
+   clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg,
+  0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
+   if (IS_ERR(clk))
+   return clk;
+
+   ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+   if (ret)
+   goto err_unregister;
+
+   return clk;
+
+err_unregister:
+   clk_unregister_divider(clk);
+
+   return ERR_PTR(ret);
+}
+
+static void sun8i_a23_apb0_setup(struct device_node *node)
+{
+   void __iomem *reg;
+   struct resource res;
+   struct clk *clk;
+
+   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+   if (IS_ERR(reg))
+   return;
+
+   clk = sun8i_a23_apb0_register(node, reg);
+   if (IS_ERR(clk))
+   goto err_unmap;
+
+   return;
+
+err_unmap:
+   iounmap(reg);
+   of_address_to_resource(node, 0, );
+   release_mem_region(res.start, resource_size());
+}
+CLK_OF_DECLARE(sun8i_a23_apb0, "allwinner,sun8i-a23-apb0-clk",
+  sun8i_a23_apb0_setup);
+
 static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev)
 {
struct device_node *np = pdev->dev.of_node;
-   const char *clk_name = np->name;
-   const char *clk_parent;
struct resource *r;
void __iomem *reg;
struct clk *clk;
@@ -33,19 +88,11 @@ static int sun8i_a23_apb0_clk_probe(struct platform_device 
*pdev)
if (IS_ERR(reg))
return PTR_ERR(reg);
 
-   clk_parent = of_clk_get_parent_name(np, 0);
-   if (!clk_parent)
-   return -EINVAL;
-
-   of_property_read_string(np, "clock-output-names", _name);
-
-   /* The A23 APB0 clock is a standard 2 bit wide divider clock */
-   clk = clk_register_divider(>dev, clk_name, clk_parent, 0, reg,
-  0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
+   clk = sun8i_a23_apb0_register(np, reg);
if (IS_ERR(clk))
return PTR_ERR(clk);
 
-   return of_clk_add_provider(np, of_clk_src_simple_get, clk);
+   return 0;
 }
 
 static const struct of_device_id sun8i_a23_apb0_clk_dt_ids[] = {
-- 
2.6.2

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[linux-sunxi] [PATCH v4 2/5] clk: sunxi: Add sun9i A80 apbs gates support

[Chen-Yu Tsai]

This patch adds support for the PRCM apbs clock gates found on the
Allwinner A80 SoC.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-simple-gates.c  | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index a94bb56a0e9e..b6859ed6913f 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -55,6 +55,7 @@ Required properties:
"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
+   "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
diff --git a/drivers/clk/sunxi/clk-simple-gates.c 
b/drivers/clk/sunxi/clk-simple-gates.c
index 0214c6548afd..c8acc0612c15 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -140,6 +140,8 @@ CLK_OF_DECLARE(sun9i_a80_apb0, 
"allwinner,sun9i-a80-apb0-gates-clk",
   sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk",
   sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_apbs, "allwinner,sun9i-a80-apbs-gates-clk",
+  sunxi_simple_gates_init);
 
 static const int sun4i_a10_ahb_critical_clocks[] __initconst = {
14, /* ahb_sdram */
-- 
2.6.2

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[linux-sunxi] [PATCH v4 5/5] ARM: dts: sun9i: Add TODO comments for the main and low power clocks

[Chen-Yu Tsai]

The main (24MHz) clock on the A80 is configurable via the PRCM address
space. The low power/speed (32kHz) clock is from an external chip, the
AC100.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index a4ce348c0831..eb69a62f6bc4 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -128,6 +128,17 @@
 */
ranges = <0 0 0 0x2000>;
 
+   /*
+* This clock is actually configurable from the PRCM address
+* space. The external 24M oscillator can be turned off, and
+* the clock switched to an internal 16M RC oscillator. Under
+* normal operation there's no reason to do this, and the
+* default is to use the external good one, so just model this
+* as a fixed clock. Also it is not entirely clear if the
+* osc24M mux in the PRCM affects the entire clock tree, which
+* would also throw all the PLL clock rates off, or just the
+* downstream clocks in the PRCM.
+*/
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -135,6 +146,13 @@
clock-output-names = "osc24M";
};
 
+   /*
+* The 32k clock is from an external source, normally the
+* AC100 codec/RTC chip. This clock is by default enabled
+* and clocked at 32768 Hz, from the oscillator connected
+* to the AC100. It is configurable, but no such driver or
+* bindings exist yet.
+*/
osc32k: osc32k_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
-- 
2.6.2

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[linux-sunxi] [PATCH v4 4/5] ARM: dts: sun9i: Add A80 PRCM clocks and reset control nodes

[Chen-Yu Tsai]

This adds the supported PRCM clocks and reset controls to the A80 dtsi.
The DAUDIO module clocks are not supported yet.

Also update clock and reset phandles for r_uart.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 79 +++-
 1 file changed, 78 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 1118bf5cc4fb..a4ce348c0831 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -164,6 +164,14 @@
 "usb_phy2", "usb_hsic_12M";
};
 
+   pll3: clk@0608 {
+   /* placeholder until implemented */
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-rate = <0>;
+   clock-output-names = "pll3";
+   };
+
pll4: clk@060c {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-pll4-clk";
@@ -350,6 +358,68 @@
"apb1_uart2", "apb1_uart3",
"apb1_uart4", "apb1_uart5";
};
+
+   cpus_clk: clk@08001410 {
+   compatible = "allwinner,sun9i-a80-cpus-clk";
+   reg = <0x08001410 0x4>;
+   #clock-cells = <0>;
+   clocks = <>, <>, <>, <>;
+   clock-output-names = "cpus";
+   };
+
+   ahbs: ahbs_clk {
+   compatible = "fixed-factor-clock";
+   #clock-cells = <0>;
+   clock-div = <1>;
+   clock-mult = <1>;
+   clocks = <_clk>;
+   clock-output-names = "ahbs";
+   };
+
+   apbs: clk@0800141c {
+   compatible = "allwinner,sun8i-a23-apb0-clk";
+   reg = <0x0800141c 0x4>;
+   #clock-cells = <0>;
+   clocks = <>;
+   clock-output-names = "apbs";
+   };
+
+   apbs_gates: clk@08001428 {
+   compatible = "allwinner,sun9i-a80-apbs-gates-clk";
+   reg = <0x08001428 0x4>;
+   #clock-cells = <1>;
+   clocks = <>;
+   clock-indices = <0>, <1>,
+   <2>, <3>,
+   <4>, <5>,
+   <6>, <7>,
+   <12>, <13>,
+   <16>, <17>,
+   <18>, <20>;
+   clock-output-names = "apbs_pio", "apbs_ir",
+   "apbs_timer", "apbs_rsb",
+   "apbs_uart", "apbs_1wire",
+   "apbs_i2c0", "apbs_i2c1",
+   "apbs_ps2_0", "apbs_ps2_1",
+   "apbs_dma", "apbs_i2s0",
+   "apbs_i2s1", "apbs_twd";
+   };
+
+   r_1wire_clk: clk@08001450 {
+   reg = <0x08001450 0x4>;
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-mod0-clk";
+   clocks = <>, <>;
+   clock-output-names = "r_1wire";
+   };
+
+   r_ir_clk: clk@08001454 {
+   reg = <0x08001454 0x4>;
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-mod0-clk";
+   clocks = <>, <>;
+   clock-output-names = "r_ir";
+   };
};
 
soc {
@@ -764,13 +834,20 @@
interrupts = ;
};
 
+   apbs_rst: reset@080014b0 {
+   reg = <0x080014b0 0x4>;
+   compatible = "allwinner,sun6i-a31-clock-reset";
+   #reset-cells = <1>;
+   };
+
r_uart: serial@08002800 {
   

[linux-sunxi] [PATCH 1/7] pinctrl: sunxi: Add A80 special pin controller

[Chen-Yu Tsai]

From: Maxime Ripard <maxime.rip...@free-electrons.com>

Like the previous designs, the A80 has a special pin controller for the
critical pins, like the PMIC bus.

Add a driver for this controller.

Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
[wens: Add A80 compatible strings to bindings doc; fix pin function
   names based on v1.3 datasheet; constify of_device_id table]
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   2 +
 drivers/pinctrl/sunxi/Kconfig  |   5 +
 drivers/pinctrl/sunxi/Makefile |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c| 181 +
 4 files changed, 189 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c

diff --git 
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index b321b26780dc..b3b6c2f210d7 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -18,6 +18,8 @@ Required properties:
   "allwinner,sun8i-a23-r-pinctrl"
   "allwinner,sun8i-a33-pinctrl"
   "allwinner,sun8i-a83t-pinctrl"
+  "allwinner,sun9i-a80-pinctrl"
+  "allwinner,sun9i-a80-r-pinctrl"
 
 - reg: Should contain the register physical address and length for the
   pin controller.
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index e68fd951129a..0252b3fa41ce 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -55,4 +55,9 @@ config PINCTRL_SUN9I_A80
def_bool MACH_SUN9I
select PINCTRL_SUNXI_COMMON
 
+config PINCTRL_SUN9I_A80_R
+   def_bool MACH_SUN9I
+   depends on RESET_CONTROLLER
+   select PINCTRL_SUNXI_COMMON
+
 endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index e08029034510..0b4b827f314b 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)   += pinctrl-sun8i-a83t.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
+obj-$(CONFIG_PINCTRL_SUN9I_A80_R)  += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c 
b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
new file mode 100644
index ..42547ffa20a8
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
@@ -0,0 +1,181 @@
+/*
+ * Allwinner A80 SoCs special pins pinctrl driver.
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ * Maxime Ripard <maxime.rip...@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun9i_a80_r_pins[] = {
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_uart"),/* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_uart"),/* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_jtag"),/* TMS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_jtag"),/* TCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_jtag"),/* TDO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PL_EINT4 */
+   SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ 

[linux-sunxi] [PATCH 2/7] ARM: dts: sun9i: Add A80 R_PIO pin controller device node

[Chen-Yu Tsai]

The A80 has a secondary pin controller. Add a device node for it.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index eb69a62f6bc4..d02ee5d520e2 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -868,5 +868,19 @@
resets = <_rst 4>;
status = "disabled";
};
+
+   r_pio: pinctrl@08002c00 {
+   compatible = "allwinner,sun9i-a80-r-pinctrl";
+   reg = <0x08002c00 0x400>;
+   interrupts = ,
+;
+   clocks = <_gates 0>;
+   resets = <_rst 0>;
+   gpio-controller;
+   interrupt-controller;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   #gpio-cells = <3>;
+   };
};
 };
-- 
2.6.2

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[linux-sunxi] [PATCH 0/7] ARM: sun9i: R_PIO, IR receiver and RSB support

[Chen-Yu Tsai]

Hi everyone,

This series adds support for various peripherals in the "special/RTC"
block of the Allwinner A80 SoC that use the PRCM clocks and reset
controls. The majority of this series are DTS patches, enabling
peripherals using existing drivers. The only driver patch is for the
R_PIO pin controller.

This series is based on my earlier sun9i PRCM series. The pinctrl 
patch has no dependencies though. All patches target sun9i-a80:

Patch 1 adds a driver for the R_PIO "special CPU" block pin controller.
This was done by Maxime over a year ago, when the A80 was first available.

Patch 2 adds the R_PIO pinctrl device node.

Patch 3 enables LED3 on the A80 Optimus board. This is driven by a GPIO
from R_PIO.

Patch 4 adds a consumer IR receiver device node, which is compatible with
earlier Allwinner SoCs, and its associated pinmux.

Patch 5 enables the consumer IR receiver on the A80 Optimus.

Patch 6 adds a device node for the RSB controller. This controller is
compatible with the one found on the A23/A33.

Patch 7 enables the RSB controller on the A80 Optimus.

Still to come are A80-related PMIC drivers and DTS patches.


Regards
ChenYu

Chen-Yu Tsai (6):
  ARM: dts: sun9i: Add A80 R_PIO pin controller device node
  ARM: dts: sun9i: optimus: Enable LED3
  ARM: dts: sun9i: Add consumer IR receiver device node and pinmux
settings
  ARM: dts: sun9i: optimus: Enable consumer IR receiver
  ARM: dts: sun9i: Add Reduced Serial Bus controller device node to A80
dtsi
  ARM: dts: sun9i: optimus: Enable Reduced Serial Bus controller

Maxime Ripard (1):
  pinctrl: sunxi: Add A80 special pin controller

 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   2 +
 arch/arm/boot/dts/sun9i-a80-optimus.dts|  24 ++-
 arch/arm/boot/dts/sun9i-a80.dtsi   |  54 ++
 drivers/pinctrl/sunxi/Kconfig  |   5 +
 drivers/pinctrl/sunxi/Makefile |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c| 181 +
 6 files changed, 265 insertions(+), 2 deletions(-)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c

-- 
2.6.2

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[linux-sunxi] [PATCH 4/7] ARM: dts: sun9i: Add consumer IR receiver device node and pinmux settings

[Chen-Yu Tsai]

The Allwinner A80 SoC has a consumer IR receiver, which is the same as
older SoCs.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index d02ee5d520e2..80777a33ee78 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -858,6 +858,18 @@
#reset-cells = <1>;
};
 
+   r_ir: ir@08002000 {
+   compatible = "allwinner,sun5i-a13-ir";
+   interrupts = ;
+   pinctrl-names = "default";
+   pinctrl-0 = <_ir_pins>;
+   clocks = <_gates 1>, <_ir_clk>;
+   clock-names = "apb", "ir";
+   resets = <_rst 1>;
+   reg = <0x08002000 0x40>;
+   status = "disabled";
+   };
+
r_uart: serial@08002800 {
compatible = "snps,dw-apb-uart";
reg = <0x08002800 0x400>;
@@ -881,6 +893,13 @@
#address-cells = <1>;
#size-cells = <0>;
#gpio-cells = <3>;
+
+   r_ir_pins: r_ir {
+   allwinner,pins = "PL6";
+   allwinner,function = "s_cir_rx";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
};
};
 };
-- 
2.6.2

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[linux-sunxi] [PATCH 7/7] ARM: dts: sun9i: optimus: Enable Reduced Serial Bus controller

[Chen-Yu Tsai]

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun9i-a80-optimus.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts 
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 79766e5867cd..c0060e4f7379 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -196,6 +196,10 @@
};
 };
 
+_rsb {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-- 
2.6.2

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[linux-sunxi] [PATCH 3/7] ARM: dts: sun9i: optimus: Enable LED3

[Chen-Yu Tsai]

LED3 is connected to pin PM15 on R_PIO.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun9i-a80-optimus.dts | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts 
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 6ce4b5e8b615..ae7db9fcb2a7 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -65,7 +65,7 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
-   pinctrl-0 = <_pins_optimus>;
+   pinctrl-0 = <_pins_optimus>, <_r_pins_optimus>;
 
/* The LED names match those found on the board */
 
@@ -74,7 +74,10 @@
gpios = < 7 1 GPIO_ACTIVE_HIGH>;
};
 
-   /* led3 is on PM15, in R_PIO */
+   led3 {
+   label = "optimus:led3:usr";
+   gpios = <_pio 1 15 GPIO_ACTIVE_HIGH>; /* PM15 */
+   };
 
led4 {
label = "optimus:led4:usr";
@@ -180,6 +183,15 @@
status = "okay";
 };
 
+_pio {
+   led_r_pins_optimus: led-pins@1 {
+   allwinner,pins = "PM15";
+   allwinner,function = "gpio_out";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-- 
2.6.2

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[linux-sunxi] [PATCH 5/7] ARM: dts: sun9i: optimus: Enable consumer IR receiver

[Chen-Yu Tsai]

The A80 Optimus board has a consumer IR receiver. Enable it in the DT.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun9i-a80-optimus.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts 
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index ae7db9fcb2a7..79766e5867cd 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -183,6 +183,10 @@
status = "okay";
 };
 
+_ir {
+   status = "okay";
+};
+
 _pio {
led_r_pins_optimus: led-pins@1 {
allwinner,pins = "PM15";
-- 
2.6.2

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Re: [linux-sunxi] clk_out_a usage in mainline

[Chen-Yu Tsai]

On Tue, Dec 1, 2015 at 11:01 PM, Danny Milosavljevic
<dan...@scratchpost.org> wrote:
> Hi Maxime,
>
> On Tue, 1 Dec 2015 10:47:37 +0100
> Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
>> Did you mux the clk_out pin somewhere?
>
> Not manually, no. Is that not done by the sunxi clock driver when
> preparing/enabling the clock?

You mux the clock output on the output pin by adding a pinctrl phandle
in whatever device node you are using it for.

> Also since the signal flatlined, I think clk_prepare_enable did
> *something*. (it probably switched away from the GPIO function; a
> shell script to simulate a poor-mans clock using GPIO was still running
> but the scope didn't show it anymore afterwards)

AFAIK the clock code does no such thing.

>
> (I thought clk_out_a was initially introduced by Chen-Yu
> Tsai for the Cubietruck Wifi but I can't find where the Wifi driver|dts
> muxes clk_out_a in 4.4-rc2 either)

It was supposed to be part of the Bluetooth support. The BT part of the
combo chip needs the clock signal, while the WiFi part doesn't. I've not
updated any of it yet.


ChenYu

>> Did you enable the clock?
>
> Back then, I enabled it very directly in
> <http://svn.nomike.com/playground/trunk/Navi/TSS463AA/Linux/tss463aa.c?p=5734>,
> search for "clk_prepare_enable". (I used the low clock rate so I could
> have seen it on my cheap scope if it worked)
>
> (Now it's nicer (but still doesn't work),
> <http://svn.nomike.com/playground/trunk/Navi/TSS463AA/Linux/tss463aa.c>
> - and it needs extra device tree attributes now)
>
> Thanks,
>Danny
>
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[linux-sunxi] Re: [PATCH v4 1/5] clk: sunxi: Add CLK_OF_DECLARE support for sun8i-a23-apb0-clk driver

[Chen-Yu Tsai]

On Tue, Dec 1, 2015 at 6:04 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Sun, Nov 29, 2015 at 11:03:06AM +0800, Chen-Yu Tsai wrote:
>> The APBS clock on sun9i is the same as the APB0 clock on sun8i. With
>> sun9i we are supporting the PRCM clocks by using CLK_OF_DECLARE,
>> instead of through a PRCM mfd device and subdevices for each clock
>> and reset control. As such we need a CLK_OF_DECLARE version of
>> the sun8i-a23-apb0-clk driver.
>>
>> Also, build it for sun9i/A80, and not just for configurations with
>> MFD_SUN6I_PRCM enabled.
>>
>> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
>> ---
>>  drivers/clk/sunxi/Makefile |  5 +--
>>  drivers/clk/sunxi/clk-sun8i-apb0.c | 71 
>> +++---
>>  2 files changed, 62 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
>> index cb4c299214ce..c55d5cd1c0e5 100644
>> --- a/drivers/clk/sunxi/Makefile
>> +++ b/drivers/clk/sunxi/Makefile
>> @@ -15,6 +15,7 @@ obj-y += clk-sun9i-core.o
>>  obj-y += clk-sun9i-mmc.o
>>  obj-y += clk-usb.o
>>
>> +obj-$(CONFIG_MACH_SUN9I) += clk-sun8i-apb0.o
>> +
>
> So sun8i doesn't use it?

Shit... I messed up. clk-sun8i-apb0.o should also be under
CONFIG_MFD_SUN6I_PRCM.

I'll send a new version of this patch. No need to keep spamming
people with the whole series.

>>  obj-$(CONFIG_MFD_SUN6I_PRCM) += \
>> - clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
>> - clk-sun8i-apb0.o
>> + clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o
>> diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c 
>> b/drivers/clk/sunxi/clk-sun8i-apb0.c
>> index 7ae5d2c2cde1..c1e2ac8f4b0d 100644
>> --- a/drivers/clk/sunxi/clk-sun8i-apb0.c
>> +++ b/drivers/clk/sunxi/clk-sun8i-apb0.c
>> @@ -17,13 +17,68 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>
>> +static struct clk *sun8i_a23_apb0_register(struct device_node *node,
>> +void __iomem *reg)
>> +{
>> + const char *clk_name = node->name;
>> + const char *clk_parent;
>> + struct clk *clk;
>> + int ret;
>> +
>> + clk_parent = of_clk_get_parent_name(node, 0);
>> + if (!clk_parent)
>> + return ERR_PTR(-EINVAL);
>> +
>> + of_property_read_string(node, "clock-output-names", _name);
>> +
>> + /* The A23 APB0 clock is a standard 2 bit wide divider clock */
>> + clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg,
>> +0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
>> + if (IS_ERR(clk))
>> + return clk;
>> +
>> + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
>> + if (ret)
>> + goto err_unregister;
>> +
>> + return clk;
>> +
>> +err_unregister:
>> + clk_unregister_divider(clk);
>> +
>> + return ERR_PTR(ret);
>> +}
>> +
>> +static void sun8i_a23_apb0_setup(struct device_node *node)
>> +{
>> + void __iomem *reg;
>> + struct resource res;
>> + struct clk *clk;
>> +
>> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
>> + if (IS_ERR(reg))
>> + return;
>> +
>> + clk = sun8i_a23_apb0_register(node, reg);
>> + if (IS_ERR(clk))
>> + goto err_unmap;
>> +
>> + return;
>> +
>> +err_unmap:
>> + iounmap(reg);
>> + of_address_to_resource(node, 0, );
>> + release_mem_region(res.start, resource_size());
>> +}
>> +CLK_OF_DECLARE(sun8i_a23_apb0, "allwinner,sun8i-a23-apb0-clk",
>> +sun8i_a23_apb0_setup);
>> +
>>  static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev)
>>  {
>>   struct device_node *np = pdev->dev.of_node;
>> - const char *clk_name = np->name;
>> - const char *clk_parent;
>>   struct resource *r;
>>   void __iomem *reg;
>>   struct clk *clk;
>> @@ -33,19 +88,11 @@ static int sun8i_a23_apb0_clk_probe(struct 
>> platform_device *pdev)
>>   if (IS_ERR(reg))
>>   return PTR_ERR(reg);
>>
>> - clk_parent = of_clk_get_parent_name(np, 0);
>> - if (!clk_parent)
>> - return -EINVAL;
>> -
>> - of_property_read_string(np, "clock-output-names", _name);
>> -
>>

[linux-sunxi] Re: [PATCH v4 1/5] clk: sunxi: Add CLK_OF_DECLARE support for sun8i-a23-apb0-clk driver

[Chen-Yu Tsai]

On Tue, Dec 1, 2015 at 8:50 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> On Tue, Dec 01, 2015 at 07:54:06PM +0800, Chen-Yu Tsai wrote:
>> On Tue, Dec 1, 2015 at 6:04 PM, Maxime Ripard
>> <maxime.rip...@free-electrons.com> wrote:
>> > Hi,
>> >
>> > On Sun, Nov 29, 2015 at 11:03:06AM +0800, Chen-Yu Tsai wrote:
>> >> The APBS clock on sun9i is the same as the APB0 clock on sun8i. With
>> >> sun9i we are supporting the PRCM clocks by using CLK_OF_DECLARE,
>> >> instead of through a PRCM mfd device and subdevices for each clock
>> >> and reset control. As such we need a CLK_OF_DECLARE version of
>> >> the sun8i-a23-apb0-clk driver.
>> >>
>> >> Also, build it for sun9i/A80, and not just for configurations with
>> >> MFD_SUN6I_PRCM enabled.
>> >>
>> >> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
>> >> ---
>> >>  drivers/clk/sunxi/Makefile |  5 +--
>> >>  drivers/clk/sunxi/clk-sun8i-apb0.c | 71 
>> >> +++---
>> >>  2 files changed, 62 insertions(+), 14 deletions(-)
>> >>
>> >> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
>> >> index cb4c299214ce..c55d5cd1c0e5 100644
>> >> --- a/drivers/clk/sunxi/Makefile
>> >> +++ b/drivers/clk/sunxi/Makefile
>> >> @@ -15,6 +15,7 @@ obj-y += clk-sun9i-core.o
>> >>  obj-y += clk-sun9i-mmc.o
>> >>  obj-y += clk-usb.o
>> >>
>> >> +obj-$(CONFIG_MACH_SUN9I) += clk-sun8i-apb0.o
>> >> +
>> >
>> > So sun8i doesn't use it?
>>
>> Shit... I messed up. clk-sun8i-apb0.o should also be under
>> CONFIG_MFD_SUN6I_PRCM.
>>
>> I'll send a new version of this patch. No need to keep spamming
>> people with the whole series.
>
> Ok.
>
>> >>  obj-$(CONFIG_MFD_SUN6I_PRCM) += \
>> >> - clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
>> >> - clk-sun8i-apb0.o
>> >> + clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o
>> >> diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c 
>> >> b/drivers/clk/sunxi/clk-sun8i-apb0.c
>> >> index 7ae5d2c2cde1..c1e2ac8f4b0d 100644
>> >> --- a/drivers/clk/sunxi/clk-sun8i-apb0.c
>> >> +++ b/drivers/clk/sunxi/clk-sun8i-apb0.c
>> >> @@ -17,13 +17,68 @@
>> >>  #include 
>> >>  #include 
>> >>  #include 
>> >> +#include 
>> >>  #include 
>> >>
>> >> +static struct clk *sun8i_a23_apb0_register(struct device_node *node,
>> >> +void __iomem *reg)
>> >> +{
>> >> + const char *clk_name = node->name;
>> >> + const char *clk_parent;
>> >> + struct clk *clk;
>> >> + int ret;
>> >> +
>> >> + clk_parent = of_clk_get_parent_name(node, 0);
>> >> + if (!clk_parent)
>> >> + return ERR_PTR(-EINVAL);
>> >> +
>> >> + of_property_read_string(node, "clock-output-names", _name);
>> >> +
>> >> + /* The A23 APB0 clock is a standard 2 bit wide divider clock */
>> >> + clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg,
>> >> +0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
>> >> + if (IS_ERR(clk))
>> >> + return clk;
>> >> +
>> >> + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
>> >> + if (ret)
>> >> + goto err_unregister;
>> >> +
>> >> + return clk;
>> >> +
>> >> +err_unregister:
>> >> + clk_unregister_divider(clk);
>> >> +
>> >> + return ERR_PTR(ret);
>> >> +}
>> >> +
>> >> +static void sun8i_a23_apb0_setup(struct device_node *node)
>> >> +{
>> >> + void __iomem *reg;
>> >> + struct resource res;
>> >> + struct clk *clk;
>> >> +
>> >> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
>> >> + if (IS_ERR(reg))
>> >> + return;
>> >> +
>> >> + clk = sun8i_a23_apb0_register(node, reg);
>> >> + if (IS_ERR(clk))
>> >> + goto err_unmap;
>> >> +
>> >> + return;
>

[linux-sunxi] Re: [PATCH] thermal: Add support for Sunxi THS on the Allwinner H3

[Chen-Yu Tsai]

On Thu, Nov 19, 2015 at 4:51 AM, Josef Gajdusek  wrote:
> This patch adds support for the Sunxi thermal sensor on the Allwinner H3.
> Also adds declaration of the H3 THS clock to clk-sunxi.c ignoring the
> dividers as they are not continuous (clk-divider.c cannot be used as it
> does not support setting an enable bit).

That is not right. See below.

> Should be easily extendable for the A33/A83T/... as they have similar but
> not completely identical sensors.
>
> Signed-off-by: Josef Gajdusek 
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt  |   1 +
>  .../devicetree/bindings/thermal/sunxi-ths.txt  |  24 ++
>  arch/arm/boot/dts/sun8i-h3.dtsi|  27 +++
>  drivers/clk/sunxi/clk-sunxi.c  |  16 ++
>  drivers/thermal/Kconfig|   7 +
>  drivers/thermal/Makefile   |   1 +
>  drivers/thermal/sunxi_ths.c| 263 
> +

Thanks for working on this.

This patch should be split into 5 patches: clock binding, clock driver,
THS binding, THS driver, and DTS updates.

>  7 files changed, 339 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/thermal/sunxi-ths.txt
>  create mode 100644 drivers/thermal/sunxi_ths.c
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
> b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 23e7bce..6d63b35 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -73,6 +73,7 @@ Required properties:
> "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
> "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
> "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
> +   "allwinner,sun8i-h3-ths-clk" - for THS on H3
>
>  Required properties for all clocks:
>  - reg : shall be the control register address for the clock.
> diff --git a/Documentation/devicetree/bindings/thermal/sunxi-ths.txt 
> b/Documentation/devicetree/bindings/thermal/sunxi-ths.txt
> new file mode 100644
> index 000..75c9211
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/sunxi-ths.txt
> @@ -0,0 +1,24 @@
> +* sunxi THS
> +
> +Required properties:
> +- compatible : "allwinner,sun8i-h3-ths"
> +- reg : Address range of the thermal registers and location of the 
> calibration
> +value

The latter is part of the Security ID (efuses) block, for which we have
Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt.
Please use a phandle to the security id block instead.

See Documentation/devicetree/bindings/nvmem/nvmem.txt for the generic
nvmem bindings.

> +- resets : Must contain an entry for each entry in reset-names.
> +   see ../reset/reset.txt for details
> +- reset-names : Must include the name "ahb"
> +- clocks : Must contain an entry for each entry in clock-names.
> +- clock-names : Must contain "ahb" for the bus gate and "ths" for the THS
> +  clock
> +
> +Example:
> +ths: ths@01c25000 {
> +   #thermal-sensor-cells = <0>;
> +   compatible = "allwinner,sun8i-h3-ths";
> +   reg = <0x01c25000 0x88>, <0x01c14234 0x4>;
> +   interrupts = ;
> +   resets = <_rst 136>;
> +   reset-names = "ahb";
> +   clocks = <_gates 72>, <_clk>;
> +   clock-names = "ahb", "ths";
> +};
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 0faa38a..b82881d 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -77,6 +77,14 @@
> };
> };
>
> +   thermal-zones {
> +   cpu_thermal: cpu_thermal {
> +   polling-delay-passive = <1000>;
> +   polling-delay = <5000>;
> +   thermal-sensors = < 0>;
> +   };
> +   };
> +
> timer {
> compatible = "arm,armv7-timer";
> interrupts =  IRQ_TYPE_LEVEL_LOW)>,
> @@ -236,6 +244,14 @@
> "ahb1_ephy", "ahb1_dbg";
> };
>
> +   ths_clk: clk@01c20074 {
> +   #clock-cells = <0>;
> +   compatible = "allwinner,sun8i-h3-ths-clk";
> +   reg = <0x01c20074 0x4>;
> +   clocks = <>;
> +   clock-output-names = "ths";
> +   };
> +
> mmc0_clk: clk@01c20088 {
> #clock-cells = <1>;
> compatible = "allwinner,sun4i-a10-mmc-clk";
> @@ -522,6 +538,17 @@
> interrupts = ;
> };
>
> +   ths: ths@01c25000 {
> +   #thermal-sensor-cells = <0>;
> +   compatible = "allwinner,sun8i-h3-ths";
> +   reg = <0x01c25000 0x88>, <0x01c14234 0x4>;
> +   

[linux-sunxi] Re: [PATCH 4/4] ARM: dts: sun5i: Add i2c axp152 pmic support for Auxtek T004 boards

[Chen-Yu Tsai]

On Fri, Nov 20, 2015 at 9:59 PM, Hans de Goede <hdego...@redhat.com> wrote:
> From: Michael van Slingerland <mich...@deviousops.nl>
>
> Add a node describing the AXP152 pmic used on Auxtek T004 boards.
>
> Signed-off-by: Michael van Slingerland <mich...@deviousops.nl>
> Signed-off-by: Hans de Goede <hdego...@redhat.com>

Acked-by: Chen-Yu Tsai <w...@csie.org>

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[linux-sunxi] Re: [PATCH 3/4] ARM: dts: sun4i: Add backlight node to pov protab2 ips9 tablet

[Chen-Yu Tsai]

On Fri, Nov 20, 2015 at 9:59 PM, Hans de Goede <hdego...@redhat.com> wrote:
> Add a node describing the lcd panel backlight on the pov protab2 ips9
> tablet.
>
> Signed-off-by: Hans de Goede <hdego...@redhat.com>

Acked-by: Chen-Yu Tsai <w...@csie.org>

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[linux-sunxi] Re: [PATCH 2/4] ARM: dts: sun5i: Add backlight node to UTOO P66 tablet

[Chen-Yu Tsai]

On Fri, Nov 20, 2015 at 9:59 PM, Hans de Goede <hdego...@redhat.com> wrote:
> Add a node describing the lcd panel backlight on the UTOO P66 tablet.
>
> Signed-off-by: Hans de Goede <hdego...@redhat.com>

Acked-by: Chen-Yu Tsai <w...@csie.org>

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[linux-sunxi] Re: [PATCH 1/4] ASoC: sun4i-codec: Add support for PA gpio pin

[Chen-Yu Tsai]

On Sat, Nov 21, 2015 at 12:30 AM, Maxime Ripard
 wrote:
> On Fri, Nov 20, 2015 at 02:47:10PM +0100, Hans de Goede wrote:
>> Add support for PA gpio pin for controlling an external amplifier as used
>> on some Allwinner boards.
>>
>> Signed-off-by: Hans de Goede 
>> ---
>>  .../devicetree/bindings/sound/sun4i-codec.txt  |  3 +++
>>  sound/soc/sunxi/sun4i-codec.c  | 25 
>> ++
>>  2 files changed, 19 insertions(+), 9 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/sound/sun4i-codec.txt 
>> b/Documentation/devicetree/bindings/sound/sun4i-codec.txt
>> index c92966b..974babe 100644
>> --- a/Documentation/devicetree/bindings/sound/sun4i-codec.txt
>> +++ b/Documentation/devicetree/bindings/sound/sun4i-codec.txt
>> @@ -14,6 +14,9 @@ Required properties:
>> - "apb": the parent APB clock for this controller
>> - "codec": the parent module clock
>>
>> +Optional properties:
>> +- pa-gpios: gpio to enable external amplifier
>
> This is a custom property, it should be prefixed by the vendor name.
>
>> +
>>  Example:
>>  codec: codec@01c22c00 {
>>   #sound-dai-cells = <0>;
>> diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
>> index bcbf4da..2aca9cd 100644
>> --- a/sound/soc/sunxi/sun4i-codec.c
>> +++ b/sound/soc/sunxi/sun4i-codec.c
>> @@ -27,6 +27,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>
>>  #include 
>>  #include 
>> @@ -101,16 +102,15 @@ struct sun4i_codec {
>>   struct regmap   *regmap;
>>   struct clk  *clk_apb;
>>   struct clk  *clk_module;
>> + struct gpio_desc *gpio_pa;
>>
>>   struct snd_dmaengine_dai_dma_data   playback_dma_data;
>>  };
>>
>>  static void sun4i_codec_start_playback(struct sun4i_codec *scodec)
>>  {
>> - /*
>> -  * FIXME: according to the BSP, we might need to drive a PA
>> -  *GPIO high here on some boards
>> -  */
>> + if (scodec->gpio_pa)
>> + gpiod_set_value_cansleep(scodec->gpio_pa, 1);
>>
>>   /* Flush TX FIFO */
>>   regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
>> @@ -125,15 +125,13 @@ static void sun4i_codec_start_playback(struct 
>> sun4i_codec *scodec)
>>
>>  static void sun4i_codec_stop_playback(struct sun4i_codec *scodec)
>>  {
>> - /*
>> -  * FIXME: according to the BSP, we might need to drive a PA
>> -  *GPIO low here on some boards
>> -  */
>> -
>>   /* Disable DAC DRQ */
>>   regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
>>  BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN),
>>  0);
>> +
>> + if (scodec->gpio_pa)
>> + gpiod_set_value_cansleep(scodec->gpio_pa, 0);
>
> You should rather plug that into DAPM, using a speaker widget, and a
> custom event function that will enable or disable the amplifier only
> when this audio path is going to be used.

Isn't an "amplifier" widget better suited?

ChenYu

> You can see such an example here:
> http://lxr.free-electrons.com/source/sound/soc/jz4740/qi_lb60.c#L29
>
> That will require to modify a bit sun4i_codec_create_card as well in
> order to add the new widgets (and routes) when the DT property is
> found.
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

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[linux-sunxi] Re: [PATCH v3 5/9] ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator nodes

[Chen-Yu Tsai]

On Fri, Nov 20, 2015 at 7:12 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Tue, Nov 17, 2015 at 12:38:24AM +0800, Chen-Yu Tsai wrote:
>> This board has a X-Powers AXP223 PMIC connected via RSB. Its regulators
>> provide power to various parts of the SoC and the board.
>>
>> Also update the regulator supply phandles.
>>
>> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
>> ---
>>  arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 79 
>> +-
>>  1 file changed, 76 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts 
>> b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
>> index 13ce68f06dd6..91a0fde47fdd 100644
>> --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
>> +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
>> @@ -68,7 +68,7 @@
>>  };
>>
>>   {
>> - vref-supply = <_vcc3v0>;
>> + vref-supply = <_dcdc1>;
>>   status = "okay";
>>
>>   button@200 {
>> @@ -96,7 +96,7 @@
>>   {
>>   pinctrl-names = "default";
>>   pinctrl-0 = <_pins_a>, <_cd_pin_sina33>;
>> - vmmc-supply = <_vcc3v0>;
>> + vmmc-supply = <_dcdc1>;
>>   bus-width = <4>;
>>   cd-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
>>   cd-inverted;
>> @@ -106,7 +106,7 @@
>>   {
>>   pinctrl-names = "default";
>>   pinctrl-0 = <_8bit_pins>;
>> - vmmc-supply = <_vcc3v0>;
>> + vmmc-supply = <_dcdc1>;
>>   bus-width = <8>;
>>   non-removable;
>>   status = "okay";
>> @@ -132,6 +132,79 @@
>>
>>  _rsb {
>>   status = "okay";
>> +
>> + axp22x: pmic@3e3 {
>> + compatible = "x-powers,axp223";
>> + reg = <0x3e3>;
>> + interrupt-parent = <_intc>;
>> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
>> + eldoin-supply = <_dcdc1>;
>> + };
>> +};
>> +
>> +#include "axp22x.dtsi"
>> +
>> +_aldo1 {
>> + regulator-always-on;
>> + regulator-min-microvolt = <300>;
>> + regulator-max-microvolt = <300>;
>> + regulator-name = "vcc-io";
>> +};
>> +
>> +_aldo2 {
>> + regulator-always-on;
>> + regulator-min-microvolt = <235>;
>> + regulator-max-microvolt = <265>;
>> + regulator-name = "vdd-dll";
>> +};
>> +
>> +_aldo3 {
>> + regulator-always-on;
>> + regulator-min-microvolt = <270>;
>> + regulator-max-microvolt = <330>;
>> + regulator-name = "vcc-pll-avcc";
>> +};
>> +
>> +_dc5ldo {
>> + regulator-always-on;
>> + regulator-min-microvolt = <90>;
>> + regulator-max-microvolt = <140>;
>> + regulator-name = "vdd-cpus";
>> +};
>> +
>> +_dcdc1 {
>> + regulator-always-on;
>> + regulator-min-microvolt = <300>;
>> + regulator-max-microvolt = <300>;
>> + regulator-name = "vcc-3v0";
>> +};
>> +
>> +_dcdc2 {
>> + regulator-always-on;
>> + regulator-min-microvolt = <90>;
>> + regulator-max-microvolt = <140>;
>> + regulator-name = "vdd-sys";
>> +};
>> +
>> +_dcdc3 {
>> + regulator-always-on;
>> + regulator-min-microvolt = <90>;
>> + regulator-max-microvolt = <140>;
>> + regulator-name = "vdd-cpu";
>> +};
>> +
>> +_dcdc5 {
>> + regulator-always-on;
>> + regulator-min-microvolt = <150>;
>> + regulator-max-microvolt = <150>;
>> + regulator-name = "vcc-dram";
>> +};
>> +
>> +_rtc_ldo {
>> + regulator-always-on;
>> + regulator-min-microvolt = <300>;
>> + regulator-max-microvolt = <300>;
>> + regulator-name = "vcc-rtc";
>>  };
>
> Isn't this supposed to be in the AXP DTSI?

Are you referring to _rtc_ldo? Yes, it should. I'll do a new version.

Thanks
ChenYu

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[linux-sunxi] Re: [PATCH v2 1/3] ARM: sunxi: Re-enable SID driver in sunxi_defconfig

[Chen-Yu Tsai]

On Fri, Nov 20, 2015 at 9:46 AM, Timo Sigurdsson
<public_tim...@silentcreek.de> wrote:
> Commit 3d0b16a66c8a ("nvmem: sunxi: Move the SID driver to the nvmem
> framework") moved the the sunxi SID driver to a new framework, but left
> sunxi_defconfig with the deprecated config symbol EEPROM_SUNXI_SID
> instead of the new symbol NVMEM_SUNXI_SID. Hence, re-enable the driver
> in sunxi_defconfig.
>
> Signed-off-by: Timo Sigurdsson <public_tim...@silentcreek.de>

Acked-by: Chen-Yu Tsai <w...@csie.org>

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[linux-sunxi] Re: [PATCH v2 2/3] ARM: sunxi: Really enable LRADC keys in sunxi_defconfig

[Chen-Yu Tsai]

On Fri, Nov 20, 2015 at 9:46 AM, Timo Sigurdsson
<public_tim...@silentcreek.de> wrote:
> Commit be8becb81bdc ("ARM: sunxi_defconfig: Enable LRADC keys
> (KEYBOARD_SUN4I_LRADC)") added CONFIG_KEYBOARD_SUN4I_LRADC=y to
> sunxi_defconfig. However, it depends on CONFIG_KEYBOARD which is
> explicitly disabled in sunxi_defconfig. Hence, the LRADC keys were
> never actually enabled. Remove the line disabling CONFIG_KEYBOARD in
> order to really enable KEYBOARD_SUN4I_LRADC.
>
> Signed-off-by: Timo Sigurdsson <public_tim...@silentcreek.de>

Acked-by: Chen-Yu Tsai <w...@csie.org>

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Re: [linux-sunxi] Re: [PATCH v3 3/3] ARM: dts: sun4i: gemei-g9: Enable sun4i audio codec support

[Chen-Yu Tsai]

On Fri, Nov 20, 2015 at 12:09 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Thu, Nov 12, 2015 at 08:53:19PM +0200, Priit Laes wrote:
>> On Mon, 2015-11-09 at 11:59 +0800, Chen-Yu Tsai wrote:
>> > On Sat, Nov 7, 2015 at 1:54 AM, Priit Laes <pl...@plaes.org> wrote:
>> > > Gemei G9 has internal speakers and headphone jack. Audio switching
>> > > from internal speakers to headphones is automatically handled by
>> > > extra FT2012Q audio amplifier chip that works out of the box.
>> >
>> > Nice that it works out of the box. The FEX file does mention:
>> >
>> > audio_pa_ctrl   = port:PH15<1><0>
>>
>> Nice catch.
>>
>> Setting it low mutes audio, and setting it back high unmutes.
>
> Then you just volunteered yourself to fix the FIXME in the driver ;)
>

Hans seems to have a patch for this in his sunxi-wip branch.
I haven't looked at it though.

ChenYu

>> > So either it is floating or pulled up by default? Since it works
>> > now I don't see any reason to block it. On the other hand once
>> > that binding is introduced it would be nice to add it for power
>> > management reasons.
>>
>> Should I just add comment about it or do something like this:
>>
>>  {
>>   status = "okay";
>>   /*
>>* TODO: Add codec_ext_pwr_pin to turn off external audio AMP
>> {
>>  codec_ext_pwr_pin: codec_ext_pwr_pin@0 {
>>allwinner,pins = "PH15";
>>allwinner,function = "gpio_out";
>>allwinner,drive = ;
>>allwinner,pull = ;
>>  }
>>}
>>*/
>> }
>
> More like
>
>  {
> codec_ext_pwr_pin: codec_ext_pwr_pin@0 {
> allwinner,pins = "PH15";
> allwinner,function = "gpio_out";
> allwinner,drive = ;
> allwinner,pull = ;
> };
> };
>
>  {
> /* This pin is used to turn off the GPIO amp pin */
> pinctrl-names = "default";
> pinctrl-0 <_ext_pwr_pin>;
> status = "okay";
> };
>
> Of course, that's a temporary measure, and you should actually use
> that GPIO to enable / disable the Amplifier when you are playing
> sound. It shouldn't be that hard with ASoC.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

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Re: [linux-sunxi] Re: [PATCH v4 4/6] reset: sunxi: Add Allwinner H3 bus resets

[Chen-Yu Tsai]

On Thu, Nov 5, 2015 at 2:47 PM, Jean-Francois Moine  wrote:
> On Wed, 4 Nov 2015 08:30:14 -0800
> Maxime Ripard  wrote:
>
>> Hi Arnd,
>>
>> On Fri, Oct 30, 2015 at 09:27:03AM +0100, Arnd Bergmann wrote:
>> > On Tuesday 27 October 2015 17:50:24 Jens Kuske wrote:
>> > >
>> > > +static int sun8i_h3_bus_reset_xlate(struct reset_controller_dev *rcdev,
>> > > +   const struct of_phandle_args 
>> > > *reset_spec)
>> > > +{
>> > > +   unsigned int index = reset_spec->args[0];
>> > > +
>> > > +   if (index < 96)
>> > > +   return index;
>> > > +   else if (index < 128)
>> > > +   return index + 32;
>> > > +   else if (index < 160)
>> > > +   return index + 64;
>> > > +   else
>> > > +   return -EINVAL;
>> > > +}
>> > > +
>> > >
>> >
>> > This looks like you are doing something wrong and should either
>> > put the actual number into DT,
>>
>> This is the actual number, except that there's some useless registers
>> in between. Allwinner documents it like that:
>>
>> 0x0   Reset 0
>> 0x4   Reset 1
>> 0xc   Reset 2
>>
>> So we have to adjust the offset to account with the blank register in
>> between (0x8).
>>
>> > or use a two-cell representation, with the first cell indicating the
>> > block (0, 1 or 2), and the second cell the index.
>>
>> And the missing register is not a block either.
>>
>> That would also imply either changing the bindings of that driver (and
>> all the current DTS that are using it), or introducing a whole new
>> driver just to deal with some extraordinary offset calculation.
>
> In the H3, the holes are not used, but what would occur if these holes
> would be used for some other purpose in future SoCs? Double mapping?

We'd have a different compatible string for it.

My suggestion for the resets is to just split them into 3 nodes: AHB
(since AHB1 and AHB2 devices are mixed together in the bunch), APB1,
and APB2 reset controls.

This follows what we have for existing SoCs, and gets rid of the unused
hole. We can use the existing "allwinner,sun6i-a31-clock-reset" and
"allwinner,sun6i-a31-ahb1-reset" compatibles.


Regards
ChenYu

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[linux-sunxi] Re: [PATCH v2 4/5] dt-bindings: document sun8i_ths

[Chen-Yu Tsai]

On Mon, Nov 23, 2015 at 4:02 PM, Josef Gajdusek  wrote:
> This patch adds the binding documentation for the sun8i_ths driver
>
> Signed-off-by: Josef Gajdusek 
> ---
>  .../devicetree/bindings/thermal/sun8i-ths.txt  | 31 
> ++
>  1 file changed, 31 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt
>
> diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt 
> b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt
> new file mode 100644
> index 000..67056bf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt
> @@ -0,0 +1,31 @@
> +* sun8i THS
> +
> +Required properties:
> +- compatible : "allwinner,sun8i-h3-ths"
> +- reg : Address range of the thermal registers and location of the 
> calibration
> +value

You are now using nvmem for the calibration data. You don't need the second
entry.

> +- resets : Must contain an entry for each entry in reset-names.
> +   see ../reset/reset.txt for details
> +- reset-names : Must include the name "ahb"
> +- clocks : Must contain an entry for each entry in clock-names.
> +- clock-names : Must contain "ahb" for the bus gate and "ths" for the THS
> +  clock
> +
> +Optional properties:
> +- nvmem-cells : Must contain an entry for each entry in nvmem-cell-names
> +- nvmem-cell-names : Must contain "calibration" for the cell containing the
> +  temperature calibration cell, if available
> +
> +Example:
> +ths: ths@01c25000 {
> +   #thermal-sensor-cells = <0>;
> +   compatible = "allwinner,sun8i-h3-ths";
> +   reg = <0x01c25000 0x88>, <0x01c14234 0x4>;

Same here.

ChenYu

> +   interrupts = ;
> +   resets = <_rst 136>;
> +   reset-names = "ahb";
> +   clocks = <_gates 72>, <_clk>;
> +   clock-names = "ahb", "ths";
> +   nvmem-cells = <_calibration>;
> +   nvmem-cell-names = "calibration";
> +};
> --
> 2.4.10
>

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[linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node

[Chen-Yu Tsai]

On Tue, Nov 24, 2015 at 2:38 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> On Tue, Nov 24, 2015 at 11:13:13AM +0800, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard
>> <maxime.rip...@free-electrons.com> wrote:
>> > Hi,
>> >
>> > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:
>> >> Add a node describing the Security ID memory to the
>> >> Allwinner H3 .dtsi file.
>> >>
>> >> Signed-off-by: Josef Gajdusek <a...@atx.name>
>> >> ---
>> >>  arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
>> >>  1 file changed, 7 insertions(+)
>> >>
>> >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi 
>> >> b/arch/arm/boot/dts/sun8i-h3.dtsi
>> >> index 0faa38a..58de718 100644
>> >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> >> @@ -359,6 +359,13 @@
>> >>   #size-cells = <0>;
>> >>   };
>> >>
>> >> + sid: eeprom@01c14000 {
>> >> + compatible = "allwinner,sun4i-a10-sid";
>> >> + reg = <0x01c14000 0x400>;
>> >
>> > The datasheet says it's 256 bytes wide, while the size here is of 1kB,
>> > is it intentional?
>>
>> My H3 datasheet (v1.1) says its 1 kB wide.
>
> Is it? in the Security ID section, it is said to be 2kb == 256B wide.

Right. I was looking at the memory map. Maybe it's sparsely mapped?
I guess we'll know soon.

ChenYu

>> It'd be nice if Allwinner actually listed the "usable" E-fuse
>> offsets and widths, instead of having us dig through the SDK code.
>
> Yep.
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

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[linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node

[Chen-Yu Tsai]

Hi,

On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard
 wrote:
> Hi,
>
> On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:
>> Add a node describing the Security ID memory to the
>> Allwinner H3 .dtsi file.
>>
>> Signed-off-by: Josef Gajdusek 
>> ---
>>  arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
>>  1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi 
>> b/arch/arm/boot/dts/sun8i-h3.dtsi
>> index 0faa38a..58de718 100644
>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> @@ -359,6 +359,13 @@
>>   #size-cells = <0>;
>>   };
>>
>> + sid: eeprom@01c14000 {
>> + compatible = "allwinner,sun4i-a10-sid";
>> + reg = <0x01c14000 0x400>;
>
> The datasheet says it's 256 bytes wide, while the size here is of 1kB,
> is it intentional?

My H3 datasheet (v1.1) says its 1 kB wide.

It'd be nice if Allwinner actually listed the "usable" E-fuse offsets
and widths, instead of having us dig through the SDK code.

Regards
ChenYu

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[linux-sunxi] [PATCH v4 4/6] regulator: axp20x: Support new AXP223 PMIC

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Reviewed-by: Mark Brown <broo...@kernel.org>
---
 drivers/regulator/axp20x-regulator.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/regulator/axp20x-regulator.c 
b/drivers/regulator/axp20x-regulator.c
index 35de22fdb7a0..55cce8125716 100644
--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
@@ -244,6 +244,7 @@ static int axp20x_set_dcdc_freq(struct platform_device 
*pdev, u32 dcdcfreq)
step = 75;
break;
case AXP221_ID:
+   case AXP223_ID:
min = 1800;
max = 4050;
def = 3000;
@@ -322,6 +323,7 @@ static int axp20x_set_dcdc_workmode(struct regulator_dev 
*rdev, int id, u32 work
break;
 
case AXP221_ID:
+   case AXP223_ID:
if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
return -EINVAL;
 
@@ -360,6 +362,7 @@ static int axp20x_regulator_probe(struct platform_device 
*pdev)
nregulators = AXP20X_REG_ID_MAX;
break;
case AXP221_ID:
+   case AXP223_ID:
regulators = axp22x_regulators;
nregulators = AXP22X_REG_ID_MAX;
break;
-- 
2.6.2

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[linux-sunxi] [PATCH v4 0/6] mfd: axp20x: Add support for RSB based AXP223

[Chen-Yu Tsai]

Hi everyone,

This is v4 of the AXP223 PMIC series.

Changes since v3:

  - Removed settings for axp223 reg_rtc_ldo from board dts files that
are already in axp22x.dtsi. The name is kept.

  - Dropped simplefb label and defconfig patches, as they are merged.

Changes since v2:

  - s/It's/Its/ for the commit messages of patches 5 and 7

  - Add Rob's Acked-by for patch 1

Changes since v1:

  - Dropped NMI interrupt controller dts patch (Merged)

  - Change MFD_AXP20X to represent the axp20x core, and drop MFD_AXP20X_CORE
  
  - Keep the axp20x core bits named axp20x.c

  - Add patch 7 to add AXP223 to sun8i-q8-common.dtsi

  - Add patch 8 & 9 to update defconfigs

  - Make axp20x drivers tristate and buildable as modules

  - Drop "_sunxi" substring from identifiers in axp20x-rsb driver


This series adds support for the Reduced Serial Bus based AXP223 PMIC.
The AXP223 is functionally identical to the AXP221, which we already
support. Only some default values for the regulators are different.
The defaults fit their recommended application, paired with different
SoCs.

Patch 1 adds AXP223 to the list of supported chips in the DT binding.

Patch 2 splits the axp20x mfd driver into 2 parts, a core library, and
an I2C driver.

Patch 3 adds an RSB based driver for the AXP223.

Patch 4 adds support for the AXP223 regulators

Patch 5 enables the AXP223 PMIC and its regulators for the Sinlinx
SinA33.

Patch 6 enables the AXP223 PMIC and its regulators for A23/A33 based
Q8 devices.


Regards
ChenYu


Chen-Yu Tsai (6):
  mfd: axp20x: Add AXP223 to list of supported PMICs in DT bindings
  mfd: axp20x: Split the driver into core and i2c bits
  mfd: axp20x: Add support for RSB based AXP223 PMIC
  regulator: axp20x: Support new AXP223 PMIC
  ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator
nodes
  ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes

 Documentation/devicetree/bindings/mfd/axp20x.txt |   7 +-
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts   |  79 +-
 arch/arm/boot/dts/sun8i-q8-common.dtsi   |  86 ++-
 drivers/mfd/Kconfig  |  25 -
 drivers/mfd/Makefile |   2 +
 drivers/mfd/axp20x-i2c.c | 127 +++
 drivers/mfd/axp20x-rsb.c |  93 +
 drivers/mfd/axp20x.c | 110 +++-
 drivers/regulator/axp20x-regulator.c |   3 +
 include/linux/mfd/axp20x.h   |  34 +-
 10 files changed, 458 insertions(+), 108 deletions(-)
 create mode 100644 drivers/mfd/axp20x-i2c.c
 create mode 100644 drivers/mfd/axp20x-rsb.c

-- 
2.6.2

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[linux-sunxi] [PATCH v4 1/6] mfd: axp20x: Add AXP223 to list of supported PMICs in DT bindings

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/mfd/axp20x.txt | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt 
b/Documentation/devicetree/bindings/mfd/axp20x.txt
index a474359dd206..fd39fa54571b 100644
--- a/Documentation/devicetree/bindings/mfd/axp20x.txt
+++ b/Documentation/devicetree/bindings/mfd/axp20x.txt
@@ -5,11 +5,12 @@ axp152 (X-Powers)
 axp202 (X-Powers)
 axp209 (X-Powers)
 axp221 (X-Powers)
+axp223 (X-Powers)
 
 Required properties:
 - compatible: "x-powers,axp152", "x-powers,axp202", "x-powers,axp209",
- "x-powers,axp221"
-- reg: The I2C slave address for the AXP chip
+ "x-powers,axp221", "x-powers,axp223"
+- reg: The I2C slave address or RSB hardware address for the AXP chip
 - interrupt-parent: The parent interrupt controller
 - interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin
 - interrupt-controller: The PMIC has its own internal IRQs
@@ -51,7 +52,7 @@ LDO3  : LDO   : ldo3in-supply
 LDO4   : LDO   : ldo24in-supply: shared supply
 LDO5   : LDO   : ldo5in-supply
 
-AXP221 regulators, type, and corresponding input supply names:
+AXP221/AXP223 regulators, type, and corresponding input supply names:
 
 RegulatorTypeSupply Name Notes
 ---- -
-- 
2.6.2

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[linux-sunxi] [PATCH v4 6/6] ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes

[Chen-Yu Tsai]

A23/A33 Q8 tablets have an X-Powers AXP223 PMIC connected via RSB. Its
regulators provide power to various parts of the SoC and the board.

Also add lcd regulator supply for simplefb and update the existing
vmmc-supply for mmc0.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-q8-common.dtsi | 86 +-
 1 file changed, 84 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi 
b/arch/arm/boot/dts/sun8i-q8-common.dtsi
index 1a69231d2da5..01ab47b32d8d 100644
--- a/arch/arm/boot/dts/sun8i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi
@@ -56,7 +56,6 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
enable-gpios = < 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
-   /* backlight is powered by AXP223 DC1SW */
};
 
chosen {
@@ -67,7 +66,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin_q8>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <4>;
cd-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
@@ -92,6 +91,85 @@
 
 _rsb {
status = "okay";
+
+   axp22x: pmic@3e3 {
+   compatible = "x-powers,axp223";
+   reg = <0x3e3>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   eldoin-supply = <_dcdc1>;
+   };
+};
+
+#include "axp22x.dtsi"
+
+_aldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-io";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <235>;
+   regulator-max-microvolt = <265>;
+   regulator-name = "vdd-dll";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <270>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_dc1sw {
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-lcd";
+};
+
+_dc5ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpus";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-3v0";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-sys";
+};
+
+_dcdc3 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpu";
+};
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram";
+};
+
+_rtc_ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-rtc";
 };
 
 _uart {
@@ -99,3 +177,7 @@
pinctrl-0 = <_uart_pins_a>;
status = "okay";
 };
+
+_lcd {
+   vcc-lcd-supply = <_dc1sw>;
+};
-- 
2.6.2

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[linux-sunxi] [PATCH v4 3/6] mfd: axp20x: Add support for RSB based AXP223 PMIC

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/mfd/Kconfig| 11 ++
 drivers/mfd/Makefile   |  1 +
 drivers/mfd/axp20x-rsb.c   | 93 ++
 drivers/mfd/axp20x.c   |  2 +
 include/linux/mfd/axp20x.h |  1 +
 5 files changed, 108 insertions(+)
 create mode 100644 drivers/mfd/axp20x-rsb.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 804cd3dcce32..13c565103e96 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -107,6 +107,17 @@ config MFD_AXP20X_I2C
  components like regulators or the PEK (Power Enable Key) under the
  corresponding menus.
 
+config MFD_AXP20X_RSB
+   tristate "X-Powers AXP series PMICs with RSB"
+   select MFD_AXP20X
+   depends on SUNXI_RSB
+   help
+ If you say Y here you get support for the X-Powers AXP series power
+ management ICs (PMICs) controlled with RSB.
+ This driver include only the core APIs. You have to select individual
+ components like regulators or the PEK (Power Enable Key) under the
+ corresponding menus.
+
 config MFD_CROS_EC
tristate "ChromeOS Embedded Controller"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a6913007d667..caea6637d5e8 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -108,6 +108,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)+= da9052-spi.o
 obj-$(CONFIG_MFD_DA9052_I2C)   += da9052-i2c.o
 obj-$(CONFIG_MFD_AXP20X)   += axp20x.o
 obj-$(CONFIG_MFD_AXP20X_I2C)   += axp20x-i2c.o
+obj-$(CONFIG_MFD_AXP20X_RSB)   += axp20x-rsb.o
 
 obj-$(CONFIG_MFD_LP3943)   += lp3943.o
 obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
diff --git a/drivers/mfd/axp20x-rsb.c b/drivers/mfd/axp20x-rsb.c
new file mode 100644
index ..3ea0d5db37d0
--- /dev/null
+++ b/drivers/mfd/axp20x-rsb.c
@@ -0,0 +1,93 @@
+/*
+ * axp20x-rsb.c - RSB driver for the X-Powers' Power Management ICs
+ *
+ * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK 
DC-DC
+ * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
+ * as well as configurable GPIOs.
+ *
+ * This driver supports the RSB variants.
+ *
+ * Author: Chen-Yu Tsai <w...@csie.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const struct of_device_id axp20x_rsb_of_match[] = {
+   { .compatible = "x-powers,axp223", .data = (void *) AXP223_ID },
+   { },
+};
+MODULE_DEVICE_TABLE(of, axp20x_rsb_of_match);
+
+static int axp20x_rsb_match_device(struct axp20x_dev *axp20x,
+struct device *dev)
+{
+   const struct of_device_id *of_id;
+
+   of_id = of_match_device(axp20x_rsb_of_match, dev);
+   if (!of_id) {
+   dev_err(dev, "Unable to match OF ID\n");
+   return -ENODEV;
+   }
+   axp20x->variant = (long) of_id->data;
+
+   return axp20x_match_device(axp20x, dev);
+}
+
+static int axp20x_rsb_probe(struct sunxi_rsb_device *rdev)
+{
+   struct axp20x_dev *axp20x;
+   int ret;
+
+   axp20x = devm_kzalloc(>dev, sizeof(*axp20x), GFP_KERNEL);
+   if (!axp20x)
+   return -ENOMEM;
+
+   ret = axp20x_rsb_match_device(axp20x, >dev);
+   if (ret)
+   return ret;
+
+   axp20x->dev = >dev;
+   axp20x->irq = rdev->irq;
+   sunxi_rsb_device_set_drvdata(rdev, axp20x);
+
+   axp20x->regmap = devm_regmap_init_sunxi_rsb(rdev, axp20x->regmap_cfg);
+   if (IS_ERR(axp20x->regmap)) {
+   ret = PTR_ERR(axp20x->regmap);
+   dev_err(>dev, "regmap init failed: %d\n", ret);
+   return ret;
+   }
+
+   return axp20x_device_probe(axp20x);
+}
+
+static int axp20x_rsb_remove(struct sunxi_rsb_device *rdev)
+{
+   struct axp20x_dev *axp20x = sunxi_rsb_device_get_drvdata(rdev);
+
+   return axp20x_device_remove(axp20x);
+}
+
+static struct sunxi_rsb_driver axp20x_rsb_driver = {
+   .driver = {
+   .name   = "axp20x-rsb",
+   .of_match_table = of_match_ptr(axp20x_rsb_of_match),
+   },
+   .probe  = axp20x_rsb_probe,
+   .remove = axp20x_rsb_remove,
+};
+module_sunxi_rsb_driver(axp20x_rsb_driver);
+
+MODULE_DESCRIPTION("PMIC MFD sunXi RSB driver for AXP20X");
+MODULE_AUTHOR("Chen-Yu Tsai <w...@csie.org>");
+MODULE_LICENSE("GPL v2");
diff --git a/drive

[linux-sunxi] [PATCH v4 5/6] ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator nodes

[Chen-Yu Tsai]

This board has a X-Powers AXP223 PMIC connected via RSB. Its regulators
provide power to various parts of the SoC and the board.

Also update the regulator supply phandles.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 79 +-
 1 file changed, 76 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts 
b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index 13ce68f06dd6..91a0fde47fdd 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -68,7 +68,7 @@
 };
 
  {
-   vref-supply = <_vcc3v0>;
+   vref-supply = <_dcdc1>;
status = "okay";
 
button@200 {
@@ -96,7 +96,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin_sina33>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <4>;
cd-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
@@ -106,7 +106,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_8bit_pins>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <8>;
non-removable;
status = "okay";
@@ -132,6 +132,79 @@
 
 _rsb {
status = "okay";
+
+   axp22x: pmic@3e3 {
+   compatible = "x-powers,axp223";
+   reg = <0x3e3>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   eldoin-supply = <_dcdc1>;
+   };
+};
+
+#include "axp22x.dtsi"
+
+_aldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-io";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <235>;
+   regulator-max-microvolt = <265>;
+   regulator-name = "vdd-dll";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <270>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_dc5ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpus";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-3v0";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-sys";
+};
+
+_dcdc3 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpu";
+};
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram";
+};
+
+_rtc_ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-rtc";
 };
 
  {
-- 
2.6.2

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