[Mesa-dev] [PATCH] svga: add some missing SVGA_STATS_* enum values, prefix strings

2017-06-16 Thread Brian Paul 
To fix the build when VMX86_STATS is defined.
Also, some minor whitespace changes to match upstream code.
---
 src/gallium/drivers/svga/svga_winsys.h | 17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_winsys.h 
b/src/gallium/drivers/svga/svga_winsys.h
index 376707d..8b8b45b 100644
--- a/src/gallium/drivers/svga/svga_winsys.h
+++ b/src/gallium/drivers/svga/svga_winsys.h
@@ -35,7 +35,6 @@
 #ifndef SVGA_WINSYS_H_
 #define SVGA_WINSYS_H_
 
-
 #include "svga_types.h"
 #include "svga_reg.h"
 #include "svga3d_reg.h"
@@ -101,6 +100,7 @@ struct svga_winsys_stats_timeframe {
 
 enum svga_stats_count {
SVGA_STATS_COUNT_BLENDSTATE,
+   SVGA_STATS_COUNT_BLITBLITTERCOPY,
SVGA_STATS_COUNT_DEPTHSTENCILSTATE,
SVGA_STATS_COUNT_RASTERIZERSTATE,
SVGA_STATS_COUNT_SAMPLER,
@@ -112,11 +112,16 @@ enum svga_stats_count {
 };
 
 enum svga_stats_time {
+   SVGA_STATS_TIME_BLIT,
+   SVGA_STATS_TIME_BLITBLITTER,
+   SVGA_STATS_TIME_BLITFALLBACK,
SVGA_STATS_TIME_BUFFERSFLUSH,
SVGA_STATS_TIME_BUFFERTRANSFERMAP,
SVGA_STATS_TIME_BUFFERTRANSFERUNMAP,
SVGA_STATS_TIME_CONTEXTFINISH,
SVGA_STATS_TIME_CONTEXTFLUSH,
+   SVGA_STATS_TIME_COPYREGION,
+   SVGA_STATS_TIME_COPYREGIONFALLBACK,
SVGA_STATS_TIME_CREATEBACKEDSURFACEVIEW,
SVGA_STATS_TIME_CREATEBUFFER,
SVGA_STATS_TIME_CREATECONTEXT,
@@ -134,6 +139,7 @@ enum svga_stats_time {
SVGA_STATS_TIME_EMITFS,
SVGA_STATS_TIME_EMITGS,
SVGA_STATS_TIME_EMITVS,
+   SVGA_STATS_TIME_EMULATESURFACEVIEW,
SVGA_STATS_TIME_FENCEFINISH,
SVGA_STATS_TIME_GENERATEINDICES,
SVGA_STATS_TIME_HWTNLDRAWARRAYS,
@@ -165,20 +171,26 @@ enum svga_stats_time {
 
 #define SVGA_STATS_COUNT_NAMES\
SVGA_STATS_PREFIX "BlendState",\
+   SVGA_STATS_PREFIX "BlitBlitterCopy",   \
SVGA_STATS_PREFIX "DepthStencilState", \
SVGA_STATS_PREFIX "RasterizerState",   \
SVGA_STATS_PREFIX "Sampler",   \
SVGA_STATS_PREFIX "SamplerView",   \
SVGA_STATS_PREFIX "SurfaceWriteFlush", \
SVGA_STATS_PREFIX "TextureReadback",   \
-   SVGA_STATS_PREFIX "VertexElement"
+   SVGA_STATS_PREFIX "VertexElement"  \
 
 #define SVGA_STATS_TIME_NAMES   \
+   SVGA_STATS_PREFIX "Blit",\
+   SVGA_STATS_PREFIX "BlitBlitter", \
+   SVGA_STATS_PREFIX "BlitFallback",\
SVGA_STATS_PREFIX "BuffersFlush",\
SVGA_STATS_PREFIX "BufferTransferMap",   \
SVGA_STATS_PREFIX "BufferTransferUnmap", \
SVGA_STATS_PREFIX "ContextFinish",   \
SVGA_STATS_PREFIX "ContextFlush",\
+   SVGA_STATS_PREFIX "CopyRegion",  \
+   SVGA_STATS_PREFIX "CopyRegionFallback",  \
SVGA_STATS_PREFIX "CreateBackedSurfaceView", \
SVGA_STATS_PREFIX "CreateBuffer",\
SVGA_STATS_PREFIX "CreateContext",   \
@@ -196,6 +208,7 @@ enum svga_stats_time {
SVGA_STATS_PREFIX "EmitFS",  \
SVGA_STATS_PREFIX "EmitGS",  \
SVGA_STATS_PREFIX "EmitVS",  \
+   SVGA_STATS_PREFIX "EmulateSurfaceView",  \
SVGA_STATS_PREFIX "FenceFinish", \
SVGA_STATS_PREFIX "GenerateIndices", \
SVGA_STATS_PREFIX "HWtnlDrawArrays", \
-- 
1.9.1

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[Mesa-dev] [Bug 101471] Mesa fails to build: unknown typename bool

2017-06-16 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=101471

--- Comment #1 from Emil Velikov  ---
I've tracked it down and have some patches in which I'm double-checking.
Mind if I Cc you so you can confirm on your end?

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Re: [Mesa-dev] [Mesa-stable] [PATCH] radeonsi: add new polaris12 pci id

2017-06-16 Thread Marek Olšák 
Reviewed-by: Marek Olšák 

It won't make it to 17.0 though, because that doesn't receive any fixes anymore.

Marek

On Fri, Jun 16, 2017 at 6:13 PM, Alex Deucher  wrote:
> Signed-off-by: Alex Deucher 
> Cc: 17.0 17.1 
> ---
>  include/pci_ids/radeonsi_pci_ids.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/include/pci_ids/radeonsi_pci_ids.h 
> b/include/pci_ids/radeonsi_pci_ids.h
> index 50f638f..9453c1c 100644
> --- a/include/pci_ids/radeonsi_pci_ids.h
> +++ b/include/pci_ids/radeonsi_pci_ids.h
> @@ -213,6 +213,7 @@ CHIPSET(0x6985, POLARIS12_, POLARIS12)
>  CHIPSET(0x6986, POLARIS12_, POLARIS12)
>  CHIPSET(0x6987, POLARIS12_, POLARIS12)
>  CHIPSET(0x6995, POLARIS12_, POLARIS12)
> +CHIPSET(0x6997, POLARIS12_, POLARIS12)
>  CHIPSET(0x699F, POLARIS12_, POLARIS12)
>
>  CHIPSET(0x6860, VEGA10_, VEGA10)
> --
> 2.5.5
>
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[Mesa-dev] [PATCH v3 02/10] tgsi/dump: print _PRECISE modifier on Instructions

2017-06-16 Thread Karol Herbst 
Signed-off-by: Karol Herbst 
Reviewed-by: Nicolai Hähnle 
---
 src/gallium/auxiliary/tgsi/tgsi_dump.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_dump.c 
b/src/gallium/auxiliary/tgsi/tgsi_dump.c
index f6eba7424b..b58e64511c 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_dump.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_dump.c
@@ -584,6 +584,10 @@ iter_instruction(
   TXT( "_SAT" );
}
 
+   if (inst->Instruction.Precise) {
+  TXT( "_PRECISE" );
+   }
+
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
   const struct tgsi_full_dst_register *dst = >Dst[i];
 
-- 
2.13.1

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[Mesa-dev] [PATCH v3 07/10] st/glsl_to_tgsi: don't optimize mul+add to mad if expression is precise

2017-06-16 Thread Karol Herbst 
Signed-off-by: Karol Herbst 
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 6cc5a39510..6ac267be94 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -1557,7 +1557,7 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
 
/* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
 */
-   if (ir->operation == ir_binop_add) {
+   if (!this->precise && ir->operation == ir_binop_add) {
   if (try_emit_mad(ir, 1))
  return;
   if (try_emit_mad(ir, 0))
-- 
2.13.1

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[Mesa-dev] [PATCH v3 08/10] nv50/ir: add precise field to Instruction

2017-06-16 Thread Karol Herbst 
Signed-off-by: Karol Herbst 
---
 src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 5c09fed05c..6835c4fa8c 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -884,6 +884,7 @@ public:
unsigned perPatch   : 1;
unsigned exit   : 1; // terminate program after insn
unsigned mask   : 4; // for vector ops
+   unsigned precise: 1; // prevent algebraic optimisations like mul+add to 
mad
 
int8_t postFactor; // MUL/DIV(if < 0) by 1 << postFactor
 
-- 
2.13.1

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[Mesa-dev] [PATCH v3 10/10] nv50/ir: disable mul+add to mad for precise instructions

2017-06-16 Thread Karol Herbst 
fixes
missrendering in TombRaider
KHR-GL44.gpu_shader5.precise_qualifier
KHR-GL45.gpu_shader5.precise_qualifier

Signed-off-by: Karol Herbst 
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 4c92a1efb5..85f3f44832 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1669,6 +1669,10 @@ AlgebraicOpt::handleABS(Instruction *abs)
 bool
 AlgebraicOpt::handleADD(Instruction *add)
 {
+   // we can't optimize to SAD/MAD if the instruction is tagged as precise
+   if (add->precise)
+  return false;
+
Value *src0 = add->getSrc(0);
Value *src1 = add->getSrc(1);
 
@@ -1712,7 +1716,7 @@ AlgebraicOpt::tryADDToMADOrSAD(Instruction *add, 
operation toOp)
   return false;
 
if (src->getInsn()->saturate || src->getInsn()->postFactor ||
-   src->getInsn()->dnz)
+   src->getInsn()->dnz || src->getInsn()->precise)
   return false;
 
if (toOp == OP_SAD) {
-- 
2.13.1

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[Mesa-dev] [PATCH v3 09/10] nv50/ir/tgsi: handle precise for most ALU instructions

2017-06-16 Thread Karol Herbst 
Signed-off-by: Karol Herbst 
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 1264dd4834..c633185893 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -3179,6 +3179,7 @@ Converter::handleInstruction(const struct 
tgsi_full_instruction *insn)
  geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
  if (op == OP_MUL && dstTy == TYPE_F32)
 geni->dnz = info->io.mul_zero_wins;
+ geni->precise = insn->Instruction.Precise;
   }
   break;
case TGSI_OPCODE_MAD:
@@ -3192,6 +3193,7 @@ Converter::handleInstruction(const struct 
tgsi_full_instruction *insn)
  geni = mkOp3(op, dstTy, dst0[c], src0, src1, src2);
  if (dstTy == TYPE_F32)
 geni->dnz = info->io.mul_zero_wins;
+ geni->precise = insn->Instruction.Precise;
   }
   break;
case TGSI_OPCODE_MOV:
-- 
2.13.1

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[Mesa-dev] [PATCH v3 04/10] tgsi: populate precise

2017-06-16 Thread Karol Herbst 
Only implemented for glsl->tgsi. Other converters just set precise to 0.

v2: remove precise paramter from ureg_tex_insn and ureg_memory_insn

Signed-off-by: Karol Herbst 
---
 src/gallium/auxiliary/tgsi/tgsi_build.c   |  3 +++
 src/gallium/auxiliary/tgsi/tgsi_ureg.c|  8 +-
 src/gallium/auxiliary/tgsi/tgsi_ureg.h| 14 ++-
 src/gallium/auxiliary/util/u_simple_shaders.c |  2 +-
 src/gallium/state_trackers/nine/nine_shader.c |  6 ++---
 src/mesa/state_tracker/st_atifs_to_tgsi.c | 36 +--
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp|  6 ++---
 src/mesa/state_tracker/st_mesa_to_tgsi.c  |  6 ++---
 8 files changed, 51 insertions(+), 30 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.c 
b/src/gallium/auxiliary/tgsi/tgsi_build.c
index 55e4d064ed..144a017768 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_build.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_build.c
@@ -651,6 +651,7 @@ tgsi_default_instruction( void )
 static struct tgsi_instruction
 tgsi_build_instruction(unsigned opcode,
unsigned saturate,
+   unsigned precise,
unsigned num_dst_regs,
unsigned num_src_regs,
struct tgsi_header *header)
@@ -665,6 +666,7 @@ tgsi_build_instruction(unsigned opcode,
instruction = tgsi_default_instruction();
instruction.Opcode = opcode;
instruction.Saturate = saturate;
+   instruction.Precise = precise;
instruction.NumDstRegs = num_dst_regs;
instruction.NumSrcRegs = num_src_regs;
 
@@ -1061,6 +1063,7 @@ tgsi_build_full_instruction(
 
*instruction = tgsi_build_instruction(full_inst->Instruction.Opcode,
  full_inst->Instruction.Saturate,
+ full_inst->Instruction.Precise,
  full_inst->Instruction.NumDstRegs,
  full_inst->Instruction.NumSrcRegs,
  header);
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c 
b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
index d2a0507d29..ca31bc4a75 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
@@ -1211,6 +1211,7 @@ struct ureg_emit_insn_result
 ureg_emit_insn(struct ureg_program *ureg,
unsigned opcode,
boolean saturate,
+   unsigned precise,
unsigned num_dst,
unsigned num_src)
 {
@@ -1224,6 +1225,7 @@ ureg_emit_insn(struct ureg_program *ureg,
out[0].insn = tgsi_default_instruction();
out[0].insn.Opcode = opcode;
out[0].insn.Saturate = saturate;
+   out[0].insn.Precise = precise;
out[0].insn.NumDstRegs = num_dst;
out[0].insn.NumSrcRegs = num_src;
 
@@ -1352,7 +1354,8 @@ ureg_insn(struct ureg_program *ureg,
   const struct ureg_dst *dst,
   unsigned nr_dst,
   const struct ureg_src *src,
-  unsigned nr_src )
+  unsigned nr_src,
+  unsigned precise )
 {
struct ureg_emit_insn_result insn;
unsigned i;
@@ -1367,6 +1370,7 @@ ureg_insn(struct ureg_program *ureg,
insn = ureg_emit_insn(ureg,
  opcode,
  saturate,
+ precise,
  nr_dst,
  nr_src);
 
@@ -1404,6 +1408,7 @@ ureg_tex_insn(struct ureg_program *ureg,
insn = ureg_emit_insn(ureg,
  opcode,
  saturate,
+ 0,
  nr_dst,
  nr_src);
 
@@ -1440,6 +1445,7 @@ ureg_memory_insn(struct ureg_program *ureg,
insn = ureg_emit_insn(ureg,
  opcode,
  FALSE,
+ 0,
  nr_dst,
  nr_src);
 
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.h 
b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
index 54f95ba565..ed8c177d51 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
@@ -546,7 +546,8 @@ ureg_insn(struct ureg_program *ureg,
   const struct ureg_dst *dst,
   unsigned nr_dst,
   const struct ureg_src *src,
-  unsigned nr_src );
+  unsigned nr_src,
+  unsigned precise );
 
 
 void
@@ -586,6 +587,7 @@ struct ureg_emit_insn_result
 ureg_emit_insn(struct ureg_program *ureg,
unsigned opcode,
boolean saturate,
+   unsigned precise,
unsigned num_dst,
unsigned num_src);
 
@@ -632,6 +634,7 @@ static inline void ureg_##op( struct ureg_program *ureg )   
\
  opcode,\
  FALSE, \
  0,

[Mesa-dev] [PATCH v3 06/10] gallium/docs: add precise instruction modifier

2017-06-16 Thread Karol Herbst 
Signed-off-by: Karol Herbst 
---
 src/gallium/docs/source/tgsi.rst | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index c65d721dec..76c82b3e88 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -26,7 +26,13 @@ each of the components of *dst*. When this happens, the 
result is said to be
 Modifiers
 ^^^
 
-TGSI supports modifiers on inputs (as well as saturate modifier on 
instructions).
+TGSI supports modifiers on inputs (as well as saturate and precise modifier
+on instructions).
+
+For arithmetic instruction having a precise modifier certain optimizations
+which may alter the result are disallowed. Example: *add(mul(a,b),c)* can't be
+optimized to TGSI_OPCODE_MAD, because some hardware only supports the fused
+MAD instruction.
 
 For inputs which have a floating point type, both absolute value and
 negation modifiers are supported (with absolute value being applied
-- 
2.13.1

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[Mesa-dev] [PATCH v3 05/10] tgsi/text: parse _PRECISE modifier

2017-06-16 Thread Karol Herbst 
v2: use str_match_no_case to fix _SAT_PRECISE detection

Signed-off-by: Karol Herbst 
---
 src/gallium/auxiliary/tgsi/tgsi_text.c | 17 ++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c 
b/src/gallium/auxiliary/tgsi/tgsi_text.c
index 93a05568f4..70ec0e4bc9 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_text.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_text.c
@@ -999,6 +999,7 @@ parse_texoffset_operand(
 static boolean
 match_inst(const char **pcur,
unsigned *saturate,
+   unsigned *precise,
const struct tgsi_opcode_info *info)
 {
const char *cur = *pcur;
@@ -1007,16 +1008,24 @@ match_inst(const char **pcur,
if (str_match_nocase_whole(, info->mnemonic)) {
   *pcur = cur;
   *saturate = 0;
+  *precise = 0;
   return TRUE;
}
 
if (str_match_no_case(, info->mnemonic)) {
   /* the instruction has a suffix, figure it out */
-  if (str_match_nocase_whole(, "_SAT")) {
+  if (str_match_no_case(, "_SAT")) {
  *pcur = cur;
  *saturate = 1;
- return TRUE;
   }
+
+  if (str_match_no_case(, "_PRECISE")) {
+ *pcur = cur;
+ *precise = 1;
+  }
+
+  if (*precise || *saturate)
+ return TRUE;
}
 
return FALSE;
@@ -1029,6 +1038,7 @@ parse_instruction(
 {
uint i;
uint saturate = 0;
+   uint precise = 0;
const struct tgsi_opcode_info *info;
struct tgsi_full_instruction inst;
const char *cur;
@@ -1043,7 +1053,7 @@ parse_instruction(
   cur = ctx->cur;
 
   info = tgsi_get_opcode_info( i );
-  if (match_inst(, , info)) {
+  if (match_inst(, , , info)) {
  if (info->num_dst + info->num_src + info->is_tex == 0) {
 ctx->cur = cur;
 break;
@@ -1064,6 +1074,7 @@ parse_instruction(
 
inst.Instruction.Opcode = i;
inst.Instruction.Saturate = saturate;
+   inst.Instruction.Precise = precise;
inst.Instruction.NumDstRegs = info->num_dst;
inst.Instruction.NumSrcRegs = info->num_src;
 
-- 
2.13.1

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[Mesa-dev] [PATCH v3 03/10] st/glsl_to_tgsi: handle precise modifier

2017-06-16 Thread Karol Herbst 
all subexpression inside an ir_assignment needs to be tagged as precise.

v2: make precise handling more global inside the visitor

Signed-off-by: Karol Herbst 
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 24d417d670..ce092347c3 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -87,6 +87,13 @@ static int swizzle_for_type(const glsl_type *type, int 
component = 0)
return swizzle;
 }
 
+static unsigned is_precise(const ir_variable *ir)
+{
+   if (!ir)
+  return 0;
+   return ir->data.precise || ir->data.invariant;
+}
+
 /**
  * This struct is a corresponding struct to TGSI ureg_src.
  */
@@ -296,6 +303,7 @@ public:
ir_instruction *ir;
 
unsigned op:8; /**< TGSI opcode */
+   unsigned precise:1;
unsigned saturate:1;
unsigned is_64bit_expanded:1;
unsigned sampler_base:5;
@@ -435,6 +443,7 @@ public:
bool have_fma;
bool use_shared_memory;
bool has_tex_txf_lz;
+   bool precise;
 
variable_storage *find_variable_storage(ir_variable *var);
 
@@ -691,6 +700,7 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned 
op,
STATIC_ASSERT(TGSI_OPCODE_LAST <= 255);
 
inst->op = op;
+   inst->precise = this->precise;
inst->info = tgsi_get_opcode_info(op);
inst->dst[0] = dst;
inst->dst[1] = dst1;
@@ -3147,6 +3157,8 @@ glsl_to_tgsi_visitor::visit(ir_assignment *ir)
st_dst_reg l;
st_src_reg r;
 
+   /* all generated instructions need to be flaged as precise */
+   this->precise = is_precise(ir->lhs->variable_referenced());
ir->rhs->accept(this);
r = this->result;
 
@@ -3238,6 +3250,7 @@ glsl_to_tgsi_visitor::visit(ir_assignment *ir)
} else {
   emit_block_mov(ir, ir->rhs->type, , , NULL, false);
}
+   this->precise = 0;
 }
 
 
-- 
2.13.1

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[Mesa-dev] [PATCH v3 01/10] tgsi: add precise flag to tgsi_instruction

2017-06-16 Thread Karol Herbst 
Signed-off-by: Karol Herbst 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Roland Scheidegger 
---
 src/gallium/auxiliary/tgsi/tgsi_build.c| 1 +
 src/gallium/include/pipe/p_shader_tokens.h | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.c 
b/src/gallium/auxiliary/tgsi/tgsi_build.c
index 00843241f8..55e4d064ed 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_build.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_build.c
@@ -642,6 +642,7 @@ tgsi_default_instruction( void )
instruction.Label = 0;
instruction.Texture = 0;
instruction.Memory = 0;
+   instruction.Precise = 0;
instruction.Padding = 0;
 
return instruction;
diff --git a/src/gallium/include/pipe/p_shader_tokens.h 
b/src/gallium/include/pipe/p_shader_tokens.h
index 1e08d97329..aa0fb3e3b3 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -638,7 +638,8 @@ struct tgsi_instruction
unsigned Label  : 1;
unsigned Texture: 1;
unsigned Memory : 1;
-   unsigned Padding: 2;
+   unsigned Precise: 1;
+   unsigned Padding: 1;
 };
 
 /*
-- 
2.13.1

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[Mesa-dev] [PATCH v3 00/10] Add precise/invariant semantics to TGSI

2017-06-16 Thread Karol Herbst 
Running Tomb Raider on Nouveau I found some flicker caused by ignoring precise
modifiers on variables inside Nouveau.

This series add precise/invariant handling to TGSI, which can be then used by
drivers to disable certain unsafe optimisations which may otherwise alter
calculations, which depend on having the same result across shaders.

This series fixes this bug in Tomb Raider and one CTS test for 4.4 and 4.5

No piglit regression on my nve6

Changes since v2:
* documentation for precise modifier
* disable TGSI MAD peephole for precise instructions
* drop MAD split patch in nv50ir

Karol Herbst (10):
  tgsi: add precise flag to tgsi_instruction
  tgsi/dump: print _PRECISE modifier on Instructions
  st/glsl_to_tgsi: handle precise modifier
  tgsi: populate precise
  tgsi/text: parse _PRECISE modifier
  gallium/docs: add precise instruction modifier
  st/glsl_to_tgsi: don't optimize mul+add to mad if expression is
precise
  nv50/ir: add precise field to Instruction
  nv50/ir/tgsi: handle precise for most ALU instructions
  nv50/ir: disable mul+add to mad for precise instructions

 src/gallium/auxiliary/tgsi/tgsi_build.c|  4 +++
 src/gallium/auxiliary/tgsi/tgsi_dump.c |  4 +++
 src/gallium/auxiliary/tgsi/tgsi_text.c | 17 --
 src/gallium/auxiliary/tgsi/tgsi_ureg.c |  8 -
 src/gallium/auxiliary/tgsi/tgsi_ureg.h | 14 -
 src/gallium/auxiliary/util/u_simple_shaders.c  |  2 +-
 src/gallium/docs/source/tgsi.rst   |  8 -
 src/gallium/drivers/nouveau/codegen/nv50_ir.h  |  1 +
 .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp  |  2 ++
 .../drivers/nouveau/codegen/nv50_ir_peephole.cpp   |  6 +++-
 src/gallium/include/pipe/p_shader_tokens.h |  3 +-
 src/gallium/state_trackers/nine/nine_shader.c  |  6 ++--
 src/mesa/state_tracker/st_atifs_to_tgsi.c  | 36 +++---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 21 ++---
 src/mesa/state_tracker/st_mesa_to_tgsi.c   |  6 ++--
 15 files changed, 101 insertions(+), 37 deletions(-)

-- 
2.13.1

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[Mesa-dev] [Bug 101471] Mesa fails to build: unknown typename bool

2017-06-16 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=101471

Bug ID: 101471
   Summary: Mesa fails to build: unknown typename bool
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: gr.mue...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org

In file included from common/ac_surface.c:31:0:
common/ac_gpu_info.h:57:2: Fehler: unbekannter Typname: »bool«
  boolhas_dedicated_vram;
  ^~~~
common/ac_gpu_info.h:58:2: Fehler: unbekannter Typname: »bool«
  boolhas_virtual_memory;
  ^~~~
common/ac_gpu_info.h:59:2: Fehler: unbekannter Typname: »bool«
  boolgfx_ib_pad_with_type2;
  ^~~~
common/ac_gpu_info.h:60:2: Fehler: unbekannter Typname: »bool«
  boolhas_hw_decode;
  ^~~~
common/ac_gpu_info.h:76:2: Fehler: unbekannter Typname: »bool«
  boolhas_userptr;
  ^~~~
common/ac_gpu_info.h:89:2: Fehler: unbekannter Typname: »bool«
  boolr600_gb_backend_map_valid;
  ^~~~
common/ac_gpu_info.h:101:1: Fehler: Unbekannter Typname »bool«; meinten Sie
»_Bool«?
 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 ^~~~
 _Bool
In file included from common/ac_surface.c:38:0:
/usr/include/libdrm/amdgpu.h:107:31: Fehler: In Konflikt stehende Typen für
»amdgpu_device_handle«
 typedef struct amdgpu_device *amdgpu_device_handle;
   ^~~~
In file included from common/ac_surface.c:31:0:
common/ac_gpu_info.h:36:16: Anmerkung: Vorherige Deklaration von
»amdgpu_device_handle« war hier
 typedef void * amdgpu_device_handle;
^~~~
make[4]: *** [Makefile:944: common/common_libamd_common_la-ac_surface.lo]
Fehler 1
make[4]: *** Es wird auf noch nicht beendete Prozesse gewartet
ar: `u' modifier ignored since `D' is the default (see `U')
In file included from common/ac_gpu_info.c:26:0:
common/ac_gpu_info.h:41:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tpci_domain;
  ^~~~
common/ac_gpu_info.h:42:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tpci_bus;
  ^~~~
common/ac_gpu_info.h:43:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tpci_dev;
  ^~~~
common/ac_gpu_info.h:44:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tpci_func;
  ^~~~
common/ac_gpu_info.h:47:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tpci_id;
  ^~~~
common/ac_gpu_info.h:50:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tpte_fragment_size;
  ^~~~
common/ac_gpu_info.h:51:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tgart_page_size;
  ^~~~
common/ac_gpu_info.h:52:2: Fehler: unbekannter Typname: »uint64_t«
  uint64_tgart_size;
  ^~~~
common/ac_gpu_info.h:53:2: Fehler: unbekannter Typname: »uint64_t«
  uint64_tvram_size;
  ^~~~
common/ac_gpu_info.h:54:2: Fehler: unbekannter Typname: »uint64_t«
  uint64_tvram_vis_size;
  ^~~~
common/ac_gpu_info.h:55:2: Fehler: unbekannter Typname: »uint64_t«
  uint64_tmax_alloc_size;
  ^~~~
common/ac_gpu_info.h:56:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tmin_alloc_size;
  ^~~~
common/ac_gpu_info.h:57:2: Fehler: unbekannter Typname: »bool«
  boolhas_dedicated_vram;
  ^~~~
common/ac_gpu_info.h:58:2: Fehler: unbekannter Typname: »bool«
  boolhas_virtual_memory;
  ^~~~
common/ac_gpu_info.h:59:2: Fehler: unbekannter Typname: »bool«
  boolgfx_ib_pad_with_type2;
  ^~~~
common/ac_gpu_info.h:60:2: Fehler: unbekannter Typname: »bool«
  boolhas_hw_decode;
  ^~~~
common/ac_gpu_info.h:61:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tnum_sdma_rings;
  ^~~~
common/ac_gpu_info.h:62:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tnum_compute_rings;
  ^~~~
common/ac_gpu_info.h:63:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tuvd_fw_version;
  ^~~~
common/ac_gpu_info.h:64:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tvce_fw_version;
  ^~~~
common/ac_gpu_info.h:65:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tme_fw_version;
  ^~~~
common/ac_gpu_info.h:66:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tpfp_fw_version;
  ^~~~
common/ac_gpu_info.h:67:2: Fehler: unbekannter Typname: »uint32_t«
  uint32_tce_fw_version;
  ^~~~
common/ac_gpu_info.h:68:2: Fehler: unbekannter Typname:

Re: [Mesa-dev] [PATCH 11/15] i965: Add isl based miptree creator

2017-06-16 Thread Jason Ekstrand 
On Fri, Jun 16, 2017 at 11:11 AM, Nanley Chery 
wrote:

> On Tue, Jun 13, 2017 at 05:50:09PM +0300, Topi Pohjolainen wrote:
> > Signed-off-by: Topi Pohjolainen 
> > ---
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 76
> +++
> >  1 file changed, 76 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > index 212dfa30ec..0854b4eb5d 100644
> > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > @@ -643,6 +643,82 @@ free_aux_state_map(enum isl_aux_state **state)
> >  }
> >
> >  static struct intel_mipmap_tree *
> > +make_surface(struct brw_context *brw, GLenum target, mesa_format format,
> > + unsigned first_level, unsigned last_level,
> > + unsigned width0, unsigned height0, unsigned depth0,
> > + unsigned num_samples, enum isl_tiling isl_tiling,
> > + isl_surf_usage_flags_t isl_usage_flags, uint32_t
> alloc_flags,
> > + struct brw_bo *bo)
> ^
> const ?
>

No.  For one thing, I'm fairly sure that, at least in the future, we'll
need to be able to modify the bo->is_scanout flag.  More importantly,
however, this is creating a mutable miptree which means that what it
returns provides a way of changing the contents of the BO so making the BO
const is a lie.


> > +{
> > +   struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
> > +   if (!mt)
> > +  return NULL;
> > +
> > +   if (!create_mapping_table(target, first_level, last_level, depth0,
> > + mt->level)) {
> > +  free(mt);
> > +  return NULL;
> > +   }
> > +
> > +   if (target == GL_TEXTURE_CUBE_MAP ||
> > +   target == GL_TEXTURE_CUBE_MAP_ARRAY)
> > +  isl_usage_flags |= ISL_SURF_USAGE_CUBE_BIT;
> > +
> > +   DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
> > +__func__,
> > +   _mesa_enum_to_string(target),
> > +   _mesa_get_format_name(format),
> > +   num_samples, width0, height0, depth0,
> > +   first_level, last_level, mt);
> > +
> > +   struct isl_surf_init_info init_info = {
> > +  .dim = get_isl_surf_dim(target),
> > +  .format = translate_tex_format(brw, format, false),
> > +  .width = width0,
> > +  .height = height0,
> > +  .depth = target == GL_TEXTURE_3D ? depth0 : 1,
> > +  .levels = last_level - first_level + 1,
> > +  .array_len = target == GL_TEXTURE_3D ? 1 : depth0,
> > +  .samples = MAX2(num_samples, 1),
> > +  .usage = isl_usage_flags,
> > +  .tiling_flags = 1u << isl_tiling
> > +   };
> > +
> > +   if (!isl_surf_init_s(>isl_dev, >surf, _info))
> > +  goto fail;
> > +
> > +   assert(mt->surf.size % mt->surf.row_pitch == 0);
> > +
> > +   if (!bo) {
> > +  unsigned pitch = mt->surf.row_pitch;
> ^
> MAYBE_UNUSED for release builds?
>

I think it's probably ok since it's passed in to brw_bo_alloc_tiled.  Then
again, I'm pretty sure topi has rebased on top of the new
brw_bo_alloc_tiled which gets rid of all this nonsense.


> This patch is
> Reviewed-by: Nanley Chery 
>
> I've taken a brief skim at the rest of the patches and it all looks
> good. Given that the rest of the series has already been reviewed, I
> think I'll stop here.
>
> Cheers,
> Nanley
>
> > +  mt->bo = brw_bo_alloc_tiled(brw->bufmgr, "isl-miptree",
> > +  mt->surf.row_pitch,
> > +  mt->surf.size / mt->surf.row_pitch,
> > +  1, isl_tiling_to_bufmgr_tiling(
> isl_tiling),
> > +  , alloc_flags);
> > +  if (!mt->bo)
> > + goto fail;
> > +
> > +  assert(pitch == mt->surf.row_pitch);
> > +   } else {
> > +  mt->bo = bo;
> > +   }
> > +
> > +   mt->first_level = first_level;
> > +   mt->last_level = last_level;
> > +   mt->target = target;
> > +   mt->format = format;
> > +   mt->refcount = 1;
> > +   mt->aux_state = NULL;
> > +
> > +   return mt;
> > +
> > +fail:
> > +   intel_miptree_release();
> > +   return NULL;
> > +}
> > +
> > +static struct intel_mipmap_tree *
> >  miptree_create(struct brw_context *brw,
> > GLenum target,
> > mesa_format format,
> > --
> > 2.11.0
> >
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Re: [Mesa-dev] [PATCH v2] swr: Don't crash when encountering a VBO with stride = 0.

2017-06-16 Thread Rowley, Timothy O 
Reviewed-by: Tim Rowley 
>

On Jun 15, 2017, at 11:24 AM, Bruce Cherniak 
> wrote:

The swr driver uses vertex_buffer->stride to determine the number
of elements in a VBO. A recent change to the state-tracker made it
possible for VBO's with stride=0. This resulted in a divide by zero
crash in the driver. The solution is to use the pre-calculated vertex
element stream_pitch in this case.

This patch fixes the crash in a number of piglit and VTK tests introduced
by 17f776c27be266f2.

There are several VTK tests that still crash and need proper handling of
vertex_buffer_index.  This will come in a follow-on patch.

v2: Correctly update all parameters for VBO constants (stride = 0).
   Also fixes the remaining crashes/regressions that v1 did
   not address, without touching vertex_buffer_index.
---
src/gallium/drivers/swr/swr_state.cpp | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/swr/swr_state.cpp 
b/src/gallium/drivers/swr/swr_state.cpp
index 08549e51a1..316872581d 100644
--- a/src/gallium/drivers/swr/swr_state.cpp
+++ b/src/gallium/drivers/swr/swr_state.cpp
@@ -1247,13 +1247,24 @@ swr_update_derived(struct pipe_context *pipe,

 pitch = vb->stride;
 if (!vb->is_user_buffer) {
-/* VBO
- * size is based on buffer->width0 rather than info.max_index
- * to prevent having to validate VBO on each draw */
-size = vb->buffer.resource->width0;
-elems = size / pitch;
-partial_inbounds = size % pitch;
-min_vertex_index = 0;
+/* VBO */
+if (!pitch) {
+   /* If pitch=0 (ie vb->stride), buffer contains a single
+* constant attribute.  Use the stream_pitch which was
+* calculated during creation of vertex_elements_state for the
+* size of the attribute. */
+   size = ctx->velems->stream_pitch[i];
+   elems = 1;
+   partial_inbounds = 0;
+   min_vertex_index = 0;
+} else {
+   /* size is based on buffer->width0 rather than info.max_index
+* to prevent having to validate VBO on each draw. */
+   size = vb->buffer.resource->width0;
+   elems = size / pitch;
+   partial_inbounds = size % pitch;
+   min_vertex_index = 0;
+}

p_data = swr_resource_data(vb->buffer.resource) + vb->buffer_offset;
 } else {
--
2.11.0

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Re: [Mesa-dev] [RFC 13/22] RFC: vulkan: Update registry for MESAX dma_buf extensions

2017-06-16 Thread Chad Versace 
On Fri 16 Jun 2017, Emil Velikov wrote:
> Hi gents,
> 
> On 8 June 2017 at 19:44, Daniel Stone  wrote:
> 
> >   - VK_MESAX_external_memory_dma_buf
> >   - VK_MESAX_external_image_dma_buf
> Perhaps not so crazy idea:
> 
> Considering a handful of the people involved (Collabora, Google,
> Intel) are Khronos members, it should be possible to have the
> extensions as EXT as opposed to MESA. Just something to consider as
> the extensions are going through the process.

I raised the topic in Khronos when I began the work. The consensus was
that the initial extensions, which are dependent on KHX, should be
prefixed with MESAX. When the final extensions arrive, which would be
based on VK_KHR_external_* instead of VK_KHX_external_*, it would be
good to rename them at that time with s/MESAX/EXT/.
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Re: [Mesa-dev] [PATCH 0/6] i965: Add RGBX, RGBA configs, even on gen9

2017-06-16 Thread Chad Versace 
On Thu 15 Jun 2017, Rob Herring wrote:
> On Tue, Jun 13, 2017 at 1:55 PM, Chad Versace  
> wrote:
> > On Fri 09 Jun 2017, Tapani Pälli wrote:
> >>
> >>
> >> On 06/08/2017 09:27 PM, Chad Versace wrote:
> >> > On Thu 08 Jun 2017, Tomasz Figa wrote:
> >> > > On Thu, Jun 8, 2017 at 4:08 PM, Tapani Pälli  
> >> > > wrote:
> >> > > >
> >> > > > On 06/08/2017 09:36 AM, Tapani Pälli wrote:
> >> > > > >
> >> > > > >
> >> > > > >
> >> > > > > On 06/08/2017 06:05 AM, Tomasz Figa wrote:
> >> > > > > >
> >> > > > > > On Wed, Jun 7, 2017 at 5:36 AM, Chad Versace 
> >> > > > > > 
> >> > > > > > wrote:
> >> > > > > > >
> >> > > > > > > More patches to break your formats... again ;)
> >> > > > > > >
> >> > > > > > > The Android framework requires support for EGLConfigs with
> >> > > > > > > HAL_PIXEL_FORMAT_RGBX_ and HAL_PIXEL_FORMAT_RGBA_. 
> >> > > > > > > This prevents
> >> > > > > > > Chrome OS from updating its Android drivers, because earlier 
> >> > > > > > > this year
> >> > > > > > > Intel disabled all rgbx formats for gen >=9 in 
> >> > > > > > > brw_surface_formats.c.
> >> > > > > > > This patch series safely (hopefully?) fixes that problem.
> >> > > > > > >
> >> > > > > > > If you want the meat, read patches 2 and 6.
> >> > > > > > >
> >> > > > > > > Chad Versace (6):
> >> > > > > > > mesa: Add _mesa_format_fallback_rgba_to_rgbx()
> >> > > > > > > i965: Add a RGBX->RGBA fallback for 
> >> > > > > > > glEGLImageTextureTarget2D()
> >> > > > > > > i965: Rename some vague format members of brw_context
> >> > > > > > > i965/dri: Add intel_screen param to 
> >> > > > > > > intel_create_winsys_renderbuffer
> >> > > > > > > i965: Move brw_context format arrays to intel_screen
> >> > > > > > > i965/dri: Support R8G8B8A8 and R8G8B8X8 configs
> >> > > > > >
> >> > > > > >
> >> > > > > > Thanks a lot Chad!
> >> > > > > >
> >> > > > > > Just to make sure, did you have a chance to test it with X11 
> >> > > > > > apps,
> >> > > > > > that were reported to have incorrect colors last time we tried
> >> > > > > > enabling these formats? I.e.
> >> > > > > > https://bugs.freedesktop.org/show_bug.cgi?id=95071
> >> >
> >> > tfiga, I only tested with glxgears. To be safe, I'll also test the KDE
> >> > apps in that bug report and reply back with the results.
> >> >
> >> > > > > I just tested this set on Android and I'm getting wrong colors 
> >> > > > > with this,
> >> > > > > red and blue swapped.
> >> >
> >> > Uh oh.
> >> >
> >> > I did something dumb. When testing this on ARC++, I chose
> >> > a BLACK-AND-WHITE game! I'll retest with a color game.
> >>
> >> It was pretty hard to keep coffee in mouth when reading this comment.
> >>
> >> > https://play.google.com/store/apps/details?id=com.ZephirothGames.AsteroidStormFREE=en
> >> >
> >> > > > I can 'fix' this by reordering the configs in 
> >> > > > intel_screen_make_configs so
> >> > > > that the new configs (RGBA, RGBX) required by Android are before the 
> >> > > > old
> >> > > > ones (BGRA, BGRX).
> >> > >
> >> > > I think that would have exactly the opposite effect on the X11 apps I
> >> > > mentioned before. In my testing, they were sensitive to the order of
> >> > > configs, due to component bit masks not being considered in selection,
> >> > > only bit depths.
> >> >
> >> > Yes.
> >> >
> >> > > However, for Android, I thought EGL already used bit masks, so
> >> > > possibly there is still an unrelated bug somewhere.
> >> >
> >> > Android certainly inspects the channel masks, using dri2_add_config().
> >> > So I'm also curious why Tapani sees swapped channels. The
> >> > platform_android.c is patched with format hacks, and I assume the same
> >> > is true for android-ia. Maybe the hacks are intefering somehow. I'll
> >> > investigate.
> >>
> >> We shouldn't have related 'hacks', but here are some changes that might be
> >> interesting or somehow related:
> >>
> >> add EGL_ALPHA_SIZE attrib:
> >>
> >> https://github.com/android-ia/frameworks-native/commit/8237c9f8eb36d4f9ead40c8cb4a68ae9518d3c9f
> >>
> >> sorting display configs:
> >>
> >> https://github.com/android-ia/frameworks-native/pull/2/commits/bb29af0777e747effacd239565f52aad96c45558
> >>
> >> visuals being added:
> >>
> >> https://github.com/android-ia/external-mesa/commit/ceac31ff7e53ec5034bc379d37ce365c000e9e4a
> >
> > I confirmed that this series causes no regressions with Gnome and KDE
> > apps. For KDE, I used Amarok as the test app. To prove to myself
> > I *really* was testing this series, I tested the series with the new
> > formats placed at the end of the array, and then I tested again with the new
> > formats placed at the start of the array. As expected, Amarok's colors
> > were correct in the first test, and were wrong in the second test (blue
> > and red were swapped.
> >
> > I still haven't succeeded in fully testing these patches against
> > Android, for a combination of technical and

Re: [Mesa-dev] [PATCH 00/16] swr: rasterizer update

2017-06-16 Thread Cherniak, Bruce 
Reviewed-by: Bruce Cherniak  

> On Jun 15, 2017, at 1:37 PM, Tim Rowley  wrote:
> 
> Highlights include: jit cache (disabled currently), work in progress
> to shrink the vertex structure used in the frontend, and refactoring
> to speed recompiles if simdintrin.h is changed.
> 
> Tim Rowley (16):
>  swr/rast: Implement JIT shader caching to disk
>  swr/rast: Fix invalid 16-bit format traits for A1R5G5B5
>  swr/rast: Remove explicit primitive id slot in the vertex layout
>  swr/rast: Rework attribute layout
>  swr/rast: Add support to PA for variable sized vertices
>  swr/rast: SIMD16 FE - improve calcDeterminantIntVertical
>  swr/rast: Add support for dynamic vertex size for VS output
>  swr/rast: Share vertex memory between VS input/output
>  swr/rast: fix early z / query interaction
>  swr/rast: Properly size GS stage scratch space
>  swr/rast: gen_llvm_types.py support for SIMD256/SIMD512
>  swr/rast: Don't transition hottile resolved --> dirty during store
>tiles
>  swr/rast: Adjust cast for gcc warning
>  swr/rast: Fix read-back of render target array index
>  swr/rast: Refactor includes to limit simdintrin.h usage
>  swr/rast: Fix read-back of viewport array index
> 
> src/gallium/drivers/swr/Makefile.sources   |   3 +
> .../swr/rasterizer/codegen/gen_llvm_types.py   |  12 +-
> .../drivers/swr/rasterizer/codegen/knob_defs.py|  17 +-
> .../swr/rasterizer/codegen/templates/gen_knobs.cpp |  64 +-
> src/gallium/drivers/swr/rasterizer/common/intrin.h | 169 
> .../drivers/swr/rasterizer/common/simd16intrin.h   |  52 --
> .../drivers/swr/rasterizer/common/simdintrin.h |  87 +-
> src/gallium/drivers/swr/rasterizer/core/api.cpp|   4 +-
> src/gallium/drivers/swr/rasterizer/core/api.h  |   2 +-
> .../drivers/swr/rasterizer/core/backend.cpp|   9 +-
> src/gallium/drivers/swr/rasterizer/core/backend.h  |   1 -
> src/gallium/drivers/swr/rasterizer/core/binner.cpp | 201 +++--
> src/gallium/drivers/swr/rasterizer/core/clip.cpp   |  24 +-
> src/gallium/drivers/swr/rasterizer/core/clip.h |  67 +-
> src/gallium/drivers/swr/rasterizer/core/context.h  |   7 +-
> src/gallium/drivers/swr/rasterizer/core/fifo.hpp   |   4 +-
> .../drivers/swr/rasterizer/core/format_traits.h|   2 +-
> .../drivers/swr/rasterizer/core/format_types.h | 149 ++--
> .../drivers/swr/rasterizer/core/format_utils.h | 882 
> .../drivers/swr/rasterizer/core/frontend.cpp   | 121 +--
> src/gallium/drivers/swr/rasterizer/core/frontend.h |  41 +-
> .../drivers/swr/rasterizer/core/multisample.h  |  10 +-
> src/gallium/drivers/swr/rasterizer/core/pa.h   |  50 +-
> src/gallium/drivers/swr/rasterizer/core/pa_avx.cpp |   3 +-
> src/gallium/drivers/swr/rasterizer/core/state.h|  91 +-
> .../drivers/swr/rasterizer/core/state_funcs.h  |  68 ++
> src/gallium/drivers/swr/rasterizer/core/utils.h| 919 +
> .../drivers/swr/rasterizer/jitter/JitManager.cpp   | 219 -
> .../drivers/swr/rasterizer/jitter/JitManager.h |  29 +
> .../drivers/swr/rasterizer/jitter/blend_jit.cpp|   7 +-
> .../drivers/swr/rasterizer/jitter/fetch_jit.cpp|   6 +-
> .../drivers/swr/rasterizer/jitter/jit_api.h|   1 +
> .../swr/rasterizer/jitter/streamout_jit.cpp|   6 +-
> src/gallium/drivers/swr/swr_draw.cpp   |   4 +
> src/gallium/drivers/swr/swr_shader.cpp | 102 ++-
> src/gallium/drivers/swr/swr_state.cpp  |  29 +-
> 36 files changed, 1966 insertions(+), 1496 deletions(-)
> create mode 100644 src/gallium/drivers/swr/rasterizer/common/intrin.h
> create mode 100644 src/gallium/drivers/swr/rasterizer/core/format_utils.h
> create mode 100644 src/gallium/drivers/swr/rasterizer/core/state_funcs.h
> 
> -- 
> 2.7.4
> 
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[Mesa-dev] [PATCH] ac: add missing stdint.h include for uint32_t

2017-06-16 Thread Emil Velikov 
From: Emil Velikov 

Cc: Mark Janes 
Signed-off-by: Emil Velikov 
---
 src/amd/common/ac_gpu_info.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index a72ab58f9a3..69e9d2828f5 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -26,6 +26,7 @@
 #ifndef AC_GPU_INFO_H
 #define AC_GPU_INFO_H
 
+#include 
 #include "amd_family.h"
 
 #ifdef __cplusplus
-- 
2.13.0

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Re: [Mesa-dev] [PATCH 11/15] i965: Add isl based miptree creator

2017-06-16 Thread Nanley Chery 
On Tue, Jun 13, 2017 at 05:50:09PM +0300, Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 76 
> +++
>  1 file changed, 76 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 212dfa30ec..0854b4eb5d 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -643,6 +643,82 @@ free_aux_state_map(enum isl_aux_state **state)
>  }
>  
>  static struct intel_mipmap_tree *
> +make_surface(struct brw_context *brw, GLenum target, mesa_format format,
> + unsigned first_level, unsigned last_level,
> + unsigned width0, unsigned height0, unsigned depth0,
> + unsigned num_samples, enum isl_tiling isl_tiling,
> + isl_surf_usage_flags_t isl_usage_flags, uint32_t alloc_flags,
> + struct brw_bo *bo)
^
const ?

> +{
> +   struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
> +   if (!mt)
> +  return NULL;
> +
> +   if (!create_mapping_table(target, first_level, last_level, depth0,
> + mt->level)) {
> +  free(mt);
> +  return NULL;
> +   }
> +
> +   if (target == GL_TEXTURE_CUBE_MAP ||
> +   target == GL_TEXTURE_CUBE_MAP_ARRAY)
> +  isl_usage_flags |= ISL_SURF_USAGE_CUBE_BIT;
> +
> +   DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
> +__func__,
> +   _mesa_enum_to_string(target),
> +   _mesa_get_format_name(format),
> +   num_samples, width0, height0, depth0,
> +   first_level, last_level, mt);
> +
> +   struct isl_surf_init_info init_info = {
> +  .dim = get_isl_surf_dim(target),
> +  .format = translate_tex_format(brw, format, false),
> +  .width = width0,
> +  .height = height0,
> +  .depth = target == GL_TEXTURE_3D ? depth0 : 1,
> +  .levels = last_level - first_level + 1,
> +  .array_len = target == GL_TEXTURE_3D ? 1 : depth0,
> +  .samples = MAX2(num_samples, 1),
> +  .usage = isl_usage_flags, 
> +  .tiling_flags = 1u << isl_tiling
> +   };
> +
> +   if (!isl_surf_init_s(>isl_dev, >surf, _info))
> +  goto fail;
> +
> +   assert(mt->surf.size % mt->surf.row_pitch == 0);
> +
> +   if (!bo) {
> +  unsigned pitch = mt->surf.row_pitch;
^
MAYBE_UNUSED for release builds?

This patch is
Reviewed-by: Nanley Chery 

I've taken a brief skim at the rest of the patches and it all looks
good. Given that the rest of the series has already been reviewed, I
think I'll stop here.

Cheers,
Nanley

> +  mt->bo = brw_bo_alloc_tiled(brw->bufmgr, "isl-miptree",
> +  mt->surf.row_pitch,
> +  mt->surf.size / mt->surf.row_pitch,
> +  1, isl_tiling_to_bufmgr_tiling(isl_tiling),
> +  , alloc_flags);
> +  if (!mt->bo)
> + goto fail;
> +
> +  assert(pitch == mt->surf.row_pitch);
> +   } else {
> +  mt->bo = bo;
> +   }
> +
> +   mt->first_level = first_level;
> +   mt->last_level = last_level;
> +   mt->target = target;
> +   mt->format = format;
> +   mt->refcount = 1;
> +   mt->aux_state = NULL;
> +
> +   return mt;
> +
> +fail:
> +   intel_miptree_release();
> +   return NULL;
> +}
> +
> +static struct intel_mipmap_tree *
>  miptree_create(struct brw_context *brw,
> GLenum target,
> mesa_format format,
> -- 
> 2.11.0
> 
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Re: [Mesa-dev] [PATCH 05/11] gbm: Pull out FourCC <-> DRIimage format table

2017-06-16 Thread Eric Engestrom 
On Friday, 2017-06-16 18:14:28 +0100, Daniel Stone wrote:
> Rather than duplicated (yet asymmetric) open-coded tables, pull them out
> to a common structure.
> 
> Signed-off-by: Daniel Stone 
> ---
>  src/gbm/Makefile.am|   1 +
>  src/gbm/backends/dri/gbm_dri.c | 105 
> ++---
>  2 files changed, 46 insertions(+), 60 deletions(-)
> 
> diff --git a/src/gbm/Makefile.am b/src/gbm/Makefile.am
> index 60b0924506..de8396000b 100644
> --- a/src/gbm/Makefile.am
> +++ b/src/gbm/Makefile.am
> @@ -5,6 +5,7 @@ pkgconfig_DATA = main/gbm.pc
>  
>  AM_CFLAGS = \
>   -I$(top_srcdir)/include \
> + -I$(top_srcdir)/src \
>   -I$(top_srcdir)/src/loader \
>   -I$(top_srcdir)/src/gbm/main \
>   $(DLOPEN_CFLAGS) \
> diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
> index 84f37d4cf5..3cdd7d505c 100644
> --- a/src/gbm/backends/dri/gbm_dri.c
> +++ b/src/gbm/backends/dri/gbm_dri.c
> @@ -48,6 +48,7 @@
>  
>  #include "gbmint.h"
>  #include "loader.h"
> +#include "util/macros.h"
>  
>  /* For importing wl_buffer */
>  #if HAVE_WAYLAND_PLATFORM
> @@ -550,6 +551,48 @@ dri_screen_create_sw(struct gbm_dri_device *dri)
> return dri_screen_create_swrast(dri);
>  }
>  
> +static const struct {
> +   uint32_t gbm_format;
> +   int dri_image_format;
> +} gbm_to_dri_image_formats[] = {
> +   { GBM_FORMAT_R8, __DRI_IMAGE_FORMAT_R8 },
> +   { GBM_FORMAT_GR88, __DRI_IMAGE_FORMAT_GR88 },
> +   { GBM_FORMAT_RGB565, __DRI_IMAGE_FORMAT_RGB565 },
> +   { GBM_FORMAT_XRGB, __DRI_IMAGE_FORMAT_XRGB },
> +   { GBM_FORMAT_ARGB, __DRI_IMAGE_FORMAT_ARGB },
> +   { GBM_FORMAT_XBGR, __DRI_IMAGE_FORMAT_XBGR },
> +   { GBM_FORMAT_ABGR, __DRI_IMAGE_FORMAT_ABGR },
> +   { GBM_FORMAT_XRGB2101010, __DRI_IMAGE_FORMAT_XRGB2101010 },
> +   { GBM_FORMAT_ARGB2101010, __DRI_IMAGE_FORMAT_ARGB2101010 },
> +};
> +
> +static int
> +gbm_format_to_dri_format(uint32_t gbm_format)
> +{
> +   int i;
> +
> +   for (i = 0; i < ARRAY_SIZE(gbm_to_dri_image_formats); i++) {
> +  if (gbm_to_dri_image_formats[i].gbm_format == gbm_format)
> + return gbm_to_dri_image_formats[i].dri_image_format;
> +   }
> +
> +   return 0;
> +}
> +
> +static uint32_t
> +gbm_dri_to_gbm_format(int dri_format)
> +{
> +   int i;
> +
> +   for (i = 0; i < ARRAY_SIZE(gbm_to_dri_image_formats); i++) {
> +  if (gbm_to_dri_image_formats[i].dri_image_format == dri_format)
> + return gbm_to_dri_image_formats[i].gbm_format;
> +   }
> +
> +   return 0;
> +}
> +

This is doing a linear search, which is fine, but this is one situation
where I like macros; you can make it constant-time by just having a file
with:

X(GBM_FORMAT_..., __DRI_IMAGE_FORMAT_...)

and in these two functions have a switch with:

#define X(gbm, dri) case gbm: return dri;

and

#define X(gbm, dri) case dri: return gbm;

It's a small list, so it doesn't really matter, and anyway it might as
well be a follow-up patch (happy to volunteer :P), so this and patches
1-3 are:
Reviewed-by: Eric Engestrom 

I'll try and review the rest tomorrow.

Cheers,
  Eric
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Re: [Mesa-dev] [PATCH 07/11] gbm: Remove is_planar_format dead code

2017-06-16 Thread Eric Engestrom 
On Friday, 2017-06-16 18:14:30 +0100, Daniel Stone wrote:
> This was only used in create_dumb() to blacklist planar formats.
> However, the start of the function already whitelists ARGB (cursor)
> and XRGB (scanout), and nothing else. So this entire function can be
> removed.
> 
> Signed-off-by: Daniel Stone 
> ---
>  src/gbm/backends/dri/gbm_dri.c | 32 +---
>  1 file changed, 1 insertion(+), 31 deletions(-)
> 
> diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
> index 4ed780cdeb..3ee1004ddd 100644
> --- a/src/gbm/backends/dri/gbm_dri.c
> +++ b/src/gbm/backends/dri/gbm_dri.c
> @@ -613,7 +613,7 @@ gbm_dri_is_format_supported(struct gbm_device *gbm,
>break;
> }
>  
> -   if ((usage & GBM_BO_USE_CURSOR) && (usage & GBM_BO_USE_RENDERING)
> +   if ((usage & GBM_BO_USE_CURSOR) && (usage & GBM_BO_USE_RENDERING))
>return 0;
>  
> if (gbm_format_to_dri_format(format) == 0)

This hunk fixes a bug introduced in the previous commit; squash it there
instead? :)
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Re: [Mesa-dev] [PATCH v1 2/3] nir: Add a lowering pass for UYVY textures Similar with support for YUYV but with byte order difference in sampler

2017-06-16 Thread Kristian H. Kristensen 
Johnson Lin  writes:

> ---
>  src/compiler/nir/nir.h   |  1 +
>  src/compiler/nir/nir_lower_tex.c | 16 
>  2 files changed, 17 insertions(+)
>
> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> index ab7ba14303b7..1b4e47058d4d 100644
> --- a/src/compiler/nir/nir.h
> +++ b/src/compiler/nir/nir.h
> @@ -2449,6 +2449,7 @@ typedef struct nir_lower_tex_options {
> unsigned lower_y_uv_external;
> unsigned lower_y_u_v_external;
> unsigned lower_yx_xuxv_external;
> +   unsigned lower_xy_uxvx_external;
>  
> /**
>  * To emulate certain texture wrap modes, this can be used
> diff --git a/src/compiler/nir/nir_lower_tex.c 
> b/src/compiler/nir/nir_lower_tex.c
> index 4ef81955513e..5593f9890b28 100644
> --- a/src/compiler/nir/nir_lower_tex.c
> +++ b/src/compiler/nir/nir_lower_tex.c
> @@ -301,6 +301,18 @@ lower_yx_xuxv_external(nir_builder *b, nir_tex_instr 
> *tex)
>nir_channel(b, xuxv, 3));
>  }
>  
> +static void lower_xy_uxvx_external(nir_builder *b, nir_tex_instr *tex) {
> +  b->cursor = nir_after_instr(>instr);
> +
> +  nir_ssa_def *y = sample_plane(b, tex, 0);
> +  nir_ssa_def *uxvx = sample_plane(b, tex, 1);
> +
> +  convert_yuv_to_rgb(b, tex,
> + nir_channel(b, y, 1),
> + nir_channel(b, uxvx, 2),
> + nir_channel(b, uxvx, 0));

This looks like it's swapping U and V channels.

> +}
> +
>  /*
>   * Emits a textureLod operation used to replace an existing
>   * textureGrad instruction.
> @@ -760,6 +772,10 @@ nir_lower_tex_block(nir_block *block, nir_builder *b,
>   progress = true;
>}
>  
> +  if ((1 << tex->texture_index) & options->lower_xy_uxvx_external) {
> + lower_xy_uxvx_external(b, tex);
> + progress = true;
> +  }
>  
>if (sat_mask) {
>   saturate_src(b, tex, sat_mask);
> -- 
> 1.9.1
>
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Re: [Mesa-dev] [PATCH 10/15] i965/miptree: Add option to resolve offsets using isl_surf

2017-06-16 Thread Nanley Chery 
On Tue, Jun 13, 2017 at 05:50:08PM +0300, Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16 
>  1 file changed, 16 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index c81d345fbc..212dfa30ec 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -1175,6 +1175,22 @@ intel_miptree_get_image_offset(const struct 
> intel_mipmap_tree *mt,
>  GLuint level, GLuint slice,
>  GLuint *x, GLuint *y)
>  {
> +   if (mt->surf.size > 0) {
> +  uint32_t x_offset_sa, y_offset_sa;
> +

A comment explaining that we need to perform a subtraction because the
ISL surf begins at first_level may be helpful. It took me some digging
to realize why it was needed.

> +  assert(level >= mt->first_level);
> +  level -= mt->first_level;
> +
> +  const unsigned z = mt->surf.dim == ISL_SURF_DIM_3D ? slice : 0;
> +  slice = mt->surf.dim == ISL_SURF_DIM_3D ? 0 : slice;
> +  isl_surf_get_image_offset_sa(>surf, level, slice, z,
> +   _offset_sa, _offset_sa);
> +
> +  *x = x_offset_sa;
> +  *y = y_offset_sa;

I'm assuming that using these intermediate variables avoids casting
warnings?


With or without the code comment, this patch is
Reviewed-by: Nanley Chery 

> +  return;
> +   }
> +
> assert(slice < mt->level[level].depth);
>  
> *x = mt->level[level].slice[slice].x_offset;
> -- 
> 2.11.0
> 
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[Mesa-dev] [PATCH 05/11] gbm: Pull out FourCC <-> DRIimage format table

2017-06-16 Thread Daniel Stone 
Rather than duplicated (yet asymmetric) open-coded tables, pull them out
to a common structure.

Signed-off-by: Daniel Stone 
---
 src/gbm/Makefile.am|   1 +
 src/gbm/backends/dri/gbm_dri.c | 105 ++---
 2 files changed, 46 insertions(+), 60 deletions(-)

diff --git a/src/gbm/Makefile.am b/src/gbm/Makefile.am
index 60b0924506..de8396000b 100644
--- a/src/gbm/Makefile.am
+++ b/src/gbm/Makefile.am
@@ -5,6 +5,7 @@ pkgconfig_DATA = main/gbm.pc
 
 AM_CFLAGS = \
-I$(top_srcdir)/include \
+   -I$(top_srcdir)/src \
-I$(top_srcdir)/src/loader \
-I$(top_srcdir)/src/gbm/main \
$(DLOPEN_CFLAGS) \
diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
index 84f37d4cf5..3cdd7d505c 100644
--- a/src/gbm/backends/dri/gbm_dri.c
+++ b/src/gbm/backends/dri/gbm_dri.c
@@ -48,6 +48,7 @@
 
 #include "gbmint.h"
 #include "loader.h"
+#include "util/macros.h"
 
 /* For importing wl_buffer */
 #if HAVE_WAYLAND_PLATFORM
@@ -550,6 +551,48 @@ dri_screen_create_sw(struct gbm_dri_device *dri)
return dri_screen_create_swrast(dri);
 }
 
+static const struct {
+   uint32_t gbm_format;
+   int dri_image_format;
+} gbm_to_dri_image_formats[] = {
+   { GBM_FORMAT_R8, __DRI_IMAGE_FORMAT_R8 },
+   { GBM_FORMAT_GR88, __DRI_IMAGE_FORMAT_GR88 },
+   { GBM_FORMAT_RGB565, __DRI_IMAGE_FORMAT_RGB565 },
+   { GBM_FORMAT_XRGB, __DRI_IMAGE_FORMAT_XRGB },
+   { GBM_FORMAT_ARGB, __DRI_IMAGE_FORMAT_ARGB },
+   { GBM_FORMAT_XBGR, __DRI_IMAGE_FORMAT_XBGR },
+   { GBM_FORMAT_ABGR, __DRI_IMAGE_FORMAT_ABGR },
+   { GBM_FORMAT_XRGB2101010, __DRI_IMAGE_FORMAT_XRGB2101010 },
+   { GBM_FORMAT_ARGB2101010, __DRI_IMAGE_FORMAT_ARGB2101010 },
+};
+
+static int
+gbm_format_to_dri_format(uint32_t gbm_format)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(gbm_to_dri_image_formats); i++) {
+  if (gbm_to_dri_image_formats[i].gbm_format == gbm_format)
+ return gbm_to_dri_image_formats[i].dri_image_format;
+   }
+
+   return 0;
+}
+
+static uint32_t
+gbm_dri_to_gbm_format(int dri_format)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(gbm_to_dri_image_formats); i++) {
+  if (gbm_to_dri_image_formats[i].dri_image_format == dri_format)
+ return gbm_to_dri_image_formats[i].gbm_format;
+   }
+
+   return 0;
+}
+
+
 static int
 gbm_dri_is_format_supported(struct gbm_device *gbm,
 uint32_t format,
@@ -795,35 +838,6 @@ gbm_dri_bo_destroy(struct gbm_bo *_bo)
free(bo);
 }
 
-static uint32_t
-gbm_dri_to_gbm_format(uint32_t dri_format)
-{
-   uint32_t ret = 0;
-
-   switch (dri_format) {
-   case __DRI_IMAGE_FORMAT_RGB565:
-  ret = GBM_FORMAT_RGB565;
-  break;
-   case __DRI_IMAGE_FORMAT_XRGB:
-  ret = GBM_FORMAT_XRGB;
-  break;
-   case __DRI_IMAGE_FORMAT_ARGB:
-  ret = GBM_FORMAT_ARGB;
-  break;
-   case __DRI_IMAGE_FORMAT_XBGR:
-  ret = GBM_FORMAT_XBGR;
-  break;
-   case __DRI_IMAGE_FORMAT_ABGR:
-  ret = GBM_FORMAT_ABGR;
-  break;
-   default:
-  ret = 0;
-  break;
-   }
-
-   return ret;
-}
-
 static struct gbm_bo *
 gbm_dri_bo_import(struct gbm_device *gbm,
   uint32_t type, void *buffer, uint32_t usage)
@@ -1126,37 +1140,8 @@ gbm_dri_bo_create(struct gbm_device *gbm,
bo->base.height = height;
bo->base.format = format;
 
-   switch (format) {
-   case GBM_FORMAT_R8:
-  dri_format = __DRI_IMAGE_FORMAT_R8;
-  break;
-   case GBM_FORMAT_GR88:
-  dri_format = __DRI_IMAGE_FORMAT_GR88;
-  break;
-   case GBM_FORMAT_RGB565:
-  dri_format = __DRI_IMAGE_FORMAT_RGB565;
-  break;
-   case GBM_FORMAT_XRGB:
-   case GBM_BO_FORMAT_XRGB:
-  dri_format = __DRI_IMAGE_FORMAT_XRGB;
-  break;
-   case GBM_FORMAT_ARGB:
-   case GBM_BO_FORMAT_ARGB:
-  dri_format = __DRI_IMAGE_FORMAT_ARGB;
-  break;
-   case GBM_FORMAT_ABGR:
-  dri_format = __DRI_IMAGE_FORMAT_ABGR;
-  break;
-   case GBM_FORMAT_XBGR:
-  dri_format = __DRI_IMAGE_FORMAT_XBGR;
-  break;
-   case GBM_FORMAT_ARGB2101010:
-  dri_format = __DRI_IMAGE_FORMAT_ARGB2101010;
-  break;
-   case GBM_FORMAT_XRGB2101010:
-  dri_format = __DRI_IMAGE_FORMAT_XRGB2101010;
-  break;
-   default:
+   dri_format = gbm_format_to_dri_format(format);
+   if (dri_format == 0) {
   errno = EINVAL;
   goto failed;
}
-- 
2.13.0

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[Mesa-dev] [PATCH 06/11] gbm: Check harder for supported formats

2017-06-16 Thread Daniel Stone 
Luckily no-one really used the is_format_supported() call, because it
only supported three formats.

Also, since buffers with alpha can be displayed on planes, stop banning
them from use.

Signed-off-by: Daniel Stone 
---
 src/gbm/backends/dri/gbm_dri.c | 40 
 1 file changed, 32 insertions(+), 8 deletions(-)

diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
index 3cdd7d505c..4ed780cdeb 100644
--- a/src/gbm/backends/dri/gbm_dri.c
+++ b/src/gbm/backends/dri/gbm_dri.c
@@ -592,29 +592,53 @@ gbm_dri_to_gbm_format(int dri_format)
return 0;
 }
 
-
 static int
 gbm_dri_is_format_supported(struct gbm_device *gbm,
 uint32_t format,
 uint32_t usage)
 {
+   struct gbm_dri_device *dri = gbm_dri_device(gbm);
+   int count;
+
+   /* Remap from GBM_BO_FORMAT_* to GBM_FORMAT_*. Luckily there are only two of
+* these. */
switch (format) {
case GBM_BO_FORMAT_XRGB:
-   case GBM_FORMAT_XBGR:
-   case GBM_FORMAT_XRGB:
+  format = GBM_FORMAT_XRGB;
   break;
case GBM_BO_FORMAT_ARGB:
-   case GBM_FORMAT_ARGB:
-  if (usage & GBM_BO_USE_SCANOUT)
- return 0;
+  format = GBM_FORMAT_ARGB;
   break;
default:
+  break;
+   }
+
+   if ((usage & GBM_BO_USE_CURSOR) && (usage & GBM_BO_USE_RENDERING)
   return 0;
+
+   if (gbm_format_to_dri_format(format) == 0)
+  return 0;
+
+   /* If there is no query, fall back to the small table which was originally
+* here. */
+   if (dri->image->base.version <= 15 || !dri->image->queryDmaBufModifiers) {
+  switch (format) {
+  case GBM_FORMAT_XRGB:
+  case GBM_FORMAT_ARGB:
+  case GBM_FORMAT_XBGR:
+ return 1;
+  default:
+ return 0;
+  }
}
 
-   if (usage & GBM_BO_USE_CURSOR &&
-   usage & GBM_BO_USE_RENDERING)
+   /* Check if the driver returns any modifiers for this format; since linear
+* is counted as a modifier, we will have at least one modifier for any
+* supported format. */
+   if (!dri->image->queryDmaBufModifiers(dri->screen, format, 0, NULL, NULL,
+ ) || count == 0) {
   return 0;
+   }
 
return 1;
 }
-- 
2.13.0

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[Mesa-dev] [PATCH 03/11] egl/wayland: Use MIN2 for wl_drm version

2017-06-16 Thread Daniel Stone 
Use a slightly more explicit version cap for binding wl_drm, so we can
add other interfaces with different versioning schemes later.

Signed-off-by: Daniel Stone 
---
 src/egl/drivers/dri2/platform_wayland.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index ae93c1b150..c1cbb11f26 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -996,11 +996,9 @@ registry_handle_global_drm(void *data, struct wl_registry 
*registry,
 {
struct dri2_egl_display *dri2_dpy = data;
 
-   if (version > 1)
-  version = 2;
if (strcmp(interface, "wl_drm") == 0) {
   dri2_dpy->wl_drm =
- wl_registry_bind(registry, name, _drm_interface, version);
+ wl_registry_bind(registry, name, _drm_interface, MIN2(version, 2));
   wl_drm_add_listener(dri2_dpy->wl_drm, _listener, dri2_dpy);
}
 }
-- 
2.13.0

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[Mesa-dev] [PATCH 07/11] gbm: Remove is_planar_format dead code

2017-06-16 Thread Daniel Stone 
This was only used in create_dumb() to blacklist planar formats.
However, the start of the function already whitelists ARGB (cursor)
and XRGB (scanout), and nothing else. So this entire function can be
removed.

Signed-off-by: Daniel Stone 
---
 src/gbm/backends/dri/gbm_dri.c | 32 +---
 1 file changed, 1 insertion(+), 31 deletions(-)

diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
index 4ed780cdeb..3ee1004ddd 100644
--- a/src/gbm/backends/dri/gbm_dri.c
+++ b/src/gbm/backends/dri/gbm_dri.c
@@ -613,7 +613,7 @@ gbm_dri_is_format_supported(struct gbm_device *gbm,
   break;
}
 
-   if ((usage & GBM_BO_USE_CURSOR) && (usage & GBM_BO_USE_RENDERING)
+   if ((usage & GBM_BO_USE_CURSOR) && (usage & GBM_BO_USE_RENDERING))
   return 0;
 
if (gbm_format_to_dri_format(format) == 0)
@@ -1047,31 +1047,6 @@ gbm_dri_bo_import(struct gbm_device *gbm,
return >base;
 }
 
-static bool
-is_planar_format(uint32_t format)
-{
-   switch (format) {
-   case GBM_FORMAT_NV12:
-   case GBM_FORMAT_NV21:
-   case GBM_FORMAT_NV16:
-   case GBM_FORMAT_NV61:
-   case GBM_FORMAT_YUV410:
-   case GBM_FORMAT_YVU410:
-   case GBM_FORMAT_YUV411:
-   case GBM_FORMAT_YVU411:
-   case GBM_FORMAT_YUV420:
-   case GBM_FORMAT_YVU420:
-   case GBM_FORMAT_YUV422:
-   case GBM_FORMAT_YVU422:
-   case GBM_FORMAT_YUV444:
-   case GBM_FORMAT_YVU444:
-  return true;
-   default:
-  return false;
-   }
-
-}
-
 static struct gbm_bo *
 create_dumb(struct gbm_device *gbm,
   uint32_t width, uint32_t height,
@@ -1093,11 +1068,6 @@ create_dumb(struct gbm_device *gbm,
   return NULL;
}
 
-   if (is_planar_format(format)) {
-  errno = EINVAL;
-  return NULL;
-   }
-
bo = calloc(1, sizeof *bo);
if (bo == NULL)
   return NULL;
-- 
2.13.0

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[Mesa-dev] [PATCH 09/11] egl/wayland: Remove more surface specifics from create_wl_buffer

2017-06-16 Thread Daniel Stone 
Signed-off-by: Daniel Stone 
---
 src/egl/drivers/dri2/platform_wayland.c | 32 ++--
 1 file changed, 14 insertions(+), 18 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 7a85cb1073..b7197d0a75 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -648,31 +648,28 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
  __DRIimage *image)
 {
struct wl_buffer *ret;
-   int fd, stride, name;
+   int width, height, fourcc;
+
+   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_WIDTH, );
+   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_HEIGHT, );
+   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FOURCC, );
 
if (dri2_dpy->capabilities & WL_DRM_CAPABILITY_PRIME) {
-  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FD, );
-  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_STRIDE, );
+  int stride, fd;
 
+  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_STRIDE, );
+  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FD, );
   ret = wl_drm_create_prime_buffer(dri2_surf->wl_drm_wrapper,
-   fd,
-   dri2_surf->base.Width,
-   dri2_surf->base.Height,
-   dri2_surf->format,
-   0, stride,
-   0, 0,
-   0, 0);
+   fd, width, height, fourcc, 0, stride,
+   0, 0, 0, 0);
   close(fd);
} else {
-  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_NAME, );
-  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_STRIDE, );
+  int stride, name;
 
+  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_STRIDE, );
+  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_NAME, );
   ret = wl_drm_create_buffer(dri2_surf->wl_drm_wrapper,
- name,
- dri2_surf->base.Width,
- dri2_surf->base.Height,
- stride,
- dri2_surf->format);
+ name, width, height, stride, fourcc);
}
 
return ret;
@@ -738,7 +735,6 @@ dri2_wl_swap_buffers_with_damage(_EGLDriver *drv,
 
dri2_surf->back->age = 1;
dri2_surf->current = dri2_surf->back;
-   dri2_surf->back = NULL;
 
if (!dri2_surf->current->wl_buffer) {
   __DRIimage *image;
-- 
2.13.0

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[Mesa-dev] [PATCH 08/11] egl/wayland: Make create_wl_buffer more generic

2017-06-16 Thread Daniel Stone 
Remove surface-specific code from create_wl_buffer, so it's now just a
generic translation from DRIimage to wl_buffer.

Signed-off-by: Daniel Stone 
---
 src/egl/drivers/dri2/platform_wayland.c | 66 +
 1 file changed, 34 insertions(+), 32 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index c1cbb11f26..7a85cb1073 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -642,51 +642,40 @@ static const struct wl_callback_listener 
throttle_listener = {
.done = wayland_throttle_callback
 };
 
-static void
-create_wl_buffer(struct dri2_egl_surface *dri2_surf)
+static struct wl_buffer *
+create_wl_buffer(struct dri2_egl_display *dri2_dpy,
+ struct dri2_egl_surface *dri2_surf,
+ __DRIimage *image)
 {
-   struct dri2_egl_display *dri2_dpy =
-  dri2_egl_display(dri2_surf->base.Resource.Display);
-   __DRIimage *image;
+   struct wl_buffer *ret;
int fd, stride, name;
 
-   if (dri2_surf->current->wl_buffer != NULL)
-  return;
-
-   if (dri2_dpy->is_different_gpu) {
-  image = dri2_surf->current->linear_copy;
-   } else {
-  image = dri2_surf->current->dri_image;
-   }
if (dri2_dpy->capabilities & WL_DRM_CAPABILITY_PRIME) {
   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FD, );
   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_STRIDE, );
 
-  dri2_surf->current->wl_buffer =
- wl_drm_create_prime_buffer(dri2_surf->wl_drm_wrapper,
-fd,
-dri2_surf->base.Width,
-dri2_surf->base.Height,
-dri2_surf->format,
-0, stride,
-0, 0,
-0, 0);
+  ret = wl_drm_create_prime_buffer(dri2_surf->wl_drm_wrapper,
+   fd,
+   dri2_surf->base.Width,
+   dri2_surf->base.Height,
+   dri2_surf->format,
+   0, stride,
+   0, 0,
+   0, 0);
   close(fd);
} else {
   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_NAME, );
   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_STRIDE, );
 
-  dri2_surf->current->wl_buffer =
- wl_drm_create_buffer(dri2_surf->wl_drm_wrapper,
-  name,
-  dri2_surf->base.Width,
-  dri2_surf->base.Height,
-  stride,
-  dri2_surf->format);
+  ret = wl_drm_create_buffer(dri2_surf->wl_drm_wrapper,
+ name,
+ dri2_surf->base.Width,
+ dri2_surf->base.Height,
+ stride,
+ dri2_surf->format);
}
 
-   wl_buffer_add_listener(dri2_surf->current->wl_buffer,
-  _buffer_listener, dri2_surf);
+   return ret;
 }
 
 static EGLBoolean
@@ -751,7 +740,20 @@ dri2_wl_swap_buffers_with_damage(_EGLDriver *drv,
dri2_surf->current = dri2_surf->back;
dri2_surf->back = NULL;
 
-   create_wl_buffer(dri2_surf);
+   if (!dri2_surf->current->wl_buffer) {
+  __DRIimage *image;
+
+  if (dri2_dpy->is_different_gpu)
+ image = dri2_surf->current->linear_copy;
+  else
+ image = dri2_surf->current->dri_image;
+
+  dri2_surf->current->wl_buffer =
+ create_wl_buffer(dri2_dpy, dri2_surf, image);
+
+  wl_buffer_add_listener(dri2_surf->current->wl_buffer,
+ _buffer_listener, dri2_surf);
+   }
 
wl_surface_attach(dri2_surf->wl_surface_wrapper,
  dri2_surf->current->wl_buffer,
-- 
2.13.0

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[Mesa-dev] [PATCH 11/11] egl/wayland: Use linux-dmabuf interface for buffers

2017-06-16 Thread Daniel Stone 
When available, use the zwp_linux_dambuf_v1 interface to create buffers,
which allows multiple planes and buffer modifiers to be used.

Signed-off-by: Daniel Stone 
---
 configure.ac|   5 +-
 src/egl/Makefile.am |  22 +++-
 src/egl/drivers/dri2/.gitignore |   2 +
 src/egl/drivers/dri2/egl_dri2.c |   7 ++
 src/egl/drivers/dri2/egl_dri2.h |  10 ++
 src/egl/drivers/dri2/platform_wayland.c | 189 +---
 6 files changed, 214 insertions(+), 21 deletions(-)
 create mode 100644 src/egl/drivers/dri2/.gitignore

diff --git a/configure.ac b/configure.ac
index 9de1b42933..8adbd07880 100644
--- a/configure.ac
+++ b/configure.ac
@@ -89,6 +89,7 @@ LIBOMXIL_BELLAGIO_REQUIRED=0.0
 LIBVA_REQUIRED=0.38.0
 VDPAU_REQUIRED=1.1
 WAYLAND_REQUIRED=1.11
+WAYLAND_PROTOCOLS_REQUIRED=1.8
 XCB_REQUIRED=1.9.3
 XCBDRI2_REQUIRED=1.8
 XCBGLX_REQUIRED=1.8.1
@@ -1673,7 +1674,9 @@ for plat in $platforms; do
case "$plat" in
wayland)
 
-   PKG_CHECK_MODULES([WAYLAND], [wayland-client >= 
$WAYLAND_REQUIRED wayland-server >= $WAYLAND_REQUIRED])
+   PKG_CHECK_MODULES([WAYLAND], [wayland-client >= 
$WAYLAND_REQUIRED wayland-server >= $WAYLAND_REQUIRED wayland-protocols >= 
$WAYLAND_PROTOCOLS_REQUIRED])
+ac_wayland_protocols_pkgdatadir=`$PKG_CONFIG 
--variable=pkgdatadir wayland-protocols`
+AC_SUBST(WAYLAND_PROTOCOLS_DATADIR, 
$ac_wayland_protocols_pkgdatadir)
 
if test "x$WAYLAND_SCANNER" = "x:"; then
AC_MSG_ERROR([wayland-scanner is needed to compile the 
wayland platform])
diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
index 81090387b5..a95e5c3230 100644
--- a/src/egl/Makefile.am
+++ b/src/egl/Makefile.am
@@ -21,6 +21,8 @@
 
 include Makefile.sources
 
+BUILT_SOURCES =
+
 AM_CFLAGS = \
-I$(top_srcdir)/include \
-I$(top_srcdir)/src/egl/main \
@@ -61,11 +63,27 @@ endif
 endif
 
 if HAVE_PLATFORM_WAYLAND
+WL_DMABUF_XML = 
$(WAYLAND_PROTOCOLS_DATADIR)/unstable/linux-dmabuf/linux-dmabuf-unstable-v1.xml
+
+drivers/dri2/linux-dmabuf-unstable-v1-protocol.c: $(WL_DMABUF_XML)
+   $(MKDIR_GEN)
+   $(AM_V_GEN)$(WAYLAND_SCANNER) code < $< > $@
+
+drivers/dri2/linux-dmabuf-unstable-v1-client-protocol.h: $(WL_DMABUF_XML)
+   $(MKDIR_GEN)
+   $(AM_V_GEN)$(WAYLAND_SCANNER) client-header < $< > $@
+
+BUILT_SOURCES += \
+   drivers/dri2/linux-dmabuf-unstable-v1-protocol.c \
+   drivers/dri2/linux-dmabuf-unstable-v1-client-protocol.h
+
 AM_CFLAGS += $(WAYLAND_CFLAGS)
 libEGL_common_la_LIBADD += $(WAYLAND_LIBS)
 libEGL_common_la_LIBADD += $(LIBDRM_LIBS)
 libEGL_common_la_LIBADD += 
$(top_builddir)/src/egl/wayland/wayland-drm/libwayland-drm.la
-dri2_backend_FILES += drivers/dri2/platform_wayland.c
+libEGL_common_la_LIBADD += $(top_builddir)/src/util/libmesautil.la
+dri2_backend_FILES += drivers/dri2/platform_wayland.c  \
+   drivers/dri2/linux-dmabuf-unstable-v1-protocol.c
 endif
 
 if HAVE_PLATFORM_DRM
@@ -118,7 +136,7 @@ g_egldispatchstubs.h: $(GLVND_GEN_DEPS)
$(top_srcdir)/src/egl/generate/egl.xml \
$(top_srcdir)/src/egl/generate/egl_other.xml > $@
 
-BUILT_SOURCES = g_egldispatchstubs.c g_egldispatchstubs.h
+BUILT_SOURCES += g_egldispatchstubs.c g_egldispatchstubs.h
 CLEANFILES = $(BUILT_SOURCES)
 
 if USE_LIBGLVND
diff --git a/src/egl/drivers/dri2/.gitignore b/src/egl/drivers/dri2/.gitignore
new file mode 100644
index 00..e96becbb54
--- /dev/null
+++ b/src/egl/drivers/dri2/.gitignore
@@ -0,0 +1,2 @@
+linux-dmabuf-unstable-v1-client-protocol.h
+linux-dmabuf-unstable-v1-protocol.c
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 020a0bc639..4bb6f09ed8 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -53,6 +53,7 @@
 #ifdef HAVE_WAYLAND_PLATFORM
 #include "wayland-drm.h"
 #include "wayland-drm-client-protocol.h"
+#include "linux-dmabuf-unstable-v1-client-protocol.h"
 #endif
 
 #ifdef HAVE_X11_PLATFORM
@@ -62,6 +63,7 @@
 #include "egl_dri2.h"
 #include "loader/loader.h"
 #include "util/u_atomic.h"
+#include "util/u_vector.h"
 
 /* The kernel header drm_fourcc.h defines the DRM formats below.  We duplicate
  * some of the definitions here so that building Mesa won't bleeding-edge
@@ -949,11 +951,16 @@ dri2_display_destroy(_EGLDisplay *disp)
case _EGL_PLATFORM_WAYLAND:
   if (dri2_dpy->wl_drm)
   wl_drm_destroy(dri2_dpy->wl_drm);
+  if (dri2_dpy->wl_dmabuf)
+  zwp_linux_dmabuf_v1_destroy(dri2_dpy->wl_dmabuf);
   if (dri2_dpy->wl_shm)
   wl_shm_destroy(dri2_dpy->wl_shm);
   wl_registry_destroy(dri2_dpy->wl_registry);
   wl_event_queue_destroy(dri2_dpy->wl_queue);
   wl_proxy_wrapper_destroy(dri2_dpy->wl_dpy_wrapper);
+  u_vector_finish(_dpy->wl_modifiers.argb);
+  u_vector_finish(_dpy->wl_modifiers.xrgb);
+

[Mesa-dev] [PATCH 04/11] gbm: Axe buffer import format conversion table

2017-06-16 Thread Daniel Stone 
Wayland buffers coming from wl_drm use the WL_DRM_FORMAT_* enums, which
are identical to GBM_FORMAT_*. Similarly, FD imports do not need to
convert between GBM and DRI FourCC, since they are (almost) completely
compatible.

Signed-off-by: Daniel Stone 
---
 src/gbm/backends/dri/gbm_dri.c | 62 +++---
 1 file changed, 22 insertions(+), 40 deletions(-)

diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
index 19be440d48..84f37d4cf5 100644
--- a/src/gbm/backends/dri/gbm_dri.c
+++ b/src/gbm/backends/dri/gbm_dri.c
@@ -859,23 +859,9 @@ gbm_dri_bo_import(struct gbm_device *gbm,
 
   image = dri->image->dupImage(wb->driver_buffer, NULL);
 
-  switch (wb->format) {
-  case WL_DRM_FORMAT_XRGB:
- gbm_format = GBM_FORMAT_XRGB;
- break;
-  case WL_DRM_FORMAT_ARGB:
- gbm_format = GBM_FORMAT_ARGB;
- break;
-  case WL_DRM_FORMAT_RGB565:
- gbm_format = GBM_FORMAT_RGB565;
- break;
-  case WL_DRM_FORMAT_YUYV:
- gbm_format = GBM_FORMAT_YUYV;
- break;
-  default:
- dri->image->destroyImage(image);
- return NULL;
-  }
+  /* GBM_FORMAT_* is identical to WL_DRM_FORMAT_*, so no conversion
+   * required. */
+  gbm_format = wb->format;
   break;
}
 #endif
@@ -904,23 +890,27 @@ gbm_dri_bo_import(struct gbm_device *gbm,
{
   struct gbm_import_fd_data *fd_data = buffer;
   int stride = fd_data->stride, offset = 0;
-  int dri_format;
+  int fourcc;
 
+  /* GBM's GBM_FORMAT_* tokens are a strict superset of the DRI FourCC
+   * tokens accepted by createImageFromFds, except for not supporting
+   * the sARGB format. Also, GBM_BO_FORMAT_* are defined differently to
+   * their GBM_FORMAT_* equivalents, so remap them here. */
   switch (fd_data->format) {
   case GBM_BO_FORMAT_XRGB:
- dri_format = GBM_FORMAT_XRGB;
+ fourcc = GBM_FORMAT_XRGB;
  break;
   case GBM_BO_FORMAT_ARGB:
- dri_format = GBM_FORMAT_ARGB;
+ fourcc = GBM_FORMAT_ARGB;
  break;
   default:
- dri_format = fd_data->format;
+ fourcc = fd_data->format;
   }
 
   image = dri->image->createImageFromFds(dri->screen,
  fd_data->width,
  fd_data->height,
- dri_format,
+ fourcc,
  _data->fd, 1,
  , ,
  NULL);
@@ -945,27 +935,19 @@ gbm_dri_bo_import(struct gbm_device *gbm,
  return NULL;
   }
 
-  switch(fd_data->format) {
-  case GBM_FORMAT_RGB565:
- fourcc = __DRI_IMAGE_FOURCC_RGB565;
- break;
-  case GBM_FORMAT_ARGB:
-  case GBM_BO_FORMAT_ARGB:
- fourcc = __DRI_IMAGE_FOURCC_ARGB;
- break;
-  case GBM_FORMAT_XRGB:
+  /* GBM's GBM_FORMAT_* tokens are a strict superset of the DRI FourCC
+   * tokens accepted by createImageFromDmaBufs2, except for not supporting
+   * the sARGB format. Also, GBM_BO_FORMAT_* are defined differently to
+   * their GBM_FORMAT_* equivalents, so remap them here. */
+  switch (fd_data->format) {
   case GBM_BO_FORMAT_XRGB:
- fourcc = __DRI_IMAGE_FOURCC_XRGB;
- break;
-  case GBM_FORMAT_ABGR:
- fourcc = __DRI_IMAGE_FOURCC_ABGR;
+ fourcc = GBM_FORMAT_XRGB;
  break;
-  case GBM_FORMAT_XBGR:
- fourcc = __DRI_IMAGE_FOURCC_XBGR;
+  case GBM_BO_FORMAT_ARGB:
+ fourcc = GBM_FORMAT_ARGB;
  break;
   default:
- errno = EINVAL;
- return NULL;
+ fourcc = fd_data->format;
   }
 
   image = dri->image->createImageFromDmaBufs2(dri->screen, fd_data->width,
@@ -982,7 +964,7 @@ gbm_dri_bo_import(struct gbm_device *gbm,
  return NULL;
   }
 
-  gbm_format = fd_data->format;
+  gbm_format = fourcc;
   break;
}
 
-- 
2.13.0

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[Mesa-dev] [PATCH 02/11] egl/wayland: Fix whitespace damage

2017-06-16 Thread Daniel Stone 
Convert tabs to spaces, fix misalignments.

Signed-off-by: Daniel Stone 
---
 src/egl/drivers/dri2/platform_wayland.c | 38 +
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index f746f0bfd1..ae93c1b150 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -438,7 +438,7 @@ back_bo_to_dri_buffer(struct dri2_egl_surface *dri2_surf, 
__DRIbuffer *buffer)
 
 static int
 get_aux_bo(struct dri2_egl_surface *dri2_surf,
-  unsigned int attachment, unsigned int format, __DRIbuffer *buffer)
+   unsigned int attachment, unsigned int format, __DRIbuffer *buffer)
 {
struct dri2_egl_display *dri2_dpy =
   dri2_egl_display(dri2_surf->base.Resource.Display);
@@ -446,9 +446,9 @@ get_aux_bo(struct dri2_egl_surface *dri2_surf,
 
if (b == NULL) {
   b = dri2_dpy->dri2->allocateBuffer(dri2_dpy->dri_screen,
-attachment, format,
-dri2_surf->base.Width,
-dri2_surf->base.Height);
+ attachment, format,
+ dri2_surf->base.Width,
+ dri2_surf->base.Height);
   dri2_surf->dri_buffers[attachment] = b;
}
if (b == NULL)
@@ -517,20 +517,20 @@ dri2_wl_get_buffers_with_format(__DRIdrawable * 
driDrawable,
   switch (attachments[i]) {
   case __DRI_BUFFER_BACK_LEFT:
  back_bo_to_dri_buffer(dri2_surf, _surf->buffers[j]);
-break;
+ break;
   default:
-if (get_aux_bo(dri2_surf, attachments[i], attachments[i + 1],
-   _surf->buffers[j]) < 0) {
-   _eglError(EGL_BAD_ALLOC, "failed to allocate aux buffer");
-   return NULL;
-}
-break;
+ if (get_aux_bo(dri2_surf, attachments[i], attachments[i + 1],
+_surf->buffers[j]) < 0) {
+_eglError(EGL_BAD_ALLOC, "failed to allocate aux buffer");
+return NULL;
+ }
+ break;
   }
}
 
*out_count = j;
if (j == 0)
-  return NULL;
+   return NULL;
 
*width = dri2_surf->base.Width;
*height = dri2_surf->base.Height;
@@ -936,7 +936,7 @@ drm_handle_device(void *data, struct wl_drm *drm, const 
char *device)
dri2_dpy->fd = loader_open_device(dri2_dpy->device_name);
if (dri2_dpy->fd == -1) {
   _eglLog(_EGL_WARNING, "wayland-egl: could not open %s (%s)",
- dri2_dpy->device_name, strerror(errno));
+  dri2_dpy->device_name, strerror(errno));
   return;
}
 
@@ -990,8 +990,9 @@ static const struct wl_drm_listener drm_listener = {
 };
 
 static void
-registry_handle_global_drm(void *data, struct wl_registry *registry, uint32_t 
name,
-  const char *interface, uint32_t version)
+registry_handle_global_drm(void *data, struct wl_registry *registry,
+   uint32_t name, const char *interface,
+   uint32_t version)
 {
struct dri2_egl_display *dri2_dpy = data;
 
@@ -1006,7 +1007,7 @@ registry_handle_global_drm(void *data, struct wl_registry 
*registry, uint32_t na
 
 static void
 registry_handle_global_remove(void *data, struct wl_registry *registry,
- uint32_t name)
+  uint32_t name)
 {
 }
 
@@ -1747,8 +1748,9 @@ static const struct wl_shm_listener shm_listener = {
 };
 
 static void
-registry_handle_global_swrast(void *data, struct wl_registry *registry, 
uint32_t name,
-  const char *interface, uint32_t version)
+registry_handle_global_swrast(void *data, struct wl_registry *registry,
+  uint32_t name, const char *interface,
+  uint32_t version)
 {
struct dri2_egl_display *dri2_dpy = data;
 
-- 
2.13.0

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[Mesa-dev] [PATCH 01/11] util: Remove u_math from u_vector

2017-06-16 Thread Daniel Stone 
u_vector.h doesn't actually use anything from u_math, but it does mean
everyone has to pull in src/gallium/auxiliary/util includes.

Just remove it, adding a  include to u_vector.c to cover
memcpy.

Signed-off-by: Daniel Stone 
---
 src/util/u_vector.c | 2 ++
 src/util/u_vector.h | 1 -
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/util/u_vector.c b/src/util/u_vector.c
index 37c4245ebe..afe0924e4c 100644
--- a/src/util/u_vector.c
+++ b/src/util/u_vector.c
@@ -20,6 +20,8 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  * IN THE SOFTWARE.
  */
+
+#include 
 #include "util/u_vector.h"
 
 int
diff --git a/src/util/u_vector.h b/src/util/u_vector.h
index c0e199cfa5..cd8a95dcbe 100644
--- a/src/util/u_vector.h
+++ b/src/util/u_vector.h
@@ -31,7 +31,6 @@
 
 #include 
 #include 
-#include "util/u_math.h"
 #include "util/macros.h"
 
 /* TODO - move to u_math.h - name it better etc */
-- 
2.13.0

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[Mesa-dev] [PATCH 00/11] EGL/Wayland modifiers, format cleanup

2017-06-16 Thread Daniel Stone 
Hi,
This series adds support for multi-planar buffers, as well as buffers
with modifiers, in the Wayland EGL client platform.

Rather than extending wl_drm, we use the generic zwp_linux_dambuf_v1
protocol, which is implemented in Weston. This makes it a bit easier to,
amongst other things, write compositors in Vulkan, or direct-to-KMS
without having to bounce through EGL.

In doing so, this de-duplicates both wl_buffer creation, as well as
a pile of DRIimage format <-> FourCC conversion tables I found in GBM.
There's no interdependency between the GBM and EGL bits, so they can
be considered separately, but 11/11 _does_ need the u_vector patch.

Happy weekend!

Cheers,
Daniel

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[Mesa-dev] [PATCH 10/11] egl/wayland: Remove duplicate wl_buffer creation code

2017-06-16 Thread Daniel Stone 
Now create_wl_buffer is generic enough, we can use it for the
EGL_WL_create_wayland_buffer_from_image extension.

Signed-off-by: Daniel Stone 
---
 src/egl/drivers/dri2/platform_wayland.c | 71 +
 1 file changed, 11 insertions(+), 60 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index b7197d0a75..96ce31c0ae 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -655,21 +655,23 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FOURCC, );
 
if (dri2_dpy->capabilities & WL_DRM_CAPABILITY_PRIME) {
+  struct wl_drm *wl_drm =
+ dri2_surf ? dri2_surf->wl_drm_wrapper : dri2_dpy->wl_drm;
   int stride, fd;
 
   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_STRIDE, );
   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FD, );
-  ret = wl_drm_create_prime_buffer(dri2_surf->wl_drm_wrapper,
-   fd, width, height, fourcc, 0, stride,
-   0, 0, 0, 0);
+  ret = wl_drm_create_prime_buffer(wl_drm, fd, width, height, fourcc, 0,
+   stride, 0, 0, 0, 0);
   close(fd);
} else {
+  struct wl_drm *wl_drm =
+ dri2_surf ? dri2_surf->wl_drm_wrapper : dri2_dpy->wl_drm;
   int stride, name;
 
   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_STRIDE, );
   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_NAME, );
-  ret = wl_drm_create_buffer(dri2_surf->wl_drm_wrapper,
- name, width, height, stride, fourcc);
+  ret = wl_drm_create_buffer(wl_drm, name, width, height, stride, fourcc);
}
 
return ret;
@@ -829,70 +831,19 @@ dri2_wl_create_wayland_buffer_from_image(_EGLDriver *drv,
struct dri2_egl_image *dri2_img = dri2_egl_image(img);
__DRIimage *image = dri2_img->dri_image;
struct wl_buffer *buffer;
-   int width, height, format, pitch;
-   enum wl_drm_format wl_format;
 
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FORMAT, );
-
-   switch (format) {
-   case __DRI_IMAGE_FORMAT_ARGB:
-  if (!(dri2_dpy->formats & HAS_ARGB))
- goto bad_format;
-  wl_format = WL_DRM_FORMAT_ARGB;
-  break;
-   case __DRI_IMAGE_FORMAT_XRGB:
-  if (!(dri2_dpy->formats & HAS_XRGB))
- goto bad_format;
-  wl_format = WL_DRM_FORMAT_XRGB;
-  break;
-   default:
-  goto bad_format;
-   }
-
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_WIDTH, );
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_HEIGHT, );
-   dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_STRIDE, );
-
-   if (dri2_dpy->capabilities & WL_DRM_CAPABILITY_PRIME) {
-  int fd;
-
-  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FD, );
-
-  buffer =
- wl_drm_create_prime_buffer(dri2_dpy->wl_drm,
-fd,
-width, height,
-wl_format,
-0, pitch,
-0, 0,
-0, 0);
-
-  close(fd);
-   } else {
-  int name;
-
-  dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_NAME, );
-
-  buffer =
- wl_drm_create_buffer(dri2_dpy->wl_drm,
-  name,
-  width, height,
-  pitch,
-  wl_format);
-   }
+   buffer = create_wl_buffer(dri2_dpy, NULL, image);
 
/* The buffer object will have been created with our internal event queue
 * because it is using the wl_drm object as a proxy factory. We want the
 * buffer to be used by the application so we'll reset it to the display's
-* default event queue */
+* default event queue. This isn't actually racy, as the only event the
+* buffer can get is a buffer release, which doesn't happen with an explicit
+* attach. */
if (buffer)
   wl_proxy_set_queue((struct wl_proxy *) buffer, NULL);
 
return buffer;
-
-bad_format:
-   _eglError(EGL_BAD_MATCH, "unsupported image format");
-   return NULL;
 }
 
 static int
-- 
2.13.0

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Re: [Mesa-dev] [PATCH 09/15] i965: Prepare slice copy for isl based miptrees

2017-06-16 Thread Nanley Chery 
On Thu, Jun 15, 2017 at 10:01:53PM +0300, Pohjolainen, Topi wrote:
> On Thu, Jun 15, 2017 at 11:39:44AM -0700, Jason Ekstrand wrote:
> > On Tue, Jun 13, 2017 at 7:50 AM, Topi Pohjolainen <
> > topi.pohjolai...@gmail.com> wrote:
> > 
> > > Signed-off-by: Topi Pohjolainen 
> > > ---
> > >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 28
> > > +--
> > >  1 file changed, 22 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > index f44bac988f..c81d345fbc 100644
> > > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > @@ -1294,7 +1294,8 @@ intel_miptree_copy_slice_sw(struct brw_context *brw,
> > >  {
> > > void *src, *dst;
> > > ptrdiff_t src_stride, dst_stride;
> > > -   int cpp = dst_mt->cpp;
> > > +   const unsigned cpp = dst_mt->surf.size > 0 ?
> > > +  (isl_format_get_layout(dst_mt->surf.format)->bpb / 8) :
> > > dst_mt->cpp;
> > >
> > > intel_miptree_map(brw, src_mt,
> > >   src_level, src_layer,
> > > @@ -1355,13 +1356,28 @@ intel_miptree_copy_slice(struct brw_context *brw,
> > >   unsigned dst_level, unsigned dst_layer)
> > >
> > >  {
> > > -   uint32_t width = minify(src_mt->physical_width0,
> > > -   src_level - src_mt->first_level);
> > > -   uint32_t height = minify(src_mt->physical_height0,
> > > -src_level - src_mt->first_level);
> > > mesa_format format = src_mt->format;
> > > +   uint32_t width, height;
> > > +
> > > +   if (src_mt->surf.size > 0) {
> > > +  width = minify(src_mt->surf.phys_level0_sa.width,
> > > + src_level - src_mt->first_level);
> > > +  height = minify(src_mt->surf.phys_level0_sa.height,
> > > +  src_level - src_mt->first_level);
> > > +
> > > +  const unsigned level_depth = src_mt->surf.dim == ISL_SURF_DIM_3D ?
> > >
> > 
> > This needs a MAYBE_UNUSED or else we'll get warnings in release builds.
> > Another option would be to do
> > 
> > if (src_mt->surf.dim == ISL_SURF_DIM_3D)
> >assert(src_layer < minify());
> > else
> >assert(src_layer < src_mt->surf.phys_level0_sa.array_len);
> > 
> > I think that would actually be better.
> 
> Thanks, used the latter locally.
> 

Patches 7, 8, and revised 9 are
Reviewed-by: Nanley Chery 

> > 
> > 
> > > + minify(src_mt->surf.phys_level0_sa.depth,
> > > +src_level - src_mt->first_level) :
> > > + src_mt->surf.phys_level0_sa.array_len;
> > > +  assert(src_layer < level_depth);
> > > +   } else {
> > > +  width = minify(src_mt->physical_width0,
> > > + src_level - src_mt->first_level);
> > > +  height = minify(src_mt->physical_height0,
> > > +  src_level - src_mt->first_level);
> > > +  assert(src_layer < src_mt->level[src_level].depth);
> > > +   }
> > >
> > > -   assert(src_layer < src_mt->level[src_level].depth);
> > > assert(src_mt->format == dst_mt->format);
> > >
> > > if (dst_mt->compressed) {
> > > --
> > > 2.11.0
> > >
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> > >
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[Mesa-dev] [PATCH] radeonsi: fix dumping shader descriptors into ddebug logs

2017-06-16 Thread Marek Olšák 
From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_debug.c | 76 ++---
 1 file changed, 41 insertions(+), 35 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_debug.c 
b/src/gallium/drivers/radeonsi/si_debug.c
index 25c3882..35bfec7 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -378,37 +378,38 @@ static void si_dump_framebuffer(struct si_context *sctx, 
FILE *f)
r600_print_texture_info(sctx->b.screen, rtex, f);
fprintf(f, "\n");
}
 }
 
 typedef unsigned (*slot_remap_func)(unsigned);
 
 static void si_dump_descriptor_list(struct si_descriptors *desc,
const char *shader_name,
const char *elem_name,
+   unsigned element_dw_size,
unsigned num_elements,
slot_remap_func slot_remap,
FILE *f)
 {
unsigned i, j;
 
for (i = 0; i < num_elements; i++) {
-   unsigned dw_offset = slot_remap(i) * desc->element_dw_size;
+   unsigned dw_offset = slot_remap(i) * element_dw_size;
uint32_t *gpu_ptr = desc->gpu_list ? desc->gpu_list : 
desc->list;
const char *list_note = desc->gpu_list ? "GPU list" : "CPU 
list";
uint32_t *cpu_list = desc->list + dw_offset;
uint32_t *gpu_list = gpu_ptr + dw_offset;
 
fprintf(f, COLOR_GREEN "%s%s slot %u (%s):" COLOR_RESET "\n",
shader_name, elem_name, i, list_note);
 
-   switch (desc->element_dw_size) {
+   switch (element_dw_size) {
case 4:
for (j = 0; j < 4; j++)
ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
gpu_list[j], 0x);
break;
case 8:
for (j = 0; j < 8; j++)
ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
gpu_list[j], 0x);
 
@@ -454,59 +455,64 @@ static unsigned si_identity(unsigned slot)
 }
 
 static void si_dump_descriptors(struct si_context *sctx,
enum pipe_shader_type processor,
const struct tgsi_shader_info *info, FILE *f)
 {
struct si_descriptors *descs =
>descriptors[SI_DESCS_FIRST_SHADER +
   processor * SI_NUM_SHADER_DESCS];
static const char *shader_name[] = {"VS", "PS", "GS", "TCS", "TES", 
"CS"};
-
-   static const char *elem_name[] = {
-   " - Constant buffer",
-   " - Shader buffer",
-   " - Sampler",
-   " - Image",
-   };
-   static const slot_remap_func remap_func[] = {
-   si_get_constbuf_slot,
-   si_get_shaderbuf_slot,
-   si_identity,
-   si_identity,
-   };
-   unsigned enabled_slots[] = {
-   sctx->const_and_shader_buffers[processor].enabled_mask >> 
SI_NUM_SHADER_BUFFERS,
-   
util_bitreverse(sctx->const_and_shader_buffers[processor].enabled_mask &
-   u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS)),
-   sctx->samplers[processor].views.enabled_mask,
-   sctx->images[processor].enabled_mask,
-   };
-   unsigned required_slots[] = {
-   info ? info->const_buffers_declared : 0,
-   info ? info->shader_buffers_declared : 0,
-   info ? info->samplers_declared : 0,
-   info ? info->images_declared : 0,
-   };
+   const char *name = shader_name[processor];
+   unsigned enabled_constbuf, enabled_shaderbuf, enabled_samplers;
+   unsigned enabled_images;
+
+   if (info) {
+   enabled_constbuf = info->const_buffers_declared;
+   enabled_shaderbuf = info->shader_buffers_declared;
+   enabled_samplers = info->samplers_declared;
+   enabled_images = info->images_declared;
+   } else {
+   enabled_constbuf = 
sctx->const_and_shader_buffers[processor].enabled_mask >>
+  SI_NUM_SHADER_BUFFERS;
+   enabled_shaderbuf = 
sctx->const_and_shader_buffers[processor].enabled_mask &
+   u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
+   enabled_shaderbuf = util_bitreverse(enabled_shaderbuf) >>
+   (32 - SI_NUM_SHADER_BUFFERS);
+   enabled_samplers = sctx->samplers[processor].views.enabled_mask;
+   enabled_images = sctx->images[processor].enabled_mask;
+   }
 
if (processor ==

Re: [Mesa-dev] [PATCH 9/9] radeonsi: don't do any flushes at the end of IBs

2017-06-16 Thread Marek Olšák 
Please ignore this patch. There are some regressions with
depth_resolve piglit tests.

Marek

On Fri, Jun 16, 2017 at 2:58 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> ---
>  src/gallium/drivers/radeonsi/si_hw_context.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c 
> b/src/gallium/drivers/radeonsi/si_hw_context.c
> index 5d930a6..b420c9f 100644
> --- a/src/gallium/drivers/radeonsi/si_hw_context.c
> +++ b/src/gallium/drivers/radeonsi/si_hw_context.c
> @@ -122,20 +122,23 @@ void si_context_gfx_flush(void *context, unsigned flags,
> }
>
> ctx->gfx_flush_in_progress = true;
>
> /* This CE dump should be done in parallel with the last draw. */
> if (ctx->ce_ib)
> si_ce_save_all_descriptors_at_ib_end(ctx);
>
> r600_preflush_suspend_features(>b);
>
> +   /* The kernel-side fence will flush everything. */
> +   ctx->b.flags = 0;
> +
> /* DRM 3.1.0 doesn't flush TC for VI correctly. */
> if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1) {
> ctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
> SI_CONTEXT_CS_PARTIAL_FLUSH |
> SI_CONTEXT_INV_GLOBAL_L2 |
> SI_CONTEXT_INV_VMEM_L1;
> }
>
> si_emit_cache_flush(ctx);
>
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH 02/15] i965: Add helper for converting isl tiling to bufmgr tiling

2017-06-16 Thread Nanley Chery 
On Fri, Jun 16, 2017 at 07:58:02AM +0300, Pohjolainen, Topi wrote:
> On Thu, Jun 15, 2017 at 05:18:22PM -0700, Nanley Chery wrote:
> > On Tue, Jun 13, 2017 at 05:50:00PM +0300, Topi Pohjolainen wrote:
> > > Signed-off-by: Topi Pohjolainen 
> > > ---
> > >  src/mesa/drivers/dri/i965/intel_blit.h | 13 +
> > >  1 file changed, 13 insertions(+)
> > > 
> > > diff --git a/src/mesa/drivers/dri/i965/intel_blit.h 
> > > b/src/mesa/drivers/dri/i965/intel_blit.h
> > > index 2604417e2d..5e4d1f5eb4 100644
> > > --- a/src/mesa/drivers/dri/i965/intel_blit.h
> > > +++ b/src/mesa/drivers/dri/i965/intel_blit.h
> > > @@ -28,6 +28,19 @@
> > >  
> > >  #include "brw_context.h"
> > >  
> > > +static inline unsigned
> > > +isl_tiling_to_bufmgr_tiling(enum isl_tiling tiling)
> > > +{
> > > +   if (tiling == ISL_TILING_X)
> > > +  return I915_TILING_X;
> > > +
> > > +   if (tiling == ISL_TILING_Y0)
> > 
> > I actually just read the patch where this function is used. Don't we
> > also need to return I915_TILING_Y for ISL_TILING_W? Maybe Jason can
> > confirm.
> 
> These values go to brw_bo_alloc_tiled() -> brw_bo_alloc() ->
> bo_alloc_internal() which only understands Y and X. Therefore W is really
> treated as NONE.
> 

Got it.

> > 
> > > +  return I915_TILING_Y;
> > > +
> > > +   /* All other are unknown to buffer allocator. */
> > 
> > It would seem that we'd like to assert for unexpected values instead of
> > failing silently.
> > 
> > > +   return I915_TILING_NONE;
> > > +}
> > > +
> > >  bool
> > >  intelEmitCopyBlit(struct brw_context *brw,
> > >GLuint cpp,
> > > -- 
> > > 2.11.0
> > > 
> > > ___
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> > > mesa-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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Re: [Mesa-dev] [PATCH 02/15] i965: Add helper for converting isl tiling to bufmgr tiling

2017-06-16 Thread Nanley Chery 
On Thu, Jun 15, 2017 at 06:23:24PM -0700, Jason Ekstrand wrote:
> On Thu, Jun 15, 2017 at 5:18 PM, Nanley Chery  wrote:
> 
> > On Tue, Jun 13, 2017 at 05:50:00PM +0300, Topi Pohjolainen wrote:
> > > Signed-off-by: Topi Pohjolainen 
> > > ---
> > >  src/mesa/drivers/dri/i965/intel_blit.h | 13 +
> > >  1 file changed, 13 insertions(+)
> > >
> > > diff --git a/src/mesa/drivers/dri/i965/intel_blit.h
> > b/src/mesa/drivers/dri/i965/intel_blit.h
> > > index 2604417e2d..5e4d1f5eb4 100644
> > > --- a/src/mesa/drivers/dri/i965/intel_blit.h
> > > +++ b/src/mesa/drivers/dri/i965/intel_blit.h
> > > @@ -28,6 +28,19 @@
> > >
> > >  #include "brw_context.h"
> > >
> > > +static inline unsigned
> > > +isl_tiling_to_bufmgr_tiling(enum isl_tiling tiling)
> > > +{
> > > +   if (tiling == ISL_TILING_X)
> > > +  return I915_TILING_X;
> > > +
> > > +   if (tiling == ISL_TILING_Y0)
> >
> > I actually just read the patch where this function is used. Don't we
> > also need to return I915_TILING_Y for ISL_TILING_W? Maybe Jason can
> > confirm.
> >
> 
> I'd rather the function not lie... Also, most places in the driver today
> that do W-tiling use I915_TILING_NONE.  Yes, I915_TILING_NONE is sort of
> LINEAR but you could also interpret it as LINEAR || UNKNOWN.
> 
> 
> > > +  return I915_TILING_Y;
> > > +
> > > +   /* All other are unknown to buffer allocator. */
> >
> > It would seem that we'd like to assert for unexpected values instead of
> > failing silently.
> >
> 
> I just pulled up my version:
> 
> https://cgit.freedesktop.org/~jekstrand/mesa/commit/?h=wip/i965-ccs-mod-v3=6133059904aeaa7bd6d4ee364014f491f59083e2
> 
> and I went with I915_TILING_NONE there.  The reason I did so was so that
> you could call
> 
> brw_bo_alloc_tiled(brw, name, surf.size,
> isl_tiling_to_i915_tiling(surf.tiling), surf.row_pitch, 0);
> 
> without having to worry about isl_tiling_to_i915_tiling asserting on you.
> 
> The only two things that the tiling is used for are scanout and fenced
> maps.  Even when we enable things like Yf scan-out, we'll probably do it
> through modifiers and not set_tiling.  At that point, the only thing that
> the I915_TILING parameters are actually needed for is doing fenced GTT maps
> (which detile on the fly).  Since you can't do a fenced map of anything
> other than X and Y-tiled,  I don't think we'll ever need to add I915_TILING
> parameters for the others because you can't do a fenced (GTT) map of a Yf,
> Ys, or W-tiled buffer anyway.
> 
> On the other hand, when used in something such as the blit code, asserting
> is probably the right thing to do.  One option would be to add a little
> alloc_bo_for_isl_surf helper which knows to map everything other than X and
> Y to LINEAR and make the general function assert.
> 
> --Jason
> 
> 

Thanks for the feedback!

> > > +   return I915_TILING_NONE;
> > > +}
> > > +
> > >  bool
> > >  intelEmitCopyBlit(struct brw_context *brw,
> > >GLuint cpp,
> > > --
> > > 2.11.0
> > >
> > > ___
> > > mesa-dev mailing list
> > > mesa-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> >
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Re: [Mesa-dev] [PATCH v2 0/3][RFC]mesa/st: glsl_to_tgsi: improved temp-reg lifetime estimation

2017-06-16 Thread Gert Wollny 
Hello Emil, 

Am Freitag, den 16.06.2017, 15:21 +0100 schrieb Emil Velikov:
> 
> Please don't use STL within core mesa code. 
May I ask why? I always try to not re-implement already available
functionality and since mesa already uses C++ it seems kind of natural
to use the STL because it provides a well tested implementation for
containers and algorithms. 

Anyway, to avoid code duplication, are there already alternative
implementations available within mesa for an array that can dynamically
grow like std::vector and std::stack, and for the algorithm
std::upper_bound working on an array?

A couple of additional ideas:
>  - where possible try to split patches even further.
> IIRC 2/3 adds some 2kloc, which may be hard to review properly.
On one hand it seems something went wrong when I was rebasing the
patches, part of 1 ended up in 2 :/

When I correct this patch 2 will add ~1500 lines of which ~700 is real
functionality and ~800 are test code that doesn't go into the library. 
I can probably split out 100 lines though, separating the two parts of
the algorithm.  

>  - do keep performance numbers within the commit summary.
> This way the details are preserved in git log for future references.
Okay.

many thanks for your comments, 
Gert 


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[Mesa-dev] [PATCH] radeonsi: add new polaris12 pci id

2017-06-16 Thread Alex Deucher 
Signed-off-by: Alex Deucher 
Cc: 17.0 17.1 
---
 include/pci_ids/radeonsi_pci_ids.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/pci_ids/radeonsi_pci_ids.h 
b/include/pci_ids/radeonsi_pci_ids.h
index 50f638f..9453c1c 100644
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -213,6 +213,7 @@ CHIPSET(0x6985, POLARIS12_, POLARIS12)
 CHIPSET(0x6986, POLARIS12_, POLARIS12)
 CHIPSET(0x6987, POLARIS12_, POLARIS12)
 CHIPSET(0x6995, POLARIS12_, POLARIS12)
+CHIPSET(0x6997, POLARIS12_, POLARIS12)
 CHIPSET(0x699F, POLARIS12_, POLARIS12)
 
 CHIPSET(0x6860, VEGA10_, VEGA10)
-- 
2.5.5

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Re: [Mesa-dev] [PATCH 11/11] intel: Enable vulkan build for gen10

2017-06-16 Thread Anuj Phogat 
On Thu, Jun 15, 2017 at 4:12 PM, Jason Ekstrand  wrote:
> 7-11 are
>
> Reviewed-by: Jason Ekstrand 
>
Thanks.
> Have you tried reverting my patch and running the CTS?
>
No, I'll do it soon.

> On Tue, Jun 13, 2017 at 11:28 AM, Anuj Phogat  wrote:
>>
>> This patch just enables building Vulkan libs for gen10. We
>> still don't have gen 10 support enabled on Vulkan.
>>
>> Signed-off-by: Anuj Phogat 
>> ---
>>  src/intel/Makefile.sources | 4 
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
>> index a877ff2..2e5dab9 100644
>> --- a/src/intel/Makefile.sources
>> +++ b/src/intel/Makefile.sources
>> @@ -261,3 +261,7 @@ VULKAN_GEN8_FILES := \
>>  VULKAN_GEN9_FILES := \
>> vulkan/gen8_cmd_buffer.c \
>> $(VULKAN_GENX_FILES)
>> +
>> +VULKAN_GEN10_FILES := \
>> +   vulkan/gen8_cmd_buffer.c \
>> +   $(VULKAN_GENX_FILES)
>> --
>> 2.9.3
>>
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[Mesa-dev] [PATCH v2 04/13] intel: common: express timestamps units in frequency

2017-06-16 Thread Lionel Landwerlin 
Rather than storing the period as a double that looses some precision.

Also fixes the Gen9LP timestamp frequency which is no 19200123 but
1920 as pointed by Ville :

https://lists.freedesktop.org/archives/intel-gfx/2017-April/125126.html

Finally add the Cannonlake timestamp frequency.

Signed-off-by: Lionel Landwerlin 
---
 src/intel/common/gen_device_info.c   | 19 ++-
 src/intel/common/gen_device_info.h   |  5 +++--
 src/intel/vulkan/anv_device.c|  2 +-
 src/mesa/drivers/dri/i965/brw_queryobj.c |  2 +-
 4 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index 89a0d9e9e76..14d3761076f 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -36,7 +36,7 @@ static const struct gen_device_info gen_device_info_i965 = {
.urb = {
   .size = 256,
},
-   .timebase_scale = 80,
+   .timestamp_frequency = 1250,
 };
 
 static const struct gen_device_info gen_device_info_g4x = {
@@ -52,7 +52,7 @@ static const struct gen_device_info gen_device_info_g4x = {
.urb = {
   .size = 384,
},
-   .timebase_scale = 80,
+   .timestamp_frequency = 1250,
 };
 
 static const struct gen_device_info gen_device_info_ilk = {
@@ -67,7 +67,7 @@ static const struct gen_device_info gen_device_info_ilk = {
.urb = {
   .size = 1024,
},
-   .timebase_scale = 80,
+   .timestamp_frequency = 1250,
 };
 
 static const struct gen_device_info gen_device_info_snb_gt1 = {
@@ -92,7 +92,7 @@ static const struct gen_device_info gen_device_info_snb_gt1 = 
{
  [MESA_SHADER_GEOMETRY] = 256,
   },
},
-   .timebase_scale = 80,
+   .timestamp_frequency = 1250,
 };
 
 static const struct gen_device_info gen_device_info_snb_gt2 = {
@@ -117,7 +117,7 @@ static const struct gen_device_info gen_device_info_snb_gt2 
= {
  [MESA_SHADER_GEOMETRY] = 256,
   },
},
-   .timebase_scale = 80,
+   .timestamp_frequency = 1250,
 };
 
 #define GEN7_FEATURES   \
@@ -127,7 +127,7 @@ static const struct gen_device_info gen_device_info_snb_gt2 
= {
.has_llc = true, \
.has_pln = true, \
.has_surface_tile_offset = true, \
-   .timebase_scale = 80
+   .timestamp_frequency = 1250
 
 static const struct gen_device_info gen_device_info_ivb_gt1 = {
GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
@@ -300,7 +300,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3 
= {
.max_tes_threads = 504,  \
.max_gs_threads = 504,   \
.max_wm_threads = 384,   \
-   .timebase_scale = 80
+   .timestamp_frequency = 1250
 
 static const struct gen_device_info gen_device_info_bdw_gt1 = {
GEN8_FEATURES, .gt = 1,
@@ -398,7 +398,7 @@ static const struct gen_device_info gen_device_info_chv = {
.max_tcs_threads = 336,  \
.max_tes_threads = 336,  \
.max_cs_threads = 56,\
-   .timebase_scale = 10.0 / 1200.0, \
+   .timestamp_frequency = 1200, \
.urb = { \
   .size = 384,  \
   .min_entries = {  \
@@ -423,7 +423,7 @@ static const struct gen_device_info gen_device_info_chv = {
.max_tes_threads = 112, \
.max_gs_threads = 112,  \
.max_cs_threads = 6 * 6,\
-   .timebase_scale = 10.0 / 19200123.0,\
+   .timestamp_frequency = 1920,\
.urb = {\
   .size = 192, \
   .min_entries = { \
@@ -595,6 +595,7 @@ static const struct gen_device_info gen_device_info_glk_2x6 
= {
.max_tcs_threads = 432,  \
.max_tes_threads = 624,  \
.max_cs_threads = 56,\
+   .timestamp_frequency = 1920, \
.urb = { \
   .size = 256,  \
   .min_entries = {  \
diff --git a/src/intel/common/gen_device_info.h 
b/src/intel/common/gen_device_info.h
index 4a467cca3ef..86daf6e5337 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -26,6 +26,7 @@
 #define GEN_DEVICE_INFO_H
 
 #include 
+#include 
 
 /**
  * Intel hardware information and quirks
@@ -159,7 +160,7 @@ struct gen_device_info
 * corresponded to 80 nanoseconds.
 *
 * Since Gen9 the numbers aren't so round, with a a frequency of 12MHz for
-* SKL (or scale factor of

[Mesa-dev] [PATCH v2 06/13] i965: Add Gen8+ sys_vars for generated OA code

2017-06-16 Thread Lionel Landwerlin 
From: Robert Bragg 

In preparation for adding XML OA metric set descriptions for Gen 8 and 9
which will result in auto generated code that depends on a number of new
system variables ($EuSubslicesTotalCount, $EuThreadsCount and
$SliceMask) this adds corresponding members to brw->perf.sys_vars.

Signed-off-by: Robert Bragg 
Reviewed-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_context.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index cf2c2cbed59..7663cf07e04 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1086,6 +1086,9 @@ struct brw_context
  uint64_t timestamp_frequency; /** $GpuTimestampFrequency */
  uint64_t n_eus;   /** $EuCoresTotalCount */
  uint64_t n_eu_slices; /** $EuSlicesTotalCount */
+ uint64_t n_eu_sub_slices; /** $EuSubslicesTotalCount */
+ uint64_t eu_threads_count;/** $EuThreadsCount */
+ uint64_t slice_mask;  /** $SliceMask */
  uint64_t subslice_mask;   /** $SubsliceMask */
  uint64_t gt_min_freq; /** $GpuMinFrequency */
  uint64_t gt_max_freq; /** $GpuMaxFrequency */
-- 
2.11.0

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[Mesa-dev] [PATCH v2 10/13] i965: perf: ensure isolated timer reports while idle don't confuse filtering

2017-06-16 Thread Lionel Landwerlin 
From: Robert Bragg 

From experimentation in IGT, we found that the OA unit might label
some report as "idle" (using an invalid context ID), right after a
report for a given context. Deltas generated by those reports actually
belong to the previous context, even though they're not labelled as
such.

This change makes ensure that while reading OA reports, we only
consider the GPU actually idle after 2 reports with an invalid context
ID.

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/brw_performance_query.c | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index d816d30032a..f7124ce621f 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -832,6 +832,7 @@ accumulate_oa_reports(struct brw_context *brw,
struct exec_node *first_samples_node;
bool in_ctx = true;
uint32_t ctx_id;
+   int out_duration = 0;
 
assert(o->Ready);
assert(obj->oa.map != NULL);
@@ -903,13 +904,27 @@ accumulate_oa_reports(struct brw_context *brw,
  * of OA counters while any other context is acctive.
  */
 if (brw->gen >= 8) {
+
if (in_ctx && report[2] != ctx_id) {
   DBG("i915 perf: Switch AWAY (observed by ID change)\n");
   in_ctx = false;
+  out_duration = 0;
} else if (in_ctx == false && report[2] == ctx_id) {
   DBG("i915 perf: Switch TO\n");
   in_ctx = true;
-  add = false;
+
+  /* From experimentation in IGT, we found that the OA unit
+   * might label some report as "idle" (using an invalid
+   * context ID), right after a report for a given context.
+   * Deltas generated by those reports actually belong to the
+   * previous context, even though they're not labelled as
+   * such.
+   *
+   * We didn't *really* Switch AWAY in the case that we e.g.
+   * saw a single periodic report while idle...
+   */
+  if (out_duration >= 1)
+ add = false;
} else if (in_ctx) {
   assert(report[2] == ctx_id);
   DBG("i915 perf: Continuation IN\n");
@@ -917,6 +932,7 @@ accumulate_oa_reports(struct brw_context *brw,
   assert(report[2] != ctx_id);
   DBG("i915 perf: Continuation OUT\n");
   add = false;
+  out_duration++;
}
 }
 
-- 
2.11.0

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[Mesa-dev] [PATCH v2 08/13] i965: Add Gen8+ INTEL_performance_query support

2017-06-16 Thread Lionel Landwerlin 
From: Robert Bragg 

Enables access to OA unit metrics on Gen8+ via INTEL_performance_query.

v2: make use of new parameters coming from gen_device_info (Lionel)

Signed-off-by: Robert Bragg 
Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/Makefile.am |   8 +-
 src/mesa/drivers/dri/i965/brw_defines.h   |   1 +
 src/mesa/drivers/dri/i965/brw_performance_query.c | 311 --
 3 files changed, 287 insertions(+), 33 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/Makefile.am 
b/src/mesa/drivers/dri/i965/Makefile.am
index 03cfe12b193..3e09fef2d21 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -116,7 +116,7 @@ EXTRA_DIST = \
 # .c and .h files in one go so we don't hit problems with parallel
 # make and multiple invocations of the same script trying to write
 # to the same files.
-brw_oa_hsw.h: brw_oa.py brw_oa_hsw.xml
-   $(PYTHON2) $(PYTHON_FLAGS) $(srcdir)/brw_oa.py 
--header=$(builddir)/brw_oa_hsw.h --chipset=hsw $(srcdir)/brw_oa_hsw.xml
-brw_oa_hsw.c: brw_oa.py brw_oa_hsw.xml
-   $(PYTHON2) $(PYTHON_FLAGS) $(srcdir)/brw_oa.py 
--code=$(builddir)/brw_oa_hsw.c --chipset=hsw $(srcdir)/brw_oa_hsw.xml
+brw_oa_%.h: brw_oa.py brw_oa_%.xml Makefile.am
+   $(PYTHON2) $(PYTHON_FLAGS) $(srcdir)/brw_oa.py 
--header=$(builddir)/brw_oa_$(*).h --chipset=$(*) $(srcdir)/brw_oa_$(*).xml
+brw_oa_%.c: brw_oa.py brw_oa_%.xml Makefile.am
+   $(PYTHON2) $(PYTHON_FLAGS) $(srcdir)/brw_oa.py 
--code=$(builddir)/brw_oa_$(*).c --chipset=$(*) $(srcdir)/brw_oa_$(*).xml
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 312dddafd77..a4794c6a1d2 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1350,6 +1350,7 @@ enum brw_pixel_shader_coverage_mask_mode {
 
 #define GEN6_MI_REPORT_PERF_COUNT ((0x28 << 23) | (3 - 2))
 
+#define GEN8_MI_REPORT_PERF_COUNT ((0x28 << 23) | (4 - 2))
 
 /* Maximum number of entries that can be addressed using a binding table
  * pointer of type SURFTYPE_BUFFER
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 66128869f4f..dc257165d13 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -72,16 +72,33 @@
 #include "brw_defines.h"
 #include "brw_performance_query.h"
 #include "brw_oa_hsw.h"
+#include "brw_oa_bdw.h"
+#include "brw_oa_chv.h"
+#include "brw_oa_sklgt2.h"
+#include "brw_oa_sklgt3.h"
+#include "brw_oa_sklgt4.h"
+#include "brw_oa_bxt.h"
 #include "intel_batchbuffer.h"
 
 #define FILE_DEBUG_FLAG DEBUG_PERFMON
 
 /*
- * The largest OA format we can use on Haswell includes:
- * 1 timestamp, 45 A counters, 8 B counters and 8 C counters.
+ * The largest OA formats we can use include:
+ * For Haswell:
+ *   1 timestamp, 45 A counters, 8 B counters and 8 C counters.
+ * For Gen8+
+ *   1 timestamp, 1 clock, 36 A counters, 8 B counters and 8 C counters
  */
 #define MAX_OA_REPORT_COUNTERS 62
 
+#define OAREPORT_REASON_MASK   0x3f
+#define OAREPORT_REASON_SHIFT  19
+#define OAREPORT_REASON_TIMER  (1<<0)
+#define OAREPORT_REASON_TRIGGER1   (1<<1)
+#define OAREPORT_REASON_TRIGGER2   (1<<2)
+#define OAREPORT_REASON_CTX_SWITCH (1<<3)
+#define OAREPORT_REASON_GO_TRANSITION  (1<<4)
+
 #define I915_PERF_OA_SAMPLE_SIZE (8 +   /* drm_i915_perf_record_header */ \
   256)  /* OA counter report */
 
@@ -535,9 +552,10 @@ drop_from_unaccumulated_query_list(struct brw_context *brw,
 static uint64_t
 timebase_scale(struct brw_context *brw, uint32_t u32_time_delta)
 {
+   const struct gen_device_info *devinfo = >screen->devinfo;
uint64_t tmp = ((uint64_t)u32_time_delta) * 10ull;
 
-   return tmp ? tmp / brw->perfquery.sys_vars.timestamp_frequency : 0;
+   return tmp ? tmp / devinfo->timestamp_frequency : 0;
 }
 
 static void
@@ -548,6 +566,28 @@ accumulate_uint32(const uint32_t *report0,
*accumulator += (uint32_t)(*report1 - *report0);
 }
 
+static void
+accumulate_uint40(int a_index,
+  const uint32_t *report0,
+  const uint32_t *report1,
+  uint64_t *accumulator)
+{
+   const uint8_t *high_bytes0 = (uint8_t *)(report0 + 40);
+   const uint8_t *high_bytes1 = (uint8_t *)(report1 + 40);
+   uint64_t high0 = (uint64_t)(high_bytes0[a_index]) << 32;
+   uint64_t high1 = (uint64_t)(high_bytes1[a_index]) << 32;
+   uint64_t value0 = report0[a_index + 4] | high0;
+   uint64_t value1 = report1[a_index + 4] | high1;
+   uint64_t delta;
+
+   if (value0 > value1)
+  delta = (1ULL << 40) + value1 - value0;
+   else
+  delta = value1 - value0;
+
+   *accumulator += delta;
+}
+
 /**
  * Given pointers to starting and ending OA snapshots, add the deltas for each
  *

[Mesa-dev] [PATCH v2 11/13] i965: perf: use gen_device_info rather then brw_context

2017-06-16 Thread Lionel Landwerlin 
Signed-off-by: Lionel Landwerlin 
Reviewed-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/brw_performance_query.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index f7124ce621f..fed0bfd8b9b 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -825,6 +825,7 @@ static void
 accumulate_oa_reports(struct brw_context *brw,
   struct brw_perf_query_object *obj)
 {
+   const struct gen_device_info *devinfo = >screen->devinfo;
struct gl_perf_query_object *o = >base;
uint32_t *start;
uint32_t *last;
@@ -903,8 +904,7 @@ accumulate_oa_reports(struct brw_context *brw,
  * For Haswell we can rely on the HW to stop the progress
  * of OA counters while any other context is acctive.
  */
-if (brw->gen >= 8) {
-
+if (devinfo->gen >= 8) {
if (in_ctx && report[2] != ctx_id) {
   DBG("i915 perf: Switch AWAY (observed by ID change)\n");
   in_ctx = false;
@@ -1616,6 +1616,7 @@ add_basic_stat_reg(struct brw_perf_query_info *query,
 static void
 init_pipeline_statistic_query_registers(struct brw_context *brw)
 {
+   const struct gen_device_info *devinfo = >screen->devinfo;
struct brw_perf_query_info *query = append_query_info(brw);
 
query->kind = PIPELINE_STATS;
@@ -1631,7 +1632,7 @@ init_pipeline_statistic_query_registers(struct 
brw_context *brw)
add_basic_stat_reg(query, VS_INVOCATION_COUNT,
   "N vertex shader invocations");
 
-   if (brw->gen == 6) {
+   if (devinfo->gen == 6) {
   add_stat_reg(query, GEN6_SO_PRIM_STORAGE_NEEDED, 1, 1,
"SO_PRIM_STORAGE_NEEDED",
"N geometry shader stream-out primitives (total)");
@@ -1680,7 +1681,7 @@ init_pipeline_statistic_query_registers(struct 
brw_context *brw)
add_basic_stat_reg(query, CL_PRIMITIVES_COUNT,
   "N primitives leaving clipping");
 
-   if (brw->is_haswell || brw->gen == 8)
+   if (devinfo->is_haswell || devinfo->gen == 8)
   add_stat_reg(query, PS_INVOCATION_COUNT, 1, 4,
"N fragment shader invocations",
"N fragment shader invocations");
@@ -1690,7 +1691,7 @@ init_pipeline_statistic_query_registers(struct 
brw_context *brw)
 
add_basic_stat_reg(query, PS_DEPTH_COUNT, "N z-pass fragments");
 
-   if (brw->gen >= 7)
+   if (devinfo->gen >= 7)
   add_basic_stat_reg(query, CS_INVOCATION_COUNT,
  "N compute shader invocations");
 
-- 
2.11.0

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[Mesa-dev] [PATCH v2 00/13] i965: Add performance query OA support on Gen 8 & 9

2017-06-16 Thread Lionel Landwerlin 
Hi,

Here is a v2 following some comments by Ken. Some patches already have
a rb-by/ack-by.

Here is the list that needs looking at : 1, 2, 3, 4, 5 & 8.

The list will probably filter some of the big patches, you can find
the branch there :

https://github.com/djdeath/mesa/commits/wip/djdeath/oa-next

Cheers,

Lionel Landwerlin (9):
  intel: common: add flag to identify platforms by name
  i965: perf: fix codegen with single operand equation
  i965: convert MI_REPORT_PERF_COUNT to genxml
  intel: common: express timestamps units in frequency
  intel: common: add number of thread per eu
  i965: perf: keep on reading reports until delimiting timestamp
  i965: perf: use gen_device_info rather then brw_context
  i965: perf: add support for Kabylake
  i965: perf: add support for Geminilake

Robert Bragg (4):
  i965: Add Gen8+ sys_vars for generated OA code
  i965: Add XML OA metric sets for Gen8+
  i965: Add Gen8+ INTEL_performance_query support
  i965: perf: ensure isolated timer reports while idle don't confuse
filtering

 src/intel/common/gen_device_info.c|69 +-
 src/intel/common/gen_device_info.h|15 +-
 src/intel/vulkan/anv_device.c | 2 +-
 src/mesa/drivers/dri/i965/Makefile.am |17 +-
 src/mesa/drivers/dri/i965/Makefile.sources|20 +-
 src/mesa/drivers/dri/i965/brw_context.h   |14 +
 src/mesa/drivers/dri/i965/brw_defines.h   | 1 +
 src/mesa/drivers/dri/i965/brw_oa.py   | 4 +-
 src/mesa/drivers/dri/i965/brw_oa_bdw.xml  | 15051 
 src/mesa/drivers/dri/i965/brw_oa_bxt.xml  |  9211 
 src/mesa/drivers/dri/i965/brw_oa_chv.xml  |  9569 +
 src/mesa/drivers/dri/i965/brw_oa_glk.xml  |  9124 
 src/mesa/drivers/dri/i965/brw_oa_hsw.xml  |26 +-
 src/mesa/drivers/dri/i965/brw_oa_kblgt2.xml   | 10455 ++
 src/mesa/drivers/dri/i965/brw_oa_kblgt3.xml   | 10500 ++
 src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml   | 10925 ++
 src/mesa/drivers/dri/i965/brw_oa_sklgt3.xml   | 10499 ++
 src/mesa/drivers/dri/i965/brw_oa_sklgt4.xml   | 10522 ++
 src/mesa/drivers/dri/i965/brw_performance_query.c |   511 +-
 src/mesa/drivers/dri/i965/brw_queryobj.c  | 2 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c |18 +
 21 files changed, 96435 insertions(+), 120 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/brw_oa_bdw.xml
 create mode 100644 src/mesa/drivers/dri/i965/brw_oa_bxt.xml
 create mode 100644 src/mesa/drivers/dri/i965/brw_oa_chv.xml
 create mode 100644 src/mesa/drivers/dri/i965/brw_oa_glk.xml
 create mode 100644 src/mesa/drivers/dri/i965/brw_oa_kblgt2.xml
 create mode 100644 src/mesa/drivers/dri/i965/brw_oa_kblgt3.xml
 create mode 100644 src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml
 create mode 100644 src/mesa/drivers/dri/i965/brw_oa_sklgt3.xml
 create mode 100644 src/mesa/drivers/dri/i965/brw_oa_sklgt4.xml

--
2.11.0
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[Mesa-dev] [PATCH v2 01/13] intel: common: add flag to identify platforms by name

2017-06-16 Thread Lionel Landwerlin 
The perf infrastructure needs to identify specific platforms, not just
generations.

Signed-off-by: Lionel Landwerlin 
---
 src/intel/common/gen_device_info.c | 26 --
 src/intel/common/gen_device_info.h |  4 
 2 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index 75284a66419..89a0d9e9e76 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -304,6 +304,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3 
= {
 
 static const struct gen_device_info gen_device_info_bdw_gt1 = {
GEN8_FEATURES, .gt = 1,
+   .is_broadwell = true,
.num_slices = 1,
.l3_banks = 2,
.max_cs_threads = 42,
@@ -324,6 +325,7 @@ static const struct gen_device_info gen_device_info_bdw_gt1 
= {
 
 static const struct gen_device_info gen_device_info_bdw_gt2 = {
GEN8_FEATURES, .gt = 2,
+   .is_broadwell = true,
.num_slices = 1,
.l3_banks = 4,
.max_cs_threads = 56,
@@ -344,6 +346,7 @@ static const struct gen_device_info gen_device_info_bdw_gt2 
= {
 
 static const struct gen_device_info gen_device_info_bdw_gt3 = {
GEN8_FEATURES, .gt = 3,
+   .is_broadwell = true,
.num_slices = 2,
.l3_banks = 8,
.max_cs_threads = 56,
@@ -412,7 +415,6 @@ static const struct gen_device_info gen_device_info_chv = {
 
 #define GEN9_LP_FEATURES   \
GEN9_FEATURES,  \
-   .is_broxton = 1,\
.gt = 1,\
.has_llc = false,   \
.num_slices = 1,\
@@ -463,6 +465,7 @@ static const struct gen_device_info gen_device_info_chv = {
 
 static const struct gen_device_info gen_device_info_skl_gt1 = {
GEN9_FEATURES, .gt = 1,
+   .is_skylake = true,
.num_slices = 1,
.l3_banks = 2,
.urb.size = 192,
@@ -470,18 +473,21 @@ static const struct gen_device_info 
gen_device_info_skl_gt1 = {
 
 static const struct gen_device_info gen_device_info_skl_gt2 = {
GEN9_FEATURES, .gt = 2,
+   .is_skylake = true,
.num_slices = 1,
.l3_banks = 4,
 };
 
 static const struct gen_device_info gen_device_info_skl_gt3 = {
GEN9_FEATURES, .gt = 3,
+   .is_skylake = true,
.num_slices = 2,
.l3_banks = 8,
 };
 
 static const struct gen_device_info gen_device_info_skl_gt4 = {
GEN9_FEATURES, .gt = 4,
+   .is_skylake = true,
.num_slices = 3,
.l3_banks = 12,
/* From the "L3 Allocation and Programming" documentation:
@@ -497,11 +503,13 @@ static const struct gen_device_info 
gen_device_info_skl_gt4 = {
 
 static const struct gen_device_info gen_device_info_bxt = {
GEN9_LP_FEATURES,
+   .is_broxton = true,
.l3_banks = 2,
 };
 
 static const struct gen_device_info gen_device_info_bxt_2x6 = {
GEN9_LP_FEATURES_2X6,
+   .is_broxton = true,
.l3_banks = 1,
 };
 /*
@@ -570,12 +578,14 @@ static const struct gen_device_info 
gen_device_info_kbl_gt4 = {
 
 static const struct gen_device_info gen_device_info_glk = {
GEN9_LP_FEATURES,
+   .is_geminilake = true,
.l3_banks = 2,
 };
 
 /*TODO: Initialize l3_banks when we know the number. */
 static const struct gen_device_info gen_device_info_glk_2x6 = {
-   GEN9_LP_FEATURES_2X6
+   GEN9_LP_FEATURES_2X6,
+   .is_geminilake = true,
 };
 
 #define GEN10_HW_INFO   \
@@ -606,22 +616,26 @@ static const struct gen_device_info 
gen_device_info_glk_2x6 = {
 
 static const struct gen_device_info gen_device_info_cnl_2x8 = {
/* GT0.5 */
-   GEN10_FEATURES(1, 1, 2)
+   GEN10_FEATURES(1, 1, 2),
+   .is_cannonlake = true,
 };
 
 static const struct gen_device_info gen_device_info_cnl_3x8 = {
/* GT1 */
-   GEN10_FEATURES(1, 1, 3)
+   GEN10_FEATURES(1, 1, 3),
+   .is_cannonlake = true,
 };
 
 static const struct gen_device_info gen_device_info_cnl_4x8 = {
/* GT 1.5 */
-   GEN10_FEATURES(1, 2, 6)
+   GEN10_FEATURES(1, 2, 6),
+   .is_cannonlake = true,
 };
 
 static const struct gen_device_info gen_device_info_cnl_5x8 = {
/* GT2 */
-   GEN10_FEATURES(2, 2, 6)
+   GEN10_FEATURES(2, 2, 6),
+   .is_cannonlake = true,
 };
 
 bool
diff --git a/src/intel/common/gen_device_info.h 
b/src/intel/common/gen_device_info.h
index 62076305194..4a467cca3ef 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -39,9 +39,13 @@ struct gen_device_info
bool is_ivybridge;
bool is_baytrail;
bool is_haswell;
+   bool is_broadwell;
bool is_cherryview;
+   bool is_skylake;
bool is_broxton;
bool is_kabylake;
+   bool is_geminilake;
+   bool is_cannonlake;
 
bool has_hiz_and_separate_stencil;
bool must_use_separate_stencil;
-- 
2.11.0

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[Mesa-dev] [PATCH v2 05/13] intel: common: add number of thread per eu

2017-06-16 Thread Lionel Landwerlin 
This will be used by to normalize OA counters.

Signed-off-by: Lionel Landwerlin 
---
 src/intel/common/gen_device_info.c | 24 ++--
 src/intel/common/gen_device_info.h |  6 ++
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index 14d3761076f..423748ea08c 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -30,6 +30,7 @@ static const struct gen_device_info gen_device_info_i965 = {
.gen = 4,
.has_negative_rhw_bug = true,
.num_slices = 1,
+   .num_thread_per_eu = 4,
.max_vs_threads = 16,
.max_gs_threads = 2,
.max_wm_threads = 8 * 4,
@@ -46,6 +47,7 @@ static const struct gen_device_info gen_device_info_g4x = {
.has_surface_tile_offset = true,
.is_g4x = true,
.num_slices = 1,
+   .num_thread_per_eu = 5,
.max_vs_threads = 32,
.max_gs_threads = 2,
.max_wm_threads = 10 * 5,
@@ -61,6 +63,7 @@ static const struct gen_device_info gen_device_info_ilk = {
.has_compr4 = true,
.has_surface_tile_offset = true,
.num_slices = 1,
+   .num_thread_per_eu = 6,
.max_vs_threads = 72,
.max_gs_threads = 32,
.max_wm_threads = 12 * 6,
@@ -79,6 +82,7 @@ static const struct gen_device_info gen_device_info_snb_gt1 = 
{
.has_surface_tile_offset = true,
.needs_unlit_centroid_workaround = true,
.num_slices = 1,
+   .num_thread_per_eu = 6, /* Not confirmed */
.max_vs_threads = 24,
.max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
.max_wm_threads = 40,
@@ -104,6 +108,7 @@ static const struct gen_device_info gen_device_info_snb_gt2 
= {
.has_surface_tile_offset = true,
.needs_unlit_centroid_workaround = true,
.num_slices = 1,
+   .num_thread_per_eu = 6, /* Not confirmed */
.max_vs_threads = 60,
.max_gs_threads = 60,
.max_wm_threads = 80,
@@ -132,6 +137,7 @@ static const struct gen_device_info gen_device_info_snb_gt2 
= {
 static const struct gen_device_info gen_device_info_ivb_gt1 = {
GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
.num_slices = 1,
+   .num_thread_per_eu = 6,
.l3_banks = 2,
.max_vs_threads = 36,
.max_tcs_threads = 36,
@@ -157,6 +163,8 @@ static const struct gen_device_info gen_device_info_ivb_gt1 
= {
 static const struct gen_device_info gen_device_info_ivb_gt2 = {
GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
.num_slices = 1,
+   .num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
+* @max_wm_threads ... */
.l3_banks = 4,
.max_vs_threads = 128,
.max_tcs_threads = 128,
@@ -182,6 +190,7 @@ static const struct gen_device_info gen_device_info_ivb_gt2 
= {
 static const struct gen_device_info gen_device_info_byt = {
GEN7_FEATURES, .is_baytrail = true, .gt = 1,
.num_slices = 1,
+   .num_thread_per_eu = 8,
.l3_banks = 1,
.has_llc = false,
.max_vs_threads = 36,
@@ -214,6 +223,7 @@ static const struct gen_device_info gen_device_info_byt = {
 static const struct gen_device_info gen_device_info_hsw_gt1 = {
HSW_FEATURES, .gt = 1,
.num_slices = 1,
+   .num_thread_per_eu = 7,
.l3_banks = 2,
.max_vs_threads = 70,
.max_tcs_threads = 70,
@@ -239,6 +249,7 @@ static const struct gen_device_info gen_device_info_hsw_gt1 
= {
 static const struct gen_device_info gen_device_info_hsw_gt2 = {
HSW_FEATURES, .gt = 2,
.num_slices = 1,
+   .num_thread_per_eu = 7,
.l3_banks = 4,
.max_vs_threads = 280,
.max_tcs_threads = 256,
@@ -264,6 +275,7 @@ static const struct gen_device_info gen_device_info_hsw_gt2 
= {
 static const struct gen_device_info gen_device_info_hsw_gt3 = {
HSW_FEATURES, .gt = 3,
.num_slices = 2,
+   .num_thread_per_eu = 7,
.l3_banks = 8,
.max_vs_threads = 280,
.max_tcs_threads = 256,
@@ -306,6 +318,7 @@ static const struct gen_device_info gen_device_info_bdw_gt1 
= {
GEN8_FEATURES, .gt = 1,
.is_broadwell = true,
.num_slices = 1,
+   .num_thread_per_eu = 7,
.l3_banks = 2,
.max_cs_threads = 42,
.urb = {
@@ -327,6 +340,7 @@ static const struct gen_device_info gen_device_info_bdw_gt2 
= {
GEN8_FEATURES, .gt = 2,
.is_broadwell = true,
.num_slices = 1,
+   .num_thread_per_eu = 7,
.l3_banks = 4,
.max_cs_threads = 56,
.urb = {
@@ -348,6 +362,7 @@ static const struct gen_device_info gen_device_info_bdw_gt3 
= {
GEN8_FEATURES, .gt = 3,
.is_broadwell = true,
.num_slices = 2,
+   .num_thread_per_eu = 7,
.l3_banks = 8,
.max_cs_threads = 56,
.urb = {
@@ -369,6 +384,7 @@ static const struct gen_device_info gen_device_info_chv = {
GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
.has_llc = false,
.num_slices = 1,
+   .num_thread_per_eu = 7,
.l3_banks = 2,
.max_vs_threads = 80,
.max_tcs_threads = 80,
@@ -414,10 +430,12 @@ static const struct gen_device_info gen_device_info_chv = 
{
}

[Mesa-dev] [PATCH v2 02/13] i965: perf: fix codegen with single operand equation

2017-06-16 Thread Lionel Landwerlin 
We did support single value operand equations, but not single variable
operand ones. In particular we were failing on "$Sampler0Bottleneck".

Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_oa.py | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_oa.py 
b/src/mesa/drivers/dri/i965/brw_oa.py
index bf950b140da..254c512a7da 100644
--- a/src/mesa/drivers/dri/i965/brw_oa.py
+++ b/src/mesa/drivers/dri/i965/brw_oa.py
@@ -214,7 +214,9 @@ def output_rpn_equation_code(set, counter, equation, 
counter_vars):
 value = stack[-1]
 
 if value in hw_vars:
-value = hw_vars[value];
+value = hw_vars[value]
+if value in counter_vars:
+value = read_funcs[value[1:]] + "(brw, query, accumulator)"
 
 c("\nreturn " + value + ";")
 
-- 
2.11.0

___
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mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 09/13] i965: perf: keep on reading reports until delimiting timestamp

2017-06-16 Thread Lionel Landwerlin 
Due to an underlying hardware race condition, we have no guarantee
that all the reports coming from the OA buffer related to the workload
we're trying to measure have landed to memory by the time all the work
submitted has completed. That means we need to keep on reading the OA
stream until we read a report with a timestamp more recent than the
timestamp recored by the MI_REPORT_PERF_COUNT at the end of the
performance query.

v2: fix uninitialized offset variable to 0 (Lionel)

v3: rework the reading to avoid blocking the user of the API unless
requested (Rob)

v4: fix a bug that makes the i965 driver reading the perf stream when
not necessary, leading to very long counter accumulation times
(Lionel)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/brw_performance_query.c | 133 ++
 1 file changed, 113 insertions(+), 20 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index dc257165d13..d816d30032a 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -219,6 +219,7 @@ struct brw_oa_sample_buf {
int refcount;
int len;
uint8_t buf[I915_PERF_OA_SAMPLE_SIZE * 10];
+   uint32_t last_timestamp;
 };
 
 /**
@@ -244,6 +245,11 @@ struct brw_perf_query_object
  struct brw_bo *bo;
 
  /**
+  * Address of mapped of @bo
+  */
+ void *map;
+
+ /**
   * The MI_REPORT_PERF_COUNT command lets us specify a unique
   * ID that will be reflected in the resulting OA report
   * that's written by the GPU. This is the ID we're expecting
@@ -681,11 +687,26 @@ discard_all_queries(struct brw_context *brw)
}
 }
 
-static bool
-read_oa_samples(struct brw_context *brw)
+enum OaReadStatus {
+   OA_READ_STATUS_ERROR,
+   OA_READ_STATUS_UNFINISHED,
+   OA_READ_STATUS_FINISHED,
+};
+
+static enum OaReadStatus
+read_oa_samples_until(struct brw_context *brw,
+  uint32_t start_timestamp,
+  uint32_t end_timestamp)
 {
+   struct exec_node *tail_node =
+  exec_list_get_tail(>perfquery.sample_buffers);
+   struct brw_oa_sample_buf *tail_buf =
+  exec_node_data(struct brw_oa_sample_buf, tail_node, link);
+   uint32_t last_timestamp = tail_buf->last_timestamp;
+
while (1) {
   struct brw_oa_sample_buf *buf = get_free_sample_buf(brw);
+  uint32_t offset;
   int len;
 
   while ((len = read(brw->perfquery.oa_stream_fd, buf->buf,
@@ -697,28 +718,94 @@ read_oa_samples(struct brw_context *brw)
 
  if (len < 0) {
 if (errno == EAGAIN)
-   return true;
+   return ((last_timestamp - start_timestamp) >=
+   (end_timestamp - start_timestamp)) ?
+  OA_READ_STATUS_FINISHED :
+  OA_READ_STATUS_UNFINISHED;
 else {
DBG("Error reading i915 perf samples: %m\n");
-   return false;
 }
- } else {
+ } else
 DBG("Spurious EOF reading i915 perf samples\n");
-return false;
- }
+
+ return OA_READ_STATUS_ERROR;
   }
 
   buf->len = len;
   exec_list_push_tail(>perfquery.sample_buffers, >link);
+
+  /* Go through the reports and update the last timestamp. */
+  offset = 0;
+  while (offset < buf->len) {
+ const struct drm_i915_perf_record_header *header =
+(const struct drm_i915_perf_record_header *) >buf[offset];
+ uint32_t *report = (uint32_t *) (header + 1);
+
+ if (header->type == DRM_I915_PERF_RECORD_SAMPLE)
+last_timestamp = report[1];
+
+ offset += header->size;
+  }
+
+  buf->last_timestamp = last_timestamp;
}
 
unreachable("not reached");
+   return OA_READ_STATUS_ERROR;
+}
+
+/**
+ * Try to read all the reports until either the delimiting timestamp
+ * or an error arises.
+ */
+static bool
+read_oa_samples_for_query(struct brw_context *brw,
+  struct brw_perf_query_object *obj)
+{
+   uint32_t *start;
+   uint32_t *last;
+   uint32_t *end;
+
+   /* We need the MI_REPORT_PERF_COUNT to land before we can start
+* accumulate. */
+   assert(!brw_batch_references(>batch, obj->oa.bo) &&
+  !brw_bo_busy(obj->oa.bo));
+
+   /* Map the BO once here and let accumulate_oa_reports() unmap
+* it. */
+   if (obj->oa.map == NULL)
+  obj->oa.map = brw_bo_map(brw, obj->oa.bo, MAP_READ);
+
+   start = last = obj->oa.map;
+   end = obj->oa.map + MI_RPC_BO_END_OFFSET_BYTES;
+
+   if (start[0] != obj->oa.begin_report_id) {
+  DBG("Spurious start report id=%"PRIu32"\n", start[0]);
+  return true;
+   }
+   if (end[0] != (obj->oa.begin_report_id + 1)) {
+  DBG("Spurious end report id=%"PRIu32"\n",

[Mesa-dev] [PATCH v2 03/13] i965: convert MI_REPORT_PERF_COUNT to genxml

2017-06-16 Thread Lionel Landwerlin 
Also make it available from gen7 only to gen7+.

Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_context.h   | 11 
 src/mesa/drivers/dri/i965/brw_performance_query.c | 33 ---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 18 +
 3 files changed, 34 insertions(+), 28 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index b1374092bac..cf2c2cbed59 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -642,6 +642,17 @@ struct brw_context
  uint32_t width, uint32_t height,
  uint32_t tile_x, uint32_t tile_y);
 
+  /**
+   * Emit an MI_REPORT_PERF_COUNT command packet.
+   *
+   * This asks the GPU to write a report of the current OA counter values
+   * into @bo at the given offset and containing the given @report_id
+   * which we can cross-reference when parsing the report (gen7+ only).
+   */
+  void (*emit_mi_report_perf_count)(struct brw_context *brw,
+struct brw_bo *bo,
+uint32_t offset_in_bytes,
+uint32_t report_id);
} vtbl;
 
struct brw_bufmgr *bufmgr;
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 1c9ddf52ea3..66128869f4f 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -468,29 +468,6 @@ snapshot_statistics_registers(struct brw_context *brw,
 }
 
 /**
- * Emit an MI_REPORT_PERF_COUNT command packet.
- *
- * This asks the GPU to write a report of the current OA counter
- * values into @bo at the given offset and containing the given
- * @report_id which we can cross-reference when parsing the report.
- */
-static void
-emit_mi_report_perf_count(struct brw_context *brw,
-  struct brw_bo *bo,
-  uint32_t offset_in_bytes,
-  uint32_t report_id)
-{
-   assert(offset_in_bytes % 64 == 0);
-
-   BEGIN_BATCH(3);
-   OUT_BATCH(GEN6_MI_REPORT_PERF_COUNT);
-   OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset_in_bytes);
-   OUT_BATCH(report_id);
-   ADVANCE_BATCH();
-}
-
-/**
  * Add a query to the global list of "unaccumulated queries."
  *
  * Queries are tracked here until all the associated OA reports have
@@ -1001,8 +978,8 @@ brw_begin_perf_query(struct gl_context *ctx,
   brw->perfquery.next_query_start_report_id += 2;
 
   /* Take a starting OA counter snapshot. */
-  emit_mi_report_perf_count(brw, obj->oa.bo, 0,
-obj->oa.begin_report_id);
+  brw->vtbl.emit_mi_report_perf_count(brw, obj->oa.bo, 0,
+  obj->oa.begin_report_id);
   ++brw->perfquery.n_active_oa_queries;
 
   /* No already-buffered samples can possibly be associated with this query
@@ -1081,9 +1058,9 @@ brw_end_perf_query(struct gl_context *ctx,
*/
   if (!obj->oa.results_accumulated) {
  /* Take an ending OA counter snapshot. */
- emit_mi_report_perf_count(brw, obj->oa.bo,
-   MI_RPC_BO_END_OFFSET_BYTES,
-   obj->oa.begin_report_id + 1);
+ brw->vtbl.emit_mi_report_perf_count(brw, obj->oa.bo,
+ MI_RPC_BO_END_OFFSET_BYTES,
+ obj->oa.begin_report_id + 1);
   }
 
   --brw->perfquery.n_active_oa_queries;
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index a5ad2ca4739..9a509240b5b 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -4145,6 +4145,22 @@ static const struct brw_tracked_state genX(vf_topology) 
= {
 
 /* -- */
 
+#if GEN_GEN >= 7
+static void
+genX(emit_mi_report_perf_count)(struct brw_context *brw,
+struct brw_bo *bo,
+uint32_t offset_in_bytes,
+uint32_t report_id)
+{
+   brw_batch_emit(brw, GENX(MI_REPORT_PERF_COUNT), mi_rpc) {
+  mi_rpc.MemoryAddress = instruction_bo(bo, offset_in_bytes);
+  mi_rpc.ReportID = report_id;
+   }
+}
+#endif
+
+/* -- */
+
 void
 genX(init_atoms)(struct brw_context *brw)
 {
@@ -4480,5 +4496,7 @@ genX(init_atoms)(struct brw_context *brw)
STATIC_ASSERT(ARRAY_SIZE(compute_atoms) <= ARRAY_SIZE(brw->compute_atoms));
brw_copy_pipeline_atoms(brw,

[Mesa-dev] [PATCH 1/2] vc4: Switch back to using a local copy of vc4_drm.h.

2017-06-16 Thread Eric Anholt 
Needing to get our uapi header from libdrm has only complicated things.
Follow intel's lead and drop our requirement for it.

Generated from 056f4f02abb7e9e4a0cf0cda0211586df5e43842 of drm-misc-next
---

Sending this patch to the list due to touching configure.ac.

 configure.ac |   2 -
 src/gallium/drivers/vc4/Makefile.am  |   3 +-
 src/gallium/drivers/vc4/Makefile.sources |   1 +
 src/gallium/drivers/vc4/vc4_drm.h| 318 +++
 4 files changed, 320 insertions(+), 4 deletions(-)
 create mode 100644 src/gallium/drivers/vc4/vc4_drm.h

diff --git a/configure.ac b/configure.ac
index ce501aef4d2b..d3d79ad18e49 100644
--- a/configure.ac
+++ b/configure.ac
@@ -79,7 +79,6 @@ LIBDRM_INTEL_REQUIRED=2.4.75
 LIBDRM_NVVIEUX_REQUIRED=2.4.66
 LIBDRM_NOUVEAU_REQUIRED=2.4.66
 LIBDRM_FREEDRENO_REQUIRED=2.4.74
-LIBDRM_VC4_REQUIRED=2.4.69
 LIBDRM_ETNAVIV_REQUIRED=2.4.80
 
 dnl Versions for external dependencies
@@ -2494,7 +2493,6 @@ if test -n "$with_gallium_drivers"; then
 ;;
 xvc4)
 HAVE_GALLIUM_VC4=yes
-PKG_CHECK_MODULES([VC4], [libdrm >= $LIBDRM_VC4_REQUIRED 
libdrm_vc4 >= $LIBDRM_VC4_REQUIRED])
 require_libdrm "vc4"
 
 PKG_CHECK_MODULES([SIMPENROSE], [simpenrose],
diff --git a/src/gallium/drivers/vc4/Makefile.am 
b/src/gallium/drivers/vc4/Makefile.am
index 0ed49b128b2d..3146b74c3f44 100644
--- a/src/gallium/drivers/vc4/Makefile.am
+++ b/src/gallium/drivers/vc4/Makefile.am
@@ -29,7 +29,6 @@ endif
 AM_CFLAGS = \
-I$(top_builddir)/src/compiler/nir \
$(LIBDRM_CFLAGS) \
-   $(VC4_CFLAGS) \
$(GALLIUM_DRIVER_CFLAGS) \
$(SIM_CFLAGS) \
$(VALGRIND_CFLAGS) \
@@ -38,7 +37,7 @@ AM_CFLAGS = \
 noinst_LTLIBRARIES = libvc4.la
 
 libvc4_la_SOURCES = $(C_SOURCES)
-libvc4_la_LIBADD = $(SIM_LIB) $(VC4_LIBS)
+libvc4_la_LIBADD = $(SIM_LIB)
 libvc4_la_LDFLAGS = $(SIM_LDFLAGS)
 
 EXTRA_DIST = kernel/README
diff --git a/src/gallium/drivers/vc4/Makefile.sources 
b/src/gallium/drivers/vc4/Makefile.sources
index 442d7a561782..ef8bb6269795 100644
--- a/src/gallium/drivers/vc4/Makefile.sources
+++ b/src/gallium/drivers/vc4/Makefile.sources
@@ -14,6 +14,7 @@ C_SOURCES := \
vc4_context.c \
vc4_context.h \
vc4_draw.c \
+   vc4_drm.h \
vc4_emit.c \
vc4_fence.c \
vc4_formats.c \
diff --git a/src/gallium/drivers/vc4/vc4_drm.h 
b/src/gallium/drivers/vc4/vc4_drm.h
new file mode 100644
index ..0caeaf3a1f24
--- /dev/null
+++ b/src/gallium/drivers/vc4/vc4_drm.h
@@ -0,0 +1,318 @@
+/*
+ * Copyright © 2014-2015 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef _VC4_DRM_H_
+#define _VC4_DRM_H_
+
+#include "drm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define DRM_VC4_SUBMIT_CL 0x00
+#define DRM_VC4_WAIT_SEQNO0x01
+#define DRM_VC4_WAIT_BO   0x02
+#define DRM_VC4_CREATE_BO 0x03
+#define DRM_VC4_MMAP_BO   0x04
+#define DRM_VC4_CREATE_SHADER_BO  0x05
+#define DRM_VC4_GET_HANG_STATE0x06
+#define DRM_VC4_GET_PARAM 0x07
+#define DRM_VC4_SET_TILING0x08
+#define DRM_VC4_GET_TILING0x09
+
+#define DRM_IOCTL_VC4_SUBMIT_CL   DRM_IOWR(DRM_COMMAND_BASE + 
DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
+#define DRM_IOCTL_VC4_WAIT_SEQNO  DRM_IOWR(DRM_COMMAND_BASE + 
DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
+#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + 
DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
+#define DRM_IOCTL_VC4_CREATE_BO   DRM_IOWR(DRM_COMMAND_BASE + 
DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
+#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE +

[Mesa-dev] [PATCH 2/2] vc4: Set shareable BOs as T tiled if possible.

2017-06-16 Thread Eric Anholt 
X11 and GL compositor performance on VC4 has been terrible because of our
SHARED-usage buffers all being forced to linear.  This swaps SHARED &&
!LINEAR buffers over to being tiled.

This is an expected win for all GL compositors during rendering (a full
copy of each shared texture per draw call), allows X11 to be used with
decent performance without a GL compositor, and improves X11 windowed
swapbuffers performance as well.  It also halves the memory usage of
shared buffers that get textured from.  The only cost should be idle
systems with a scanout-only buffer that isn't flagged as LINEAR, in which
case the memory bandwidth cost of scanout goes up ~25%.
---
 src/gallium/drivers/vc4/vc4_bufmgr.c|   7 ++
 src/gallium/drivers/vc4/vc4_resource.c  | 111 ++--
 src/gallium/drivers/vc4/vc4_simulator.c |   8 +++
 3 files changed, 93 insertions(+), 33 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_bufmgr.c 
b/src/gallium/drivers/vc4/vc4_bufmgr.c
index 12af7f8a9ef2..25e95ff3c50f 100644
--- a/src/gallium/drivers/vc4/vc4_bufmgr.c
+++ b/src/gallium/drivers/vc4/vc4_bufmgr.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "util/u_hash_table.h"
 #include "util/u_memory.h"
@@ -282,6 +283,12 @@ vc4_bo_last_unreference_locked_timed(struct vc4_bo *bo, 
time_t time)
 return;
 }
 
+struct drm_vc4_set_tiling set_tiling = {
+.handle = bo->handle,
+.modifier = DRM_FORMAT_MOD_NONE,
+};
+(void)vc4_ioctl(screen->fd, DRM_IOCTL_VC4_SET_TILING, _tiling);
+
 if (cache->size_list_size <= page_index) {
 struct list_head *new_list =
 ralloc_array(screen, struct list_head, page_index + 1);
diff --git a/src/gallium/drivers/vc4/vc4_resource.c 
b/src/gallium/drivers/vc4/vc4_resource.c
index 5aaa31d6e67d..2ff7f8b08dbe 100644
--- a/src/gallium/drivers/vc4/vc4_resource.c
+++ b/src/gallium/drivers/vc4/vc4_resource.c
@@ -29,10 +29,12 @@
 #include "util/u_surface.h"
 #include "util/u_upload_mgr.h"
 
+#include "vc4_drm.h"
 #include "vc4_screen.h"
 #include "vc4_context.h"
 #include "vc4_resource.h"
 #include "vc4_tiling.h"
+#include "drm_fourcc.h"
 
 static bool miptree_debug = false;
 
@@ -575,27 +577,67 @@ vc4_resource_create(struct pipe_screen *pscreen,
 struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl);
 struct pipe_resource *prsc = >base;
 
-/* We have to make shared be untiled, since we don't have any way to
- * communicate metadata about tiling currently.
+/* Use a tiled layout if we can, for better 3D performance. */
+rsc->tiled = true;
+
+/* VBOs/PBOs are untiled (and 1 height). */
+if (tmpl->target == PIPE_BUFFER)
+rsc->tiled = false;
+
+/* MSAA buffers are linear. */
+if (tmpl->nr_samples > 1)
+rsc->tiled = false;
+
+/* No tiling when we're sharing with another device (pl111). */
+if (screen->ro && (tmpl->bind & PIPE_BIND_SCANOUT))
+rsc->tiled = false;
+
+/* Cursors are always linear, and the user can request linear as
+ * well.
  */
-if (tmpl->target == PIPE_BUFFER ||
-tmpl->nr_samples > 1 ||
-(tmpl->bind & (PIPE_BIND_SCANOUT |
-   PIPE_BIND_LINEAR |
-   PIPE_BIND_SHARED |
-   PIPE_BIND_CURSOR))) {
+if (tmpl->bind & (PIPE_BIND_LINEAR |
+  PIPE_BIND_CURSOR)) {
 rsc->tiled = false;
-} else {
-rsc->tiled = true;
 }
 
-if (tmpl->target != PIPE_BUFFER)
-rsc->vc4_format = get_resource_texture_format(prsc);
+/* No shared objects with LT format -- the kernel only has T-format
+ * metadata.  LT objects are small enough it's not worth the trouble
+ * to give them metadata to tile.
+ */
+if ((tmpl->bind & PIPE_BIND_SHARED) &&
+vc4_size_is_lt(prsc->width0, prsc->height0, rsc->cpp)) {
+rsc->tiled = false;
+}
 
 vc4_setup_slices(rsc);
 if (!vc4_resource_bo_alloc(rsc))
 goto fail;
 
+if (tmpl->bind & PIPE_BIND_SHARED) {
+assert(rsc->slices[0].tiling == VC4_TILING_FORMAT_T);
+
+struct drm_vc4_set_tiling set_tiling = {
+.handle = rsc->bo->handle,
+.modifier = DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
+};
+int ret = vc4_ioctl(screen->fd,
+DRM_IOCTL_VC4_SET_TILING,
+_tiling);
+
+/* If we hit this, we're probably on an old kernel.  Fall back
+ * to linear.
+ */
+if (ret != 0) {
+rsc->tiled = false;
+

Re: [Mesa-dev] [PATCH 2/2] ac/sid.h: don't use parentheses in PKT3_RELEASE_MEM definition

2017-06-16 Thread Alex Deucher 
On Fri, Jun 16, 2017 at 8:30 AM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> The parses skips the line if it contains parentheses.

Series is:
Reviewed-by: Alex Deucher 

> ---
>  src/amd/common/sid.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
> index c69f4f6..a8c78c1 100644
> --- a/src/amd/common/sid.h
> +++ b/src/amd/common/sid.h
> @@ -163,21 +163,21 @@
>  #define PKT3_ME_INITIALIZE 0x44 /* not on CIK */
>  #define PKT3_COND_WRITE0x45
>  #define PKT3_EVENT_WRITE   0x46
>  #define PKT3_EVENT_WRITE_EOP   0x47 /* not on GFX9 */
>  /* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets
>   * are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and
>   * DST_SEL=MC. Only CIK chips are affected.
>   */
>  /* fix CP DMA before uncommenting: */
>  /*#define PKT3_EVENT_WRITE_EOS   0x48*/ /* not on GFX9 */
> -#define PKT3_RELEASE_MEM   0x49 /* GFX9+ (any ring) or 
> GFX8 (compute ring only) */
> +#define PKT3_RELEASE_MEM   0x49 /* GFX9+ [any ring] or 
> GFX8 [compute ring only] */
>  #define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */
>  #define PKT3_ACQUIRE_MEM   0x58 /* new for CIK */
>  #define PKT3_SET_CONFIG_REG0x68
>  #define PKT3_SET_CONTEXT_REG   0x69
>  #define PKT3_SET_SH_REG0x76
>  #define PKT3_SET_SH_REG_OFFSET 0x77
>  #define PKT3_SET_UCONFIG_REG   0x79 /* new for CIK */
>  #define PKT3_LOAD_CONST_RAM0x80
>  #define PKT3_WRITE_CONST_RAM   0x81
>  #define PKT3_DUMP_CONST_RAM0x83
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH v1 5/7] android: enable texture-float

2017-06-16 Thread Emil Velikov 
On 16 June 2017 at 15:45, Matt Turner  wrote:
> On Fri, Jun 16, 2017 at 6:18 AM, Emil Velikov  
> wrote:
>> On 15 June 2017 at 21:47, Robert Foss  wrote:
>>> From: Rob Herring 
>>>
>>> This is required by freedreno at least for GLES3 support.
>>>
>>> See docs/patents.txt for information about turning this on for s/w
>>> renderers.
>>>
>> I'm inclined to agree with Tapani. We're not lawyers and with the
>> patent expiring in half a year, I think we can defer this toggle to
>> builders and their legal teams ;-)
>
> It's not expiring in half a year.
>
> ARB_texture_float references US Patent #6,650,327 [1]: which was filed
> June 16 1998.
>
> According to [2], the patent expires 20 years from the filing date,
> giving an expiration of June 17 2018. So, 1 year and 1 day.
>
> And for good measure, the patent on S3TC [3] expires Oct 2 2017. I
> think we should have a party :)
>
Apologies for the mix up and thanks for the correction Matt. A S3TC
goodbye party sounds like a plan ;-)

-Emil
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Re: [Mesa-dev] [PATCH v1 5/7] android: enable texture-float

2017-06-16 Thread Matt Turner 
On Fri, Jun 16, 2017 at 6:18 AM, Emil Velikov  wrote:
> On 15 June 2017 at 21:47, Robert Foss  wrote:
>> From: Rob Herring 
>>
>> This is required by freedreno at least for GLES3 support.
>>
>> See docs/patents.txt for information about turning this on for s/w
>> renderers.
>>
> I'm inclined to agree with Tapani. We're not lawyers and with the
> patent expiring in half a year, I think we can defer this toggle to
> builders and their legal teams ;-)

It's not expiring in half a year.

ARB_texture_float references US Patent #6,650,327 [1]: which was filed
June 16 1998.

According to [2], the patent expires 20 years from the filing date,
giving an expiration of June 17 2018. So, 1 year and 1 day.

And for good measure, the patent on S3TC [3] expires Oct 2 2017. I
think we should have a party :)

[1] https://www.google.com/patents/US6650327
[2] https://en.wikipedia.org/wiki/Term_of_patent_in_the_United_States
[3] https://www.google.com/patents/US6775417
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Re: [Mesa-dev] [PATCH v1 5/7] android: enable texture-float

2017-06-16 Thread Emil Velikov 
On 16 June 2017 at 15:30, Rob Clark  wrote:
> On Fri, Jun 16, 2017 at 9:49 AM, Emil Velikov  
> wrote:
>> On 16 June 2017 at 14:25, Rob Clark  wrote:
>>> On Fri, Jun 16, 2017 at 9:18 AM, Emil Velikov  
>>> wrote:
 On 15 June 2017 at 21:47, Robert Foss  wrote:
> From: Rob Herring 
>
> This is required by freedreno at least for GLES3 support.
>
> See docs/patents.txt for information about turning this on for s/w
> renderers.
>
 I'm inclined to agree with Tapani. We're not lawyers and with the
 patent expiring in half a year, I think we can defer this toggle to
 builders and their legal teams ;-)

>>>
>>> Not really sure what msg from Tapani you are referring to.  But tbh,
>>> what we really want is a separate option for sw renderers.
>>>
>> This quote from the cover letter
>> "I'm not sure about patch to enable texture-float, should this be left
>> as a 'policy decision' for end distribution, it's not enabled by
>> default on desktop?"
>
> I think the only reason it isn't enabled by default is because
> (currently) the same option covers both hw drivers and sw drivers.
> Otoh, i965 ignores this option and always advertised texture-float.
>
> Anyways, if android has some way to conditionalize this based on some
> var set in board file, that might be an option.  Ideally I think we
> want to get to the point where we can build android with upstream
> mesa, without having to carry patches.
>
Fully support the zero patches topic. Yet since none of us is a lawyer
so it's understandable to be cautious ;-)
If people agree to enable it for non SW drivers, be that like i965 or
otherwise, let's have that consistent across Mesa.

Emil
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Re: [Mesa-dev] [RFC 13/22] RFC: vulkan: Update registry for MESAX dma_buf extensions

2017-06-16 Thread Emil Velikov 
Hi gents,

On 8 June 2017 at 19:44, Daniel Stone  wrote:

>   - VK_MESAX_external_memory_dma_buf
>   - VK_MESAX_external_image_dma_buf
Perhaps not so crazy idea:

Considering a handful of the people involved (Collabora, Google,
Intel) are Khronos members, it should be possible to have the
extensions as EXT as opposed to MESA. Just something to consider as
the extensions are going through the process.

-Emil
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[Mesa-dev] [Bug 101467] swr driver leaks memory (texture management)

2017-06-16 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=101467

Bug ID: 101467
   Summary: swr driver leaks memory (texture management)
   Product: Mesa
   Version: 17.1
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Gallium/swr
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: ago...@igalia.com
QA Contact: mesa-dev@lists.freedesktop.org

This is, basically, the same report than bug 23530.

If you run the piglit test to check above's bug with the swr driver, oom-killer
kicks in:
https://cgit.freedesktop.org/piglit/tree/tests/texturing/streaming-texture-leak.c

My command line is something like:
$ LIBGL_ALWAYS_SOFTWARE=1 GALLIUM_DRIVER=swr
/home/local/piglit/bin/streaming-texture-leak -auto

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Re: [Mesa-dev] [PATCH v1 5/7] android: enable texture-float

2017-06-16 Thread Rob Clark 
On Fri, Jun 16, 2017 at 9:49 AM, Emil Velikov  wrote:
> On 16 June 2017 at 14:25, Rob Clark  wrote:
>> On Fri, Jun 16, 2017 at 9:18 AM, Emil Velikov  
>> wrote:
>>> On 15 June 2017 at 21:47, Robert Foss  wrote:
 From: Rob Herring 

 This is required by freedreno at least for GLES3 support.

 See docs/patents.txt for information about turning this on for s/w
 renderers.

>>> I'm inclined to agree with Tapani. We're not lawyers and with the
>>> patent expiring in half a year, I think we can defer this toggle to
>>> builders and their legal teams ;-)
>>>
>>
>> Not really sure what msg from Tapani you are referring to.  But tbh,
>> what we really want is a separate option for sw renderers.
>>
> This quote from the cover letter
> "I'm not sure about patch to enable texture-float, should this be left
> as a 'policy decision' for end distribution, it's not enabled by
> default on desktop?"

I think the only reason it isn't enabled by default is because
(currently) the same option covers both hw drivers and sw drivers.
Otoh, i965 ignores this option and always advertised texture-float.

Anyways, if android has some way to conditionalize this based on some
var set in board file, that might be an option.  Ideally I think we
want to get to the point where we can build android with upstream
mesa, without having to carry patches.

BR,
-R

>> I'm not sure if there is any use to build swrast/llvmpipe for android
>> build, so maybe the thing to do is remove them (if they are built for
>> android currently), and then enable texture-float.
>>
> There was a similar idea on the autotools side, but it never really
> got finished/ack/merged.
>
> I realise it's a tad annoying, but I'd just give it until the patent
> expires and enable it everywhere - we could even fold the s3tc code
> within mesa.
>
> -Emil
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Re: [Mesa-dev] [PATCH v2 0/3][RFC]mesa/st: glsl_to_tgsi: improved temp-reg lifetime estimation

2017-06-16 Thread Emil Velikov 
Hi Gert,

Welcome to Mesa, and apologies for chiming in so late.

Please don't use STL within core mesa code. While some places do use
it, those are quite isolated and have specific role.
For example:
 - st/clover - heavily templated, pure C++
 - drivers/swr - as above
 - drivers/nouveau/codegen - mix of STL and local alternatives of STL
 - drivers/r600/sb - somewhat lightweight on STL usage.

A couple of additional ideas:
 - where possible try to split patches even further.
IIRC 2/3 adds some 2kloc, which may be hard to review properly.
 - do keep performance numbers within the commit summary.
This way the details are preserved in git log for future references.

Thanks
Emil
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Re: [Mesa-dev] [PATCH v1 6/7] android: add etnaviv driver build support

2017-06-16 Thread Rob Herring 
On Fri, Jun 16, 2017 at 8:24 AM, Emil Velikov  wrote:
> Hi Rob,
>
> There's a handful of small nitpicks, but nothing serious.
>
> On 15 June 2017 at 21:47, Robert Foss  wrote:
>> From: Rob Herring 
>>
>> Add etnaviv to Android makefiles.
>>
>> Signed-off-by: Rob Herring 
>> ---


>> @@ -46,7 +47,7 @@ LOCAL_CPPFLAGS += -std=c++11
>>
>>  # We need libmesa_nir to get NIR's generated include directories.
>>  LOCAL_MODULE := libmesa_gallium
>> -LOCAL_STATIC_LIBRARIES += libmesa_nir
>> +LOCAL_STATIC_LIBRARIES += libmesa_nir libmesa_loader
>>
> Do we really need the loader here? Afaict module does not export any
> headers/etc that we need?
> We should only need it in the final link stage, although it's there already.

I could be left over from the first iteration of renderonly. These
patches started a while back.

Rob
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Re: [Mesa-dev] [PATCH v1 7/7] android: build imx-drm winsys

2017-06-16 Thread Emil Velikov 
Hi Rob,

I missed something in the pl111+vc4 case, which is also applicable here.

If one selects the DC w/o the GPU the build will fail. To resolve that
one option is to simply pull the GPU static libs as dependencies for
the DC ones. Some example/specifics below.

On 15 June 2017 at 21:47, Robert Foss  wrote:

> --- /dev/null
> +++ b/src/gallium/winsys/imx/drm/Android.mk

> +# get C_SOURCES
> +#include $(LOCAL_PATH)/Makefile.sources
As with 6/7 uncomment + use the C_SOURCES.


> +
> +ifneq ($(HAVE_GALLIUM_FREEDRENO),)
> +$(eval GALLIUM_LIBS += $(LOCAL_MODULE) libmesa_winsys_freedreno)
Typo - s/libmesa_winsys_freedreno/libmesa_winsys_imx/

+ need the libmesa_pipe_etnaviv and libmesa_winsys_etnaviv as
mentioned above, otherwise we'll fail at build time when etnaviv is
not explicitly set. If you can think of alternative ways to address
this, please go ahead.

Thanks
Emil
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Re: [Mesa-dev] [PATCH v1 5/7] android: enable texture-float

2017-06-16 Thread Emil Velikov 
On 16 June 2017 at 14:25, Rob Clark  wrote:
> On Fri, Jun 16, 2017 at 9:18 AM, Emil Velikov  
> wrote:
>> On 15 June 2017 at 21:47, Robert Foss  wrote:
>>> From: Rob Herring 
>>>
>>> This is required by freedreno at least for GLES3 support.
>>>
>>> See docs/patents.txt for information about turning this on for s/w
>>> renderers.
>>>
>> I'm inclined to agree with Tapani. We're not lawyers and with the
>> patent expiring in half a year, I think we can defer this toggle to
>> builders and their legal teams ;-)
>>
>
> Not really sure what msg from Tapani you are referring to.  But tbh,
> what we really want is a separate option for sw renderers.
>
This quote from the cover letter
"I'm not sure about patch to enable texture-float, should this be left
as a 'policy decision' for end distribution, it's not enabled by
default on desktop?"

> I'm not sure if there is any use to build swrast/llvmpipe for android
> build, so maybe the thing to do is remove them (if they are built for
> android currently), and then enable texture-float.
>
There was a similar idea on the autotools side, but it never really
got finished/ack/merged.

I realise it's a tad annoying, but I'd just give it until the patent
expires and enable it everywhere - we could even fold the s3tc code
within mesa.

-Emil
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Re: [Mesa-dev] [PATCH v1 4/7] gbm: add XBGR8888 support for dumb buffers

2017-06-16 Thread Daniel Stone 
Hi,

On 15 June 2017 at 21:47, Robert Foss  wrote:
> From: Rob Herring 
> diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
> index 19be440d48..58b62ac361 100644
> --- a/src/gbm/backends/dri/gbm_dri.c
> +++ b/src/gbm/backends/dri/gbm_dri.c
> @@ -1067,7 +1067,7 @@ create_dumb(struct gbm_device *gbm,
> is_cursor = (usage & GBM_BO_USE_CURSOR) != 0 &&
>format == GBM_FORMAT_ARGB;
> is_scanout = (usage & GBM_BO_USE_SCANOUT) != 0 &&
> -  format == GBM_FORMAT_XRGB;
> +  (format == GBM_FORMAT_XRGB || format == GBM_FORMAT_XBGR);

Funny, I've just been exactly here myself, cursing at the weird and
asymmetric hardcoded list of formats. Good times.

Reviewed-by: Daniel Stone 

Cheers,
Daniel
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Re: [Mesa-dev] [PATCH v1 5/7] android: enable texture-float

2017-06-16 Thread Rob Clark 
On Fri, Jun 16, 2017 at 9:18 AM, Emil Velikov  wrote:
> On 15 June 2017 at 21:47, Robert Foss  wrote:
>> From: Rob Herring 
>>
>> This is required by freedreno at least for GLES3 support.
>>
>> See docs/patents.txt for information about turning this on for s/w
>> renderers.
>>
> I'm inclined to agree with Tapani. We're not lawyers and with the
> patent expiring in half a year, I think we can defer this toggle to
> builders and their legal teams ;-)
>

Not really sure what msg from Tapani you are referring to.  But tbh,
what we really want is a separate option for sw renderers.

I'm not sure if there is any use to build swrast/llvmpipe for android
build, so maybe the thing to do is remove them (if they are built for
android currently), and then enable texture-float.

BR,
-R
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Re: [Mesa-dev] [PATCH v1 2/7] etnaviv: Add return statement to etna_amode so compiler is happy

2017-06-16 Thread Christian Gmeiner 
2017-06-16 14:54 GMT+02:00 Emil Velikov :
> On 15 June 2017 at 21:47, Robert Foss  wrote:
>> From: Tomeu Vizoso 
>>
>> Signed-off-by: Robert Foss 
>> ---
>>  src/gallium/drivers/etnaviv/etnaviv_compiler.c | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler.c 
>> b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
>> index eafb511bb8..8f73113059 100644
>> --- a/src/gallium/drivers/etnaviv/etnaviv_compiler.c
>> +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
>> @@ -885,6 +885,8 @@ etna_amode(struct tgsi_ind_register indirect)
>> default:
>>assert(!"Invalid swizzle");
>> }
>> +
>> +   return 0;
> All the cases are handled correctly and even the default one will
> never be reached.
> Guess the compiler isn't smart enough, since we're using int:2 while
> in reality we're storing an enum and using enum:2 might not always
> work.
>
> Alternative solutions is s/assert/unreachable/. The call will be up-to
> the etna devs, but including something like the above (in the commit
> summary or elsewhere) will be a good idea, IMHO.
>

I really like Emil's idea of s/assert/unreachable/

greets
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Re: [Mesa-dev] [PATCH v1 6/7] android: add etnaviv driver build support

2017-06-16 Thread Emil Velikov 
Hi Rob,

There's a handful of small nitpicks, but nothing serious.

On 15 June 2017 at 21:47, Robert Foss  wrote:
> From: Rob Herring 
>
> Add etnaviv to Android makefiles.
>
> Signed-off-by: Rob Herring 
> ---
>  Android.mk|  5 +--
>  src/gallium/Android.mk|  1 +
>  src/gallium/auxiliary/Android.mk  |  5 +--
>  src/gallium/auxiliary/renderonly/renderonly.c |  1 +
>  src/gallium/drivers/etnaviv/Android.mk| 47 
> +++
>  src/gallium/winsys/etnaviv/drm/Android.mk | 35 
>  6 files changed, 90 insertions(+), 4 deletions(-)
>  create mode 100644 src/gallium/drivers/etnaviv/Android.mk
>  create mode 100644 src/gallium/winsys/etnaviv/drm/Android.mk
>
> diff --git a/Android.mk b/Android.mk
> index de37f4600f..b4dc8321a6 100644
> --- a/Android.mk
> +++ b/Android.mk
> @@ -24,7 +24,7 @@
>  # BOARD_GPU_DRIVERS should be defined.  The valid values are
>  #
>  #   classic drivers: i915 i965
> -#   gallium drivers: swrast freedreno i915g nouveau r300g r600g radeonsi vc4 
> virgl vmwgfx
> +#   gallium drivers: swrast freedreno i915g nouveau r300g r600g radeonsi vc4 
> virgl vmwgfx etnaviv
>  #
>  # The main target is libGLES_mesa.  For each classic driver enabled, a DRI
>  # module will also be built.  DRI modules will be loaded by libGLES_mesa.
> @@ -56,7 +56,8 @@ gallium_drivers := \
> radeonsi.HAVE_GALLIUM_RADEONSI \
> vmwgfx.HAVE_GALLIUM_VMWGFX \
> vc4.HAVE_GALLIUM_VC4 \
> -   virgl.HAVE_GALLIUM_VIRGL
> +   virgl.HAVE_GALLIUM_VIRGL \
> +   etnaviv.HAVE_GALLIUM_ETNAVIV
>
>  ifeq ($(BOARD_GPU_DRIVERS),all)
>  MESA_BUILD_CLASSIC := $(filter HAVE_%, $(subst ., , $(classic_drivers)))
> diff --git a/src/gallium/Android.mk b/src/gallium/Android.mk
> index 0915579127..0280574405 100644
> --- a/src/gallium/Android.mk
> +++ b/src/gallium/Android.mk
> @@ -43,6 +43,7 @@ SUBDIRS += winsys/radeon/drm winsys/amdgpu/drm 
> drivers/radeonsi drivers/radeon
>  SUBDIRS += winsys/vc4/drm drivers/vc4
>  SUBDIRS += winsys/virgl/drm winsys/virgl/vtest drivers/virgl
>  SUBDIRS += winsys/svga/drm drivers/svga
> +SUBDIRS += winsys/etnaviv/drm drivers/etnaviv drivers/renderonly
>  SUBDIRS += state_trackers/dri
>
>  # sort to eliminate any duplicates
> diff --git a/src/gallium/auxiliary/Android.mk 
> b/src/gallium/auxiliary/Android.mk
> index e2a1fc214e..a562774a9a 100644
> --- a/src/gallium/auxiliary/Android.mk
> +++ b/src/gallium/auxiliary/Android.mk
> @@ -31,7 +31,8 @@ include $(CLEAR_VARS)
>  LOCAL_SRC_FILES := \
> $(C_SOURCES) \
> $(NIR_SOURCES) \
> -   $(VL_STUB_SOURCES)
> +   $(VL_STUB_SOURCES) \
> +   $(RENDERONLY_SOURCES)
>
>  LOCAL_C_INCLUDES := \
> $(GALLIUM_TOP)/auxiliary/util
> @@ -46,7 +47,7 @@ LOCAL_CPPFLAGS += -std=c++11
>
>  # We need libmesa_nir to get NIR's generated include directories.
>  LOCAL_MODULE := libmesa_gallium
> -LOCAL_STATIC_LIBRARIES += libmesa_nir
> +LOCAL_STATIC_LIBRARIES += libmesa_nir libmesa_loader
>
Do we really need the loader here? Afaict module does not export any
headers/etc that we need?
We should only need it in the final link stage, although it's there already.

>  LOCAL_WHOLE_STATIC_LIBRARIES += cpufeatures
>
> diff --git a/src/gallium/auxiliary/renderonly/renderonly.c 
> b/src/gallium/auxiliary/renderonly/renderonly.c
> index d3ed214f4e..dda7f4471a 100644
> --- a/src/gallium/auxiliary/renderonly/renderonly.c
> +++ b/src/gallium/auxiliary/renderonly/renderonly.c
> @@ -35,6 +35,7 @@
>  #include "pipe/p_screen.h"
>  #include "util/u_inlines.h"
>  #include "util/u_memory.h"
> +#include "loader.h"
>
Seemingly unrelated change. Please split out if we really need it.

>  struct renderonly *
>  renderonly_dup(const struct renderonly *ro)
> diff --git a/src/gallium/drivers/etnaviv/Android.mk 
> b/src/gallium/drivers/etnaviv/Android.mk
> new file mode 100644
> index 00..7e9b2ae1b2
> --- /dev/null
> +++ b/src/gallium/drivers/etnaviv/Android.mk
> @@ -0,0 +1,47 @@
> +# Copyright (C) 2016 Linaro, Ltd, Rob Herring 
> +#
> +# Permission is hereby granted, free of charge, to any person obtaining a
> +# copy of this software and associated documentation files (the "Software"),
> +# to deal in the Software without restriction, including without limitation
> +# the rights to use, copy, modify, merge, publish, distribute, sublicense,
> +# and/or sell copies of the Software, and to permit persons to whom the
> +# Software is furnished to do so, subject to the following conditions:
> +#
> +# The above copyright notice and this permission notice shall be included
> +# in all copies or substantial portions of the Software.
> +#
> +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

Re: [Mesa-dev] [PATCH v1 5/7] android: enable texture-float

2017-06-16 Thread Emil Velikov 
On 15 June 2017 at 21:47, Robert Foss  wrote:
> From: Rob Herring 
>
> This is required by freedreno at least for GLES3 support.
>
> See docs/patents.txt for information about turning this on for s/w
> renderers.
>
I'm inclined to agree with Tapani. We're not lawyers and with the
patent expiring in half a year, I think we can defer this toggle to
builders and their legal teams ;-)

-Emil
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Re: [Mesa-dev] [PATCH v1 4/7] gbm: add XBGR8888 support for dumb buffers

2017-06-16 Thread Emil Velikov 
On 15 June 2017 at 21:47, Robert Foss  wrote:
> From: Rob Herring 
>
> Signed-off-by: Rob Herring 
> ---
>  src/gbm/backends/dri/gbm_dri.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
> index 19be440d48..58b62ac361 100644
> --- a/src/gbm/backends/dri/gbm_dri.c
> +++ b/src/gbm/backends/dri/gbm_dri.c
> @@ -1067,7 +1067,7 @@ create_dumb(struct gbm_device *gbm,
> is_cursor = (usage & GBM_BO_USE_CURSOR) != 0 &&
>format == GBM_FORMAT_ARGB;
> is_scanout = (usage & GBM_BO_USE_SCANOUT) != 0 &&
> -  format == GBM_FORMAT_XRGB;
> +  (format == GBM_FORMAT_XRGB || format == GBM_FORMAT_XBGR);
AFAICT there's no other parts that need updating.

Still, the commit message should mention, an actual use case for the
extra format.

With that
Reviewed-by: Emil Velikov 

Emil
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Re: [Mesa-dev] [PATCH v1 3/7] gallium: os_process fixes for Android

2017-06-16 Thread Emil Velikov 
On 16 June 2017 at 04:38, Chih-Wei Huang  wrote:
> 2017-06-16 4:47 GMT+08:00 Robert Foss :
>> From: Rob Herring 
>>
>> Signed-off-by: Rob Herring 
>> ---
>>  src/gallium/auxiliary/os/os_process.c | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/gallium/auxiliary/os/os_process.c 
>> b/src/gallium/auxiliary/os/os_process.c
>> index 6622b9b2bc..af5d22bf84 100644
>> --- a/src/gallium/auxiliary/os/os_process.c
>> +++ b/src/gallium/auxiliary/os/os_process.c
>> @@ -34,7 +34,7 @@
>>  #  include 
>>  #elif defined(__GLIBC__) || defined(__CYGWIN__)
>>  #  include 
>> -#elif defined(PIPE_OS_BSD) || defined(PIPE_OS_APPLE)
>> +#elif defined(PIPE_OS_BSD) || defined(PIPE_OS_APPLE) || 
>> defined(PIPE_OS_ANDROID)
>>  #  include 
>>  #elif defined(PIPE_OS_HAIKU)
>>  #  include 
>> @@ -59,6 +59,7 @@ os_get_process_name(char *procname, size_t size)
>>  {
>> const char *name;
>>
>> +
Unrelated whitespace change.

>> /* First, check if the GALLIUM_PROCESS_NAME env var is set to
>>  * override the normal process name query.
>>  */
>> @@ -86,7 +87,7 @@ os_get_process_name(char *procname, size_t size)
>>
>>  #elif defined(__GLIBC__) || defined(__CYGWIN__)
>>name = program_invocation_short_name;
>> -#elif defined(PIPE_OS_BSD) || defined(PIPE_OS_APPLE)
>> +#elif defined(PIPE_OS_BSD) || defined(PIPE_OS_APPLE) || 
>> defined(PIPE_OS_ANDROID)
>>/* *BSD and OS X */
>>name = getprogname();
>>  #elif defined(PIPE_OS_HAIKU)
>> --
>
> I have submitted another patch to fix
> the same issue about 2 weeks ago.
> My suggestion is just define PIPE_OS_BSD
> for Android. This allows Android to share features
> inherited from (Open)BSD and avoid further changes
> like this one.
>
> Please see:
> https://lists.freedesktop.org/archives/mesa-dev/2017-June/157754.html
>
And as mentioned in the thread - assuming both BSD and Linux does not
sound like a good idea.
Let's go ahead with this, but Rob please apply some polish on the
commit message. Some example follows:

"gallium: android: use BSD code path for os_get_process_name

The function getprogname() is available on Android, since it reuses
various BSD solutions C runtime."

With the above
Reviewed-by: Emil Velikov 

-Emil
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[Mesa-dev] [PATCH 1/9] radeonsi: add separate HUD counters for CB and DB cache flushes

2017-06-16 Thread Marek Olšák 
From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_pipe_common.h |  3 ++-
 src/gallium/drivers/radeon/r600_query.c   | 17 -
 src/gallium/drivers/radeon/r600_query.h   |  3 ++-
 src/gallium/drivers/radeonsi/si_state_draw.c  |  7 ---
 4 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 45ed5ba..887c111 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -588,21 +588,22 @@ struct r600_common_context {
unsignednum_draw_calls;
unsignednum_prim_restart_calls;
unsignednum_spill_draw_calls;
unsignednum_compute_calls;
unsignednum_spill_compute_calls;
unsignednum_dma_calls;
unsignednum_cp_dma_calls;
unsignednum_vs_flushes;
unsignednum_ps_flushes;
unsignednum_cs_flushes;
-   unsignednum_fb_cache_flushes;
+   unsignednum_cb_cache_flushes;
+   unsignednum_db_cache_flushes;
unsignednum_L2_invalidates;
unsignednum_L2_writebacks;
uint64_tnum_alloc_tex_transfer_bytes;
unsignedlast_tex_ps_draw_ratio; /* for query */
 
/* Render condition. */
struct r600_atomrender_cond_atom;
struct pipe_query   *render_cond;
unsignedrender_cond_mode;
boolrender_cond_invert;
diff --git a/src/gallium/drivers/radeon/r600_query.c 
b/src/gallium/drivers/radeon/r600_query.c
index bce4317..ca8bab0 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -118,22 +118,25 @@ static bool r600_query_sw_begin(struct 
r600_common_context *rctx,
break;
case R600_QUERY_NUM_VS_FLUSHES:
query->begin_result = rctx->num_vs_flushes;
break;
case R600_QUERY_NUM_PS_FLUSHES:
query->begin_result = rctx->num_ps_flushes;
break;
case R600_QUERY_NUM_CS_FLUSHES:
query->begin_result = rctx->num_cs_flushes;
break;
-   case R600_QUERY_NUM_FB_CACHE_FLUSHES:
-   query->begin_result = rctx->num_fb_cache_flushes;
+   case R600_QUERY_NUM_CB_CACHE_FLUSHES:
+   query->begin_result = rctx->num_cb_cache_flushes;
+   break;
+   case R600_QUERY_NUM_DB_CACHE_FLUSHES:
+   query->begin_result = rctx->num_db_cache_flushes;
break;
case R600_QUERY_NUM_L2_INVALIDATES:
query->begin_result = rctx->num_L2_invalidates;
break;
case R600_QUERY_NUM_L2_WRITEBACKS:
query->begin_result = rctx->num_L2_writebacks;
break;
case R600_QUERY_TC_OFFLOADED_SLOTS:
query->begin_result = rctx->tc ? rctx->tc->num_offloaded_slots 
: 0;
break;
@@ -260,22 +263,25 @@ static bool r600_query_sw_end(struct r600_common_context 
*rctx,
break;
case R600_QUERY_NUM_VS_FLUSHES:
query->end_result = rctx->num_vs_flushes;
break;
case R600_QUERY_NUM_PS_FLUSHES:
query->end_result = rctx->num_ps_flushes;
break;
case R600_QUERY_NUM_CS_FLUSHES:
query->end_result = rctx->num_cs_flushes;
break;
-   case R600_QUERY_NUM_FB_CACHE_FLUSHES:
-   query->end_result = rctx->num_fb_cache_flushes;
+   case R600_QUERY_NUM_CB_CACHE_FLUSHES:
+   query->end_result = rctx->num_cb_cache_flushes;
+   break;
+   case R600_QUERY_NUM_DB_CACHE_FLUSHES:
+   query->end_result = rctx->num_db_cache_flushes;
break;
case R600_QUERY_NUM_L2_INVALIDATES:
query->end_result = rctx->num_L2_invalidates;
break;
case R600_QUERY_NUM_L2_WRITEBACKS:
query->end_result = rctx->num_L2_writebacks;
break;
case R600_QUERY_TC_OFFLOADED_SLOTS:
query->end_result = rctx->tc ? rctx->tc->num_offloaded_slots : 
0;
break;
@@ -1824,21 +1830,22 @@ static struct pipe_driver_query_info 
r600_driver_query_list[] = {
X("draw-calls", DRAW_CALLS, UINT64, 
AVERAGE),
X("prim-restart-calls", PRIM_RESTART_CALLS, UINT64, 
AVERAGE),
X("spill-draw-calls",

[Mesa-dev] [PATCH 4/9] radeonsi: flush CB after MSAA only when transitioning from CB to textures

2017-06-16 Thread Marek Olšák 
From: Marek Olšák 

The main flush before texturing is done after the FMASK decompress pass.

CB after MSAA rendering is not flushed in set_framebuffer_state and also
not in memory_barrier if the current color buffer is MSAA. We fully rely
on the FMASK decompress pass for the flushing.

Some CB decompress and resolve passes need an explicit flush before and
after.
---
 src/gallium/drivers/radeonsi/si_blit.c  | 29 ++
 src/gallium/drivers/radeonsi/si_state.c | 43 ++---
 2 files changed, 58 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 0993ebd..1159594 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -398,20 +398,28 @@ si_decompress_depth(struct si_context *sctx,
 * state becomes 0 for the whole mipmap tree and all planes.
 * (there is nothing else to flush)
 */
if (tex->tc_compatible_htile) {
if (r600_can_sample_zs(tex, false))
tex->dirty_level_mask = 0;
if (r600_can_sample_zs(tex, true))
tex->stencil_dirty_level_mask = 0;
}
}
+   /* set_framebuffer_state takes care of coherency for single-sample.
+* The DB->CB copy uses CB for the final writes.
+*/
+   if (copy_planes && tex->resource.b.b.nr_samples > 1) {
+   sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
+SI_CONTEXT_INV_GLOBAL_L2 |
+SI_CONTEXT_FLUSH_AND_INV_CB;
+   }
 }
 
 static void
 si_decompress_sampler_depth_textures(struct si_context *sctx,
 struct si_textures_info *textures)
 {
unsigned i;
unsigned mask = textures->needs_depth_decompress_mask;
 
while (mask) {
@@ -480,36 +488,49 @@ static void si_blit_decompress_color(struct pipe_context 
*ctx,
 
for (layer = first_layer; layer <= checked_last_layer; layer++) 
{
struct pipe_surface *cbsurf, surf_tmpl;
 
surf_tmpl.format = rtex->resource.b.b.format;
surf_tmpl.u.tex.level = level;
surf_tmpl.u.tex.first_layer = layer;
surf_tmpl.u.tex.last_layer = layer;
cbsurf = ctx->create_surface(ctx, >resource.b.b, 
_tmpl);
 
+   /* Required before and after FMASK and DCC_DECOMPRESS. 
*/
+   if (custom_blend == sctx->custom_blend_fmask_decompress 
||
+   custom_blend == sctx->custom_blend_dcc_decompress)
+   sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
+
si_blitter_begin(ctx, SI_DECOMPRESS);
util_blitter_custom_color(sctx->blitter, cbsurf, 
custom_blend);
si_blitter_end(ctx);
 
+   if (custom_blend == sctx->custom_blend_fmask_decompress 
||
+   custom_blend == sctx->custom_blend_dcc_decompress)
+   sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
+
pipe_surface_reference(, NULL);
}
 
/* The texture will always be dirty if some layers aren't 
flushed.
 * I don't think this case occurs often though. */
if (first_layer == 0 && last_layer >= max_layer) {
rtex->dirty_level_mask &= ~(1 << level);
}
}
 
sctx->decompression_enabled = false;
sctx->framebuffer.do_update_surf_dirtiness = old_update_dirtiness;
+
+   sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
+SI_CONTEXT_INV_GLOBAL_L2 |
+SI_CONTEXT_INV_VMEM_L1;
 }
 
 static void
 si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
unsigned first_level, unsigned last_level)
 {
/* CMASK or DCC can be discarded and we can still end up here. */
if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
return;
 
@@ -1148,27 +1169,35 @@ void si_resource_copy_region(struct pipe_context *ctx,
pipe_surface_reference(_view, NULL);
pipe_sampler_view_reference(_view, NULL);
 }
 
 static void si_do_CB_resolve(struct si_context *sctx,
 const struct pipe_blit_info *info,
 struct pipe_resource *dst,
 unsigned dst_level, unsigned dst_z,
 enum pipe_format format)
 {
+   /* Required before and after CB_RESOLVE. */
+   sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
+
si_blitter_begin(>b.b, SI_COLOR_RESOLVE |

[Mesa-dev] [PATCH 9/9] radeonsi: don't do any flushes at the end of IBs

2017-06-16 Thread Marek Olšák 
From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_hw_context.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c 
b/src/gallium/drivers/radeonsi/si_hw_context.c
index 5d930a6..b420c9f 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -122,20 +122,23 @@ void si_context_gfx_flush(void *context, unsigned flags,
}
 
ctx->gfx_flush_in_progress = true;
 
/* This CE dump should be done in parallel with the last draw. */
if (ctx->ce_ib)
si_ce_save_all_descriptors_at_ib_end(ctx);
 
r600_preflush_suspend_features(>b);
 
+   /* The kernel-side fence will flush everything. */
+   ctx->b.flags = 0;
+
/* DRM 3.1.0 doesn't flush TC for VI correctly. */
if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1) {
ctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
SI_CONTEXT_CS_PARTIAL_FLUSH |
SI_CONTEXT_INV_GLOBAL_L2 |
SI_CONTEXT_INV_VMEM_L1;
}
 
si_emit_cache_flush(ctx);
 
-- 
2.7.4

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[Mesa-dev] [PATCH 5/9] radeonsi/gfx9: indirect buffers and all CP packets use TC L2

2017-06-16 Thread Marek Olšák 
From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_compute.c|  5 +++--
 src/gallium/drivers/radeonsi/si_pipe.c   |  6 --
 src/gallium/drivers/radeonsi/si_state.c  |  4 +++-
 src/gallium/drivers/radeonsi/si_state_draw.c | 19 +++
 4 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_compute.c 
b/src/gallium/drivers/radeonsi/si_compute.c
index 79b107e..65f3261 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -781,22 +781,23 @@ static void si_launch_grid(
 
si_decompress_compute_textures(sctx);
 
/* Add buffer sizes for memory checking in need_cs_space. */
r600_context_add_resource_size(ctx, >shader.bo->b.b);
/* TODO: add the scratch buffer */
 
if (info->indirect) {
r600_context_add_resource_size(ctx, info->indirect);
 
-   /* The hw doesn't read the indirect buffer via TC L2. */
-   if (r600_resource(info->indirect)->TC_L2_dirty) {
+   /* Indirect buffers use TC L2 on GFX9, but not older hw. */
+   if (sctx->b.chip_class <= VI &&
+   r600_resource(info->indirect)->TC_L2_dirty) {
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
r600_resource(info->indirect)->TC_L2_dirty = false;
}
}
 
si_need_cs_space(sctx);
 
if (!sctx->cs_shader_state.initialized)
si_initialize_compute(sctx);
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 9f6e3c2..960f21a 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -994,22 +994,24 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws)
!(sscreen->b.debug_flags & DBG_NO_RB_PLUS) &&
(sscreen->b.family == CHIP_STONEY ||
 sscreen->b.family == CHIP_RAVEN);
}
 
(void) mtx_init(>shader_parts_mutex, mtx_plain);
sscreen->use_monolithic_shaders =
(sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 
sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
-   SI_CONTEXT_INV_VMEM_L1 |
-   SI_CONTEXT_INV_GLOBAL_L2;
+   SI_CONTEXT_INV_VMEM_L1;
+   if (sscreen->b.chip_class <= VI)
+   sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
+
sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
 
if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | 
DBG_CS;
 
for (i = 0; i < num_compiler_threads; i++)
sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
for (i = 0; i < num_compiler_threads_lowprio; i++)
sscreen->tm_low_priority[i] = 
si_create_llvm_target_machine(sscreen);
 
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index ab27af2..2a2c3c0 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -4008,21 +4008,23 @@ static void si_memory_barrier(struct pipe_context *ctx, 
unsigned flags)
 
/* MSAA color, any depth and any stencil are flushed in
 * si_decompress_textures when needed.
 */
if (flags & PIPE_BARRIER_FRAMEBUFFER &&
sctx->framebuffer.nr_samples <= 1) {
sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
 SI_CONTEXT_WRITEBACK_GLOBAL_L2;
}
 
-   if (flags & PIPE_BARRIER_INDIRECT_BUFFER)
+   /* Indirect buffers use TC L2 on GFX9, but not older hw. */
+   if (sctx->screen->b.chip_class <= VI &&
+   flags & PIPE_BARRIER_INDIRECT_BUFFER)
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 }
 
 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
 {
struct pipe_blend_state blend;
 
memset(, 0, sizeof(blend));
blend.independent_blend_enable = true;
blend.rt[0].colormask = 0xf;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index d13c8b7..2b000e7 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1313,29 +1313,32 @@ void si_draw_vbo(struct pipe_context *ctx, const struct 
pipe_draw_info *info)
r600_resource(indexbuf)->TC_L2_dirty = false;
}
}
 
if (info->indirect) {
struct pipe_draw_indirect_info *indirect = info->indirect;
 
/* Add the buffer size for memory checking in need_cs_space. */

[Mesa-dev] [PATCH 6/9] radeonsi/gfx9: enable the constant engine

2017-06-16 Thread Marek Olšák 
From: Marek Olšák 

I think this kernel commit fixes it:
 drm/amdgpu:use FRAME_CNTL for new GFX ucode
---
 src/gallium/drivers/radeonsi/si_pipe.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 960f21a..895d53f 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -194,24 +194,21 @@ static struct pipe_context *si_create_context(struct 
pipe_screen *screen,
}
 
sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
   si_context_gfx_flush, sctx);
 
/* SI + AMDGPU + CE = GPU hang */
if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib &&
sscreen->b.chip_class != SI &&
/* These can't use CE due to a power gating bug in the kernel. */
sscreen->b.family != CHIP_CARRIZO &&
-   sscreen->b.family != CHIP_STONEY &&
-   /* Some CE bug is causing green screen corruption w/ MPV video
-* playback and occasional corruption w/ 3D. */
-   sscreen->b.chip_class != GFX9) {
+   sscreen->b.family != CHIP_STONEY) {
sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
if (!sctx->ce_ib)
goto fail;
 
if (ws->cs_add_const_preamble_ib) {
sctx->ce_preamble_ib =
   ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 
if (!sctx->ce_preamble_ib)
goto fail;
-- 
2.7.4

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[Mesa-dev] [PATCH 8/9] radeonsi: don't emit partial flushes at the end of IBs

2017-06-16 Thread Marek Olšák 
From: Marek Olšák 

The kernel sort of does the same thing with fences.
---
 src/gallium/drivers/radeonsi/si_hw_context.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c 
b/src/gallium/drivers/radeonsi/si_hw_context.c
index 345825a..5d930a6 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -122,27 +122,27 @@ void si_context_gfx_flush(void *context, unsigned flags,
}
 
ctx->gfx_flush_in_progress = true;
 
/* This CE dump should be done in parallel with the last draw. */
if (ctx->ce_ib)
si_ce_save_all_descriptors_at_ib_end(ctx);
 
r600_preflush_suspend_features(>b);
 
-   ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
-   SI_CONTEXT_PS_PARTIAL_FLUSH;
-
/* DRM 3.1.0 doesn't flush TC for VI correctly. */
-   if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
-   ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
+   if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1) {
+   ctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
+   SI_CONTEXT_CS_PARTIAL_FLUSH |
+   SI_CONTEXT_INV_GLOBAL_L2 |
SI_CONTEXT_INV_VMEM_L1;
+   }
 
si_emit_cache_flush(ctx);
 
if (ctx->trace_buf)
si_trace_emit(ctx);
 
if (ctx->is_debug) {
/* Save the IB for debug contexts. */
radeon_clear_saved_cs(>last_gfx);
radeon_save_cs(ws, cs, >last_gfx);
-- 
2.7.4

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[Mesa-dev] [PATCH 7/9] radeonsi/gfx9: keep reusing the same buffer/address for the gfx9 flush fence

2017-06-16 Thread Marek Olšák 
From: Marek Olšák 

instead of using a monotonic suballocator
---
 src/gallium/drivers/radeonsi/si_pipe.c   |  6 ++
 src/gallium/drivers/radeonsi/si_pipe.h   |  2 ++
 src/gallium/drivers/radeonsi/si_state_draw.c | 16 
 3 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 895d53f..11dcbe3 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -57,20 +57,21 @@ static void si_destroy_context(struct pipe_context *context)
r600_resource_reference(>ce_ram_saved_buffer, NULL);
pipe_resource_reference(>esgs_ring, NULL);
pipe_resource_reference(>gsvs_ring, NULL);
pipe_resource_reference(>tf_ring, NULL);
pipe_resource_reference(>tess_offchip_ring, NULL);
pipe_resource_reference(>null_const_buf.buffer, NULL);
r600_resource_reference(>border_color_buffer, NULL);
free(sctx->border_color_table);
r600_resource_reference(>scratch_buffer, NULL);
r600_resource_reference(>compute_scratch_buffer, NULL);
+   r600_resource_reference(>wait_mem_scratch, NULL);
 
si_pm4_free_state(sctx, sctx->init_config, ~0);
if (sctx->init_config_gs_rings)
si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
si_pm4_delete_state(sctx, vgt_shader_config, 
sctx->vgt_shader_config[i]);
 
if (sctx->fixed_func_tcs_shader.cso)
sctx->b.b.delete_tcs_state(>b.b, 
sctx->fixed_func_tcs_shader.cso);
if (sctx->custom_dsa_flush)
@@ -236,20 +237,25 @@ static struct pipe_context *si_create_context(struct 
pipe_screen *screen,
   sizeof(*sctx->border_color_table));
if (!sctx->border_color_buffer)
goto fail;
 
sctx->border_color_map =
ws->buffer_map(sctx->border_color_buffer->buf,
   NULL, PIPE_TRANSFER_WRITE);
if (!sctx->border_color_map)
goto fail;
 
+   sctx->wait_mem_scratch = (struct r600_resource*)
+   pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
+   if (!sctx->wait_mem_scratch)
+   goto fail;
+
si_init_all_descriptors(sctx);
si_init_state_functions(sctx);
si_init_shader_functions(sctx);
si_init_ia_multi_vgt_param_table(sctx);
 
if (sctx->b.chip_class >= CIK)
cik_init_sdma_functions(sctx);
else
si_init_dma_functions(sctx);
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index e734595..f6fe11b 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -258,20 +258,22 @@ struct si_context {
struct r600_common_context  b;
struct blitter_context  *blitter;
void*custom_dsa_flush;
void*custom_blend_resolve;
void*custom_blend_fmask_decompress;
void*custom_blend_eliminate_fastclear;
void*custom_blend_dcc_decompress;
struct si_screen*screen;
LLVMTargetMachineReftm; /* only non-threaded compilation */
struct si_shader_ctx_state  fixed_func_tcs_shader;
+   struct r600_resource*wait_mem_scratch;
+   unsignedwait_mem_number;
 
struct radeon_winsys_cs *ce_ib;
struct radeon_winsys_cs *ce_preamble_ib;
struct r600_resource*ce_ram_saved_buffer;
struct u_suballocator   *ce_suballocator;
unsignedce_ram_saved_offset;
uint16_ttotal_ce_ram_allocated;
boolce_need_synchronization:1;
 
boolgfx_flush_in_progress:1;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 2b000e7..85ceaca 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -947,23 +947,22 @@ void si_emit_cache_flush(struct si_context *sctx)
}
if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | 
EVENT_INDEX(0));
}
 
/* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
 * wait for idle on GFX9. We have to use a TS event.
 */
if (sctx->b.chip_class >= GFX9 && flush_cb_db) {
-   struct r600_resource *rbuf = NULL;

[Mesa-dev] [PATCH 0/9] RadeonSI cache flush optimizations

2017-06-16 Thread Marek Olšák 
Hi,

This series:
- reworks CB (MSAA-only) and DB flushes
- removes L2 flushes for CP packets and indirect buffers for GFX9
- enables the constant engine for GFX9 (yay!)
- removes all flushes and waits from the end of IBs (relying on
  the kernel fence to do that)

The rework of CB and DB flushes is the most interesting piece. It
takes advantage of the fact and DB and CB MSAA rendering is always
followed by a decompression pass before shader reads except when HTILE
is TC-compatible, but the infrastructure is there.

We can use the color/depth_needs_decompression tracking to determine
exactly when a surface is transitioned from CB/DB writes to shader
reads and do the cache flush in the decompress function. This has
the advantage that we don't have to flush DB and CB-MSAA in set_frame-
buffer_state and memory_barrier.

For TC-compatible HTILE, the code still marks depth textures as
needing decompression, but the decompress function will not do any
decompression, it will only do the cache flush.

It significantly reduces the number of DB flushes. If an app doesn't
use depth texturing, the driver never flushes DB. Apps overusing
memory_barrier(FRAMEBUFFER) will also see a lot fewer DB flushes.
For example, DeusEx:MD has 10x fewer DB flushes per frame now.
Not that it helps performance there, but it's good to have it.

Same for CB MSAA. If the current framebuffer is MSAA, set_framebuffer-
_state, memory_barrier, and texture_barrier don't flush CB. The CB
flush is only done after the decompression pass where we are 100% sure
that TC reads will follow.

Please review.

Marek
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[Mesa-dev] [PATCH 3/9] radeonsi: unify CB_RESOLVE blitter invocation code

2017-06-16 Thread Marek Olšák 
From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_blit.c | 35 +-
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index f0abfdc..0993ebd 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -1142,31 +1142,45 @@ void si_resource_copy_region(struct pipe_context *ctx,
util_blitter_blit_generic(sctx->blitter, dst_view, ,
  src_view, src_box, src_width0, src_height0,
  PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, 
NULL,
  false);
si_blitter_end(ctx);
 
pipe_surface_reference(_view, NULL);
pipe_sampler_view_reference(_view, NULL);
 }
 
+static void si_do_CB_resolve(struct si_context *sctx,
+const struct pipe_blit_info *info,
+struct pipe_resource *dst,
+unsigned dst_level, unsigned dst_z,
+enum pipe_format format)
+{
+   si_blitter_begin(>b.b, SI_COLOR_RESOLVE |
+(info->render_condition_enable ? 0 : 
SI_DISABLE_RENDER_COND));
+   util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
+ info->src.resource, info->src.box.z,
+ ~0, sctx->custom_blend_resolve,
+ format);
+   si_blitter_end(>b.b);
+}
+
 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
 const struct pipe_blit_info *info)
 {
struct si_context *sctx = (struct si_context*)ctx;
struct r600_texture *src = (struct r600_texture*)info->src.resource;
struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
MAYBE_UNUSED struct r600_texture *rtmp;
unsigned dst_width = u_minify(info->dst.resource->width0, 
info->dst.level);
unsigned dst_height = u_minify(info->dst.resource->height0, 
info->dst.level);
enum pipe_format format = info->src.format;
-   unsigned sample_mask = ~0;
struct pipe_resource *tmp, templ;
struct pipe_blit_info blit;
 
/* Check basic requirements for hw resolve. */
if (!(info->src.resource->nr_samples > 1 &&
  info->dst.resource->nr_samples <= 1 &&
  !util_format_is_pure_integer(format) &&
  !util_format_is_depth_or_stencil(format) &&
  util_max_layer(info->src.resource, 0) == 0))
return false;
@@ -1219,29 +1233,22 @@ static bool do_hardware_msaa_resolve(struct 
pipe_context *ctx,
if (sctx->b.chip_class >= GFX9 &&
info->dst.resource->last_level != 0)
goto resolve_to_temp;
 
vi_dcc_clear_level(>b, dst, info->dst.level,
   0x);
dst->dirty_level_mask &= ~(1 << info->dst.level);
}
 
/* Resolve directly from src to dst. */
-   si_blitter_begin(ctx, SI_COLOR_RESOLVE |
-(info->render_condition_enable ? 0 : 
SI_DISABLE_RENDER_COND));
-   util_blitter_custom_resolve_color(sctx->blitter,
- info->dst.resource, 
info->dst.level,
- info->dst.box.z,
- info->src.resource, 
info->src.box.z,
- sample_mask, 
sctx->custom_blend_resolve,
- format);
-   si_blitter_end(ctx);
+   si_do_CB_resolve(sctx, info, info->dst.resource,
+info->dst.level, info->dst.box.z, format);
return true;
}
 
 resolve_to_temp:
/* Shader-based resolve is VERY SLOW. Instead, resolve into
 * a temporary texture and blit.
 */
memset(, 0, sizeof(templ));
templ.target = PIPE_TEXTURE_2D;
templ.format = info->src.resource->format;
@@ -1261,27 +1268,21 @@ resolve_to_temp:
 
tmp = ctx->screen->resource_create(ctx->screen, );
if (!tmp)
return false;
rtmp = (struct r600_texture*)tmp;
 
assert(!rtmp->surface.is_linear);
assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
 
/* resolve */
-   si_blitter_begin(ctx, SI_COLOR_RESOLVE |
-(info->render_condition_enable ? 0 : 
SI_DISABLE_RENDER_COND));
-   util_blitter_custom_resolve_color(sctx->blitter, tmp, 0, 0,
- info->src.resource, info->src.box.z,
-

[Mesa-dev] [PATCH 2/9] radeonsi: flush DB caches only when transitioning from DB to texturing

2017-06-16 Thread Marek Olšák 
From: Marek Olšák 

Use the mechanism of si_decompress_textures, but instead of doing
the actual decompression, just flag the DB cache flush there.

This removes a lot of unnecessary DB cache flushes.
---
 src/gallium/drivers/radeonsi/si_blit.c| 36 +--
 src/gallium/drivers/radeonsi/si_descriptors.c | 17 +++--
 src/gallium/drivers/radeonsi/si_pipe.h|  1 +
 src/gallium/drivers/radeonsi/si_state.c   | 21 
 src/gallium/drivers/radeonsi/si_state_draw.c  |  6 ++---
 5 files changed, 56 insertions(+), 25 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 9c38ae9..f0abfdc 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -337,24 +337,20 @@ si_decompress_depth(struct si_context *sctx,
levels_s = level_mask & tex->stencil_dirty_level_mask;
 
if (levels_s) {
if (r600_can_sample_zs(tex, true))
inplace_planes |= PIPE_MASK_S;
else
copy_planes |= PIPE_MASK_S;
}
}
 
-   assert(!tex->tc_compatible_htile || levels_z == 0);
-   assert(!tex->tc_compatible_htile || levels_s == 0 ||
-  !r600_can_sample_zs(tex, true));
-
/* We may have to allocate the flushed texture here when called from
 * si_decompress_subresource.
 */
if (copy_planes &&
(tex->flushed_depth_texture ||
 r600_init_flushed_depth_texture(>b.b, >resource.b.b, 
NULL))) {
struct r600_texture *dst = tex->flushed_depth_texture;
unsigned fully_copied_levels;
unsigned levels = 0;
 
@@ -377,24 +373,44 @@ si_decompress_depth(struct si_context *sctx,
first_layer, last_layer,
0, u_max_sample(>resource.b.b));
 
if (copy_planes & PIPE_MASK_Z)
tex->dirty_level_mask &= ~fully_copied_levels;
if (copy_planes & PIPE_MASK_S)
tex->stencil_dirty_level_mask &= ~fully_copied_levels;
}
 
if (inplace_planes) {
-   si_blit_decompress_zs_in_place(
-   sctx, tex,
-   levels_z, levels_s,
-   first_layer, last_layer);
+   if (!tex->tc_compatible_htile) {
+   si_blit_decompress_zs_in_place(
+   sctx, tex,
+   levels_z, levels_s,
+   first_layer, last_layer);
+   }
+
+   /* Only in-place decompression needs to flush DB caches, or
+* when we don't decompress but TC-compatible planes are dirty.
+*/
+   sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
+SI_CONTEXT_INV_GLOBAL_L2 |
+SI_CONTEXT_INV_VMEM_L1;
+
+   /* If we flush DB caches for TC-compatible depth, the dirty
+* state becomes 0 for the whole mipmap tree and all planes.
+* (there is nothing else to flush)
+*/
+   if (tex->tc_compatible_htile) {
+   if (r600_can_sample_zs(tex, false))
+   tex->dirty_level_mask = 0;
+   if (r600_can_sample_zs(tex, true))
+   tex->stencil_dirty_level_mask = 0;
+   }
}
 }
 
 static void
 si_decompress_sampler_depth_textures(struct si_context *sctx,
 struct si_textures_info *textures)
 {
unsigned i;
unsigned mask = textures->needs_depth_decompress_mask;
 
@@ -1343,25 +1359,29 @@ static boolean si_generate_mipmap(struct pipe_context 
*ctx,
vi_disable_dcc_if_incompatible_format(>b, tex, base_level,
  format);
si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
  base_level, first_layer, last_layer);
 
/* Clear dirty_level_mask for the levels that will be overwritten. */
assert(base_level < last_level);
rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
 last_level - base_level);
 
+   sctx->generate_mipmap_for_depth = rtex->is_depth;
+
si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
util_blitter_generate_mipmap(sctx->blitter, tex, format,
 base_level, last_level,
 first_layer, last_layer);
si_blitter_end(ctx);
+
+   sctx->generate_mipmap_for_depth = false;
return true;
 }
 
 static void

Re: [Mesa-dev] [PATCH v1 2/7] etnaviv: Add return statement to etna_amode so compiler is happy

2017-06-16 Thread Emil Velikov 
On 15 June 2017 at 21:47, Robert Foss  wrote:
> From: Tomeu Vizoso 
>
> Signed-off-by: Robert Foss 
> ---
>  src/gallium/drivers/etnaviv/etnaviv_compiler.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler.c 
> b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
> index eafb511bb8..8f73113059 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_compiler.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
> @@ -885,6 +885,8 @@ etna_amode(struct tgsi_ind_register indirect)
> default:
>assert(!"Invalid swizzle");
> }
> +
> +   return 0;
All the cases are handled correctly and even the default one will
never be reached.
Guess the compiler isn't smart enough, since we're using int:2 while
in reality we're storing an enum and using enum:2 might not always
work.

Alternative solutions is s/assert/unreachable/. The call will be up-to
the etna devs, but including something like the above (in the commit
summary or elsewhere) will be a good idea, IMHO.

-Emil
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Re: [Mesa-dev] [PATCH 2/2] radeonsi: disable primitive restart for non-strip prims based on app list

2017-06-16 Thread Marc Di Luzio 
Hi,

>From what I'm aware this is the progress on the fixes:

TotalWarhammer and HitmanPro should now have a fix in shipping.
MadMax, DeusExMD and DirtRally have the fix in a patch making it's way
through our internal testing.

We would still very much prefer to not have a special case for our games
within compiled code in gallium trunk, the case in r300_chipset.c doesn't
appear analogous.

We'll be pushing up the priority for those remaining patches internally. If
however the consensus is to get this fixed ASAP then we'd rather the code
path be data controlled by drirc or at least an environment variable we (or
users) can set in our launch scripts in the interim weeks.

Cheers,

-
Marc Di Luzio
Linux Group Lead @ Feral Interactive Ltd.

On 16 June 2017 at 12:45, Marek Olšák  wrote:

> Hi,
>
> Feral's games still enable primitive restart for all draw calls.
>
> FYI, I will push this patch on Monday if there is no other feedback.
> Some other points:
> - This is not the first occurrence of private app lists in drivers.
> r300 also has an app list in r300_chipset.c.
> - The list of Feral's games needing this workaround was indeed
> complete at the time of writing the patch.
>
> Marek
>
>
> On Tue, Apr 25, 2017 at 11:26 AM, Marc Di Luzio
>  wrote:
> >> Thanks. Do you plan to update the games not to enable primitive
> >> restart for non-strip primitives?
> >
> > I won't be able to give a decent time frame yet, but yes I'll make sure
> it's
> > on our schedule.
> >
> > -
> > Marc Di Luzio
> > Linux Group Lead @ Feral Interactive Ltd.
> >
> > On 25 April 2017 at 10:15, Marek Olšák  wrote:
> >>
> >> On Tue, Apr 25, 2017 at 11:09 AM, Marc Di Luzio
> >>  wrote:
> >> > Hi Marek,
> >> >
> >> > I agree with Ken here.
> >> >
> >> > For what it's worth, the list of our titles that use primitive restart
> >> > here
> >> > is likely the full list. DXMD was the first as far as I know - see
> >> >
> >> > https://cgit.freedesktop.org/mesa/mesa/commit/?id=
> e33f31d61f5e9019f8b0bac0378dfb8fd1147421.
> >> > It also appears to be an app side issue so we will patch as needed.
> >> >
> >> > In the future let us know first, in pretty much all cases we'd prefer
> to
> >> > make the change on our side instead of adding game specific hacks in
> >> > Mesa.
> >>
> >> Thanks. Do you plan to update the games not to enable primitive
> >> restart for non-strip primitives?
> >>
> >> Marek
> >>
> >> >
> >> > Cheers,
> >> >
> >> >
> >> > -
> >> > Marc Di Luzio
> >> > Linux Group Lead @ Feral Interactive Ltd.
> >> >
> >> > On 24 April 2017 at 23:26, Kenneth Graunke 
> >> > wrote:
> >> >>
> >> >> On Monday, April 24, 2017 6:22:41 AM PDT Marek Olšák wrote:
> >> >> > From: Marek Olšák 
> >> >> >
> >> >> > ---
> >> >> >  src/gallium/drivers/radeonsi/si_pipe.c   | 20 +
> >> >> >  src/gallium/drivers/radeonsi/si_pipe.h   |  1 +
> >> >> >  src/gallium/drivers/radeonsi/si_state_draw.c | 45
> >> >> > 
> >> >> >  3 files changed, 54 insertions(+), 12 deletions(-)
> >> >> >
> >> >> > diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
> >> >> > b/src/gallium/drivers/radeonsi/si_pipe.c
> >> >> > index 1a83564..53a8201 100644
> >> >> > --- a/src/gallium/drivers/radeonsi/si_pipe.c
> >> >> > +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> >> >> > @@ -29,20 +29,29 @@
> >> >> >  #include "radeon/radeon_uvd.h"
> >> >> >  #include "util/u_memory.h"
> >> >> >  #include "util/u_suballoc.h"
> >> >> >  #include "util/u_tests.h"
> >> >> >  #include "vl/vl_decoder.h"
> >> >> >  #include "../ddebug/dd_util.h"
> >> >> >
> >> >> >  #define SI_LLVM_DEFAULT_FEATURES \
> >> >> >   "+DumpCode,+vgpr-spilling,-fp32-denormals,-xnack"
> >> >> >
> >> >> > +/* DX10/11 apply primitive restart to strip primitive types only.
> */
> >> >> > +static const char *apps_with_prim_restart_dx_behavior[] = {
> >> >> > + "DeusExMD",
> >> >> > + "DirtRally",
> >> >> > + "HitmanPro",
> >> >> > + "MadMax",
> >> >> > + "TotalWarhammer",
> >> >> > +};
> >> >> > +
> >> >>
> >> >> Hi Marek,
> >> >>
> >> >> You seem to be adding driver workarounds for an incomplete list of
> >> >> Feral
> >> >> Interactive's titles.  Presumably, if you're going to go this route,
> >> >> you
> >> >> may need to add more of them.  Or, perhaps this is something they can
> >> >> fix in their translator layer, so they only enable it when they want
> >> >> it?
> >> >>
> >> >> I've copied Marc and Alex from Feral in case they want to weigh in.
> >> >>
> >> >> --Ken
> >> >
> >> >
> >
> >
>
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[Mesa-dev] [PATCH 1/2] ac: parse EVENT_WRITE_EOP, RELEASE_MEM, WAIT_REG_MEM, NOWHERE

2017-06-16 Thread Marek Olšák 
From: Marek Olšák 

---
 src/amd/common/ac_debug.c | 46 ++
 src/amd/common/sid.h  |  1 +
 2 files changed, 47 insertions(+)

diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c
index a8f81bf..79473ec 100644
--- a/src/amd/common/ac_debug.c
+++ b/src/amd/common/ac_debug.c
@@ -213,20 +213,66 @@ static uint32_t *ac_parse_packet3(FILE *f, uint32_t *ib, 
int *num_dw,
case PKT3_EVENT_WRITE:
ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, ib[1],
S_028A90_EVENT_TYPE(~0));
print_named_value(f, "EVENT_INDEX", (ib[1] >> 8) & 0xf, 4);
print_named_value(f, "INV_L2", (ib[1] >> 20) & 0x1, 1);
if (count > 0) {
print_named_value(f, "ADDRESS_LO", ib[2], 32);
print_named_value(f, "ADDRESS_HI", ib[3], 16);
}
break;
+   case PKT3_EVENT_WRITE_EOP:
+   ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, ib[1],
+   S_028A90_EVENT_TYPE(~0));
+   print_named_value(f, "EVENT_INDEX", (ib[1] >> 8) & 0xf, 4);
+   print_named_value(f, "TCL1_VOL_ACTION_ENA", (ib[1] >> 12) & 
0x1, 1);
+   print_named_value(f, "TC_VOL_ACTION_ENA", (ib[1] >> 13) & 0x1, 
1);
+   print_named_value(f, "TC_WB_ACTION_ENA", (ib[1] >> 15) & 0x1, 
1);
+   print_named_value(f, "TCL1_ACTION_ENA", (ib[1] >> 16) & 0x1, 1);
+   print_named_value(f, "TC_ACTION_ENA", (ib[1] >> 17) & 0x1, 1);
+   print_named_value(f, "ADDRESS_LO", ib[2], 32);
+   print_named_value(f, "ADDRESS_HI", ib[3], 16);
+   print_named_value(f, "DST_SEL", (ib[3] >> 16) & 0x3, 2);
+   print_named_value(f, "INT_SEL", (ib[3] >> 24) & 0x7, 3);
+   print_named_value(f, "DATA_SEL", ib[3] >> 29, 3);
+   print_named_value(f, "DATA_LO", ib[4], 32);
+   print_named_value(f, "DATA_HI", ib[5], 32);
+   break;
+   case PKT3_RELEASE_MEM:
+   ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, ib[1],
+   S_028A90_EVENT_TYPE(~0));
+   print_named_value(f, "EVENT_INDEX", (ib[1] >> 8) & 0xf, 4);
+   print_named_value(f, "TCL1_VOL_ACTION_ENA", (ib[1] >> 12) & 
0x1, 1);
+   print_named_value(f, "TC_VOL_ACTION_ENA", (ib[1] >> 13) & 0x1, 
1);
+   print_named_value(f, "TC_WB_ACTION_ENA", (ib[1] >> 15) & 0x1, 
1);
+   print_named_value(f, "TCL1_ACTION_ENA", (ib[1] >> 16) & 0x1, 1);
+   print_named_value(f, "TC_ACTION_ENA", (ib[1] >> 17) & 0x1, 1);
+   print_named_value(f, "TC_NC_ACTION_ENA", (ib[1] >> 19) & 0x1, 
1);
+   print_named_value(f, "TC_WC_ACTION_ENA", (ib[1] >> 20) & 0x1, 
1);
+   print_named_value(f, "TC_MD_ACTION_ENA", (ib[1] >> 21) & 0x1, 
1);
+   print_named_value(f, "DST_SEL", (ib[2] >> 16) & 0x3, 2);
+   print_named_value(f, "INT_SEL", (ib[2] >> 24) & 0x7, 3);
+   print_named_value(f, "DATA_SEL", ib[2] >> 29, 3);
+   print_named_value(f, "ADDRESS_LO", ib[3], 32);
+   print_named_value(f, "ADDRESS_HI", ib[4], 32);
+   print_named_value(f, "DATA_LO", ib[5], 32);
+   print_named_value(f, "DATA_HI", ib[6], 32);
+   print_named_value(f, "CTXID", ib[7], 32);
+   break;
+   case PKT3_WAIT_REG_MEM:
+   print_named_value(f, "OP", ib[1], 32);
+   print_named_value(f, "ADDRESS_LO", ib[2], 32);
+   print_named_value(f, "ADDRESS_HI", ib[3], 32);
+   print_named_value(f, "REF", ib[4], 32);
+   print_named_value(f, "MASK", ib[5], 32);
+   print_named_value(f, "POLL_INTERVAL", ib[6], 16);
+   break;
case PKT3_DRAW_INDEX_AUTO:
ac_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[1], ~0);
ac_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[2], ~0);
break;
case PKT3_DRAW_INDEX_2:
ac_dump_reg(f, R_028A78_VGT_DMA_MAX_SIZE, ib[1], ~0);
ac_dump_reg(f, R_0287E8_VGT_DMA_BASE, ib[2], ~0);
ac_dump_reg(f, R_0287E4_VGT_DMA_BASE_HI, ib[3], ~0);
ac_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[4], ~0);
ac_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[5], ~0);
diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index d329ad9..c69f4f6 100644
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -273,20 +273,21 @@
 #define   R_500_DMA_DATA_WORD0 0x500 /* 0x[packet number][word index] 
*/
 #define S_500_CP_SYNC(x)   (((unsigned)(x) & 0x1) << 31)
 #define S_500_SRC_SEL(x)   (((unsigned)(x) & 0x3) << 29)
 #define   V_500_SRC_ADDR   0
 #define   V_500_GDS1 /*

[Mesa-dev] [PATCH 2/2] ac/sid.h: don't use parentheses in PKT3_RELEASE_MEM definition

2017-06-16 Thread Marek Olšák 
From: Marek Olšák 

The parses skips the line if it contains parentheses.
---
 src/amd/common/sid.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index c69f4f6..a8c78c1 100644
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -163,21 +163,21 @@
 #define PKT3_ME_INITIALIZE 0x44 /* not on CIK */
 #define PKT3_COND_WRITE0x45
 #define PKT3_EVENT_WRITE   0x46
 #define PKT3_EVENT_WRITE_EOP   0x47 /* not on GFX9 */
 /* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets
  * are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and
  * DST_SEL=MC. Only CIK chips are affected.
  */
 /* fix CP DMA before uncommenting: */
 /*#define PKT3_EVENT_WRITE_EOS   0x48*/ /* not on GFX9 */
-#define PKT3_RELEASE_MEM   0x49 /* GFX9+ (any ring) or 
GFX8 (compute ring only) */
+#define PKT3_RELEASE_MEM   0x49 /* GFX9+ [any ring] or 
GFX8 [compute ring only] */
 #define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */
 #define PKT3_ACQUIRE_MEM   0x58 /* new for CIK */
 #define PKT3_SET_CONFIG_REG0x68
 #define PKT3_SET_CONTEXT_REG   0x69
 #define PKT3_SET_SH_REG0x76
 #define PKT3_SET_SH_REG_OFFSET 0x77
 #define PKT3_SET_UCONFIG_REG   0x79 /* new for CIK */
 #define PKT3_LOAD_CONST_RAM0x80
 #define PKT3_WRITE_CONST_RAM   0x81
 #define PKT3_DUMP_CONST_RAM0x83
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 2/2] st/vdpau: fold vdpau_interop.h and vdpau_dmabuf.h

2017-06-16 Thread Ilia Mirkin 
On Fri, Jun 16, 2017 at 8:15 AM, Emil Velikov  wrote:
> On 16 June 2017 at 13:11, Ilia Mirkin  wrote:
>> On Jun 16, 2017 8:09 AM, "Emil Velikov"  wrote:
>>
>> On 16 June 2017 at 13:00, Ilia Mirkin  wrote:
>>> On Fri, Jun 16, 2017 at 7:51 AM, Emil Velikov 
>>> wrote:
 On 25 April 2017 at 15:32, Emil Velikov  wrote:
> On 25 April 2017 at 15:06, Christian König 
> wrote:
>> Am 25.04.2017 um 15:17 schrieb Ilia Mirkin:
>>>
>>> [SNIP]
>>> Is there a patch I should test?
>>
>>
>> Patch is attached, but only compile tested.
>>
>> Basically if OpenGL/VDPAU interop worked before with Kodi/MPV it should
>> still keep working.
>>
> I think we can make nouveau_drm_screen_create private and drop it from
> dri.sym, vdpau.sym + dri-vdpau.dyn
> Not 100% sure though ... we might need it for Xinerama.
>
 Ilia, did you had the chance to test the patch with or w/o the extra
 bits suggested?
>>>
>>> This was not on my radar for testing. What needs testing exactly?
>>
>>> Apply the patch and see if OpenGL/VDPAU in Kodi/MPV still works with
>>> nouveau.
>>> Do try it with DRI2 and DRI3. My extra suggestions can be sorted at a
>>> later stage.
>>>
>>> https://patchwork.freedesktop.org/patch/152674/
>>>
>>
>> Opengl + vdpau never work in mpv/Kodi. Problem solved?
>>
> Hmm surely GL VDPAU interop worked somewhere/somehow? Maarten do you
> recall how/where you tested it as you added the nouveau bits?
>
> If nothing comes to mind, we might as well merge the patch. I have a
> crazy idea that the patch alongside few extra actually might get it
> working ;-) But that for later.

GL/VDPAU interop works. Just not the way that mpv/kodi use it (at
least today). I'm not inclined to particularly worry about it... this
can all be reverted later if necessary.

  -ilia
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Re: [Mesa-dev] [PATCH 2/2] st/vdpau: fold vdpau_interop.h and vdpau_dmabuf.h

2017-06-16 Thread Emil Velikov 
On 16 June 2017 at 13:11, Ilia Mirkin  wrote:
> On Jun 16, 2017 8:09 AM, "Emil Velikov"  wrote:
>
> On 16 June 2017 at 13:00, Ilia Mirkin  wrote:
>> On Fri, Jun 16, 2017 at 7:51 AM, Emil Velikov 
>> wrote:
>>> On 25 April 2017 at 15:32, Emil Velikov  wrote:
 On 25 April 2017 at 15:06, Christian König 
 wrote:
> Am 25.04.2017 um 15:17 schrieb Ilia Mirkin:
>>
>> [SNIP]
>> Is there a patch I should test?
>
>
> Patch is attached, but only compile tested.
>
> Basically if OpenGL/VDPAU interop worked before with Kodi/MPV it should
> still keep working.
>
 I think we can make nouveau_drm_screen_create private and drop it from
 dri.sym, vdpau.sym + dri-vdpau.dyn
 Not 100% sure though ... we might need it for Xinerama.

>>> Ilia, did you had the chance to test the patch with or w/o the extra
>>> bits suggested?
>>
>> This was not on my radar for testing. What needs testing exactly?
>
>> Apply the patch and see if OpenGL/VDPAU in Kodi/MPV still works with
>> nouveau.
>> Do try it with DRI2 and DRI3. My extra suggestions can be sorted at a
>> later stage.
>>
>> https://patchwork.freedesktop.org/patch/152674/
>>
>
> Opengl + vdpau never work in mpv/Kodi. Problem solved?
>
Hmm surely GL VDPAU interop worked somewhere/somehow? Maarten do you
recall how/where you tested it as you added the nouveau bits?

If nothing comes to mind, we might as well merge the patch. I have a
crazy idea that the patch alongside few extra actually might get it
working ;-) But that for later.

-Emil
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Re: [Mesa-dev] [PATCH 2/2] st/vdpau: fold vdpau_interop.h and vdpau_dmabuf.h

2017-06-16 Thread Ilia Mirkin 
On Jun 16, 2017 8:09 AM, "Emil Velikov"  wrote:

On 16 June 2017 at 13:00, Ilia Mirkin  wrote:
> On Fri, Jun 16, 2017 at 7:51 AM, Emil Velikov 
wrote:
>> On 25 April 2017 at 15:32, Emil Velikov  wrote:
>>> On 25 April 2017 at 15:06, Christian König 
wrote:
 Am 25.04.2017 um 15:17 schrieb Ilia Mirkin:
>
> [SNIP]
> Is there a patch I should test?


 Patch is attached, but only compile tested.

 Basically if OpenGL/VDPAU interop worked before with Kodi/MPV it should
 still keep working.

>>> I think we can make nouveau_drm_screen_create private and drop it from
>>> dri.sym, vdpau.sym + dri-vdpau.dyn
>>> Not 100% sure though ... we might need it for Xinerama.
>>>
>> Ilia, did you had the chance to test the patch with or w/o the extra
>> bits suggested?
>
> This was not on my radar for testing. What needs testing exactly?

Apply the patch and see if OpenGL/VDPAU in Kodi/MPV still works with
nouveau.
Do try it with DRI2 and DRI3. My extra suggestions can be sorted at a
later stage.

https://patchwork.freedesktop.org/patch/152674/


Opengl + vdpau never work in mpv/Kodi. Problem solved?



-Emil
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Re: [Mesa-dev] [PATCH 2/2] st/vdpau: fold vdpau_interop.h and vdpau_dmabuf.h

2017-06-16 Thread Emil Velikov 
On 16 June 2017 at 13:00, Ilia Mirkin  wrote:
> On Fri, Jun 16, 2017 at 7:51 AM, Emil Velikov  
> wrote:
>> On 25 April 2017 at 15:32, Emil Velikov  wrote:
>>> On 25 April 2017 at 15:06, Christian König  wrote:
 Am 25.04.2017 um 15:17 schrieb Ilia Mirkin:
>
> [SNIP]
> Is there a patch I should test?


 Patch is attached, but only compile tested.

 Basically if OpenGL/VDPAU interop worked before with Kodi/MPV it should
 still keep working.

>>> I think we can make nouveau_drm_screen_create private and drop it from
>>> dri.sym, vdpau.sym + dri-vdpau.dyn
>>> Not 100% sure though ... we might need it for Xinerama.
>>>
>> Ilia, did you had the chance to test the patch with or w/o the extra
>> bits suggested?
>
> This was not on my radar for testing. What needs testing exactly?

Apply the patch and see if OpenGL/VDPAU in Kodi/MPV still works with nouveau.
Do try it with DRI2 and DRI3. My extra suggestions can be sorted at a
later stage.

https://patchwork.freedesktop.org/patch/152674/

-Emil
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Re: [Mesa-dev] [PATCH 2/2] st/vdpau: fold vdpau_interop.h and vdpau_dmabuf.h

2017-06-16 Thread Ilia Mirkin 
On Fri, Jun 16, 2017 at 7:51 AM, Emil Velikov  wrote:
> On 25 April 2017 at 15:32, Emil Velikov  wrote:
>> On 25 April 2017 at 15:06, Christian König  wrote:
>>> Am 25.04.2017 um 15:17 schrieb Ilia Mirkin:

 [SNIP]
 Is there a patch I should test?
>>>
>>>
>>> Patch is attached, but only compile tested.
>>>
>>> Basically if OpenGL/VDPAU interop worked before with Kodi/MPV it should
>>> still keep working.
>>>
>> I think we can make nouveau_drm_screen_create private and drop it from
>> dri.sym, vdpau.sym + dri-vdpau.dyn
>> Not 100% sure though ... we might need it for Xinerama.
>>
> Ilia, did you had the chance to test the patch with or w/o the extra
> bits suggested?

This was not on my radar for testing. What needs testing exactly?
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Re: [Mesa-dev] [PATCH 2/2] st/vdpau: fold vdpau_interop.h and vdpau_dmabuf.h

2017-06-16 Thread Emil Velikov 
On 25 April 2017 at 15:32, Emil Velikov  wrote:
> On 25 April 2017 at 15:06, Christian König  wrote:
>> Am 25.04.2017 um 15:17 schrieb Ilia Mirkin:
>>>
>>> [SNIP]
>>> Is there a patch I should test?
>>
>>
>> Patch is attached, but only compile tested.
>>
>> Basically if OpenGL/VDPAU interop worked before with Kodi/MPV it should
>> still keep working.
>>
> I think we can make nouveau_drm_screen_create private and drop it from
> dri.sym, vdpau.sym + dri-vdpau.dyn
> Not 100% sure though ... we might need it for Xinerama.
>
Ilia, did you had the chance to test the patch with or w/o the extra
bits suggested?

-Emil
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Re: [Mesa-dev] R600/AMDGPU fixes for Clover

2017-06-16 Thread Emil Velikov 
On 15 June 2017 at 14:03, Aaron Watry  wrote:
> Hey all,
>
> We haven't landed the fixes to break the r600g dependency on AMDGPU yet.
> I'm headed out of town for a long weekend and don't feel like risking the
> push before being gone for five days.
>
> I've got a v3 of Emil's patch 4/5 that removes the AMDGPU header dependency
> from r600 and I'm good with the status of Jan's 3-patch series.  I'm hoping
> we can square that away early next week unless is gets resolved while I'm
> gone.
>
I've double-checked and Jan's 1-3 (squashed 2+3) alongside my 4-5
resolve all the issues I could notice.
Pushed the lot and I'll parse through patchwork in a moment.

Thanks
Emil
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Re: [Mesa-dev] [PATCH 2/2] radeonsi: disable primitive restart for non-strip prims based on app list

2017-06-16 Thread Marek Olšák 
Hi,

Feral's games still enable primitive restart for all draw calls.

FYI, I will push this patch on Monday if there is no other feedback.
Some other points:
- This is not the first occurrence of private app lists in drivers.
r300 also has an app list in r300_chipset.c.
- The list of Feral's games needing this workaround was indeed
complete at the time of writing the patch.

Marek


On Tue, Apr 25, 2017 at 11:26 AM, Marc Di Luzio
 wrote:
>> Thanks. Do you plan to update the games not to enable primitive
>> restart for non-strip primitives?
>
> I won't be able to give a decent time frame yet, but yes I'll make sure it's
> on our schedule.
>
> -
> Marc Di Luzio
> Linux Group Lead @ Feral Interactive Ltd.
>
> On 25 April 2017 at 10:15, Marek Olšák  wrote:
>>
>> On Tue, Apr 25, 2017 at 11:09 AM, Marc Di Luzio
>>  wrote:
>> > Hi Marek,
>> >
>> > I agree with Ken here.
>> >
>> > For what it's worth, the list of our titles that use primitive restart
>> > here
>> > is likely the full list. DXMD was the first as far as I know - see
>> >
>> > https://cgit.freedesktop.org/mesa/mesa/commit/?id=e33f31d61f5e9019f8b0bac0378dfb8fd1147421.
>> > It also appears to be an app side issue so we will patch as needed.
>> >
>> > In the future let us know first, in pretty much all cases we'd prefer to
>> > make the change on our side instead of adding game specific hacks in
>> > Mesa.
>>
>> Thanks. Do you plan to update the games not to enable primitive
>> restart for non-strip primitives?
>>
>> Marek
>>
>> >
>> > Cheers,
>> >
>> >
>> > -
>> > Marc Di Luzio
>> > Linux Group Lead @ Feral Interactive Ltd.
>> >
>> > On 24 April 2017 at 23:26, Kenneth Graunke 
>> > wrote:
>> >>
>> >> On Monday, April 24, 2017 6:22:41 AM PDT Marek Olšák wrote:
>> >> > From: Marek Olšák 
>> >> >
>> >> > ---
>> >> >  src/gallium/drivers/radeonsi/si_pipe.c   | 20 +
>> >> >  src/gallium/drivers/radeonsi/si_pipe.h   |  1 +
>> >> >  src/gallium/drivers/radeonsi/si_state_draw.c | 45
>> >> > 
>> >> >  3 files changed, 54 insertions(+), 12 deletions(-)
>> >> >
>> >> > diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
>> >> > b/src/gallium/drivers/radeonsi/si_pipe.c
>> >> > index 1a83564..53a8201 100644
>> >> > --- a/src/gallium/drivers/radeonsi/si_pipe.c
>> >> > +++ b/src/gallium/drivers/radeonsi/si_pipe.c
>> >> > @@ -29,20 +29,29 @@
>> >> >  #include "radeon/radeon_uvd.h"
>> >> >  #include "util/u_memory.h"
>> >> >  #include "util/u_suballoc.h"
>> >> >  #include "util/u_tests.h"
>> >> >  #include "vl/vl_decoder.h"
>> >> >  #include "../ddebug/dd_util.h"
>> >> >
>> >> >  #define SI_LLVM_DEFAULT_FEATURES \
>> >> >   "+DumpCode,+vgpr-spilling,-fp32-denormals,-xnack"
>> >> >
>> >> > +/* DX10/11 apply primitive restart to strip primitive types only. */
>> >> > +static const char *apps_with_prim_restart_dx_behavior[] = {
>> >> > + "DeusExMD",
>> >> > + "DirtRally",
>> >> > + "HitmanPro",
>> >> > + "MadMax",
>> >> > + "TotalWarhammer",
>> >> > +};
>> >> > +
>> >>
>> >> Hi Marek,
>> >>
>> >> You seem to be adding driver workarounds for an incomplete list of
>> >> Feral
>> >> Interactive's titles.  Presumably, if you're going to go this route,
>> >> you
>> >> may need to add more of them.  Or, perhaps this is something they can
>> >> fix in their translator layer, so they only enable it when they want
>> >> it?
>> >>
>> >> I've copied Marc and Alex from Feral in case they want to weigh in.
>> >>
>> >> --Ken
>> >
>> >
>
>
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[Mesa-dev] [Bug 101252] eglGetDisplay() is not thread safe

2017-06-16 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=101252

Emil Velikov  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #1 from Emil Velikov  ---
Thanks for the report Emre.

Should be fixed in master as of
commit 311c0916588c4a596ca7e7b4bce89b059e0f
Author: Eric Engestrom 
Date:   Thu Jun 15 23:53:55 2017 +0100

egl/display: make platform detection thread-safe


Please give it a try and reopen if the issue persists.
Meanwhile we'll pick those for the stable release (might be 17.1.4, since the
17.1.3 queue is already out).

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