Re: [time-nuts] GPIB programming 'íb' style
John,
So for NI488.2 it is clear, I will go finding the
new stuff in their site... I hope to find ;-)
It would be great if they have produced some
table with the old and the new calls. I'll dig.
For porlogix I'll take a look at the timelab source,
good idea. At the moment I don't own one
and was in my concerns if I could actually write
code for it not too differently from what I already know...
Before I get one ;-)
Thanks, that was exactly the starter info I was looking.
Luis Cupido.
ct1dmk.
p.s. Many tks also to all the other replies.
On 1/23/2012 5:49 AM, John Miles wrote:
There is currently no complete, supported NI488.2 ("ib...") API
implementation for Prologix adapters. If you have TimeLab installed, check
out gpibport.cpp in the drivers\shared directory underneath the installation
folder, and you'll see separate code paths for the two interfaces (actually
three, counting the Prologix GPIB-LAN hardware).
One minor point to note: if you want to author for NI488.2, many of the
ib... calls have been removed in the 64-bit Windows edition of the NI488.2
API, so you'll end up using ibconfig() in a lot of places where you formerly
used the older functions. For instance, ibtmo(ID, timeout) would be
replaced by ibconfig(id, IbcTMO, timeout). The older API is still available
in 32-bit land, but it would be better for any new code to use the newer
guidelines, which is why I'd recommend looking at the TimeLab source rather
than my older GPIB stuff if you want to see some actual working code.
-- john
___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
[time-nuts] GPIB programming 'íb' style
Is it possible to program under Windows, still using the old_style national instruments 'ib...' calls. when using USB-GPIB interfaces like prologix or others ? many tks. Luis Cupido. ct1dmk. p.s.(I only have real GPIB 'c' programming experience on MSDOS all the rest is using high level stuff like labview. I have no clue about what GPIB-USB does when we leave the 'automagic' install & use scenario). ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] seek info 'DSP technology' and other modules
Hope you all had a great entering in 2012. Googling around I could not find any tech info on any of the "transiac" or "DSP technology" modules (I could find only many surplus sales...) these are late eighties camac modules... I have no clue if the companies exist or changed names or extinct etc. Any a light on the subject ? (or has catalogs/manuals of such) tks. Luis Cupido. ct1dmk p.s. Also for "Kinetic Systems" and "LeCroy" it seems hard too but I could find some stuff, but even so not what I wanted :-( ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] yet again more VMSK
Just read this one... I just wonder if I did anything that terrible in a past life to deserve reading this ... ;-) Recently on Microwaves and RF. http://mwrf.com/Articles/ArticleID/23644/23644.html lc. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Sine to LVDS
I had similar need some time ago and I found that a differential pair with two (pnp) BFR93 worked much better than any comparator(three or four tested, but not the adcmp604). (was a pll reference and I judged the impact of such observing the phase noise at microwaves). lc. ct1dmk. On 9/9/2011 12:29 PM, Javier Herrero wrote: Thanks for the reminder :) Te available 180MHz signal has that level, and it is quite heavily bandpass filtered, since it comes from a multiplier chain from an 45MHz OCXO, so the ADCMP604 will fit nicely Best regards, Javier El 09/09/2011 13:07, Bruce Griffiths escribió: Javier Herrero wrote: Hello all, I think that the same question that has been discuted here a zillion times but usually around 10MHz... anyway, what would be the best way to convert a sine wave to a LVDS clock (preferably duty cycle 50%) at 180MHz? Texas Instruments suggest a LVDS receiver as a comparator http://www.ti.com/lit/an/slyt180/slyt180.pdf but time ago this was discussed here, and not very favoured due to the high hysteresis of the LVDS receivers. Regards, Javier Use a true LVDS comparator (e.g. ADCMP604). With 1:1 transformer coupled input and a pair of inverse parallel schottky diodes across the inputs together with series resistors between the transformer secondary to the comparator inputs should suffice for inputs of +16dBm or more. With sufficient input from a low noise source a cycle to cycle jitter of 1-2ps should be feasible. Sub picosecond jitter is feasible if one cascades a series of low pass filtered limiter stages. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Gerhard. This was an old thing I asked a month ago or so... Only the MSB of the accumulator is used to serve as reference to a pll. No sin or DAC involved ;-) Luis Cupido. ct1dmk On 7/21/2011 6:10 PM, dk...@arcor.de wrote: IMHO, that would require a sine table with a steerable number of entries. Very problematic for a tunable DDS, but doable for a fixed frequency application, although address mirroring for ROM size reduction would require real address comparators instead just using the 2 MSBs as a selector. The table could also be in RAM instead of ROM without large increase of the cost in an FPGA, so with some processor support one might approach "tunable". regards, Gerhard It crossed my mind of messing somehow with the phase accumulator metrics but did not figure a way... that is a good suggestion I will investigate in that direction... (or maybe... if you do have a bit of free time to drop me a couple of lines more, could you please detail a bit more as so far I did not caught the idea clearly enough to start coding...) On 7/21/2011 9:11 AM, Magnus Danielson wrote: You want to consider a phase-accumulator with a steerable or suitable sequence length. That way you can match up the ratio to form a suitable for the frequency you want and the spurioses will become harmonics so to speak. Such a phase-accumulator gets shortend and takes some comparision of phase-state to translate state at the end of the sequence to the next period. A bit more logic, but comes with some nice properties. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Magnus, It crossed my mind of messing somehow with the phase accumulator metrics but did not figure a way... that is a good suggestion I will investigate in that direction... (or maybe... if you do have a bit of free time to drop me a couple of lines more, could you please detail a bit more as so far I did not caught the idea clearly enough to start coding...) Luis Cupido. ct1dmk. p.s. No problem with the delay... ;-) On 7/21/2011 9:11 AM, Magnus Danielson wrote: On 21/06/11 12:48, Luis Cupido wrote: Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). You want to consider a phase-accumulator with a steerable or suitable sequence length. That way you can match up the ratio to form a suitable for the frequency you want and the spurioses will become harmonics so to speak. Such a phase-accumulator gets shortend and takes some comparision of phase-state to translate state at the end of the sequence to the next period. A bit more logic, but comes with some nice properties. Cheers, Magnus - this reply was only a month late... ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Thanks Jim, Joseph already pointed me to a pdf in a previous post. Now it is digestion time... should I say congestion !!! those MASH delta-sigmas are killing me... lc. ct1dmk. On 6/23/2011 4:30 AM, Jim Lux wrote: On 6/22/11 3:36 PM, Luis Cupido wrote: I knew I must not have been the fist one to be looking for such. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4014919 (unfortunately I'm not ieee member and $30 looks more like a book price to me... not an article... bahhh!) Luis Cupido. ct1dmk. if you email the author, often they will send you a pdf of the paper (or they'll have it on the web). The standard IEEE copyright assignment lets the author self publish on their own website or by sending reprints electronically. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Indeed, may google be... Thanks, Joseph. lc ct1dmk. On 6/23/2011 12:12 AM, Joseph M Gwinn wrote: May Google be with you: A search on the title and an author yielded: <http://petrified.ucsd.edu/~ispg-adm/pubs/mtt-s_2006.pdf> From: Luis Cupido To: Discussion of precise time and frequency measurement Date: 06/22/2011 06:37 PM Subject:Re: [time-nuts] DDS'ery narrow scoped. Sent by:time-nuts-boun...@febo.com I knew I must not have been the fist one to be looking for such. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4014919 (unfortunately I'm not ieee member and $30 looks more like a book price to me... not an article... bahhh!) Luis Cupido. ct1dmk. On 6/21/2011 11:48 AM, Luis Cupido wrote: Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). lc ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
I knew I must not have been the fist one to be looking for such. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4014919 (unfortunately I'm not ieee member and $30 looks more like a book price to me... not an article... bahhh!) Luis Cupido. ct1dmk. On 6/21/2011 11:48 AM, Luis Cupido wrote: Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). lc ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS - Cosine v. Sine LUT
Hi Brent, A quarter table cos is exactly the same as a quarter table sin. Only backwards, and not telling which quarter it is makes it a quarter of either sin or cos. For one single output becomes irrelevant as you only need one. So I think it is just a matter of taste the name to call it. Luis Cupido. ct1dmk. On 6/21/2011 8:03 PM, KD0GLS wrote: On Jun 21, 2011, at 13:39, Chris Albertson wrote: I used only 90 degrees of the table. Yes, as did I and most implementations, but why a cosine quarter-table instead of the more common sine? A quick look at the data sheets (and the waveforms in the theory-of-op sections) for the two devices suggests they are clearly calling out one or the other, but without rationale regarding the choice. .73, Brent, KD0GLS, Minneapolis ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
I've played with the core from altera for a while, but since I was only interested in 1 bit I'm now playing with my own code. Trivial variations on the plain old clocked accumulator architecture. lc On 6/21/2011 7:37 AM, Javier Herrero wrote: What it the topology you're using now? Also, I would like to know which DDS core are you using? (since I will need to use one quite soon, probably on a Cyclone IV E) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). lc ct1dmk. On 6/21/2011 7:43 AM, Javier Herrero wrote: But I forgot to add that the resultant jitter will be also the sampling rate period (10ns at 100MHz), so I think that the output will not be too clean... so I'm afraid it will not be a great improvement over using only the MSB :) Regards, Javier El 21/06/2011 08:37, Javier Herrero escribió: I supppose that then you will need the digital version of the DDS -> Filter -> Comparator think, usign a FIR and outputing the sign of the resultant signal. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Hi Ulrich, Loop bandwidth could be in the KHz region or even less. I could choose more or less freely from Hz to many KHz but there are obvious tradeoffs and it is hard to decide. The phase noise of the VCO when I go too narrow versus the ammount of spurs when I go too wide. Application is the first LO for an experiment in SDR radio at VHF-SHF region,(not HF). Luis Cupido. ct1dmk. On 6/21/2011 10:03 AM, Ulrich Bangert wrote: Luis, the information that you are concerned about close carrier spurs that will pass through the PLL's low pass filter is not precise enough: are you talking about a few Hz, a few ten Hz, a few 100 Hz away from the carrier or are you going to build a device for precise timing applications where also spurs far below (perhaps orders of magnitude below) 1 Hz may be of concern? Best regards Ulrich Bangert, DF6JB -Ursprungliche Nachricht- ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Hi, I'm an Altera user and would say the DDS core generator is really very good, I would expect it to be not too different from Xilinx these days. (does anyone that lives on both worlds know better ?) lc ct1dmk. On 6/21/2011 10:03 AM, Ulrich Bangert wrote: John, as usual I second your opinion and I did have already on my mind to suggest XILINX's DDS compiler to the group too. However your statement to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) has pushed me up! When I tell the compiler to generate me a 150 dB SFDR DDS then it produces an block with 28 (!) bits output witdh for the DAC. So, I am asking myself what wonder-chips you may be using as DAC for your DDS that features a dynamic range high enough to really measure a 150 dB SFDR? Best regards Ulrich Bangert, DF6JB -Ursprüngliche Nachricht- Von: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] Im Auftrag von John Miles Gesendet: Dienstag, 21. Juni 2011 00:52 An: 'Discussion of precise time and frequency measurement' Betreff: Re: [time-nuts] DDS'ery I'm not familiar with Altera's DDS options, but I will say that Xilinx's DDS compiler is superb. It can be configured to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) As Javier hinted, the reason you can't use the MSB directly is that its transition point is not necessarily stationary between cycles of the frequency you're trying to synthesize. It will flop around all over the place. You need at least a few more bits in most applications -- remember that in an n-bit word, the magnitude represented by the n-1 LSBs is almost as much as the bit-n MSB. When DDS technology was first becoming popular in the 1980s, Qualcomm was one of the main vendors, and they required external DACs. High-speed DACs were pricy and used a lot of power, so I imagine that a great many people tried feeding the MSB directly to the filter, as I did. It could be feasible at some selected frequencies or at very high clock/output ratios, but in the general case the output signal is just comically awful. You would need a truly massive filter to provide the needed flywheel effect to make up for those missing bits. And it would need to be a BPF, not just an LPF, because not all of the artifacts associated with output quantization are above the desired carrier frequency. Sometimes the MSB's toggle period is going to be shorter than it should be, and sometimes it's going to be longer. -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts- boun...@febo.com] On Behalf Of Luis Cupido Sent: Monday, June 20, 2011 9:46 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DDS'ery Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Thanks. Luis cupido. ct1dmk. On 6/20/2011 4:52 PM, Javier Herrero wrote: To reduce the spurii due to quantization distortion. Here is an explanation, in Section 4 http://www.analog.com/static/imported- files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf Regards, Javier El 20/06/2011 17:39, Luis Cupido escribió: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi- bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] DDS'ery narrow scoped.
Folks, Many thanks to you all, for the info. This is indeed a great forum. My aplic. is a DDS signal that will serve as reference for a pll with a relatively narrow loop filter. As I said before. Most replies presume the analog world with DAC filters etc etc. But that I know ;-) I'm digging out the possibilities in the digital side not involving going back to analog and back to digital. this is how this started :-) Now that you all have been so kind in the great comments you gave, please let me just be very very very specific. Imagine an FPGA and a square wave coming out. Just that. Nothing more. (That is what I had in mind when querying about the MSB usage in the first place.) My first approach was the ACC MSB (and that is working already on the bench.) So I'm researching a way to have that digital output cleaner (spurs) without leaving the digital(FPGA) world sticking to the block diagram of one FPGA one digital output. Specially worried about close in spurs (the far away ones won't bother me much). That is really scenario I'm trying to picture if there is any hope to generate a cleaner digital output out of an FPGA (dds with whatever processing required to be done after and producing a square wave). Thanks for your patience. Luis Cupido. ct1dmk P.S. At the moment I'm testing on the bench with a real FPGA cyclone III with a 48bit dds at 100MHz fclock and at circa 6 and 18MHz output and it is not that bad. I got better than -60dBc in the desired ranges. So not too unhappy for a start ;-) PLL cleans 99% of it... but the close in spurs are annoying. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. ... Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Thanks. Luis cupido. ct1dmk. On 6/20/2011 4:52 PM, Javier Herrero wrote: To reduce the spurii due to quantization distortion. Here is an explanation, in Section 4 http://www.analog.com/static/imported-files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf Regards, Javier El 20/06/2011 17:39, Luis Cupido escribió: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Thanks for the comments... Yes the key is obviously the low pass filtering one has the other doesn't. I had mainly in my mind a PLL following that ACC. so actually driving a phase comparator of a PLL (narrow enough loop bw) that problem would not exist. Ok great. Good point on the mixer we got to have nothing in the alias region for it to be ok. (not my application at the moment but will keep that in mind) Thanks guys... Luis Cupido. ct1dmk. On 6/20/2011 4:11 PM, Graham / KE9H wrote: Luis: No, not the same. The most significant bit out of the accumulator has the alias information on it (Fs +/- Fo), so it still needs to be run through the low pass filter to clean off the alias signals. The alias signals manifest themselves as jitter, so no amount of just clipping will remove them. If your application is not sensitive to the alias frequencies, then OK to drive out of the DDS directly. If you are driving something like a mixer in a wide band radio, then you still need to use the low pass filters. They don't call them anti-alias filters for no reason. --- Graham / KE9H == On 6/20/2011 9:46 AM, Luis Cupido wrote: Folks, a quick one... A DDS, that is an accumulator with a DAC followed by a low pass filter and comparator (zero crossing) to produce a square wave to drive a PLL or a MIXER or else (at logic levels). Isn't it the very same thing as just using the most significant bit of the accumulator. Or am I missing something here ? Comments appreciated. thanks. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Forgot the sine table... I meant obviously <...an accumulator 'sine table' and DAC...> lc. On 6/20/2011 3:46 PM, Luis Cupido wrote: Folks, a quick one... A DDS, that is an accumulator with a DAC followed by a low pass filter and comparator (zero crossing) to produce a square wave to drive a PLL or a MIXER or else (at logic levels). Isn't it the very same thing as just using the most significant bit of the accumulator. Or am I missing something here ? Comments appreciated. thanks. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] DDS'ery
Folks, a quick one... A DDS, that is an accumulator with a DAC followed by a low pass filter and comparator (zero crossing) to produce a square wave to drive a PLL or a MIXER or else (at logic levels). Isn't it the very same thing as just using the most significant bit of the accumulator. Or am I missing something here ? Comments appreciated. thanks. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Darn you people....
Hi Bert, Well, without the averaging I think I was correct (I was obviously not considering the averaging). Your implementation with averaging surely smooth this proportionally and yes you end up better than 0.0625 as more you integrate. Please consider then the numbers you may find relevant and the corresponding integration time. (that was not really the point in my email). But since all topologies can average I presume you agree that potential differences between systems as remarked in my email still apply. Namely an offset at a frequency drift that is basic behavior of any FLL you wont have on a PLL. All that may fall below most practical needs(1), I agree... But in the timenuts spirit ought to be pointed out... right ? ;-) Luis Cupido ct1dmk. p.s. (1) folks running several Cesium stds don't be offended I'm not saying your needs are not practical :-) ;-) hi Bert, VE2ZAZ wrote: Luis, You said: <> On my GPSDO design, a single 16-second frequency sample does have a resolution of 0.0625Hz. But the FLL firmware does averaging over as many samples as you want before adjusting the OCXO. So I don't agree with your statement that the ZAZ gpsdo won't lock better than 0.0625Hz. In fact, I have never seen my design go worse than 1x10E-9. It usually sit below 5x10E-10. This concurs with the many reports I got from other users. Please elaborate. Thanks, Bert, VE2ZAZ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Darn you people....
Bob, You must be aware that the VE2ZAZ GPSDO does not lock the 10MHz phase to the phase of the 1pps. It is a frequency counter which uses the frequency error to correct the 10MHz VCXO. So it is a frequency locked loop FLL. By definition on a PLL you will have the phase error being used to compensate the 10MHz VCXO On a FLL a frequency error is required to compensate the 10MHzVCXO While having a permanent very very slow OCXO trend (drift or aging) a PLL(order 2) will exhibit a constant phase error while the frequency is right. With an FLL it will have a constant frequency error. Furthermore the frequency counting resolution is 16 seconds, so the ZAZ gpsdo won't lock better than 0.0625Hz. A PLL scheme, thunderbolt, the old Brook Shera's, the 10KHz James Miller's, or my reflock (I or II) will get you always on the ballpark. This PLL/FLL aspect is a subtle difference that has absolutely no expression whatsoever for radio-ham applications both TX and RX on HF to microwaves etc. application to which it was targeted and serve very well. But you will surely start to see these small aspects when you step into the next level of timenutness !!! Apparently you have both feet there... looking at sub Hz you're infected that's a fact ;-) Luis Cupido. ct1dmk. Bob Bownes wrote: First it was building a VE2ZAZ GPSDO with an 10881 I happened across. Next came the TICII's followed closely by the 5370B. Then the thunderbolt. Now it's time to break down and get 10Mhz/5Mhz distributed to all the instruments in the lab. (Still looking for a distribution amp) Now the ZAZ GPSDO and the thunderbolt are side by side on the bench. Both said they were locked last night. But they were about 0.10hz apart. Now the GPSDO voltage adjust is all the way to the bottom rail. I have no idea what time it is! Grrr. :) I suspect the 10881. :( ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] chip scale Cs133 cell.
http://spectrum.ieee.org/semiconductors/devices/chipscale-atomic-clock Luis Cupido ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] spur prediction DDS software
Jim, Bob, Henry, Brian, Thanks to all. Very good. yeap, I do work on matlab so I think there is plenty now to keep me busy ;-) tks. Luis Cupido ct1dmk. p.s.(what's cooking) I need a relatively narrow tunning range but absolutely free of close in spurs, willing to see if a modest size DDS (inside an FPGA) will do so... and what parameters will be... ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] spur prediction DDS software
Hi, Is there a DDS spur prediction software around ? I mean for an arbitrary DDS design, like I would implement with logic or fpga etc. A code where I can enter nr of bits adc bits etc. (not a thing for a particular analog-devices chip or other dds chip) tks. Luis Cupido ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Software defined spectrum analyzer
Tks, folks. I saw the diagram on the manual, albeit a bit too simplified but ok, indeed we can have an idea. For LO I suspect that might be one of those clock generators IC with VCO + PLL plus a a lot of programmable dividers and really would match the simplified diagram they have As for the digital part I have no idea, but would not be surprised of that very simplistic single chip approach sound card chip and an USB micro to feed the control bits to the PLL chip... It may well be a very very simple thing hardware wise. ...hence, I'm still curious ;-) Luis Cupido. jimlux wrote: Don Latham wrote: Hi Luis:I, too, am curious. But I haven't opened it yet. I suspect something like an FPGA feeding a fast a/d somewhere in the 50-70 MHz range. That is, a decomposition. There may be a synthesized LO and mixer to get to the 50 MHz. The info on the website says or used to say something about an sdr modified to act as a spectrum analyzer. One of the things I like about the device that played a part in my purchase is the availability of a 10 MHz reference input. as a good time-nut that shows some serious engineering attention to accuracy. Don I'm going to guess much simpler inside.. Essentially a programmable receiver like the Icom PCR1000, but with better bandwidth, running into a pair of 192kHz ADCs, for which easy USB interfacing is available. The question is really what does the 4GHz LO in the front look like? It's almost certainly some sort of VCO PLL scheme, probably with multiple VCOs. But, do they use a DDS? Probably not... They probably have a fast PLL that settles quickly so they step through in 100 kHz steps or so. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Software defined spectrum analyzer
Hi Don. I'm ultra curious of how they did it. How did they covered the full BW they have. Did you looked inside, or did they sent a block diagram? (...I was born curious... it is not a new symptom!) Luis Cupido. ct1dmk. Don Latham wrote: I have one of the original analyzers, and I'm quite satisfied with it. Note that there is a set of drivers so that the device can be used as, say an SDR. There's also a nice USB power meter available from Mini-Circuits for about $700, although I do not have one. Don - Original Message - From: "Geraldo Lino de Campos" To: Sent: Friday, December 10, 2010 6:13 PM Subject: [time-nuts] Software defined spectrum analyzer I found this device on the net. It seems quite capable for the price. Does anyone have experience with it, or the previous version? http://www.signalhound.com/ Geraldo gera...@decampos.net ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] GPS simulator,
> But they mention software to generate sequences. Hummm... right... so I think we need to look inside one to be sure what it is... lc ct1dmk. jimlux wrote: Luis Cupido wrote: Hi, The fact they refer that atmospheric s/n degradation and dropouts etc being replayed precisely lead me to think this is just a spectrum rec/play machine (no mod/demod of any kind) like the ham-oriented "time machine" but for GPS. http://www.expandedspectrumsystems.com/prod2.html Luis Cupido. ct1dmk. But they mention software to generate sequences. It's actually a fairly clever idea. It's easy to stream 16.3xx Mbps from a modern computer, so you could generate an arbitarily complex signal off line.. For a lot of applications this would be great. A nice test source that you could replay on command. The only question I'd have is whether the 1 bit DAC can adequately represent the real-life complex signal. I suppose, intuitively, since your receiver is digitizing it with a 1 bit ADC... And, I have a question whether the 1 bit DAC can produce a high enough fidelity waveform for a higher performance receiver that uses a multibit digitizer. Since the clock you are recording and playing back with isn't necessarily as good as the one on the satellite, you probably couldn't use this for testing your precision receiver. It would be like introducing a random propagation variation or coax length variation in the system. It is intriguing though.. a homebrew version could be quite simple.. you can get the USB interface and a small FPGA pretty easily. One of those 10.23 MHz crystals from Rick might be handy... ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] GPS simulator,
Hi, The fact they refer that atmospheric s/n degradation and dropouts etc being replayed precisely lead me to think this is just a spectrum rec/play machine (no mod/demod of any kind) like the ham-oriented "time machine" but for GPS. http://www.expandedspectrumsystems.com/prod2.html Luis Cupido. ct1dmk. Bob Camp wrote: Hi It's not real clear that they do anything more than sample the RX and play it back for the TX. Bob Sent from my iPhone On Nov 25, 2010, at 9:39 AM, "J. Forster" wrote: Agreed. The trick is to properly partition what is done in hardware ane what is done in software. This could eliminate a lot of logic hardware. Clearly, the RF stuff and modulator are hardware. Ditto PR code generation. Everything else in SW, I think. FWIW, -John === Hi One bit serial at 16 MHz isn't all that fancy any more. Sounds like a shift register feeding a couple filters. The money must be in the receive side. Bob On Nov 24, 2010, at 5:14 PM, erniepe...@aol.com wrote: Hi, found an interesting unit. I think it is not for the usual pocket money for a time-nuts. have a look... http://www.chronos.co.uk/pdfs/rac/labsat.pdf Rgds Ernie. -Original Message- From: John Green To: time-nuts@febo.com Sent: Mon, Nov 22, 2010 6:43 pm Subject: [time-nuts] GPS jamming susceptibility Given that this is an extremely sensitive topic and completely illegal lso, let me just state at the outset that I have no interest in amming anyone's GPS. A while back, I was looking at one of those hinese discount electronics websites, I'm sure we all have, and oticed a GPS jammer for sale. I had been wanting to do some jamming usceptibility testing for quite some time but had never got around to uilding a generator to test with. The thing was cheap so I ordered t. After it arrived, I opened it up, first thing, to see how it was ade. It has a dual 555 oscillator, a couple of analog switches, a 1.9 Hz VCO, a single amplifier. It doesn't look capable of putting out ore than 50 milliwatts or so into a 2 inch antenna. I was somewhat ubious that it would do anything, so I took it to the bench where the 3801 lives and turned it on. Within 2 seconds, the holdover LED lit. immediately turned it off and within a few more seconds, the oldover LED was back off. The GPS antenna is perhaps 35 feet away ith a cinder block wall, a brick wall, and a metal roof in between. I lso put a 15 Db attenuator between it and the antenna with almost the ame result. I am going to do more testing with it wired into the GPS ownfeed an an adjustable attenuator in line just to see how much ignal it takes. That way, there will be little danger of messing with nyone's reception. It is just a simple sweeper so it must do its job y brute force. I am amazed that it took so little to shut my Z3801 own. Has anyone here had any actual experience testing GPS receivers or susceptibility? ___ ime-nuts mailing list -- time-nuts@febo.com o unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts nd follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Simulation
(in production yes I agree) In research things are different. You wouldn't mind to make an selection of fets or else to obtain the very top specs of a certain unique instrument design as the real final product are the results you may obtain with that instrument and not at all it's design... So many nice stories about gear that worked only with a certain set of parts way off the manufacturers expressed data... one day I'll drop a few here just for amusement. Luis Cupido ct1dmk. J. Forster wrote: FWIW, IMO any engineer who uses undocumented or uncontrolled parameters or instructions in a production design is a fool. If you are that silly, you must fully specify the selection criteria. -John === Bob Camp wrote: Hi Simply a few stories I thought I would share. Simulate design. Use manufacturer's published models. Build design. Note differences. Call manufacturer. Answer - switched die three years ago, Ft is now " much better " ( now 3x old parts ). Odd they never mentioned that to people who work for the same company. Simulate design, Build design, verify design, ship it for a few years. Odd things start to happen. Look at some parts. Package looks different. Ask around. Line got moved to other side of big ocean. Process got " tweaked" beta is now 4x what it was. Again all inside the same company. Both cases were excused by industry standard specs that had no upper limit. We had whole departments devoted to tracking this sort of stuff. It still happened on a regular basis. 30 years later the specs on the devices and their published models are still the " old version " ones. there are also designs that depend on "non-data-sheet" performance of particular devices. There's a very low noise, very low leakage fet popular in charge amplifiers. It has a JEDEC 2N number (which I can't remember off hand), but only the ones from one particular company (in England) actually work in the circuits, and even then, there's some hand selection involved. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] rapid startup GPSDO
(*) uW Radio ham application where you arrive on the top of the hill and switch all equipment on and can be making contacts minutes after having better than 1e-8(1e-9). that's precisely the sort of application I'm looking at.. Wheels stopped to on-the-air in <20 minutes. Then... Look no further ;-) Reflock to 1pps is your thing. Take a look of all variants by VE1ALQ and G8ACE (there is also a japanese variation... can't recall). all those variants may use my reflockI 1pps CPLD config. Luis Cupido. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] rapid startup GPSDO
Jim, The implementation I've done on "reflock II" (on a MAXII CPLD form Altera http://www.qsl.net/ct1dmk/reflock.html ) Had fast aqs time in mind(*). It captures in few 1pps pulses and could stabilize to about 1% of dac range in quite less then 60s. How slower you need it to be in addition to the above timings depends on how much you want to average the 1pps. Having it fast it would obviously track the 1pps jitter. 'how good you need' -> 'how slow it has to be' These timings are off course after your GPS starts producing good enough 1pps pulses. Luis Cupido. CT1DMK. P.S. Super cheap approach is the reflockI (on a $5 CPLD) for which I made also a 1pps code. (but a few less specs and addons than II) (*) uW Radio ham application where you arrive on the top of the hill and switch all equipment on and can be making contacts minutes after having better than 1e-8(1e-9). jimlux wrote: Is there some (inexpensive) GPSDO that has a "time from power on in an unknown location to reasonably stable" in the <5 minute category? Frequency accuracy in the 1E-9 range would be fine. A regular old GPS has a Time to First Fix well under that, and it should be cranking out 1pps pulses with 1E-7 or 1E-8 precision pretty quickly.. Would it be fair to say that after 100 seconds, one could theoretically have driven that down another factor of 10? As I understand it, a thunderbolt needs some number of hours after turn on to stabilize, but just how bad is it after, say, 5 minutes. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Info on MTI osc.
Tks, Bruce, Tks, John, Looks that is it. (I could not find the info... must improve my googling skils hi). Not sure how to decipher the reference but at least I know it is a 5MHz and know what kind of performance to expect, in principle. Many thanks. Luis Cupido. ct1dmk. John Miles wrote: Looks like the 230 series is still supported by Milliren: http://www.mti-milliren.com/pdfs/230.pdf -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com]on Behalf Of Luis Cupido Sent: Thursday, July 01, 2010 4:20 PM To: Discussion of precise time and frequency measurement Subject: [time-nuts] Info on MTI osc. Does anyone has data on the MTI 230-0546-A OCXO (5MHz). ( If no datasheet, just pinout best guess may help ). Many thanks. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Info on MTI osc.
Does anyone has data on the MTI 230-0546-A OCXO (5MHz). ( If no datasheet, just pinout best guess may help ). Many thanks. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Best OCXOs, phasenoise wise.
I'm quite sure someone has went down this road... so I better ask first. Phase noise wise what would be the best OCXO's that we could find around, taken from equipments, or ebay etc. I have in mind essentially the HP ones. the PIEZZO ISOTEMP, CMAK, Vecton(harder to find) and some of the small wenzels, BLIBEY, OACs and a few more. Not necessarily just 10MHz... other freqs are of interest too. Any generic heading info/help? Many Thanks. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DCF77 clock with UTC display
Folks, I have one that displayed CET time so I opened it and discover a suspicious set of solder-shortable pads I shorted them (few trials) and bingo !!! It displays now in UTC. It even shows a small "utc" symbol on the display. It is a "stabo funktimer II" But stabo no longer has them on their web site... (it was 10 years ago I got it) More, I'm out of the official DCF77 range and it receives beautifully (I believe it is due to the fact they used a big rod ant) If it helps the find one I can take a picture of mine. Luis Cupido. ct1dmk. Rob Kimberley wrote: You could try Meinberg in Germany. www.meinberg.de Rob Kimberley -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of AL1 Sent: 06 June 2010 4:42 PM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DCF77 clock with UTC display Hi Giuseppe, i remember that Elektor had such a description; but i don' know when, i am looking for it... Alain Bouchet F4GBC - Original Message - From: "Giuseppe Marullo" To: "Discussion of precise time and frequency measurement" Sent: Sunday, June 06, 2010 1:55 AM Subject: Re: [time-nuts] DCF77 clock with UTC display DCF77 is transmitted in CET/CEST and so receivers generally just display the received data with some allowing other TZ offsets as it can be received in the UK for example. I also lucked out when looking for one where >daylight savings adjustments could be removed . Mike, exactly what I am experiencing. I am starting to believe that I will have to ask to ham radio manifacturers (like MFJ but they are US based) until they will develop a specific product, or I will have to build it myself, like a DCF77 receiver with some ehm, custom handling of the summer time... I can't believe there is no such need for aviation or other fields. Giuseppe Marullo ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Simple PLL chips, gone ?
Hi, I'm looking for a relatively simple PLL chip like LMX1501 or similar. I mean, looking for a new design, that is something that is easy to source (known to be in production etc) recent/modern enough to provide a low phase noise. Is for VHF/UHF below 500MHz application and will be for MHz steps (no small steps required). Albeit reasonably low phase noise will be wanted. What seems to be available from An.Dev. and Nat.Sem. are way too unnecessarily complex and I would like it to not have a zilion registers to load via spi. (might use just a small corner of a CPLD to load it). Are the simple ones gone obsolete, or simple no longer in the web pages ??? ok... I think you got the idea... I'm looking for the basic think... Any suggestions of what might be usable/available. Thanks. Luis Cupido ct1dmk. p.s. I know it doesn't matter to have a modern complex one as some microcontroller will be programming it etc etc... That I know already ;-) ... no need to tell me :-) but... if a simple ones exist why should I go complex ! ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Symmetricom 5115A Phase Noise Allen Deviation TestSet on ePay
Hi Tom, 10log I have no doubts that money=power... from years of personal experience of little power ;-) ;-). Luis Cupido. ct1dmk. Tom Holmes, N8ZM wrote: Hi Luis... Is that based on 10Log, or 20Log? I'm thinking Money = Power ;-). Regards, Tom Holmes, N8ZM Tipp City, OH EM79xx -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Luis Cupido Sent: Wednesday, April 07, 2010 9:36 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Symmetricom 5115A Phase Noise Allen Deviation TestSet on ePay about 16dB down (I think). :-) lc ct1dmk. Steve Rooke wrote: Ah! but is it cheaper than US $15,865.00? On 8 April 2010 01:05, Luis Cupido wrote: BTW, I have this recently developed for another application http://w3ref.cfn.ist.utl.pt/cupido/dl/050.jpg it has all it takes to make that type of instrument with all that performance or better. (2x100ms/s 16bit ADC, 40k FPGA and USB2 interface). (both clock and triggers can come externally from low PN sources)... 40ke Cyc III fpga has more than enough multipliers and etc for the sort of conversions and correlations needed... and the display and fancy interface would happen in the PC. Anyone feels attracted to do some coding ??? Luis Cupido ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Symmetricom 5115A Phase Noise Allen Deviation TestSet on ePay
about 16dB down (I think). :-) lc ct1dmk. Steve Rooke wrote: Ah! but is it cheaper than US $15,865.00? On 8 April 2010 01:05, Luis Cupido wrote: BTW, I have this recently developed for another application http://w3ref.cfn.ist.utl.pt/cupido/dl/050.jpg it has all it takes to make that type of instrument with all that performance or better. (2x100ms/s 16bit ADC, 40k FPGA and USB2 interface). (both clock and triggers can come externally from low PN sources)... 40ke Cyc III fpga has more than enough multipliers and etc for the sort of conversions and correlations needed... and the display and fancy interface would happen in the PC. Anyone feels attracted to do some coding ??? Luis Cupido ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Symmetricom 5115A Phase Noise Allen Deviation TestSet on ePay
BTW, I have this recently developed for another application http://w3ref.cfn.ist.utl.pt/cupido/dl/050.jpg it has all it takes to make that type of instrument with all that performance or better. (2x100ms/s 16bit ADC, 40k FPGA and USB2 interface). (both clock and triggers can come externally from low PN sources)... 40ke Cyc III fpga has more than enough multipliers and etc for the sort of conversions and correlations needed... and the display and fancy interface would happen in the PC. Anyone feels attracted to do some coding ??? Luis Cupido ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] CPLDs for clock dividers
You may try Altera. Quatus web 9.1 is 1.5Gb and painless to setup. https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp lc. ct1dmk. paul swed wrote: I also did the web install and need to go back and add more options. How painful. Enough to drive me away from this project On Thu, Feb 4, 2010 at 6:26 PM, Gerhard Hoffmann wrote: paul swed wrote: Well not having a lot of luck with the xilinx wise application. Its a 6.5 GB tar and after a good 5 hr plus download the tar doesn't open with zipgenious But 6.5 GB to work a cpld. Seems crazy to me. I also had no luck two weeks ago with the single file download. The web install worked ok, however. It downloads many smaller files. I think my very slow DSL connection is to blame here. :-( Two years ago, when I still lived in Berlin, Xilinx used to have one of the few servers that were capable to max out my (then) 16 MBit/s link. @ Ulrich: Did you see a show stopper with the Xilinx Coolrunners? I have used them before and liked them. Really fast and they consume close to no power. I'd like to deploy them for something jitter-critical very soon. regards, Gerhard dk4xp ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] CPLDs for clock dividers
Hi Ulrich. Initially I was doing two measurements first one was a simple XOR followed by a low pass filter an then acquire the signal (not so simple to measure anything sensible as it might look). second was by using the signal on the input of a microwave PLO oscillator and look at the output signal at about 12GHz on the SA. (and many times at 24GHz and higher). Certainly not good enough to let me derive jitter figures (without pain) but very effective to compare between signals coming from different sources (in the present case logic circuits). Nowadays I only go the microwave/mmW option to 'see' how it 'sounds'... and differences 'pop up' to your eyes/years just like that. ;-) Luis Cupido. ct1dmk P.S. I did a lot of exprimentation long time ago when I was palying with the LO for the DSN rx, where I was looking for phase noise to be quite low at 1Hz offsets. This to tell that noise far away from the carrier was also not a big concern for me at the time. Ulrich Bangert wrote: Luis, with the help of Bruce I have been trying to put the digital part of a linear phase comparator (for oscillator characterization) into some different Xilinx CPLDs. Only to find out that there must be a lot of "analogue kind" interactions between blocks within the CPLD that had originally been understood as being purely digital circuitry. I have the tool chain for ALTERA available as well and I find it highly interesting that your experience with the MAXII is that good. I will give them a try! Can you explain a bit what measurement possibilities for jitter you have available to make these conclusions from? Best regards Ulrich, DF6JB -Ursprungliche Nachricht- Von: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] Im Auftrag von Luis Cupido Gesendet: Donnerstag, 4. Februar 2010 15:21 An: Discussion of precise time and frequency measurement Betreff: Re: [time-nuts] CPLDs for clock dividers I understand your arguments... I just wonder why reality differs. I had a design (GPSDO) that I tested on a FPGA (Cyclone) and the same on MAXII and the difference was abyssal !!! Whatever... the MAXII family has a unbeatable jitter performance compared to discrete logic... That I can tell by direct observation. Other CPLD's I can't tell much only MAX3000 that was slightly worst and MAX7000 that was the same as TTL +/-. Know nothing about Xilinx or others... There are so many devices nowadays that I do accept that we may no longer set a guideline of what is good or bad in general terms anymore. Luis Cupido. ct1dmk. Gerhard Hoffmann wrote: Luis Cupido wrote: That is not by any means a CPLD. it is a big FPGA and I bet it would be doing a bazilon things besides the divider. It shares the CPLD's problems of ground and VCC bounce. The Virtex was completely empty otherwise and the counter was stoppable, so it was easy to see the culprit. Having a hundred ground pins should be more of an advantage and wether the innards are fine-grained (FPGA) or sum-of-products-cells (CPLD) really does not matter. 73s, Gerhard, DK4XP ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] CPLDs for clock dividers
I understand your arguments... I just wonder why reality differs. I had a design (GPSDO) that I tested on a FPGA (Cyclone) and the same on MAXII and the difference was abyssal !!! Whatever... the MAXII family has a unbeatable jitter performance compared to discrete logic... That I can tell by direct observation. Other CPLD's I can't tell much only MAX3000 that was slightly worst and MAX7000 that was the same as TTL +/-. Know nothing about Xilinx or others... There are so many devices nowadays that I do accept that we may no longer set a guideline of what is good or bad in general terms anymore. Luis Cupido. ct1dmk. Gerhard Hoffmann wrote: Luis Cupido wrote: That is not by any means a CPLD. it is a big FPGA and I bet it would be doing a bazilon things besides the divider. It shares the CPLD's problems of ground and VCC bounce. The Virtex was completely empty otherwise and the counter was stoppable, so it was easy to see the culprit. Having a hundred ground pins should be more of an advantage and wether the innards are fine-grained (FPGA) or sum-of-products-cells (CPLD) really does not matter. 73s, Gerhard, DK4XP ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] CPLDs for clock dividers
I favoured descrete logic a lot to keep phase noise low until I tested the latest CPLD's I believe that despite the bad things one can identify as potential threats to phase noise not all those fears really materialize in many real devices, and second, the recent devices have very high speed of operation thus scaling down all those jitter effects we might be afraid of. Some of those devices operate at 300MHz without trouble (and have sub ns rise and fall times internally) and many times the limitation is the device package otherwise way above 300MHz would be possible (also if you are afraid of design issues you can even control the way fitting and interconnections are made inside the CPLD...if you want) The key is that on TTL you can't possibly do it too wrong and on a CPLD you may do from very good to very bad designs, all doing the same function !!! Also if you need a divider with a complexity that involves a few (5 or 6) TTL IC's... Just forget, you are orders of magnitude better with one of this new devices. This all with the assumption that we are comparing a bunch of discrete logic IC's with a modern CPLD doing the exact same function (designed properly) and "Nothing Else" inside. Luis Cupido ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] CPLDs for clock dividers
Gerhard, That is not by any means a CPLD. it is a big FPGA and I bet it would be doing a bazilon things besides the divider. Hummm... not really adds to the original question I'm afraid ;-) Luis Cupido, ct1dmk. Gerhard Hoffmann wrote: I have done that with a Virtex4-SX on a ML402 board for fun and because a customer insisted on it. It was a desaster on the spectrum analyzer. It will probably work if you resynchronize the CPLD output with a 74LVC1G74 to the original clock. regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] CPLDs for clock dividers
Hi Matt, If you are only doing the divider thing with them they are excellent. If you have a lot other things running inside you may increase your jitter... Have experience with Altera both maxII and max3xxx, MaxII being the best showing jitters near the picosecond (challenging any measurement setup you might think of). Way better than TTL. Luis Cupido. ct1dmk. Matt Ettus wrote: Does anyone have any experience using CPLDs for very low phase noise dividers? You can get an XC9536XL from Xilinx for around $1, and I thought it would make a good divide by 2 through 10 device. Matt ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] OT: Practical PLL low noise?
Frank, You might want to take a look in here also. Hardly gets any simpler than this ;-) http://w3ref.cfn.ist.utl.pt/cupido/reflock.html Luis Cupido ct1dmk. On 02/02/10 16:50, francesco messineo wrote: Hello all, sorry for the OT, but I know there're many real electronic artists here. As an amateur radio operator I often use transverters, some home made. They usually can be made sigthly better (RF and noise-wise) than japanese transceivers. However often the LO xtal oscillator drifts too much for comfortable digital and weak signal work. Now the big question: is there any PLL design that can lock 22 MHz and 42 MHz xtal oscillator to a 10 MHz reference (typically from a GPSDO) without adding significant noise to the oscillators? The LOs usually go to a single or doube balanced diode mixer like the famous minicircuit ones, and at that point the RF signal has been already amplified by 10 or 20 dB stage(s). Other options would be "ovenizing" the LOs or making a DDS sinth. Now, what would be more practical approach from the home construction point? Thanks Frank IZ8DWF ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Test Equipment
But only starts at 5GHz :-( :-( Luis Cupido ct1dmk John Miles wrote: You could also get really hardcore and build the VNA described in DUBUS 4/2009 by HB9TXV. Very nice piece of work, usable to 30 GHz. -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com]on Behalf Of Lux, Jim (337C) Sent: Thursday, January 21, 2010 3:44 PM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Test Equipment -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Gerhard Hoffmann Sent: Thursday, January 21, 2010 2:50 PM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Test Equipment Lux, Jim (337C) wrote: What frequency ranges? If you are interested in <60MHz, then something like the TenTec TAPR VNA ($600) connects to a PC or a mac. Works as a signal generator and as a 2 port VNA. Or this one: http://groups.yahoo.com/group/VNWA/ (DG8SAQ) Excellent to 500 MHz, quite usable to 1300 MHz. Does 6 or 12 term error correction, most of this VNA is software. I'm just using one to tune a 100 MHz oscillator with opened loop. :-) The only drawback is that one cannot measure compression because the absolute levels vary over f. But then it can embed / de-embed, virtual match, display the Q and equivalent circuit of a crystal from S11 measurement, L, C, time gating and and and. Outstanding.. that one is very competitive in price (using a ballpark $2/GBP conversion) to the TAPR one. I'm glad that more of these are becoming available (as assembled units, not as kits..) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Help identifying coax connector type
Hi Glen, Looks indeed like an SMP but I believe it is a siemens 1.0/2.3 used on the DIN41612 backplanes (note the retention spring in the back to allow them to lock inside the 41612/M connectors shell). Luis Cupido. ct1dmk. p.s. don't know if 1.0/2.3 connectors will mate with SMP or not. Glenn Little WB4UIV wrote: The larger push on connector is an SMP. This is used a lot in microwave for IF cables. This is a 75 Ohm connector. 73 Glenn WB4UIV At 03:38 AM 12/7/2009, you wrote: I have recently acquired a number of nice coax parts, but I'm not sure exactly what connector types they are. If anybody can help me identify them, I'd appreciate it! First, are these spiffy jacks. They look somewhat like SMB, but are too large as far as I know. Too small for BNC, and there's no bayonet. http://www.flickr.com/photos/24004...@n03/4165880386/ http://www.flickr.com/photos/24004...@n03/4165880282/ http://www.flickr.com/photos/24004...@n03/4165880166/ Next is this coax jumper cable. Unknown connectors on both ends: http://www.flickr.com/photos/24004...@n03/4165122135/ http://www.flickr.com/photos/24004...@n03/4165122541/ http://www.flickr.com/photos/24004...@n03/4165122411/ Last is another cable, with yet another unknown connector on it: http://www.flickr.com/photos/24004...@n03/4165881034/ Thanks! -Pete ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Help identifying coax connector type
Hi Robert, ... 43 or BT43 (BT=British Telecom) is a private reference only for British. hi ;-) It is 1.6/5.6 for the rest of us. (patent is siemens afaik) Luis Cupido. ct1dmk. Robert Atkinson wrote: Hi Peter, They are Type 43 or BT43 connectors. 75R used in telecomms digital equipment in Europe. Robert G8RPI. --- On Mon, 7/12/09, Peter Loron wrote: From: Peter Loron Subject: [time-nuts] Help identifying coax connector type To: "Discussion of precise time and frequency measurement" Date: Monday, 7 December, 2009, 8:38 I have recently acquired a number of nice coax parts, but I'm not sure exactly what connector types they are. If anybody can help me identify them, I'd appreciate it! First, are these spiffy jacks. They look somewhat like SMB, but are too large as far as I know. Too small for BNC, and there's no bayonet. http://www.flickr.com/photos/24004...@n03/4165880386/ http://www.flickr.com/photos/24004...@n03/4165880282/ http://www.flickr.com/photos/24004...@n03/4165880166/ Next is this coax jumper cable. Unknown connectors on both ends: http://www.flickr.com/photos/24004...@n03/4165122135/ http://www.flickr.com/photos/24004...@n03/4165122541/ http://www.flickr.com/photos/24004...@n03/4165122411/ Last is another cable, with yet another unknown connector on it: http://www.flickr.com/photos/24004...@n03/4165881034/ Thanks! -Pete ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Amatuer Radio Information
> Sorry for the extreme off-topic, but it's just to witness that VHF > isn't dead and many of us don't even have HF antennas and still enjoy > the activity in the VHF challenging bands all the year. Yeap , you're right... I'm only active from 1296MHz and above, and I could have activity (both building/setting-up and operating) orders of magnitude higher than I could possibly handle. My 2cents to help changing the general misconception that above HF there is very little do do... On the contrary... > many of us don't even have HF antennas Hummm... What is HF ??? ;-) :-) Luis Cupido ct1dmk. http://w3ref.cfn.ist.utl.pt/cupido/ . Op... this one was very off-topic, my apologies. Although I posted it at a very precise time ;-) francesco messineo wrote: On 11/25/09, Robert Darlington wrote: Out here I'm almost exclusively on HF bands using the modern digital communications modes like PSK31. The first license (Technician) will not get you on the HF bands unless you count 6 meter (50MHz) as HF. well, 6m isn't anything like HF (imho). In 10 years I haven't heard a soul on 6 so I don't really even bother with listening anymore. To get on HF, the General license will get you 95% of what Extra wow... I think I worked something like 90 dxcc countries with modest setup in less than three years (but that was in 2001-2003). For sure I worked all europe and all african active countries with 10W into a homemade vertical J-pole antenna back in the best years of the last solar cycle. Now with a medium-sized beam in the right months I can work from USA to Japan (with 100W only). I see from the cluster spots that USA and all american continent are also much more blessed with 6m propagation all the year with respect to europe in this very low cycle minimum. Sorry for the extreme off-topic, but it's just to witness that VHF isn't dead and many of us don't even have HF antennas and still enjoy the activity in the VHF challenging bands all the year. Amateur radio has so many different aspect that any technical person can find always new challenging aspects to explore. No band is dead if someone has the right interest in it! best 73 F ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] fast freq. synthesis schemes
Brian, Wow, a lot of nice reading I have here. Thanks. Luis Cupido. ct1dmk. brimda...@aol.com wrote: Luis wrote: I'm looking for the schemes used on the frequency synthesizers that change frequency in few microseconds time (or less) Does anyone know of some paper or tech notes from some instrument or modules that show block diagrams of such? I've never done much with fast PLL's, but here's some references for direct analog and direct digital synthesizers: --- One of the "classic" synthesizer books that covers direct synthesis techniques is available in a reasonably priced paperback reprint ( but the photos aren't as nice as I recall from the original hardcover ): Frequency Synthesizers: Theory and Design, Third Edition Vadim Manassewitsch Wiley-Interscience _http://www.amazon.com/Frequency-Synthesizers-Theory-Vadim-Manassewitsch/dp/ 0471772631/_ (http://www.amazon.com/Frequency-Synthesizers-Theory-Vadim-Manassewitsch/dp/0471772631/) --- My favorite DDS book reprints many of the classic DDS papers: Direct Digital Frequency Synthesizers V. Kroupa (ed) IEEE Press _http://www.amazon.com/Direct-Digital-Frequency-Synthesizers-Venceslav/dp/07 80334388_ (http://www.amazon.com/Direct-Digital-Frequency-Synthesizers-Venceslav/dp/0780334388) --- Another good reprint to have on hand, but not specific to your fast-switching question, is the following: Phase Noise in Signal Sources (Theory and Application) W. P. Robins Peter Peregrinus Ltd / IEE _http://www.amazon.com/Phase-Signal-Sources-Theory-Application/dp/086341026X /_ (http://www.amazon.com/Phase-Signal-Sources-Theory-Application/dp/086341026X/) --- This web page about the HP 51xx family includes some HP direct synthesis app notes and articles: _http://www.hpmemory.org/news/5100/hp5100_page_00.htm_ (http://www.hpmemory.org/news/5100/hp5100_page_00.htm) _http://www.hpmemory.org/an/pdf/an_96.pdf_ (http://www.hpmemory.org/an/pdf/an_96.pdf) --- Rick Karlquist's UFFC papers are a great read on direct synthesizer topology, albeit geared towards a specific application: _http://www.karlquist.com/FCS95.pdf_ (http://www.karlquist.com/FCS95.pdf) _http://www.karlquist.com/FCS96.pdf_ (http://www.karlquist.com/FCS96.pdf) --- For IEEE/UFFC members, the UFFC archive is a good resource for synthesizer design info: _http://www.ieee-uffc.org/main/publications/fcs/index.asp_ (http://www.ieee-uffc.org/main/publications/fcs/index.asp) --- The basic Comstron frequency plan is summarized in their 1988 patent: _http://www.google.com/patents?id=bgA7EBAJ&dq=4725786_ (http://www.google.com/patents?id=bgA7EBAJ&dq=4725786) The Comstrons make great lab synthesizers, and are often available cheap on e$ay but I'd advise keeping a spares unit on hand for troubleshooting and repair. --- have fun, Brian ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] fast freq. synthesis schemes
My fear is "in the loop bandwidth" is a lot of BW as I need a wide loop for it to be fast. Okay, it sounds a nice path to investigate. tks. lc Lux, Jim (337C) wrote: On 10/15/09 5:56 AM, "Luis Cupido" wrote: Hi Bert, Thanks for the input. briefly; -Phase noise is not too important -It is to make just a few (and cost is not a major issue) The suggestions using prescalers or any other high speed digital chips may bring simplicity while compared with the design using multiple loops and harmonic mixers and samplers that is something I had in mind when I place the question out. I was wondering if recent technology would make possible to have a simpler approach. I like your first suggestion but I fear the spurious... I have no clue how bad it will be, but I guess I can only be sure if I make a prototype of that. The second one I must check how small would be the step... 1 MHz would be enough for a start. The spurs might not be as bad as you think... The newer crop of DDS include some forms of error cancellation for close in spur reduction, so the "in the loop bandwidth" part is cleaner. Also, maybe you can use clever choice of DDS clock rate to make sure that you only need "nice" phase increments that evenly divide into the lookup table length. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] fast freq. synthesis schemes
Hi Bert, Thanks for the input. briefly; -Phase noise is not too important -It is to make just a few (and cost is not a major issue) The suggestions using prescalers or any other high speed digital chips may bring simplicity while compared with the design using multiple loops and harmonic mixers and samplers that is something I had in mind when I place the question out. I was wondering if recent technology would make possible to have a simpler approach. I like your first suggestion but I fear the spurious... I have no clue how bad it will be, but I guess I can only be sure if I make a prototype of that. The second one I must check how small would be the step... 1 MHz would be enough for a start. Thanks Luis Cupido. ewkeh...@aol.com wrote: Luis There is not really enough information to make a good recommendation. Is this a one off or is the plan to make multiple units, what are the phase noise requirements, what are the cost limitations? If cost is a major issue there are in my opinion only two options. In both cases a VCO has to be used presetting with a fast D/A. In the first case you pre scale by 16 and feed an AD 9910 DDS as a programmable divider using a 100 MHz output in to a Hittite HNC 439 phase comparator with all the shortcomings of a DDS multiplied by the total divider ratio. The second option is a Hittite HMC 700 fractional PLL and use 50 or 60 MHZ compare frequency. You have to pre scale by 2 . Having used the all the above components I can tell you the DDS works reliable at 1200 MHz in and the 700 works great at 9 GHz. I have not gone for switching speed but in my case emphasis is on phase noise and resolution. As a matter of fact a friend of mine and I are doing a low cost signal generator from 100KHz to 26 GHz in one Hz resolution using the Hittite 700 part. Phase noise goal at 8 GHz is -100 dbc, 10 KHz offset. We use surplus yigs. Bert Kehren WB5MZJ In a message dated 10/14/2009 3:25:33 P.M. Eastern Daylight Time, cup...@mail.ua.pt writes: Hi, I'm looking for the schemes used on the frequency synthesizers that change frequency in few microseconds time (or less) at microwaves lets say circa 12-18Ghz) Obviously with some resolution (let's say 100Khz step or in that order)(otherwise it would be a trivial exercise in the BW of the PLL loop filter) Does anyone know of some paper or tech notes from some instrument or modules that show block diagrams of such? I have many info on mw synthesizers but all fall into microwave radio style of things with much higher resolution (khz and less) and much longer switching times (millisencods or more). Info on fast stuff I can't really find. I'm thinking of experimenting on something along those lines so... all comments are welcome. Thanks. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] fast freq. synthesis schemes
>> I would use a DDS, but only for fine tuning >> in a summing loop. E.g., use a >> DAC to pretune the varactor or YTO to >> within 50 or so MHz, feed the sampler >> LO port with a clean 100 MHz crystal, >> then close the loop by comparing the >> sampler IF to the DDS-generated offset signal. > > This is a nice technique. The trick is in making sure you > lock to the right comb and the right side.. Jim, I had no problems doing that on my old design LO was a bit higher in frequency making it easier and yes the harmonic mixer was driven with 18-20dBm OK as it is not a power critical application. And on top of that the micro-controller driving that had a self calibration routine that scanned through stepping 50MHz and adjusting DAC for a zero PFD output then store on a table, that on normal use the uC interpolates within each 50MHz tabled point to get the right DAC value. (uC times are not to be considered here as all calculations are done much before during the so called setup time) So cleverness on board (i.e. microprocessor and soft) is not a problem for the application. My issue is RF and microwave simplicity ;-) tks for your good comments and articles. Luis Cupido. ct1dmk Lux, Jim (337C) wrote: -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of John Miles Sent: Wednesday, October 14, 2009 4:44 PM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] fast freq. synthesis schemes Pretuning is the right strategy, but for microsecond agility, YIGs may be the wrong choice due to their main-coil inductance. If I were building an agile 12-18 GHz synthesizer I'd try a heterodyne scheme with varactor-tuned oscillators and a fixed (or very coarsely tuned) YIG or DRO. Either way, you would probably use a sampler, such as the parts in the Aeroflex/Metelics catalog, to construct the outermost PLL. Suitable counter and PFD chips exist as well (Hittite etc.) but samplers are cheaper and easier to use if you don't mind designing the IF circuitry for them. Ooohh.. Sampling Phase Detectors or Harmonic Mixers.. The problem is that you have to hit them with a lot of power on the reference port (+20dBm wouldn't be unusual) Depending on your application, making that much LO power that is suitably quiet is a challenge. Presumably, though, you're not DC power limited, so that helps. Getting a PLL with simple single integer N is pretty easy with the Hittite parts, especially if you can tolerate N that is a multiple of 4 or 8. There's a paper out there by S.K.Smith, et al., that describes a breadboard PLL we did at 8GHz, where we drove the reference input with the output of a DDS mixed with a fixed signal. http://tmo.jpl.nasa.gov/progress_report/42-166/166A.pdf take a look at Figure 6 and 7 However, that won't change in less than a microsecond (the loop bandwidth is too narrow).. you could widen up the loop bandwidth, but the reference source would need to be quieter (not a challenge.. we didn't take any special efforts to make our DDS quiet, etc.) The earlier paper by Cook, et al., http://tmo.jpl.nasa.gov/progress_report/42-156/156C.pdf shows a more traditional SPD DRO PLL, and gives some performance analysis of the loop. Just as in the Smith paper, tuning speed wasn't a big deal for us, but the theory is there to generalize it. I would use a DDS, but only for fine tuning in a summing loop. E.g., use a DAC to pretune the varactor or YTO to within 50 or so MHz, feed the sampler LO port with a clean 100 MHz crystal, then close the loop by comparing the sampler IF to the DDS-generated offset signal. This is a nice technique. The trick is in making sure you lock to the right comb and the right side.. But the external DAC can help with that. That way the PN is dominated by the lower N factor assocaited with the 100 MHz comb, and the resolution is determined by the DDS. Yes. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] fast freq. synthesis schemes
Thank you all by your replies. There are very good suggestions to investigate. The solutions that a DDS is a reference of large loop BW PLL may have indeed spurious issues and is not so attractive. The use of a DAC for coarse tune to get it near lock is to be considered yes... I'll detail a bit using to John's email (makes it easier to address issues one by one) > Pretuning is the right strategy, but for microsecond agility, Yes, I have always considered a DAC (as in my previous design) > YIGs may be the wrong choice due to their main-coil inductance. No YIGs. It is Hyperabrupt Varactor Tunned Oscillator known as HTO's and yes it is full 12-18 and another model for 8-12GHz > If I were building an agile 12-18 GHz synthesizer I'd try a heterodyne > scheme with varactor-tuned oscillators and a fixed > (or very coarsely tuned) YIG or DRO. ... > I would use a DDS, but only for fine tuning in a summing loop. > E.g., use a > DAC to pretune the varactor or YTO to within 50 or so MHz, > feed the sampler > LO port with a clean 100 MHz crystal, then close the loop by > comparing the > sampler IF to the DDS-generated offset signal. ... John, you described very closely the design I've implemented quite sucessfully a few years back with just two minor differences, I use the DDS as a reference (not in a adding loop) and the coarse tunned LO is another simple VCO and PLL in the 1-2GHz range with big steps (IF is about 250MHz and 100KHz step for a fixed 10MHz ref. and less than 1Hz resolution if the 10MHz ref came from a 100MHz DDS). Works absolutely great but per design all was in the ms switching time region, serial dac 2x serial PLL chips all in the same 3 wire bus and the 100KHz fcomp etc. Not easy to get any faster with simple changes. Rescaling/redesigning the same concept into the microsecond range is a lot of effort and I was thinking if a redesign (including the lessons learned) would be the way to go or there was some other clever schemes for the fast switching synthesizers. I would hate myself if I start this design while missing a much simpler approach. That is the nearly the full story. A lot more comments can come and I will be happy an thankful. Thanks. Luis Cupido. ct1dmk. Hi John. John Miles wrote: Pretuning is the right strategy, but for microsecond agility, YIGs may be the wrong choice due to their main-coil inductance. If I were building an agile 12-18 GHz synthesizer I'd try a heterodyne scheme with varactor-tuned oscillators and a fixed (or very coarsely tuned) YIG or DRO. Either way, you would probably use a sampler, such as the parts in the Aeroflex/Metelics catalog, to construct the outermost PLL. Suitable counter and PFD chips exist as well (Hittite etc.) but samplers are cheaper and easier to use if you don't mind designing the IF circuitry for them. I would use a DDS, but only for fine tuning in a summing loop. E.g., use a DAC to pretune the varactor or YTO to within 50 or so MHz, feed the sampler LO port with a clean 100 MHz crystal, then close the loop by comparing the sampler IF to the DDS-generated offset signal. That way the PN is dominated by the lower N factor assocaited with the 100 MHz comb, and the resolution is determined by the DDS. -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com]on Behalf Of Magnus Danielson Sent: Wednesday, October 14, 2009 1:48 PM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] fast freq. synthesis schemes Bob Camp wrote: Hi At least on paper you can run a DDS at VHF/UHF and put it into a (very) wideband PLL driving a 12-18 GHz VCO. As mentioned previously - spurs will be an issue. You also will need to get a hold of some DDS chips with GHz-ish clock rates. One could use a suitably high frequency VCO or even YIG, locked to a DDS and then use a suitable fixed oscillator for up-conversion. The PLL locking would also use a DAC for VCO "bias" being updated at the same time as the DDS. A look-up-table could be used for top DDS frequency to bias conversion and a calibration round could be used to trim the table up to minimize the bias-error. That way the VCO can be quick-jumped and the PLL will immediatly steer the frequency back into lock. The PLL loop thus only needs to handle error in bias-table, the remaining difference in frequency and phase-relationship. Quite a different task than the overall lock-range. An ADC for the non-biased value of the loop-filtered detector would enable calibrations to be made automatic. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscr
[time-nuts] fast freq. synthesis schemes
Hi, I'm looking for the schemes used on the frequency synthesizers that change frequency in few microseconds time (or less) at microwaves lets say circa 12-18Ghz) Obviously with some resolution (let's say 100Khz step or in that order)(otherwise it would be a trivial exercise in the BW of the PLL loop filter) Does anyone know of some paper or tech notes from some instrument or modules that show block diagrams of such? I have many info on mw synthesizers but all fall into microwave radio style of things with much higher resolution (khz and less) and much longer switching times (millisencods or more). Info on fast stuff I can't really find. I'm thinking of experimenting on something along those lines so... all comments are welcome. Thanks. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Newbie looking for GPSDO kit or Project sites
Hi, Depending how deep you want, to go you must note that this one from ve2zaz (btw which is a great design given it's simplicity) is a FLL not a PLL. (unlike most of the others that really lock the phase of the signal to the 10KHz or 1pps). Luis Cupido. ct1dmk. Roberto Barrios wrote: If you want to get your hands dirty, I'd suggest you to try VE2ZAZ's design. I've built a few GPSDOs and this one is the one I liked most. http://ve2zaz.net/GPS_Std/GPS_Std.htm Roberto Date: Tue, 13 Oct 2009 13:30:10 +0100 From: "David C. Partridge" Subject: Re: [time-nuts] Newbie looking for GPSDO kit or Project sites To: "'Discussion of precise time and frequency measurement'" Message-ID: <7f8db3beeb144011940a58bdf82f3...@apollo> Content-Type: text/plain; charset="us-ascii" Do you actually want to build your own from scratch, or just buy something like a Trimble Thunderbolt and add a PSU and housing? If the latter then look for seller fluke.l (that's a lower case letter "L") on eBay if you should want one right now, or if you aren't in a hurry wait for the next "group buy" of these here. If the former, how sophisticated do you want to get? These beesties can go from real simple: <http://www.jrmiller.demon.co.uk/projects/ministd/frqstd0.htm> to really moderately complex such as: <http://www.rt66.com/~shera/index_fs.htm> I'm sure there have probably been more recent designs too that have gotten even smarter ... Dave -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Ray Hudson Sent: 13 October 2009 12:53 To: time-nuts@febo.com Subject: [time-nuts] Newbie looking for GPSDO kit or Project sites Hi there; being a new "Time nut" I'm looking for kit/project web sites & info on building a GPSDO PLL. Any info welcomed. Ta Ray. _ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL question
Hi Dick, 'cause it may not integrate long enough... 'cause it may have poor phase noise... ;-) (it is however a very good question though, as one must be really sure what it does and then be motivated to improve it...) Luis Cupido ct1dmk. Richard W. Solomon wrote: Dumb question time: If the NavSync has an on-board synthesizer locked to GPS, why do you need to lock that to another oscillator ?? 73, Dick, W1KSZ -Original Message- From: gonzo moto Sent: Aug 7, 2009 1:32 AM To: time-nuts@febo.com Subject: [time-nuts] PLL question Hi Guys, I'm in the process of building a GPSDO which started out life based on G3RUH's design, but suffered a bit of feature creep. The GPS I'm using is the NavSync CW12, so I'll run the Freq_Out at 10MHz. I'm wondering if I should run the PLL at 10MHz or if there is an advantage dividing the two signals down to (say)10KHz. Does the averaging at 10kHz (and introduced errors of the dividers) outweigh the 'no averaging' and no additional errors syncing at the fundamental freq? I can think of arguments each way, but lack the test equipment to prove either way. Suggestions would be appreciated. Regards, ian _ View photos of singles in your area Click Here http://a.ninemsn.com.au/b.aspx?URL=http%3A%2F%2Fdating%2Eninemsn%2Ecom%2Eau%2Fsearch%2Fsearch%2Easpx%3Fexec%3Dgo%26tp%3Dq%26gc%3D2%26tr%3D1%26lage%3D18%26uage%3D55%26cl%3D14%26sl%3D0%26dist%3D50%26po%3D1%26do%3D2%26trackingid%3D1046138%26r2s%3D1&_t=773166090&_r=Hotmail_Endtext&_m=EXT ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] GPSDO project - 66.667MHz from 10MHz
Nic, I think yes but I'm not sure, please check Darrel's VE1ALQ and NTMS(Kent Britain) for reflock I pcb's and/or kits (as I've not heard from them recently). I believe TAPR is no longer offering the reflock II kit :-( Luis Cupido ct1dmk. Nic McLean wrote: Hi Luis, Are kits available again for your design? 73's Nic VK2KXN / VK5ZAT Subject: Re: [time-nuts] GPSDO project - 66.667MHz from 10MHz Both for locking with a 10MHz or 1pps you have a single chip solution using one of my reflock designs. http://w3ref.cfn.ist.utl.pt/cupido/reflock.html For a 1pps lock of fractional 1/3 frequencies you have already a code. (check the list of files for reflock 1) For locking a 66.666(6) VCXO to 10MHz you can use the same reflock I design and the configuration is kind of trivial (but no one asked for it before) and I can make a file for you. Luis Cupido ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] GPSDO project - 66.667MHz from 10MHz
Both for locking with a 10MHz or 1pps you have a single chip solution using one of my reflock designs. http://w3ref.cfn.ist.utl.pt/cupido/reflock.html For a 1pps lock of fractional 1/3 frequencies you have already a code. (check the list of files for reflock 1) For locking a 66.666(6) VCXO to 10MHz you can use the same reflock I design and the configuration is kind of trivial (but no one asked for it before) and I can make a file for you. Luis Cupido ct1dmk. From: Bruce Griffiths To: Discussion of precise time and frequency measurement Sent: Sunday, 28 June, 2009 11:04:49 PM Subject: Re: [time-nuts] GPSDO project Hal Murray wrote: You want 66. MHz from 10 MHz. I can think of several approaches. 1) Patch the radio stuff to work with 10 MHz. Since 10 MHz is common from things like GPSDOs or Telco surplus rubidium clocks, somebody may have done that already. 2) Build a PLL. The first step is probably to find a 66.666 MHz oscillator that has an external fine tuning pin. Then it's divide by 20 and 3, compare, filter... 3) Get to 66.666 MHz by dividing by 3 then multiplying by 2 and 5. I don't know much about this area, but there was a lot of discussion here a few months ago. Check the archives. Actually need to multiply 3.333.. MHz by 20 (5 x 2 x 2) No need to multiply by 2 or 4, if the output of the divide by 3 is a 1/3 duty cycle square wave, one can extract the 2nd (or 4th) harmonic of the square wave repetition rate with a filter. Amplify and multiply by 5 (can use the same approach as used in the 5370A/B frequency multiplier chain (1 transistor per multiplier) and filter. A high level injection locked divider can have lower close in phase noise than a digital one. 4) Use a DDS chip to synthesize 66.666 MHz. Analog Devices makes lots of nice ones. One problem with DDSes is that they normally make spurs. But they aren't a problem if the target frequency is a clean multiple of the source frequency. 20/3 doesn't sound clean, but I'd have to do a lot of work to check the details. There may be a clean frequency that is close enough to 66.666 MHz and/or one that has spurs that are far enough out so you can filter them. 5) Use a low cost 66.666 MHz oscillator and live with the error. You may be able to correct any errors. The key step would be to feed the 66.666 MHz to a counter running off the T-Bolt clock so you know the real frequency of your 66.666 MHz osc. Suppose your 66.666 MHz is 73 ppm fast and you want to listen to 12.123 MHz. You would set the radio to listen to 73 PPM below 12.123 MHz. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] 5370B yet again
Hi, I do have a HP5335A and after the many comments about the 5370 I'm curious if there is something I'd be better off with the 5370 instead of my 5334 I've read the specs of both but... better ask the experts ;-) Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] OT: Verilog/VHDL discussion list created...
I believe it is to be ham or hobby oriented Am I right ? (If so some rewording of the list purpose might be adequate... thinking out loud...) Luis Cupido ct1dmk. Scott Newell wrote: > At 12:29 PM 4/14/2009 , John Miles wrote: >> ... for those who would like to participate in HDL discussions that aren't >> on-topic for existing lists: >> >> http://groups.yahoo.com/group/HDLTalk >> >> Any VHDL or Verilog HDL-related topics are welcome. > > How will this compare to comp.lang.verilog, comp.lang.vhdl, and > comp.arch.fpga? > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency Divider
Bruce, There is a trick... That JTAG interface made with a 74HC244 is powered from the target board, If the target board runs at 5v so it will work at 5v. No doubts here... But if the target runs at 3v3 the 74HC244 gets powered at 3v3 (and it works fine, no need for the target device to be tolerant to anything, it gets within whatever VDD it uses...) and the 74HC244 seems to be tolerant to whatever comes out of the PC LPT port, but has a few series resistors though. Amazingly it even works at 2v5 ! The byteblasterMV from Altera is just like that and it works great, and programs from the small CPLDs up to most of the FPGA's (except for some more recent ones that require someting else... but is not a voltage issue). I'm running one for ages now with zero issues in both 5v chips and 3v3 chips. I even made a byteblasterII (to use on the more recent FPGA's) with the same 74HC244 (adding a few bits to the original byteblasterMV for the additional features required) and it works just fine even with Cyclone devices. Luis Cupido. ct1dmk. Bruce Griffiths wrote: > Luis Cupido wrote: >> >>> The CPLDs are programmed via the JTAG port. >>> Suitable JTAG programming cables are readily availble. >>> >> Or you can build one to use the LPT port of your PC using just a 74HC244. >> >> >> Luis Cupido. >> ct1dmk. >> >> ___ >> time-nuts mailing list -- time-nuts@febo.com >> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> and follow the instructions there. >> >> > Luis > > Using a 74HC244 may be somewhat problematic with CPLDs that don't have > 5V tolerant inputs. > Even when using a device with 5V tolerant inputs a 74HCT244 may be more > suitable for translating LVCMOS logic level outputs from the CPLD. > > Bruce > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Frequency Divider
> The CPLDs are programmed via the JTAG port. > Suitable JTAG programming cables are readily availble. Or you can build one to use the LPT port of your PC using just a 74HC244. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Close-in phase noise (long reply)
Brian, Was there any particular reason to go from 5MHz to 20MHz in two steps ? couldn't be just one x4 stage followed by the filter (preferably xtal) ? Luis Cupido. ct1dmk. wa1...@att.net wrote: > John- > > The BPFs in the 5 to 20MHz chain are just 7-pole LC > filters with the goal of trying to keep any other > harmonics other than the desired at least -50dBc. > Xtal filters would be the better choice, no doubt. > > The -50dBc level is clearly not the best > that one could get, but was enough for an earlier > 240GHz project. I just used the same OCXOs and early > stages of multipliers to get the latest system running > on 630GHz. > > In the 241GHz system, I ended up building a direct > frequency synthesizer to get 110MHz from a 10MHz > drive signal. At the time, the Freq West PLL > blocks I used wanted a VHF signal to drive > the sampling detector to phase lock the L-band > cavity VCO. The original Freq West units used 5th OT > xtals for the commercial applications. > > By later experimentation, I found that > the same sampling detector would also work with a > much lower frequency reference and still lock the > loop. The risk however is that the PLL might lock > on the wrong harmonic of the reference (i.e.: value of N) > or can have higher reference spur levels since the > PLL was designed assuming a VHF reference and not an > HF reference frequency. But this is not a commercial > design project, and I can live with a difficult alignment > procedure or initial power-up PLL lock troubles. > > But all this aside, my efforts are currently aimed at > best close-in noise within the first 1KHz of BW around > the carrier. > > The PLL bricks all seem to have several kHz of loop BW, > so my close-in noise going from 20MHz to 1320MHz should > be only slightly worse than 20Log(n), with n=66 in my case. > But I'm not ruling out the chance of 1/f noise (or similar) > showing up from the sampling detector or some other yet-to-be > determined source. > > However my focus is currently on the 5MHz to 20MHz portion > of the LO chain and to be sure the gain stages are not > running near compression. I do still agree with your > earlier comment about getting the most from that portion > of the chain. > > -Brian, WA1ZMS > > -Original Message- > From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com]on > Behalf Of John Miles > Sent: Tuesday, December 16, 2008 7:53 PM > To: Discussion of precise time and frequency measurement > Subject: Re: [time-nuts] Close-in phase noise question...more info... > > >> More info on the LO chain: >> >> 1) 5MHz Wenzel OCXO <--Custom Osc for me. >> 2) MSA-1105 buffer MMIC and lumped LPF >> 3) 5MHz to 10MHz 1N5711 diode based doubler >> 4) MSA-1105 buffer and lumped LPF >> 5) 10MHz to 20MHz 1N5711 diode based doubler >> 6) 20MHz BPF > > What kind of BPF? A really narrow crystal filter would be nice here. (You > have basically reproduced the 8568A/B's 20 MHz reference section.) > >> 7) 20MHz drives sampling detector inside surplus Frequency >> West PLL block to lock 1320MHz cavity oscillator. > > Sounds OK as long as the sampler loop's noise floor doesn't limit you. I > haven't measured the in-band residual floor of any bricks but I'd be > surprised if an SRD multiplier wouldn't be quieter. > >> 8) 1320MHz drives Frequency West SRD multiplier to 6.6GHz. > > If I wanted to get to several GHz with what's in my junk box right now, I > would do what you did to get to 20 MHz, BPF it with a multipole crystal > filter, and then use a few more multiplier stages to get somewhere between > 100 MHz and 1 GHz, a la the 8662A reference section, depending on the choice > of the next stage. > > That VHF drive signal would go into either an HP 33002A or 33004A SRD > multiplier, or one of the Picosecond NLTL multipliers (e.g., > http://www.picosecond.com/product/product.asp?prod_id=109 ) I picked up in > their fire sale when they shut down their fab. > >> 9) 6.6GHz to 39.6GHz Milliwave diode multiplier/amp/filter >> 10) 39.6GHz to 79.2GHz in varactor doubler >> 11) 79.2GHz to 158.4GHz in varactor doubler >> 12) 158.4GHz into x4 sub-harmonic mixer > > AFAIK the rest of the chain is fine. I'd focus on getting rid of the brick > PLL, or at least taking pains to make sure that it's not the problem, before > worrying about the MMICs in your early stages. > > Remember that there's no point in optimizing the PN of any one stage much > below the input-referred residual noise of the following stage. MMICs, in > saturation or not, are pretty quiet. Quieter than sa
Re: [time-nuts] Close-in phase noise question...
Brian, I also think the linear operation would be better, but not so sure if bipolar transistors wouldn't be preferred over MMIC's for this (on bottom part of the spectrum) (ok... is not so handy). What I can certainly add to the discussion is that power amplification followed by higher rate varactor multiplication is considerably better than a multiple lower multiplication ratios chain. I had that experience on the 411GHz where from a 70MHz(*) xtal osc amplified to several Watt driving varactors and cavities. I jump with few steps to about 45GHz as opposed to a DB6NT like LO chain which was noticeably worst in the close in noise. Using mixers without driving hard the LO or the RF with same marginal level on both ports is possible but you will be in trouble with level settings :-( Not sure how much you would gain there... theoretically something... but then AM to PM conversion is against you so not sure if better or worst. Luis Cupido ct1dmk. (*) x12 x9 x3 x2 w/ 9th harm corner cube harm mixer if my memory serves me well wa1...@att.net wrote: > Bruce- > > OK... So, linear operation does therefore seem to be the preferred > way to operate these MMICs rather than operation into compression. > That's what I seem to be observing if only because my final RF > frequency is so high and RX bandwidth so low. > > Having said that, if my frequency synthesis scheme involves a mixer > does the same effect of low frequency noise to phase noise conversion still > take place? After all, the mixer element is typically into compression > if it's a FET based mixer. I assume a diode mixer is more immune to > similar effects? > > I'm trying to grow my intuitive understanding of the subtle sources of > noise. But I don't recall Maas giving much info on this topic in > his otherwise excellent text. > > As always, thanks for your sagely advice. > > -Brian > > > -Original Message- > From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com]on > Behalf Of Bruce Griffiths > Sent: Monday, December 15, 2008 5:00 PM > To: Discussion of precise time and frequency measurement > Subject: Re: [time-nuts] Close-in phase noise question... > > > wa1...@att.net wrote: >> Looking for comment here... >> >> The background: >> I'm working on a sub mm-wave LO chain for >> a ham radio application. While chasing issues >> of close-in phase (ie: within 1KHz of RF >> carrier) by peeling the "layers of the onion", >> I'm starting to question the performance of >> the MMICs that are used as buffers and amps >> following my Wenzel reference OCXOs. >> >> Question(s): >> Should any MMIC be allowed to be driven >> close to compression or into compression >> when striving for best close-in noise? >> >> I know and have seen the NF of a MMIC >> degrade while in compression, but my >> target right now is close-in noise rather >> than broadband noise. >> >> My design, in summary, takes 5MHz up to 630GHz >> via several multipliers and PLL stages. >> >> -Brian >> > Brian > > The increased nonlinearity when driven into compression will enhance the > conversion of low frequency noise to phase noise. > > Bruce > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Designing and building an OCXO and GPSDO
Bruce, John, Tks for all your comments about that topic. really interesting. Luis Cupido. ct1dmk. Bruce Griffiths wrote: > Luis Cupido wrote: >> Bruce, >> John, >> ... >> >> And at smaller offsets like 100Hz and less ? >> Shouldn't the improvement be even bigger ? >> Closer to the carrier we are dealing with bigger signals >> so the ADC issues like resolution should be less important, >> and the limiting factor should really be the the >> phase noise of the LO's and etc. >> Am I right ? >> >> >> Luis Cupido. >> ct1dmk. >> >> >> >> > Luis > > The R&S FMU 36 is a baseband analyser employing a pair of 80MSPS ADCs so > only the preamp, ADC, and 80MHz oscillator phase noise should be > significant (assuming the calculation roundoff noise isnt a factor). > > Bruce > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Designing and building an OCXO and GPSDO
Bruce, John, ... And at smaller offsets like 100Hz and less ? Shouldn't the improvement be even bigger ? Closer to the carrier we are dealing with bigger signals so the ADC issues like resolution should be less important, and the limiting factor should really be the the phase noise of the LO's and etc. Am I right ? Luis Cupido. ct1dmk. Bruce Griffiths wrote: > Luis > > The R+S FMU36 has a phase noise floor of around -143dBc/Hz (offset > > 10kHz) with a 10MHz input. > Whereas the R+S FSU67 has a phase noise floor of around -133dBcdBc/Hz > (offset = 10kHz) with a 640Mhz input. > > There is a definite improvement at lower frequencies but not quite as > much as one might have expected. > > Bruce > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Designing and building an OCXO and GPSDO
Bruce, tks for your reply. > The latest spectrum analyser offerings from Agilent have similar phase > noise floors for both the millimeter wave and low frequency spectrum > analysers. Yes, but kind of puzzles me a bit since I would be expecting phase noises more than 10x worst on a SA covering DC to 1GHz (+/-) (since the LO for this is an YIG oscillator circa 3GHz locked to a reference) comparing with an FFT analyzer that uses a few tens MHz sample rate. Assuming similar 10MHz reference oscillator the SA gets it multiplied by 300 while a low freq SA (preferably FFT) gets it multiplied by 10 maximum. How can they claim similar performance ?! --- Ok on the rest, tks. Luis Cupido. Bruce Griffiths wrote: > Luis > > The latest spectrum analyser offerings from Agilent have similar phase > noise floors for both the millimeter wave and low frequency spectrum > analysers. > However the low frequency analysers have a lower "flicker" noise corner. > > The noise floor of a good double balanced mixer is still 30-40dB lower > than that a spectrum analyser. > > Thus you are stuck with using a low bandwidth phase lock loop to get > down to the mixer noise floor. > > Alternatively a dual (first conversion uses analog mixers, 2nd > conversion uses DSP techniques) conversion Costas receiver using 4 > mixers and 4 ADCs should go down to -170dBc @ offsets of 100Hz or so > when correlation techniques are employed. Its a pity the TSC5120A doesnt > allow independent access to all 4 of its ADC inputs so a quad of > external mixers can be employed to extend the technique to the > millimeter wave region. > > All you need is 4 high resolution ADCs and an offset generator or 2. > A couple of high end sound cards may be suitable at least for testing > the concepts. > > Bruce > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Designing and building an OCXO and GPSDO
Related to this, I have a question in my mind for sometime. How close to a decent phase-noise setup are we if we down convert and use a low frequency spectrum analyzer ? (downconverting with the best XTAL LO we can imagine). My target is microwaves and millimeter waves so I have to down convert anyway, Or then I have to live with what my spectrum analyzer show me (a tek 492, in my case). --- Rephrasing the question, how much better are the low frequency spectrum analyzers comparing to the microwave spectrum analysers (in phase noise I mean)? Any comments ? Luis Cupido. ct1dmk. P.S.(I know that I'm limites to 100Hz RBW with my 492... and I would like also to measure closer than that ) John Miles wrote: > If you don't want pushbutton convenience, you can measure the close-in phase > noise with not much more than a $5 mixer and $2 opamp. It will take a lot > of "sweat equity," and you will need to build two of whatever you're > measuring, or buy/borrow a known-cleaner source at the same frequency. > > TSC analyzers are great but they are not the only way to go. Actually their > biggest advantages lie in their size/weight and the fact that the reference > doesn't have to be at the same frequency as the DUT. Other than that, their > performance is not necessarily better than a homebrew single-mixer > quadrature PLL or an 11848A. > > -- john, KE5FX > > >> -Original Message- >> From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] >> Behalf Of [EMAIL PROTECTED] >> Sent: Wednesday, August 13, 2008 4:40 PM >> To: time-nuts@febo.com >> Subject: Re: [time-nuts] Designing and building an OCXO and GPSDO >> >> >> Yup, I agree. >> >> I wish I did have one of those TSC5120A's! >> >> Or "at least" an E5052A/B. >> >> bye, >> Said >> ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] I want a good micro-controller
Another view ! I found myself going in another direction recently... PC104 :-) ... Designing a board for a really small think, one's favorite either PIC 51's ATmel freescale or whatever seems to be fine. A small demo board or existing PCB from some vendors seems fine to me also. but when it comes to a medium to high power thing lets say in the ARM category and above, it becomes a lot easier to use a PC104 board. Specially because those pop-up on ebay at less than most of the kits and demo boards for uC that have 1/100 of the processing power. Not to mention the tools available that are the same as any for the PC architecture... Compilers assemblers etc... sky is the limit. ROM can be a compactFlash-ide disk, a few bucks you get 1Gb if you want, plus Ethernet, LCD/VGA USB LPT, 2xRS232 etc (depending on the specific model). For more complex things it just doesn't pay to make a specific PCB (unless for big qty business production)... Last year I got on ebay a few 233MHz Pentium PC104 with eth10/100 + 2xRS232 + lpt + 2xusb + Kb for 30euro each!!! What else could we do with that money ?! ;-) Ok fine they eat [EMAIL PROTECTED] not exactely low power... but there are better ones... my 2 cents ;-) Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] I want a good micro-controller
>There are any number of >choices, including the PIC line, which everyone but me seems to love. Bill, You're not alone ;-) Luis Cupido. ct1dmk. wje wrote: >My favorite for many uses is the Freescale MC68HC908QT4, or others in >that series. Freescale provides a complete C development environment >for free. The QT4 is an 8-pin package, with up to 6 I/O pins. I've used >it for everything from a 555 timer replacement to the controller for an >RPM meter, to the controller for a GPS/Rb/xtal freqency standard. Of >course, for many purposes it doesn't particularly matter whose chip you >use, as long as the tools are adequate. There are any number of >choices, including the PIC line, which everyone but me seems to love. > Bill Ezell > -- > They said 'Windows or better' > so I used Linux. > >John Miles wrote: > > It's sort of a religious matter, but if you are looking for an easy-to-use > part with great, free C/C++ support, you'd most likely be happy with the > AtMEGA series. > > -- john, KE5FX > > > > -Original Message- > From: [EMAIL PROTECTED] [[2]mailto:[EMAIL PROTECTED] > Behalf Of Jim Palfreyman > Sent: Tuesday, August 12, 2008 11:06 PM > To: Discussion of precise time and frequency measurement > Subject: Re: [time-nuts] I want a good micro-controller > > > Bruce, > > Yes that's exactly my plan. No GPS and designed for field use. A halfway > decent crystal with interpolation from 1 PPS timestamps should provide > decent results. And anything else I can dream up. > > Bottom line is I need to know which micro-controller to embrace. > > Thanks Didier for your suggestion. Any others? > > Jim > > > > > ___ > time-nuts mailing list -- [EMAIL PROTECTED] > To unsubscribe, go to > [4]https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > > References > >1. mailto:[EMAIL PROTECTED] >2. mailto:[EMAIL PROTECTED] >3. mailto:time-nuts@febo.com >4. https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?
I do agree with Richard, comparators are quite bad... Having played with interfacing signals to FPGA 'ad nausea' I found that the only simple scheme that works better than biased (or feedback) cmos gates and of course much better than ECL line receivers or comparators (even cmos gates biased sometimes exhibit some strange issues specially when no signal is present)... As I was saying the best I could find was a differential pair of fets set to not too high gain. Signal is not step-square to the ps but the outcome on jitter viewed from inside the FPGA is the best of all many combinations I've tried, imediately followed by a differential pair of microwave bipolar transistors which preform excellent also... (note gains about 5 only, resistors set to naturally clip the signal to 0 - 2.5V (FPGA friendly) by the nature of the differential pair behaviour). (PFET or PNP) All the rest is crap compared to this... At least in my experiments. discrete but simple... sometimes super-duper ic's are not the best option. Luis Cupido. ct1dmk. p.s. my interest was wide band so filtering amplifying and clipping (by far the best solution) was not an option for me. Rick Karlquist wrote: > Comparators have very wideband, high gain inputs with typically > high noise figures. The effective input noise is determined by > the noise figure and the comparator bandwidth and the fact > the the comparator only utilizes a few mV of the input signal. If you are > trying to square up a 10 MHz signal, and noise from DC-1000 MHz > is affecting the comparator switching time, you have unnecessarily > added a bunch of noise above 10 MHz. You can't filter this noise > back out after the comparator output. That's the theory of it. > > 1/f noise is not the issue. CMOS gates have lower input noise > IN RELATION TO THE SIGNAL LEVEL involved. Comparators only use > a few mV of your signal. That's why the high gain is bad. > > The ideal circuit is a bandpass linear amplifier that makes a > large filtered 10 MHz sine wave, which is then passively clipped with > diodes at the logic levels you need. This is based on the paradigm > described by John Dick (of JPL) in his 1990 PTTI paper on zero > crossing detectors (someone posted that paper I think; anyone know > the URL?). It is clear IMHO that a comparator is just about exactly > the opposite of what Dr. Dick prescribed. > > In any event, if you actually test real comparators, you will > find them to be universally lousy. I will be happy to be proven > wrong if someone is aware of a good comparator. It's just that > I have never met I comparator I liked :-) > > Rick Karlquist N6RK > > > Didier Juges wrote: >> Rick, >> >> Can you explain #2? >> >> I understand ECL has more jitter, so I understand excluding ECL based >> comparators, but why excluding ALL comparators? It seems to me the >> comparators allow tighter control of the threshold, so it sounds as if it >> would help at very low frequencies, unless the higher 1/f noise of the >> compartor dominates other factors. >> >> How does the 1/f noise of a CMOS gate compare to an analog comparator? >> >> Didier KO4BB >> >>> -Original Message- >>> From: [EMAIL PROTECTED] >>> [mailto:[EMAIL PROTECTED] On Behalf Of Rick Karlquist >>> Sent: Thursday, July 31, 2008 3:14 PM >>> To: Discussion of precise time and frequency measurement >>> Subject: Re: [time-nuts] What is a Time-Nut grade Zero >>> Crossing Circuit? >>> >>> Two things NOT to do: >>> >>> 1. Do NOT use ECL. CMOS is much lower jitter. >>> >>> 2. Do NOT use a comparator to square up the sine wave. >>> Especially don't use a ultrafast ECL based comparator. >>> >> > > > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Home built Ammonia cell std !! / Home built cesium clocks???
We dont get much info/comments about this But what would an ammonia cell standard be able to do. I mean frequency/time wise. Maybe easier and simpler ? comments ? Luis Cupido. ct1dmk. (I understand the frequencies are much higher but that is not a problem, at least for me). ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Fast frequency counting question
Hi Bruce, I don't know what you mean by low resolution but I can easily think of more than 12 bit at higher than 150Ms/s. > will tend to limit the effective resolution in determining the zero > crossing locations. by no means zero crossing is to be used. we do have much more information than that... phase info is all over in all sampled points not just on zero crossings. This is why I've said some transform to produce a spectrogram. Maybe this is the reason why you mention the need of so many integrations and the "unpractical" comment, as you are thinking of using only a tiny fraction of the information available. ... interesting topic :-) Luis Cupido. p.s. however even tens of thousands of measurements of 1ms windows is a few minutes !!! Bruce Griffiths wrote: > Probably impractical as the sampling noise is so high that it will > require tens of thousands of measurements to get the noise down to the > required level and meanwhile the temperature etc will have changed > significantly. Also the relatively low ADC resolution and nonlinearities > will tend to limit the effective resolution in determining the zero > crossing locations. > > Bruce > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Fast frequency counting question
Right... Not necessarily an FFT, other transforms are quite well suited to this. FFT was just my quick way to let the idea out ;-). lc. Magnus Danielson wrote: > From: Luis Cupido <[EMAIL PROTECTED]> > Subject: Re: [time-nuts] Fast frequency counting question > Date: Mon, 05 May 2008 00:08:07 +0100 > Message-ID: <[EMAIL PROTECTED]> > >> Couldn't it be: >> digitizing, process the data with a sliding FFT >> (making a spectrogram) plus deconvolve >> with the system line broadening response, >> and if all chirps are equal then repeating >> the above N times for resolution increase. > > Not quite so easy. First of all, this type of transient response signal is not > well suited for FFT. Then, I am not sure the repeatability of the signal is > valid to such a degree that an accurate curve is achieved. I think the basic > approach is fairly right, but that they are stretching the limits somewhat of > that particular counter for this specific measurement. > > Cheers, > Magnus > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Fast frequency counting question
Couldn't it be: digitizing, process the data with a sliding FFT (making a spectrogram) plus deconvolve with the system line broadening response, and if all chirps are equal then repeating the above N times for resolution increase. Luis Cupido ct1dmk. Pete wrote: > Murray, > > I may be out in left field (again), but isn't this > a textbook measurement for a fast sampling > 'scope? I think most of the recent devices in > this category have 500MHz to 10+GHz > sampling rate, with plenty of memory depth. > They can output a time record via GPIB, > USB or whatever. > > The time record can be post-processed to > yield actual zero crossings. You also get all > the amplitude data, which should help with > analysis. > > Some of the newer 'scopes have the post- > processing software built in & there is at > least one source of PC based timing > analysis available. > > Pete Rawson > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] simple GPS nmea display.
Tested, It works great. tks. lc ct1dmk. [EMAIL PROTECTED] wrote: > Was it VisualGPS?? > > www.visualgps.net > > 73, > Mike, N1JEZ > "A closed mouth gathers no feet" > > ----- Original Message - > From: "Luis Cupido" <[EMAIL PROTECTED]> > To: "Discussion of precise time and frequency measurement" > > Sent: Saturday, March 01, 2008 8:21 AM > Subject: [time-nuts] simple GPS nmea display. > > >> Hi, >> >> Long time ago I had a simple software (win 95/98) >> that displayed GPS sats position ax/el and strength >> etc from the nmea info. >> I can't find it or remember its name and nowadays >> searching google with anything containing GPS gets >> tones of stuff... garbage in this perspective... >> >> Can anyone point me to any simple program, must run >> on older machines (windows 98) be and free. >> I mean very basic stuff for sanity checks of system >> antena etc. >> >> Thanks. >> >> Luis Cupido. >> ct1dmk. >> >> >> ___ >> time-nuts mailing list -- time-nuts@febo.com >> To unsubscribe, go to >> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> and follow the instructions there. >> > > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] simple GPS nmea display.
Tks, Mike, It was something very similar Will try that one tks. Luis Cupido. ct1dmk. [EMAIL PROTECTED] wrote: > Was it VisualGPS?? > > www.visualgps.net > > 73, > Mike, N1JEZ > "A closed mouth gathers no feet" > > ----- Original Message - > From: "Luis Cupido" <[EMAIL PROTECTED]> > To: "Discussion of precise time and frequency measurement" > > Sent: Saturday, March 01, 2008 8:21 AM > Subject: [time-nuts] simple GPS nmea display. > > >> Hi, >> >> Long time ago I had a simple software (win 95/98) >> that displayed GPS sats position ax/el and strength >> etc from the nmea info. >> I can't find it or remember its name and nowadays >> searching google with anything containing GPS gets >> tones of stuff... garbage in this perspective... >> >> Can anyone point me to any simple program, must run >> on older machines (windows 98) be and free. >> I mean very basic stuff for sanity checks of system >> antena etc. >> >> Thanks. >> >> Luis Cupido. >> ct1dmk. >> >> >> ___ >> time-nuts mailing list -- time-nuts@febo.com >> To unsubscribe, go to >> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> and follow the instructions there. >> > > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Simple NMEA Display
Hi Tom, That I know ;-) I meant something more visual :-) Tks anyway. Luis Cupido. ct1dmk. Tom Clifton wrote: > From: Luis Cupido <[EMAIL PROTECTED]> > Can anyone point me to any simple program, must run > on older machines (windows 98) be and free. > I mean very basic stuff for sanity checks of system > antena etc. > -- > Very basic, Very Simple and very Free.. Use the > hyperterminal program that comes with windows 4800 > baud 8,N,1 and just look at the serial data > > http://www.gpsinformation.org/dale/nmea.htm > > for information on how to decode by "hand" > > > > > > Never miss a thing. Make Yahoo your home page. > http://www.yahoo.com/r/hs > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] simple GPS nmea display.
Hi, Long time ago I had a simple software (win 95/98) that displayed GPS sats position ax/el and strength etc from the nmea info. I can't find it or remember its name and nowadays searching google with anything containing GPS gets tones of stuff... garbage in this perspective... Can anyone point me to any simple program, must run on older machines (windows 98) be and free. I mean very basic stuff for sanity checks of system antena etc. Thanks. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PC-104 ISA by Luis Cupido
Tks Dean, Not yet ruled out a silly mistake (so thanks for the tips, double check it again)... but... as you saw on my previous post it looks like this is a peculiarity of this PC the south bridge or whatever as on others it seems to work fine. tks, for the book reference ;-) will look for it. lc. Dean Weiten wrote: > Luis, > > As have many others, I've stubbed my toes on ISA interfacing lots of > times. The best reference on the subject is "Interfacing to the IBM (r) > Personal Computer", by Lewis C. Egeebrecht, from Sams. It's old and may > be out of print, but it's an essential resource for anybody dealing with > 8 or 16-bit ISA. You will have to ignore the sections in PS/2 Micro > Channel architecture of course :-) There are a few typos (e.g chapter > 10 - description of SBHE - SBHE should be inverted, and /SBHE=0 A0=1 is > odd byte 8 bit transfer not "invalid") but it is an *excellent* reference. > > Back to your problem. 8 bit I/O should work if you are decoding the > lower 16 bits of address (NB **only** 16 bits) qualified by AEN low and > using /IOW & /IOR to strobe. One common error that I've made a few > times is to ignore the AEN, which typically works but messes up the DMA > so that floppy drive access fails. Be sure to leave I/O Channel Ready > alone unless you want to extend the I/O cycle time; and then only drive > it low when your device is accessed. > > To enable 16 bit I/O, you drive I/O CS 16 low when you have valid > address to your board (address & AEN, no need for strobe), then you must > do an 8 bit or a 16 bit cycle in accordance with A0 & /SBHE. This > because the X86 instruction set allows for 8 and 16 bit I/O, and you > don't know which one you will be seeing when you get selected. > > That should be all there is to it. All this with the caveat of course > that free advice is worth... well, you know :-) > > Regards, > > > Dean Weiten > dmw -at- weiten.com > > > > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PC104 isa
Hi Stanley, My simple test to see that something is wrong was: - Just 8 bits bus, and simple port 0x330 decoding. - MSDOS and debug.exe - doesn't work. test 2 - nothing connected and data-line is pulled down with a resistor - verified to be down during read (w/ ocilloscope) - inport returns 0xff on all ports except the ones on board. :-( test 3 since ISA is connected to a bridge, and MSDOS does nothing until you tell him to, ISA datalines have no activity at debug.exe prompt. - nothing connected and data-line is shorted to gnd - inport returns 0xff on all ports except the ones on board. :-( So it is not reading from isa !!! I'm interfacing an FPGA to it and got stuck with this issue. It works with a good old 486 though ;-) Thanks for help. Luis Cupido. ct1dmk. Stanley Reynolds wrote: > > - Original Message ---- > From: Luis Cupido <[EMAIL PROTECTED]> > To: time-nuts@febo.com > Sent: Tuesday, February 26, 2008 6:53:12 AM > Subject: [time-nuts] PC104 isa > > Hi, > > As there are experts here for sure I > risk this off topic question (it is not so > off topic in the application where it is used). > > I have a PC104 from kontron (mops_lcd) that > I can't read IO ports from the ISA bus, The write > to ports is ok but the read gets 0xff always. > (even with datalines forced '0' all the time) > Looks that IO input is comming from elsewhere > as onboard devices like LPT or COM work well > I suspect a bridge config or whatever... > Kontron support doesn't really help and I > wonder if anyone has stepped into this before... > > Thanks and sorry for off topic. > > Luis Cupido. > ct1dmk. > > Sorry no experence, but have you tried more than one I/O add-on board and > which ones ? How about a header Ribbon cable / cables? Do you have only two > boards ? Are you using a 8 bit XT or 16 bit AT board ? How is the I/O board > setup, interrupts,DMA, and memory - I/O address ? > > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > > > > > Looking for last minute shopping deals? > Find them fast with Yahoo! Search. > http://tools.search.yahoo.com/newsearch/category.php?category=shopping > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] PC104 isa
Hi, As there are experts here for sure I risk this off topic question (it is not so off topic in the application where it is used). I have a PC104 from kontron (mops_lcd) that I can't read IO ports from the ISA bus, The write to ports is ok but the read gets 0xff always. (even with datalines forced '0' all the time) Looks that IO input is comming from elsewhere as onboard devices like LPT or COM work well I suspect a bridge config or whatever... Kontron support doesn't really help and I wonder if anyone has stepped into this before... Thanks and sorry for off topic. Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] favorite microcontroller module?
Hi, 2 cents ;-) My stuff uses 51's or PC architectures and my tiny stuff uses PIC... So sticking to the subject under discussion I would say my favorite uCont. is a 51&derivate and for the small stuff small PICs I know that someone may reply that nowadays PIC are bigger and better, but I'm yet to find a guy who is equally happy in both PIC and 51's(AVR's ARM's etc)worlds saying that for complex jobs programed in C he likes better the PIC over the others. Three things I don't like to see: - Someone fitting a huge DSP and tcpip and etc into a small PIC (is it a challenge or idiocy ???) - Someone blinking a led with a ARM or a black-fin etc. (just avoiding to learn 2 pic instructions !!!) - Someone doing a tricky job using a micro-controller to do something that is a simple logic job, CPLD or whatever. Luis Cupido. ct1dmk P.S.Wishing to be professional hobbyist... but the boss don't let me :-( stuck to the first part (second part on weekends). ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] GPS Locked and Unlocked Performance Comparison
Hi, I got also a 10KHz version fit on a CPLD as per request of W7QX in early 2004 (for 100MHz etc) and later for N1JEZ and G6GXK (this time having also 10MHz). All is on my web pages since then but only if you look in detail in the configuration list files you find it... I must rearrange my web layout as some stuff is not so visible, sorry. on the other hand I suffer from extra queries about things I have there... ;-) Anyway, is is the the same old straightforward style of design (as the others) and has both XOR and FF outputs available. Unfortunately I do not have a Jupiter RX so I did not any real performance tests on it only some basic functional tests :-( ... I'm stuck to 1pps ;-) Luis Cupido. ct1dmk http://w3ref.cfn.ist.utl.pt/cupido/ Dave Brown wrote: > There's a published design very similar to James Millers from Andy > Talbot- > > http://www.frars.org.uk/cgi-bin/render.pl?pageid=1285 > > I think they were both published about the same time originally. > He uses a 4046 for the phase detector and suggests a decent OCXO but > otherwise very much the same. > > DaveB, NZ > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] is there a "best bet" advanced hobbyist buildable GPSDOdesign?
Ok. I understand now what you suggest. Thanks for the explanation. Luis Cupido. ct1dmk. Bruce Griffiths wrote: > Luis Cupido wrote: >> Bruce, >> >> > No analog filtering of the D flipflop output is required. >> >> Now you got me lost. >> >> We were talking about a GPSDO, that is locking >> an VCXO on the GPS time (1pps or else) >> So by the end of it you need an analog >> signal to control the voltage input of the VCXO. Right ? >> >> Where you get that from ? >> If not by filtering your flip-flop output >> what else you have in between the 1pps and the VCXO ? >> CPU's DAC's >> > Some software, including a sigma delta DAC, the effect of which is no > different, in principle, than the filtering etc required by any of your > phase detector implementations. > The 1 bit phase error samples are processed in software (or hardware > depending on one's inclinations, expertise, etc) in a similar way that > samples from an N (>1) phase detector samples are, to produce a digital > output for a DAC which drives the OCXO EFC input. The only difference is > that a sigma delta DAC is used instead of a conventional DAC. > >> if so how does your complexity arguments still apply ? >> >> >> > The interpretation of "complexity " depends on ones background and > experience. > The originator of the thread indicated that they had some microprocessor > software experience. >> Luis Cupido >> > I was trying to tailor the design to the stated strengths of the > originator of the thread. > > If one is trying to "squeeze" the ultimate in performance when using a > GPS receiver to discipline an OCXO, then carrier phase measurements > potentially offer much higher performance than can be achieved by using > the PPS output of a typical GPS timing receiver. > However only a few commercially available GPS receivers are suitable for > this application. > The GPS receiver oscillators all have to be phase locked to the OCXO > being disciplined. > This approach has been used in at least one commercially available GPSDOCXO. > In principle a GPS receiver has all the required measurement hardware, > so all that is required are suitable algorithms implemented in either > software running on a DSP, microprocessor, etc, or implemented in > hardware (CPLD etc). > > Bruce > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] is there a "best bet" advanced hobbyist buildable GPSDOdesign?
Hi Michael, Yes that may be true (but I did not test any of that...) Well... with digital prog. logic devices that operate at similar speed than HC and AC should be true yes. On the fast CPLDs that run past 300MHz the jitter should have scale down proportionally (I imagine) but I have no clue if that is similar, better or still worst than HC or AC. Yeap... Nice thing to test Hummm... I'm still thinking how to test such... :-) Luis Cupido. ct1dmk. michael taylor wrote: > On Dec 12, 2007 7:33 AM, Luis Cupido <[EMAIL PROTECTED]> wrote: >> Very good, I do respect the usage of a bunch of CMOS/TTL chips if >> someone doesn't want to spend the >> effort of learning how to use a CPLD. When it comes to use CPUs for >> tasks better done by straight logic (and there are many examples >> out there) then I think it is not the right option. >> All understood so let's not discuss that any further. > > Bruce also alludes to the higher jitters of CPLD versus Advanced/High > Speed CMOS logic gates (AC or HC families). > > This has to do with the programmable nature of CPLD / FPGA ICs as I > understand it. > Ref: <http://www.febo.com/pipermail/time-nuts/2007-April/025299.html> > > -Michael > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] is there a "best bet" advanced hobbyist buildable GPSDOdesign?
Bruce, > I've used plenty of CPLDs but see no reason to use one when it isnt > necessary. The sentence in my perspective sounds a bit like this: I've used plenty of TTL and CMOS but see no reason to use them when I could fit them all on a CPLD. I do understand that some may not want to get into this kind of devices, however I see not much of a difference of learning you way with microcontrollers, CPLDs or with any digital IC's these days. CPLDs in general do bring simplicity but do require learning how to use them and for various reasons that may be undesirable and be confused with a complexity issue while it is just a learning issue. Very good, I do respect the usage of a bunch of CMOS/TTL chips if someone doesn't want to spend the effort of learning how to use a CPLD. When it comes to use CPUs for tasks better done by straight logic (and there are many examples out there) then I think it is not the right option. All understood so let's not discuss that any further. --- > No analog filtering of the D flipflop output is required. Now you got me lost. We were talking about a GPSDO, that is locking an VCXO on the GPS time (1pps or else) So by the end of it you need an analog signal to control the voltage input of the VCXO. Right ? Where you get that from ? If not by filtering your flip-flop output what else you have in between the 1pps and the VCXO ? CPU's DAC's if so how does your complexity arguments still apply ? Luis Cupido ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] is there a "best bet" advanced hobbyist buildable GPSDOdesign?
Hi Bruce, Fine, you don't like the words "far better performance"... okay ;-) you do recognize the small advantage in noise but gave no relevance to the other aspects namely the lock acquisition, the fact that I can monitor the jitter over time etc. (all of them were contained in my word "performance" not just the noise). you wrote, > By all means try them, Humm?! I did tried them, that's exactly what I said !!! Note that I do have the hardware on a CPLD so schemes can be done on type-compile-and-test basis without soldering wires hi ;-) > but why add the power consumption and complexity > of a CPLD if it offers little improvement in performance? G, using a CPLD does not add complexity, it is just one chip and it offers the commodity of being easily configured etc. Also the power consumption is surely not an issue, if you are not happy with the 50 to 100mA you may draw from 3.3v just use a low power CPLD (like tha maxIIZ) and get only 10 to 20mA. On the comments about the filter and bandwidth I do agree with you it would be good to have most of it digital (doesn't need to be necessarily on a CPU... inside the CPLD is the same) I do have versions with integration also in digital and I'm still in the process of improving it. I believe I may get rid off of some of the inconvenient analog filtering, in the next VHDL iterations hi ;-) One thing is puzzling me, if you suggest using a single D flip-flop and want it simple as you say I presume you have also to filter in analog ?! So you end up with a slightly worst phase comparator and the less convenient analog filter :-( Or do you need to add a microcontroller and a DAC ? If that is the case, there goes off your complexity issue much higher than a simple CPLD. Luis Cupido. ct1dmk ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] is there a "best bet" advanced hobbyist buildable GPSDOdesign?
Hi Bruce and Scott. >> What about sampling both the VXCO and 1PPS at a 200MHZ rate? >> That should determine the phase difference within no more than a 10ns >> inaccuracy. >> Simplicity is good but when using a CPLD or an FPGA no need to get simple if a better design still fits inside the chip ;-) Indeed those style of phase measuring schemes have far better performance than the simple flip flop or similar. I say this because I had all the logic on a CPLD to play with so I tried a large number of phase locking schemes and could compare them. First of all the lock capture range can become a bit independent of the integration time with a proportional phase lag counting method. Some counting methods will inherently search for lock when lock is lost. Some of those methods also have lock acquisition times orders of magnitude smaller. On the other hand on CPLD (or FPGA) complexity doesn't cost more as this stuff is ultra extra small considering the size of a today's CPLD (eg. maxII w/ 1570 macrocells). No matter what you do a medium CPLD will be only used 10 to 20% not more. What I use on the reflock II is a time lag counter from the 1pps to next clock, and this value drive a dac. Only a small integration time is done digitally and the large integration time if one requires that is done with a classical R and C without any active components right before the Vtune of the VCXO. Therefore not a big DAC resolution is required (I use 12-14bit) since the averaging is on the outside in an analog filter in which simple 64 seconds integration time will grant you 6 bit more resolution. It may look a strange combination of a modern devices and a old fashioned filter but it had by far outperformed all the designs I could test w/ microporcessors + dac (in which some noise did get through), or lack stability. Luis Cupido ct1dmk. http://w3ref.cfn.ist.utl.pt/cupido/ Bruce Griffiths wrote: > Scott > > Scott Burris wrote: >> OK, so for the DAC piece, why not just use an NXP LPC ARM chip for the >> microcontroller, and use a 32bit PCM output followed by a low pass filter as >> the VXCO EFC? The DAC just needs high resolution, not accuracy, right? >> > True, but a Sigma delta DAC has far superior performance to a PWM DAC or > a standard DAC especially when the long term stability is not critical > and a faast response isnt required. > NIST use sigma delta DACs in their precision AC waveform generator and > to calibrate their Johnson noise thermometer systems. >> Or would the switching noise from the processor modulate the control >> voltage? >> > Its best to have the processor drive an external current steering switch > (74HC4053) to switch a stable current into the summing junction of an > inverting opamp. > If you want I can send you a suitable circuit schematic. > With a suitable circuit one can just use a voltage reference and a > resistor to set the current, a spare analog switch can be used in > series with the feedback resistor to provide temperature compensation > (important for good short and medium term stability). HP/Agilent in > effect use a similar temperature compensated current steering technique > in their 34401A 6.5 digit DVM. > Ulrich has uses similar techniques albeit with the sigma delta DAC logic > implemented in a gate array to achieve high resolution and good short > term stability. > In this application the DAC need not respond as fast so it can be > implemented in software. >> I would hope the filter would clean any such noise, but I'll be the first to >> admit >> that the farther we get into the analog domain, the more I'm out of my >> comfort zone. >> >> I'm still trying to wrap my brain around the phase detection piece of this. >> I've studied the Shera controller with it's 24Mhz oscillator and divided >> down >> sample of the VXCO and I'm can't get past thinking that this ends up >> adding jitter. With more modern parts can't the phase be measured more >> directly? What about sampling both the VXCO and 1PPS at a 200MHZ rate? >> That should determine the phase difference within no more than a 10ns >> inaccuracy. >> >> > Eliminate such unnecessary cost and complexity with a single D flipflop > phase detector (D connected to 10MHz signal or a divided down > subharmonic thereof, CLK connected to PPS) the circuit will > automatically adapt to achieve a resolution determined by the PPS jitter > (picoseconds if you have a good enough PPS source, a few nanosec with a > sawtooth corrected PPS signal from an M12M timing receiver, a few tens > of nanosec with an uncorrected PPS signal from an M12M timing receiver). > Thus its resolution is far better than when using a 24MHz
Re: [time-nuts] is there a "best bet" advanced hobbyist buildable GPSDO design?
Scott, you have also: http://w3ref.cfn.ist.utl.pt/cupido/reflock.html lab grade consider using reflock II for kits I think TAPR still has those... Luis Cupido ct1dmk. Scott Burris wrote: > Hi, > > Like many, I've acquired a fair amount of surplus test equipment off of Ebay > which could use the services of good master frequency standard. So I'm > looking to discipline an HP 10811 VXCO to provide this. > > Any general consensus about the best design for a hobbyist to build? > I'm familiar with the Brooks Shera design, the G4JNT Jupiter-T design, > the TAC-2 circuit, and the VE2ZAZ design. I take it from discussions > I've seen in the archives of this list that the VE2ZAZ design makes a > number of simplification/performance tradeoffs. > > Is there a design I haven't listed which is "better" than the others? > I'm quite familiar with microcontrollers, FPGAs, spinning my own > PCBs, etc, so I'll roll my own if I have to, but I'd prefer to build > a variation on someone's tried and true design. > > I'm aware of products like the Fury, but I'd like something I could tinker > with, and the cost is hard to justify for a hobbyist. > > Scott > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
