[time-nuts] 1PPS questions

[VE7HR]

Are there any suggested method to reduce your 1 PPS signal to a safe level for 
your test equipment?
It seems like my HP Z8316A is outputting slightly more than 5V into 50 Ohms. 

Up till now I have been using a 10 MHz output from the Z3816A. But I understand 
1PPS is a better signal to put to Channel A. 

My HP 5372A seems to default to 2V Max level if you hit instrument default.  I 
am starting to like it so I don’t want to trash an input module.  

I think I might try a TICC in the near future but for now I will have to slum 
with the vintage HP iron. 

Thanks
Dave
VE7HR 

Sent from my iPhone
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[time-nuts] Time goodies at Stuff Day

[Walter Shawlee 2]

We weren't able to host our usual annual stuff day event in person this 
year,

so it has all moved on line instead. You can see the items here:
https://www.sphere.bc.ca/test/stuffday.html 



There is a special section just for *time fans* if you want to avoid 
everything else:

https://www.sphere.bc.ca/test/stuffday.html#timefans

Some interesting *Austron, KODE and Efratom* bits for you to look over. 
I will have more related
time and frequency items posted in the next week as well, so let me know 
any requests. We also have
plug ins for the Argo Systems rubidium stabilized frequency calibration 
system in the Tektronix section,

although the AS210 itself is now gone..

all the best,
and happy 4th of July this weekend! (and it's Canada Day here today on 
the 1st)


-walter

--
Walter Shawlee 2
Sphere Research Corp. 3394 Sunnyside Rd.
West Kelowna, BC, V1Z 2V4 CANADA
Phone: +1 (250-769-1834 -:- http://www.sphere.bc.ca
+We're all in one boat, no matter how it looks to you. (WS2)
+All you need is love. (John Lennon)
+But, that doesn't mean other things don't come in handy. (WS2)
+Nature is trying very hard to make us succeed, but nature does not depend on 
us.
We are not the only experiment. (R. Buckminster Fuller)

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Re: [time-nuts] 30 MHz freq adjust by Hz

[glenlist]

FB

I was thinking of FM on the (30 MHz) carrier. (which the FM- the 
deviation  will multiply) .


(A multiplication does not change the information rate  of course)

BUT  you are right ! that's not what will happen, there is no FM !  
there are (relatd) unmodulated discrete frequency components added in.


and the resultant peak phase will multiply.

as for spurs, 20 or 30 dB down at a < 5 Hz offset (or whatever the 
difference frequency is the difference) that will be quite reasonable 
for the application.



On 02/07/2020 09:59, Bob kb8tq wrote:

Hi

Um …. e …..

If the phase spur is at 1.5 Hz at 10 MHz, it still will be at 1.5 Hz 
at 1296. The multiplication process

does not change the offset frequency.

What you *do* get is a change in level. If the spur is 40 db down at 
10 MHz, then it goes up by 10 log (1296 / 10).

Net result is that your 40 db down spur is now at about 20 db down.

Bob


On Jul 1, 2020, at 7:54 PM, glenlist > wrote:


RRR

Stability over about a 2 minute period, preferably within a Hz at 
1296 MHz , IE about 1e-09 is all that is required. I'll make it and 
figure out what I missed :-). The unwanted sideband (and some of the 
original will of course leak through depending on the DBM balance) 
will generate spurs on the output. And the few Hz spurs will multiply 
up 100 times ot being 150Hz instead of 1.5Hz spurs at a gig . I 
also thought of downconverting (with any XO) by  aliasing and then 
using a 455kc or 10.7  or 4.5 5.5 MHz etc IF filter (and then 
chopping and aliasing back up) .  Hmm or a crystal. al la cheap 
crystal lattice filter single xtal.. But now its getting a bit more 
complex than a 74HC4316 pair  (as 2 x DBM)  and a microcontroller 
although HC4316s etc start to leak through a bit at 30 MHz. remember 
the SSB difficulty was as much as the (wideband) polyphase quadrature 
filter (the mass of R and C) performance, and design of the day 
limiting attainable long term carrier suppression.  in this case, it 
is just single freq quadrature at 30 Mhz I need to generate. We will 
see !


cheers


On 02/07/2020 09:40, Bob kb8tq wrote:

Hi

The same “small fraction of a degree” and “small fraction of a db” issues that 
plagued the analog SSB
generation process still get into this approach. For “good” ADEV you need spurs 
down below the
-130 dbc range (and likely much lower). This only gets you to 60 db or so ….

Bob


On Jul 1, 2020, at 5:38 PM, glen english LIST  wrote:

Hi Bob

I imagine in physics there are times when you want an oscillator to move a few 
Hz for offset, and the oscillator is fixed due to some physical / atomic 
property.

yes, the whole thing will be phase locked, so no issue with freq error. For a 
fixed frequency operation , +45 and -45 deg networks for the HF will be 
accurate enough.I'll actually look at generating it out of the micro that 
is already on the board (as it loads the PLL and also indicates to the user 
presence of 10 MHz and input level) . see what the jitter calculates to be.

Anyway, thats one way to do it I guess if you have a source that is not quite 
where you want it but otherwise good.

hi hi , an SSB generator ha ha who'd thought I would be back in analog SSB 
generators after my years in SDR...

g

On 2/07/2020 12:14 am, Bob kb8tq wrote:

Hi

There is a NIST paper (somewhere) that has an example of doing this. Like any 
image
reject mixer approach, it only does just so well. It’s no different than 
generating SSB
the same way. You get a spur that is 40 to 60 db down at the “image” frequency. 
You can
tweak this or that to get it to the 60 db point, how long it will stay there …. 
that depends … :)

Since you are summing a very low frequency signal with a very high frequency 
one, the
accuracy of the low frequency signal does not need to be very good. A 1% 
accurate
5 Hz will be off by 0.05 Hz. Your combo also will only be off by 0.05Hz. For a 
lot of
Ham sort of stuff, that’s plenty good enough.

Indeed, the noise of the 5Hz and the mixer setup does get into the act. That may
rule out a simple R/C oscillator as the source of the 5 Hz “tone”…..

Bob


On Jun 30, 2020, at 9:36 PM, glen english LIST  wrote:

Hello group

I have an idea that might work, and I wanted to discuss  with likeminded that 
might already have experience with the problem.

Shifting a fixed oscillator a few Hz using a image reject mixer.

background : From time to time I (and others) make lock boards for ham gear, 
pulling the internal VCXO (vary from 11 to 55 MHz ish - which are out by a few 
Hz ) in against a 10 MHz input. Frequency accuracy is required for narrow band 
modes, and low phase noise 10kHz-200kHz is required as not to desense your ham 
neighbours.

I use fast LVDS diff receivers to square stuff up and ADF4157 high res fract 
and about 10Hz BW. That's all fine.  That aside, there are a bunch of radio 
that have only XOs, no control facility. Varying the supply voltage as a means 

Re: [time-nuts] 30 MHz freq adjust by Hz

[glenlist]

RRR

Stability over about a 2 minute period, preferably within a Hz at 1296 
MHz , IE about 1e-09 is all that is required. I'll make it and figure 
out what I missed :-). The unwanted sideband (and some of the original 
will of course leak through depending on the DBM balance) will generate 
spurs on the output. And the few Hz spurs will multiply up 100 times ot 
being 150Hz instead of 1.5Hz spurs at a gig . I also thought of 
downconverting (with any XO) by  aliasing and then using a 455kc or 
10.7  or 4.5 5.5 MHz etc IF filter (and then chopping and aliasing back 
up) .  Hmm or a crystal. al la cheap crystal lattice filter single 
xtal.. But now its getting a bit more complex than a 74HC4316 pair  (as 
2 x DBM)  and a microcontroller although HC4316s etc start to leak 
through a bit at 30 MHz. remember the SSB difficulty was as much as the 
(wideband) polyphase quadrature filter (the mass of R and C) 
performance, and design of the day limiting attainable long term carrier 
suppression.  in this case, it is just single freq quadrature at 30 Mhz 
I need to generate. We will see !


cheers


On 02/07/2020 09:40, Bob kb8tq wrote:

Hi

The same “small fraction of a degree” and “small fraction of a db” issues that 
plagued the analog SSB
generation process still get into this approach. For “good” ADEV you need spurs 
down below the
-130 dbc range (and likely much lower). This only gets you to 60 db or so ….

Bob


On Jul 1, 2020, at 5:38 PM, glen english LIST  wrote:

Hi Bob

I imagine in physics there are times when you want an oscillator to move a few 
Hz for offset, and the oscillator is fixed due to some physical / atomic 
property.

yes, the whole thing will be phase locked, so no issue with freq error. For a 
fixed frequency operation , +45 and -45 deg networks for the HF will be 
accurate enough.I'll actually look at generating it out of the micro that 
is already on the board (as it loads the PLL and also indicates to the user 
presence of 10 MHz and input level) . see what the jitter calculates to be.

Anyway, thats one way to do it I guess if you have a source that is not quite 
where you want it but otherwise good.

hi hi , an SSB generator ha ha who'd thought I would be back in analog SSB 
generators after my years in SDR...

g

On 2/07/2020 12:14 am, Bob kb8tq wrote:

Hi

There is a NIST paper (somewhere) that has an example of doing this. Like any 
image
reject mixer approach, it only does just so well. It’s no different than 
generating SSB
the same way. You get a spur that is 40 to 60 db down at the “image” frequency. 
You can
tweak this or that to get it to the 60 db point, how long it will stay there …. 
that depends … :)

Since you are summing a very low frequency signal with a very high frequency 
one, the
accuracy of the low frequency signal does not need to be very good. A 1% 
accurate
5 Hz will be off by 0.05 Hz. Your combo also will only be off by 0.05Hz. For a 
lot of
Ham sort of stuff, that’s plenty good enough.

Indeed, the noise of the 5Hz and the mixer setup does get into the act. That may
rule out a simple R/C oscillator as the source of the 5 Hz “tone”…..

Bob


On Jun 30, 2020, at 9:36 PM, glen english LIST  wrote:

Hello group

I have an idea that might work, and I wanted to discuss  with likeminded that 
might already have experience with the problem.

Shifting a fixed oscillator a few Hz using a image reject mixer.

background : From time to time I (and others) make lock boards for ham gear, 
pulling the internal VCXO (vary from 11 to 55 MHz ish - which are out by a few 
Hz ) in against a 10 MHz input. Frequency accuracy is required for narrow band 
modes, and low phase noise 10kHz-200kHz is required as not to desense your ham 
neighbours.

I use fast LVDS diff receivers to square stuff up and ADF4157 high res fract 
and about 10Hz BW. That's all fine.  That aside, there are a bunch of radio 
that have only XOs, no control facility. Varying the supply voltage as a means 
of control is one way, but that doesnt work for the ovenized nor internal 
regulator types.

Other people to solve this problem by applying an external oscillator that has 
been disclipined - usually like crappy SiLabs spury synthesiser chips that can 
produce the oddball reference frequencies like 31.28234MHz ! Actually they are 
pretty good for what they are, but they are certainly not as clean close in , 
and particularly poor in spurs far away. they are what they are.

Of course the great way is a DDS , and run something like a 400-700 MHz 
VCO/SAW/BAW clock. One needs to go that high to get decent oscillator Q , and 
of course the DDS needs the high clock. The clock is of course  pulled to the 
10 MHz with something like a ADF4002 etc integer synth running high BW like 200 
kHz to kill to close in VCO noise.  But that's alot of stuff

*** I thought in the shower this morning of inserted a block, and shifting the 
internal radio oscillator (running at say 31.28234MHz the few Hertz 

Re: [time-nuts] 30 MHz freq adjust by Hz

[Bob kb8tq]

Hi

The same “small fraction of a degree” and “small fraction of a db” issues that 
plagued the analog SSB
generation process still get into this approach. For “good” ADEV you need spurs 
down below the 
-130 dbc range (and likely much lower). This only gets you to 60 db or so ….

Bob

> On Jul 1, 2020, at 5:38 PM, glen english LIST  
> wrote:
> 
> Hi Bob
> 
> I imagine in physics there are times when you want an oscillator to move a 
> few Hz for offset, and the oscillator is fixed due to some physical / atomic 
> property.
> 
> yes, the whole thing will be phase locked, so no issue with freq error. For a 
> fixed frequency operation , +45 and -45 deg networks for the HF will be 
> accurate enough.I'll actually look at generating it out of the micro that 
> is already on the board (as it loads the PLL and also indicates to the user 
> presence of 10 MHz and input level) . see what the jitter calculates to be.
> 
> Anyway, thats one way to do it I guess if you have a source that is not quite 
> where you want it but otherwise good.
> 
> hi hi , an SSB generator ha ha who'd thought I would be back in analog SSB 
> generators after my years in SDR...
> 
> g
> 
> On 2/07/2020 12:14 am, Bob kb8tq wrote:
>> Hi
>> 
>> There is a NIST paper (somewhere) that has an example of doing this. Like 
>> any image
>> reject mixer approach, it only does just so well. It’s no different than 
>> generating SSB
>> the same way. You get a spur that is 40 to 60 db down at the “image” 
>> frequency. You can
>> tweak this or that to get it to the 60 db point, how long it will stay there 
>> …. that depends … :)
>> 
>> Since you are summing a very low frequency signal with a very high frequency 
>> one, the
>> accuracy of the low frequency signal does not need to be very good. A 1% 
>> accurate
>> 5 Hz will be off by 0.05 Hz. Your combo also will only be off by 0.05Hz. For 
>> a lot of
>> Ham sort of stuff, that’s plenty good enough.
>> 
>> Indeed, the noise of the 5Hz and the mixer setup does get into the act. That 
>> may
>> rule out a simple R/C oscillator as the source of the 5 Hz “tone”…..
>> 
>> Bob
>> 
>>> On Jun 30, 2020, at 9:36 PM, glen english LIST  
>>> wrote:
>>> 
>>> Hello group
>>> 
>>> I have an idea that might work, and I wanted to discuss  with likeminded 
>>> that might already have experience with the problem.
>>> 
>>> Shifting a fixed oscillator a few Hz using a image reject mixer.
>>> 
>>> background : From time to time I (and others) make lock boards for ham 
>>> gear, pulling the internal VCXO (vary from 11 to 55 MHz ish - which are out 
>>> by a few Hz ) in against a 10 MHz input. Frequency accuracy is required for 
>>> narrow band modes, and low phase noise 10kHz-200kHz is required as not to 
>>> desense your ham neighbours.
>>> 
>>> I use fast LVDS diff receivers to square stuff up and ADF4157 high res 
>>> fract and about 10Hz BW. That's all fine.  That aside, there are a 
>>> bunch of radio that have only XOs, no control facility. Varying the supply 
>>> voltage as a means of control is one way, but that doesnt work for the 
>>> ovenized nor internal regulator types.
>>> 
>>> Other people to solve this problem by applying an external oscillator that 
>>> has been disclipined - usually like crappy SiLabs spury synthesiser chips 
>>> that can produce the oddball reference frequencies like 31.28234MHz ! 
>>> Actually they are pretty good for what they are, but they are certainly not 
>>> as clean close in , and particularly poor in spurs far away. they are what 
>>> they are.
>>> 
>>> Of course the great way is a DDS , and run something like a 400-700 MHz 
>>> VCO/SAW/BAW clock. One needs to go that high to get decent oscillator Q , 
>>> and of course the DDS needs the high clock. The clock is of course  pulled 
>>> to the 10 MHz with something like a ADF4002 etc integer synth running high 
>>> BW like 200 kHz to kill to close in VCO noise.  But that's alot of stuff
>>> 
>>> *** I thought in the shower this morning of inserted a block, and shifting 
>>> the internal radio oscillator (running at say 31.28234MHz the few Hertz 
>>> either side it needs to move.)
>>> 
>>> - by using an image reject (full complex)  mixer with a +/- 5 Hz oscillator 
>>> applied.
>>> 
>>> - by using a analog or digital variable delay line to remove or insert 
>>> delay as to strecth or contract the period . almost like a phase modulator, 
>>> but I think it is going to wrap and cause trouble. Hmm if I play with the 
>>> high and low period separately, I might be able to fix it when it wraps. 
>>> But that technique will likely insert noise for any soet of small easy 
>>> implementation.
>>> 
>>> - alias to close to baseband using another oscillator (fixed) and then 
>>> alias back up. Aliasing technique are  very cheap and useful in DSP. Hmm 
>>> that might be soemthing I do in DSP for other signal processing tricks, but 
>>> not on a small board .
>>> 
>>> The  cpx mixer is the 1st thought :
>>> 
>>> Perhaps a 

Re: [time-nuts] 30 MHz freq adjust by Hz

[Bob kb8tq]

Hi

Um …. e ….. 

If the phase spur is at 1.5 Hz at 10 MHz, it still will be at 1.5 Hz at 1296. 
The multiplication process 
does not change the offset frequency. 

What you *do* get is a change in level. If the spur is 40 db down at 10 MHz, 
then it goes up by 10 log (1296 / 10).
Net result is that your 40 db down spur is now at about 20 db down.

Bob 


> On Jul 1, 2020, at 7:54 PM, glenlist  wrote:
> 
> RRR 
> 
> Stability over about a 2 minute period, preferably within a Hz at 1296 MHz , 
> IE about 1e-09 is all that is required. I'll make it and figure out what I 
> missed :-). The unwanted sideband (and some of the original will of course 
> leak through depending on the DBM balance) will generate spurs on the output. 
> And the few Hz spurs will multiply up 100 times ot being 150Hz instead of 
> 1.5Hz spurs at a gig . I also thought of downconverting (with any XO) by  
> aliasing and then using a 455kc or 10.7  or 4.5 5.5 MHz etc IF filter (and 
> then chopping and aliasing back up) .  Hmm or a crystal. al la cheap crystal 
> lattice filter single xtal.. But now its getting a bit more complex than a 
> 74HC4316 pair  (as 2 x DBM)  and a microcontroller although HC4316s etc 
> start to leak through a bit at 30 MHz. remember the SSB difficulty was as 
> much as the (wideband) polyphase quadrature filter (the mass of R and C) 
> performance, and design of the day limiting attainable long term carrier 
> suppression.  in this case, it is just single freq quadrature at 30 Mhz I 
> need to generate. We will see !
> 
> cheers
> 
> 
> 
> On 02/07/2020 09:40, Bob kb8tq wrote:
>> Hi
>> 
>> The same “small fraction of a degree” and “small fraction of a db” issues 
>> that plagued the analog SSB
>> generation process still get into this approach. For “good” ADEV you need 
>> spurs down below the 
>> -130 dbc range (and likely much lower). This only gets you to 60 db or so ….
>> 
>> Bob
>> 
>>> On Jul 1, 2020, at 5:38 PM, glen english LIST  
>>>  wrote:
>>> 
>>> Hi Bob
>>> 
>>> I imagine in physics there are times when you want an oscillator to move a 
>>> few Hz for offset, and the oscillator is fixed due to some physical / 
>>> atomic property.
>>> 
>>> yes, the whole thing will be phase locked, so no issue with freq error. For 
>>> a fixed frequency operation , +45 and -45 deg networks for the HF will be 
>>> accurate enough.I'll actually look at generating it out of the micro 
>>> that is already on the board (as it loads the PLL and also indicates to the 
>>> user presence of 10 MHz and input level) . see what the jitter calculates 
>>> to be.
>>> 
>>> Anyway, thats one way to do it I guess if you have a source that is not 
>>> quite where you want it but otherwise good.
>>> 
>>> hi hi , an SSB generator ha ha who'd thought I would be back in analog SSB 
>>> generators after my years in SDR...
>>> 
>>> g
>>> 
>>> On 2/07/2020 12:14 am, Bob kb8tq wrote:
 Hi
 
 There is a NIST paper (somewhere) that has an example of doing this. Like 
 any image
 reject mixer approach, it only does just so well. It’s no different than 
 generating SSB
 the same way. You get a spur that is 40 to 60 db down at the “image” 
 frequency. You can
 tweak this or that to get it to the 60 db point, how long it will stay 
 there …. that depends … :)
 
 Since you are summing a very low frequency signal with a very high 
 frequency one, the
 accuracy of the low frequency signal does not need to be very good. A 1% 
 accurate
 5 Hz will be off by 0.05 Hz. Your combo also will only be off by 0.05Hz. 
 For a lot of
 Ham sort of stuff, that’s plenty good enough.
 
 Indeed, the noise of the 5Hz and the mixer setup does get into the act. 
 That may
 rule out a simple R/C oscillator as the source of the 5 Hz “tone”…..
 
 Bob
 
> On Jun 30, 2020, at 9:36 PM, glen english LIST  
>  wrote:
> 
> Hello group
> 
> I have an idea that might work, and I wanted to discuss  with likeminded 
> that might already have experience with the problem.
> 
> Shifting a fixed oscillator a few Hz using a image reject mixer.
> 
> background : From time to time I (and others) make lock boards for ham 
> gear, pulling the internal VCXO (vary from 11 to 55 MHz ish - which are 
> out by a few Hz ) in against a 10 MHz input. Frequency accuracy is 
> required for narrow band modes, and low phase noise 10kHz-200kHz is 
> required as not to desense your ham neighbours.
> 
> I use fast LVDS diff receivers to square stuff up and ADF4157 high res 
> fract and about 10Hz BW. That's all fine.  That aside, there are a 
> bunch of radio that have only XOs, no control facility. Varying the 
> supply voltage as a means of control is one way, but that doesnt work for 
> the ovenized nor internal regulator types.

Re: [time-nuts] 30 MHz freq adjust by Hz

[glen english LIST]

Hi Bob

I imagine in physics there are times when you want an oscillator to move 
a few Hz for offset, and the oscillator is fixed due to some physical / 
atomic property.


yes, the whole thing will be phase locked, so no issue with freq error. 
For a fixed frequency operation , +45 and -45 deg networks for the HF 
will be accurate enough.    I'll actually look at generating it out of 
the micro that is already on the board (as it loads the PLL and also 
indicates to the user presence of 10 MHz and input level) . see what the 
jitter calculates to be.


Anyway, thats one way to do it I guess if you have a source that is not 
quite where you want it but otherwise good.


hi hi , an SSB generator ha ha who'd thought I would be back in analog 
SSB generators after my years in SDR...


g

On 2/07/2020 12:14 am, Bob kb8tq wrote:

Hi

There is a NIST paper (somewhere) that has an example of doing this. Like any 
image
reject mixer approach, it only does just so well. It’s no different than 
generating SSB
the same way. You get a spur that is 40 to 60 db down at the “image” frequency. 
You can
tweak this or that to get it to the 60 db point, how long it will stay there …. 
that depends … :)

Since you are summing a very low frequency signal with a very high frequency 
one, the
accuracy of the low frequency signal does not need to be very good. A 1% 
accurate
5 Hz will be off by 0.05 Hz. Your combo also will only be off by 0.05Hz. For a 
lot of
Ham sort of stuff, that’s plenty good enough.

Indeed, the noise of the 5Hz and the mixer setup does get into the act. That may
rule out a simple R/C oscillator as the source of the 5 Hz “tone”…..

Bob


On Jun 30, 2020, at 9:36 PM, glen english LIST  wrote:

Hello group

I have an idea that might work, and I wanted to discuss  with likeminded that 
might already have experience with the problem.

Shifting a fixed oscillator a few Hz using a image reject mixer.

background : From time to time I (and others) make lock boards for ham gear, 
pulling the internal VCXO (vary from 11 to 55 MHz ish - which are out by a few 
Hz ) in against a 10 MHz input. Frequency accuracy is required for narrow band 
modes, and low phase noise 10kHz-200kHz is required as not to desense your ham 
neighbours.

I use fast LVDS diff receivers to square stuff up and ADF4157 high res fract 
and about 10Hz BW. That's all fine.  That aside, there are a bunch of radio 
that have only XOs, no control facility. Varying the supply voltage as a means 
of control is one way, but that doesnt work for the ovenized nor internal 
regulator types.

Other people to solve this problem by applying an external oscillator that has 
been disclipined - usually like crappy SiLabs spury synthesiser chips that can 
produce the oddball reference frequencies like 31.28234MHz ! Actually they are 
pretty good for what they are, but they are certainly not as clean close in , 
and particularly poor in spurs far away. they are what they are.

Of course the great way is a DDS , and run something like a 400-700 MHz 
VCO/SAW/BAW clock. One needs to go that high to get decent oscillator Q , and 
of course the DDS needs the high clock. The clock is of course  pulled to the 
10 MHz with something like a ADF4002 etc integer synth running high BW like 200 
kHz to kill to close in VCO noise.  But that's alot of stuff

*** I thought in the shower this morning of inserted a block, and shifting the 
internal radio oscillator (running at say 31.28234MHz the few Hertz either side 
it needs to move.)

- by using an image reject (full complex)  mixer with a +/- 5 Hz oscillator 
applied.

- by using a analog or digital variable delay line to remove or insert delay as 
to strecth or contract the period . almost like a phase modulator, but I think 
it is going to wrap and cause trouble. Hmm if I play with the high and low 
period separately, I might be able to fix it when it wraps. But that technique 
will likely insert noise for any soet of small easy implementation.

- alias to close to baseband using another oscillator (fixed) and then alias 
back up. Aliasing technique are  very cheap and useful in DSP. Hmm that might 
be soemthing I do in DSP for other signal processing tricks, but not on a small 
board .

The  cpx mixer is the 1st thought :

Perhaps a commutating HC-CMOS switch quadrature DBM (like HC4316) with the 
complex LO +/- 5 Hz coming from something I can dream up.

For a single frequency, I would be able to get the quadrature matching at least 
-60 over temperature  in my experience with something like this..

That would be the unwanted sideband down that far. Of course with square wave 
drive, the mixer will be sensitive to the harmonic series, but the input is 
squeaky clean, so that's no issue. ALTHOUGH hmm the close in noise say + /- 10 
Hz would get a say as it would be aliased in, but the 10Hz noise on those XOs 
is usually prety good, and for this purpose, it is the noise at offsets  of 
10kHz up to 300kHz that are the 

Re: [time-nuts] low power divide by 5

[jimlux]

On 7/1/20 1:41 PM, ed breya wrote:

Yeah, I know. I was just lamenting the lack of nice medium-density count 
functions in 74AC. It's hard to beat the simplicity of a '390 when you 




Anyway, I've always liked having a wide assortment of MSI logic devices 
available in all families, that you just hook up and it goes - no setup, 
no programming. I've saved lots of counter types for possible use. One 
obscure one is the MC14566, with divide 6 counters for clock time 
readout and generation, in the old days.


That's sort of the design goal for the 22V10 and earlier PAL devices - 
keep them in familiar DIP packages, power on the corners like the IC 
gods intended, and you can program it to replicate a whole variety of 
MSI functionality, often with the same pinout.


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Re: [time-nuts] low power divide by 5

[Richard (Rick) Karlquist]

I designed a marine radio in 1976 that used 74LS161's.
They could do something like 15 MHz on a good day
at room temperature.  I did a lot of characterization
on them.  100 MHz?  In your dreams...

BTW, if you want to divide by ten in the LS family,
the 74LS160 is a better choice, because it will
divide by 10 without any logic feedback.  It still
won't do 100 MHz.

73
Rick N6RK

On 7/1/2020 1:37 PM, Perry Sandeen via time-nuts wrote:

Learned List

When I was looking for a 100 MHz divide by 10 in a dip package I was advised by 
someone on the list to use the 74LS161.
  It's available on Ebay on ebay from several sources for reasonable prices.
Regards,
Perrier
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Re: [time-nuts] 30 MHz freq adjust by Hz

[Steve - Home]

Hello Glen,

Any progress on the Anylocker? I’d still like to get two for the FT817, 1pps 
input first choice, 10 MHz second choice. 

Cheers,

Steve
WB0DBS



> On Jul 1, 2020, at 2:30 AM, glen english LIST  
> wrote:
> 
> Hello group
> 
> I have an idea that might work, and I wanted to discuss  with likeminded that 
> might already have experience with the problem.
> 
> Shifting a fixed oscillator a few Hz using a image reject mixer.
> 
> background : From time to time I (and others) make lock boards for ham gear, 
> pulling the internal VCXO (vary from 11 to 55 MHz ish - which are out by a 
> few Hz ) in against a 10 MHz input. Frequency accuracy is required for narrow 
> band modes, and low phase noise 10kHz-200kHz is required as not to desense 
> your ham neighbours.
> 
> I use fast LVDS diff receivers to square stuff up and ADF4157 high res fract 
> and about 10Hz BW. That's all fine.  That aside, there are a bunch of 
> radio that have only XOs, no control facility. Varying the supply voltage as 
> a means of control is one way, but that doesnt work for the ovenized nor 
> internal regulator types.
> 
> Other people to solve this problem by applying an external oscillator that 
> has been disclipined - usually like crappy SiLabs spury synthesiser chips 
> that can produce the oddball reference frequencies like 31.28234MHz ! 
> Actually they are pretty good for what they are, but they are certainly not 
> as clean close in , and particularly poor in spurs far away. they are what 
> they are.
> 
> Of course the great way is a DDS , and run something like a 400-700 MHz 
> VCO/SAW/BAW clock. One needs to go that high to get decent oscillator Q , and 
> of course the DDS needs the high clock. The clock is of course  pulled to the 
> 10 MHz with something like a ADF4002 etc integer synth running high BW like 
> 200 kHz to kill to close in VCO noise.  But that's alot of stuff
> 
> *** I thought in the shower this morning of inserted a block, and shifting 
> the internal radio oscillator (running at say 31.28234MHz the few Hertz 
> either side it needs to move.)
> 
> - by using an image reject (full complex)  mixer with a +/- 5 Hz oscillator 
> applied.
> 
> - by using a analog or digital variable delay line to remove or insert delay 
> as to strecth or contract the period . almost like a phase modulator, but I 
> think it is going to wrap and cause trouble. Hmm if I play with the high and 
> low period separately, I might be able to fix it when it wraps. But that 
> technique will likely insert noise for any soet of small easy implementation.
> 
> - alias to close to baseband using another oscillator (fixed) and then alias 
> back up. Aliasing technique are  very cheap and useful in DSP. Hmm that might 
> be soemthing I do in DSP for other signal processing tricks, but not on a 
> small board .
> 
> The  cpx mixer is the 1st thought :
> 
> Perhaps a commutating HC-CMOS switch quadrature DBM (like HC4316) with the 
> complex LO +/- 5 Hz coming from something I can dream up.
> 
> For a single frequency, I would be able to get the quadrature matching at 
> least -60 over temperature  in my experience with something like this..
> 
> That would be the unwanted sideband down that far. Of course with square wave 
> drive, the mixer will be sensitive to the harmonic series, but the input is 
> squeaky clean, so that's no issue. ALTHOUGH hmm the close in noise say + /- 
> 10 Hz would get a say as it would be aliased in, but the 10Hz noise on those 
> XOs is usually prety good, and for this purpose, it is the noise at offsets  
> of 10kHz up to 300kHz that are the most important.  Control bandwidth only 
> has to track thermal drift in the radio, have be fractions of a Hz, so the 
> system could spend some time calculating and generating the LO.
> 
> Anyone tried this (IE shifting the frequency of the source)  ? Comments ?
> 
> Glen
> 
> (VK1XX, AI6UM)
> 
> 
> 
> 
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Re: [time-nuts] low power divide by 5

[Alex Pummer]

There was once upon the time a very good data/application-book from 
Fairchild for TTL logic, they published many different modulo frequency 
dividers with 50% duty-cycle for the "9316" which is the functional 
equivalent grandfather  for 74161 and therefore for the AC161 to.
For frequency division, if the output is used  for analog application it 
is preferable to have 50% duty-cycle.

Alex
KJ6UHN

On 7/1/2020 2:03 PM, Peter McCollum wrote:

When I was looking for a 100 MHz divide by 10 in a dip package I was

advised by someone on the list to use the 74LS161.
  It's available on Ebay on ebay from several sources for reasonable
prices.

74LS161 won't go that fast - 20-25 MHz is max.

Pete


On Wed, Jul 1, 2020 at 2:46 PM Perry Sandeen via time-nuts <
time-nuts@lists.febo.com> wrote:


Learned List

When I was looking for a 100 MHz divide by 10 in a dip package I was
advised by someone on the list to use the 74LS161.
  It's available on Ebay on ebay from several sources for reasonable prices.
Regards,
Perrier
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Re: [time-nuts] low power divide by 5

[Peter McCollum]

>When I was looking for a 100 MHz divide by 10 in a dip package I was
advised by someone on the list to use the 74LS161.
 It's available on Ebay on ebay from several sources for reasonable
prices.

74LS161 won't go that fast - 20-25 MHz is max.

Pete


On Wed, Jul 1, 2020 at 2:46 PM Perry Sandeen via time-nuts <
time-nuts@lists.febo.com> wrote:

> Learned List
>
> When I was looking for a 100 MHz divide by 10 in a dip package I was
> advised by someone on the list to use the 74LS161.
>  It's available on Ebay on ebay from several sources for reasonable prices.
> Regards,
> Perrier
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>
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Re: [time-nuts] low power divide by 5

[ed breya]

Tom wrote:
"Ed, For division, there's less need for a dedicated divide-by-10 
counter since the '161 and '163 are *presettable* synchronous binary 
counters. As such you can wire them to divide by anything from 2 to 16, 
which includes 10. In addition they are *cascadable*, which means that 
you can create synchronous 8- or 12- or 16- or 20-bit or even larger 
dividers. The datasheets for these counters sometimes show examples of 
multi-chip dividers. Attached is a photo of a 'LS00 plus 3 'LS161 
counters configured as divide-by-1173 counter. The 2nd photo is a 
divide-by-3295 count. You can see it's just a matter of changing the 
jumpers on the preset pins.


/On 6/29/2020 3:32 PM, ed breya wrote:Looks like the AC161 and AC163 are 
readily available, so they may be />/rigged for divide 5. It seems that of the counters surviving into AC, />/only binary ones are included, and the oddballs like decade are />/considered unnecessary - apparently nobody divides by 10 anymore, />/except inside of a processor."/



Yeah, I know. I was just lamenting the lack of nice medium-density count 
functions in 74AC. It's hard to beat the simplicity of a '390 when you 
want divide 5s and 10s, having two complete bi-quinary counters in one 
package, ready to go. I've used HC390s and 393s often for up to 20 MHz, 
and always assumed I could get the AC versions if needed, although I 
usually go with ECL above that anyway, so this issue never came up for me.


I haven't looked at my 74AC parts inventory in a while, but I think I 
may have a couple '390s or '393s - I guess I'll have to hang on to them 
for "special" occasions. One thing I found interesting in my recent 
searching for AC parts, is that the AC4040 is available. That's my 
favorite counter for dividing by big numbers, good for any integer to 
4095, in one package, plus some simple external diode or glue logic 
feedback.


Anyway, I've always liked having a wide assortment of MSI logic devices 
available in all families, that you just hook up and it goes - no setup, 
no programming. I've saved lots of counter types for possible use. One 
obscure one is the MC14566, with divide 6 counters for clock time 
readout and generation, in the old days.


Ed
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[time-nuts] low power divide by 5

[Perry Sandeen via time-nuts]

Learned List

When I was looking for a 100 MHz divide by 10 in a dip package I was advised by 
someone on the list to use the 74LS161. 
 It's available on Ebay on ebay from several sources for reasonable prices.
Regards,
Perrier
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Re: [time-nuts] 30 MHz freq adjust by Hz

[Bob kb8tq]

Hi

There is a NIST paper (somewhere) that has an example of doing this. Like any 
image 
reject mixer approach, it only does just so well. It’s no different than 
generating SSB
the same way. You get a spur that is 40 to 60 db down at the “image” frequency. 
You can
tweak this or that to get it to the 60 db point, how long it will stay there …. 
that depends … :)

Since you are summing a very low frequency signal with a very high frequency 
one, the
accuracy of the low frequency signal does not need to be very good. A 1% 
accurate 
5 Hz will be off by 0.05 Hz. Your combo also will only be off by 0.05Hz. For a 
lot of
Ham sort of stuff, that’s plenty good enough. 

Indeed, the noise of the 5Hz and the mixer setup does get into the act. That 
may 
rule out a simple R/C oscillator as the source of the 5 Hz “tone”…..

Bob

> On Jun 30, 2020, at 9:36 PM, glen english LIST  
> wrote:
> 
> Hello group
> 
> I have an idea that might work, and I wanted to discuss  with likeminded that 
> might already have experience with the problem.
> 
> Shifting a fixed oscillator a few Hz using a image reject mixer.
> 
> background : From time to time I (and others) make lock boards for ham gear, 
> pulling the internal VCXO (vary from 11 to 55 MHz ish - which are out by a 
> few Hz ) in against a 10 MHz input. Frequency accuracy is required for narrow 
> band modes, and low phase noise 10kHz-200kHz is required as not to desense 
> your ham neighbours.
> 
> I use fast LVDS diff receivers to square stuff up and ADF4157 high res fract 
> and about 10Hz BW. That's all fine.  That aside, there are a bunch of 
> radio that have only XOs, no control facility. Varying the supply voltage as 
> a means of control is one way, but that doesnt work for the ovenized nor 
> internal regulator types.
> 
> Other people to solve this problem by applying an external oscillator that 
> has been disclipined - usually like crappy SiLabs spury synthesiser chips 
> that can produce the oddball reference frequencies like 31.28234MHz ! 
> Actually they are pretty good for what they are, but they are certainly not 
> as clean close in , and particularly poor in spurs far away. they are what 
> they are.
> 
> Of course the great way is a DDS , and run something like a 400-700 MHz 
> VCO/SAW/BAW clock. One needs to go that high to get decent oscillator Q , and 
> of course the DDS needs the high clock. The clock is of course  pulled to the 
> 10 MHz with something like a ADF4002 etc integer synth running high BW like 
> 200 kHz to kill to close in VCO noise.  But that's alot of stuff
> 
> *** I thought in the shower this morning of inserted a block, and shifting 
> the internal radio oscillator (running at say 31.28234MHz the few Hertz 
> either side it needs to move.)
> 
> - by using an image reject (full complex)  mixer with a +/- 5 Hz oscillator 
> applied.
> 
> - by using a analog or digital variable delay line to remove or insert delay 
> as to strecth or contract the period . almost like a phase modulator, but I 
> think it is going to wrap and cause trouble. Hmm if I play with the high and 
> low period separately, I might be able to fix it when it wraps. But that 
> technique will likely insert noise for any soet of small easy implementation.
> 
> - alias to close to baseband using another oscillator (fixed) and then alias 
> back up. Aliasing technique are  very cheap and useful in DSP. Hmm that might 
> be soemthing I do in DSP for other signal processing tricks, but not on a 
> small board .
> 
> The  cpx mixer is the 1st thought :
> 
> Perhaps a commutating HC-CMOS switch quadrature DBM (like HC4316) with the 
> complex LO +/- 5 Hz coming from something I can dream up.
> 
> For a single frequency, I would be able to get the quadrature matching at 
> least -60 over temperature  in my experience with something like this..
> 
> That would be the unwanted sideband down that far. Of course with square wave 
> drive, the mixer will be sensitive to the harmonic series, but the input is 
> squeaky clean, so that's no issue. ALTHOUGH hmm the close in noise say + /- 
> 10 Hz would get a say as it would be aliased in, but the 10Hz noise on those 
> XOs is usually prety good, and for this purpose, it is the noise at offsets  
> of 10kHz up to 300kHz that are the most important.  Control bandwidth only 
> has to track thermal drift in the radio, have be fractions of a Hz, so the 
> system could spend some time calculating and generating the LO.
> 
> Anyone tried this (IE shifting the frequency of the source)  ? Comments ?
> 
> Glen
> 
> (VK1XX, AI6UM)
> 
> 
> 
> 
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Re: [time-nuts] low power divide by 5

[jimlux]

On 7/1/20 5:24 AM, Detlef Schuecker via time-nuts wrote:

Hi,

there are three JK-FF, with Q1 as MSB, Q3 as LSB. J1,K1 ist input to Q1,
etc. .
There are 8^6 possibilties (6 inputs to the Qx or QxNOT or to HIGH or to
LOW) of which
2069 generate a cycle length of 5.

The following wiring will generate the cycle 1 3 5 2 4 :

J1=Q2
K1=Q1
J2=Q3
K2=Q2
J3=Q2NOT
K3=Q1

Q3 is output with a 3/5 duty cycle.
The unused state 0 will migrate to 1,6->0,7->0.
So the machine does not get stuck.

Cheers
Detlef





And one can still buy 74AC109 dual JK which supposedly toggle at >100MHz.



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Re: [time-nuts] low power divide by 5

[Dan Kemppainen]

Just a thought:

https://www.analog.com/media/en/technical-documentation/data-sheets/hmc438.pdf

Although it isn't really 'low power', and the input and output ranges 
are somewhat limited. Certainly not logic level.


Dan




On 7/1/2020 2:50 AM, time-nuts-requ...@lists.febo.com wrote:

Message: 4
Date: Wed, 1 Jul 2020 00:47:32 +0200
From: dschuecker
To:time-nuts@lists.febo.com
Subject: Re: [time-nuts] low power divide by 5
Message-ID:
Content-Type: text/plain; charset=utf-8; format=flowed

Hi,

a divide by five should possible with a synchronous state-machine made
of 3 ( sufficiently fast-) JK-FlipFlops.

All 3 FFs are clocked with the input freq. , the outputs of the FFs are
fed back to the the JK-inputs,? the divided freq. is output of one of
the FFs.

Additional constraints: no external ANDs or ORs or NOTs, the
state-machine does not get stuck in the 3 unused states.

This turned out to be a very interesting problem and I do not yet come
up with a solution. Maybe there is none. Analytical solutions all
failed, I will try a brute force enumeration attack tomorrow.

lots of fun !

Cheers


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Re: [time-nuts] FA 2 Counter variations

[Stan, W1LE via time-nuts]

My FA-2 variation has:

FA-2 Precision

Freq Counter

BG7TBL

on the top left of the face plate.

There is also a variation for frequency coverage. Mine is good to 12 GHz.

Stan, W1LE


On 7/1/2020 2:13 AM, Perry Sandeen via time-nuts wrote:

Learned List,
Checking the Ebay listings for the FA-2 counter I saw three variations. One had 
just BG7TBL on the bottom of the face plate.
A second -since deleted- had BG7TBL XX- XX-  (date).
A third one was labeled?? BG7TBL 20190622. All had wildly different prices.
So is this just some form of date coding or is there some technical difference?
Regards,
Perrier




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[time-nuts] low power divide by 5

[Detlef Schuecker via time-nuts]

Hi,

there are three JK-FF, with Q1 as MSB, Q3 as LSB. J1,K1 ist input to Q1, 
etc. .
There are 8^6 possibilties (6 inputs to the Qx or QxNOT or to HIGH or to 
LOW) of which
2069 generate a cycle length of 5.

The following wiring will generate the cycle 1 3 5 2 4 :

J1=Q2
K1=Q1
J2=Q3
K2=Q2
J3=Q2NOT
K3=Q1

Q3 is output with a 3/5 duty cycle.
The unused state 0 will migrate to 1,6->0,7->0.
So the machine does not get stuck.

Cheers
Detlef 


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Re: [time-nuts] low power divide by 5

[dschuecker]

hm,

first example of divide by 5 needs an additional AND, second example 
gets stuck in an unused state :(


Cheers

Detlef

Am 01.07.2020 um 02:14 schrieb David:

Here's a web page with several JK flip-flop dividers, including divide
by 5:

http://www.play-hookey.com/digital/counters/frequency_dividers.html

Dave

On 2020-06-30 15:47, dschuecker wrote:


Hi,

a divide by five should possible with a synchronous state-machine made of 3 ( 
sufficiently fast-) JK-FlipFlops.

All 3 FFs are clocked with the input freq. , the outputs of the FFs are fed 
back to the the JK-inputs,  the divided freq. is output of one of the FFs.

Additional constraints: no external ANDs or ORs or NOTs, the state-machine does 
not get stuck in the 3 unused states.

This turned out to be a very interesting problem and I do not yet come up with 
a solution. Maybe there is none. Analytical solutions all failed, I will try a 
brute force enumeration attack tomorrow.

lots of fun !

Cheers

Detlef

Am 30.06.2020 um 08:37 schrieb Hal Murray: You might try the 74AC161, which 
works to 73MHz at 3.3V or 103 MHz at 5V, -40
to 85C.
Set the data inputs to DCBA = 1011 and connect an inverter from the carry
output (pin 15) to the Load input (pin 9) to divide by 5. See http://
www.techlib.com/electronics/74161Divider.htm [1] You didn't read the data sheet 
carefully enough.  That 73 MHz is the bragging
number for sales people, often not useful.  For something like this, you need
to add the clock-to-out for the ripple carry, prop time through inverter, and
setup time at the load input.

I was going to ask whether 73MHz included the delay through the inverter, but
it's much worse than that.  The clock to out on the RCO pin is 21 ns.  Even
without the inverter, it won't make 50 MHz.

You can save a few ns if you use a FF with inverting output instead of an
inverter.  That adds a pipeline stage so you have to adjust the constant that
gets loaded.  Setup time on a 3V AC74 is 4.3 ns which gets to 40 MHz (actually
only 39.5).

At 5V,
AC161 clk-RCO is 15.2
AC74 setup is 3.1
So that works - 54.6 MHz.

Using an inverter:
AC161 clk-RCO is 15.2
AC04 prop 5.9
AC161 setup 5.3
That's 37.9 MHz

(That's all assuming I didn't fatfinger anything.)

I like Richard Karlquist's trick of using a data bit to reload.
Unfortunately, for the AC161, the data out isn't significantly faster than the
carry out.

If I did the numbers correctly, that's 35 MHz at 3.3V and 49.3 MHz at 5V.

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Links:
--
[1] http://www.techlib.com/electronics/74161Divider.htm
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Re: [time-nuts] low power divide by 5

[Gerhard Hoffmann]

Am 01.07.20 um 03:04 schrieb Hal Murray:

What logic family might be appropriate for a divide by 5 from 50 to 10MHz,
low power, running off 3.3 or 5V?

How important is the "low" power?  Do you have other logic/CPU around?

Do you need 50/50 duty cycle (or close) or is 20/80 OK?

How about a CPU with a counter/timer block setup to divide by 5 and the CPU
sleeping (if it doesn't have anything else to do)?

What is available in the small FPGA or PAL space?

In the divide-by-81 thread I have proposed a Xilinx Coolrunner, with
VHDL code, and a link to a prefabricated Chinese board. Just replace
the 81 by 5 and choose the new On/Off ratio.

< 
https://www.digikey.de/product-detail/de/xilinx-inc/XC2C64A-5VQG44C/122-1420-ND/966601 
    >



Prices are slowly rising, that's Xilinx' way of saying: we don't like it 
anymore,

but we usually don't obsolete anything.
I'm just doing a custom reciprocal frequency counter with SPI interface 
in one,
and my crystal oven infrastructure board uses such a 2C64 for its 1pps 
generator
and switchable direction 2FF phase detector. You can do a lot of things 
with just 64


flipflops. It's weird, but Coolrunner Flipflops can act on both rising 
and falling


clock edge if required.


Much modern logic is aimed at the high speed market which usually means thin
oxide which leaks.  I'm pretty sure I've seen some FPGA/PAL families that are
old but still very active just because their idle power is very low - the last
family before things started to leak.

When it was new, Xilinx demonstrated the Coolrunner with a battery
made from 3 apples or oranges and some wire.





How about a shift register?  It needs a reset signal to get started.




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Re: [time-nuts] low power divide by 5

[Mike Ingle]

Hi,

As suggested by others, another approach could be to use a cpld of some
type, for example look at the lattice mach  or the old cool-runner
varieties.
You can usually DDR the clock.  This should give the same symmetry as the
input clock.  With a 50% duty cycle 50MHz input this should give a 10MHz
50% output;
In VHDL for example:

process(clk)
begin
if (rising_edge(clk) or falling_edge(clk)) then
  if (cnt < 5) then
cnt <= cnt + 1;
  else
cnt <= 0;
divided_by_five <= not(divided_by_five);
  end if;
 end if;
end process;

and there are usually built in DDR IP's from the vendors.

-- mike

On Wed, Jul 1, 2020 at 8:50 AM Robert LaJeunesse 
wrote:

> Take a look at the "modified" shift-register like counter in the attached
> jpg file. When simulated online it behaved as expected for a divide by 5. I
> believe it also is self-clearing from illegal states, but the other
> simulator I tested that in wasn't good for documenting the design.
>
> Bob L.
>
> > Sent: Tuesday, June 30, 2020 at 6:47 PM
> > From: "dschuecker" 
> > To: time-nuts@lists.febo.com
> > Subject: Re: [time-nuts] low power divide by 5
> >
> > Hi,
> >
> > a divide by five should possible with a synchronous state-machine made
> > of 3 ( sufficiently fast-) JK-FlipFlops.
> >
> > All 3 FFs are clocked with the input freq. , the outputs of the FFs are
> > fed back to the the JK-inputs,  the divided freq. is output of one of
> > the FFs.
> >
> > Additional constraints: no external ANDs or ORs or NOTs, the
> > state-machine does not get stuck in the 3 unused states.
> >
> > This turned out to be a very interesting problem and I do not yet come
> > up with a solution. Maybe there is none. Analytical solutions all
> > failed, I will try a brute force enumeration attack tomorrow.
> >
> > lots of fun !
> >
> > Cheers
> >
> > Detlef
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[time-nuts] FA 2 Counter variations

[Perry Sandeen via time-nuts]

Learned List,
Checking the Ebay listings for the FA-2 counter I saw three variations. One had 
just BG7TBL on the bottom of the face plate.
A second -since deleted- had BG7TBL XX- XX-  (date).
A third one was labeled  BG7TBL 20190622. All had wildly different prices.
So is this just some form of date coding or is there some technical difference?
Regards,
Perrier



   
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[time-nuts] 30 MHz freq adjust by Hz

[glen english LIST]

Hello group

I have an idea that might work, and I wanted to discuss  with likeminded 
that might already have experience with the problem.


Shifting a fixed oscillator a few Hz using a image reject mixer.

background : From time to time I (and others) make lock boards for ham 
gear, pulling the internal VCXO (vary from 11 to 55 MHz ish - which are 
out by a few Hz ) in against a 10 MHz input. Frequency accuracy is 
required for narrow band modes, and low phase noise 10kHz-200kHz is 
required as not to desense your ham neighbours.


I use fast LVDS diff receivers to square stuff up and ADF4157 high res 
fract and about 10Hz BW. That's all fine.  That aside, there are a 
bunch of radio that have only XOs, no control facility. Varying the 
supply voltage as a means of control is one way, but that doesnt work 
for the ovenized nor internal regulator types.


Other people to solve this problem by applying an external oscillator 
that has been disclipined - usually like crappy SiLabs spury synthesiser 
chips that can produce the oddball reference frequencies like 
31.28234MHz ! Actually they are pretty good for what they are, but they 
are certainly not as clean close in , and particularly poor in spurs far 
away. they are what they are.


Of course the great way is a DDS , and run something like a 400-700 MHz 
VCO/SAW/BAW clock. One needs to go that high to get decent oscillator Q 
, and of course the DDS needs the high clock. The clock is of course  
pulled to the 10 MHz with something like a ADF4002 etc integer synth 
running high BW like 200 kHz to kill to close in VCO noise.  But that's 
alot of stuff


*** I thought in the shower this morning of inserted a block, and 
shifting the internal radio oscillator (running at say 31.28234MHz the 
few Hertz either side it needs to move.)


- by using an image reject (full complex)  mixer with a +/- 5 Hz 
oscillator applied.


- by using a analog or digital variable delay line to remove or insert 
delay as to strecth or contract the period . almost like a phase 
modulator, but I think it is going to wrap and cause trouble. Hmm if I 
play with the high and low period separately, I might be able to fix it 
when it wraps. But that technique will likely insert noise for any soet 
of small easy implementation.


- alias to close to baseband using another oscillator (fixed) and then 
alias back up. Aliasing technique are  very cheap and useful in DSP. Hmm 
that might be soemthing I do in DSP for other signal processing tricks, 
but not on a small board .


The  cpx mixer is the 1st thought :

Perhaps a commutating HC-CMOS switch quadrature DBM (like HC4316) with 
the complex LO +/- 5 Hz coming from something I can dream up.


For a single frequency, I would be able to get the quadrature matching 
at least -60 over temperature  in my experience with something like this..


That would be the unwanted sideband down that far. Of course with square 
wave drive, the mixer will be sensitive to the harmonic series, but the 
input is squeaky clean, so that's no issue. ALTHOUGH hmm the close in 
noise say + /- 10 Hz would get a say as it would be aliased in, but the 
10Hz noise on those XOs is usually prety good, and for this purpose, it 
is the noise at offsets  of 10kHz up to 300kHz that are the most 
important.  Control bandwidth only has to track thermal drift in the 
radio, have be fractions of a Hz, so the system could spend some time 
calculating and generating the LO.


Anyone tried this (IE shifting the frequency of the source)  ? Comments ?

Glen

(VK1XX, AI6UM)




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Re: [time-nuts] low power divide by 5

[Robert LaJeunesse]

Take a look at the "modified" shift-register like counter in the attached jpg 
file. When simulated online it behaved as expected for a divide by 5. I believe 
it also is self-clearing from illegal states, but the other simulator I tested 
that in wasn't good for documenting the design.

Bob L.

> Sent: Tuesday, June 30, 2020 at 6:47 PM
> From: "dschuecker" 
> To: time-nuts@lists.febo.com
> Subject: Re: [time-nuts] low power divide by 5
>
> Hi,
> 
> a divide by five should possible with a synchronous state-machine made 
> of 3 ( sufficiently fast-) JK-FlipFlops.
> 
> All 3 FFs are clocked with the input freq. , the outputs of the FFs are 
> fed back to the the JK-inputs,  the divided freq. is output of one of 
> the FFs.
> 
> Additional constraints: no external ANDs or ORs or NOTs, the 
> state-machine does not get stuck in the 3 unused states.
> 
> This turned out to be a very interesting problem and I do not yet come 
> up with a solution. Maybe there is none. Analytical solutions all 
> failed, I will try a brute force enumeration attack tomorrow.
> 
> lots of fun !
> 
> Cheers
> 
> Detlef
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Re: [time-nuts] low power divide by 5

[jimlux]

On 6/30/20 5:04 PM, Richard (Rick) Karlquist wrote:


On 6/30/2020 3:47 PM, dschuecker wrote:

Hi,

a divide by five should possible with a synchronous state-machine made 
of 3 ( sufficiently fast-) JK-FlipFlops.


All 3 FFs are clocked with the input freq. , the outputs of the FFs 
are fed back to the the JK-inputs,  the divided freq. is output of one 
of the FFs.



Detlef




Nice ideas, but JK flip flops seem to have become extinct in
newer logic families.

It might be interesting to see what could be done
using one of those programmable logic devices (PLD).





Oddly, those too are hard to find.. The venerable 22V10 (which I used in 
the 1980s) is still available (as the ATF22V10 from Microchip/semi), 
targeting the military market (probably to "build to print" stuff 
designed in the 80s and 90s)


But it's interesting - lots of 20k gate FPGAs and such, not so many 
"dozen flip flops and 2 dozen gates" devices.




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Re: [time-nuts] low power divide by 5

[Hal Murray]

> What logic family might be appropriate for a divide by 5 from 50 to 10MHz,
> low power, running off 3.3 or 5V?

How important is the "low" power?  Do you have other logic/CPU around?

Do you need 50/50 duty cycle (or close) or is 20/80 OK?

How about a CPU with a counter/timer block setup to divide by 5 and the CPU 
sleeping (if it doesn't have anything else to do)?

What is available in the small FPGA or PAL space?

Much modern logic is aimed at the high speed market which usually means thin 
oxide which leaks.  I'm pretty sure I've seen some FPGA/PAL families that are 
old but still very active just because their idle power is very low - the last 
family before things started to leak.

How about a shift register?  It needs a reset signal to get started.


-- 
These are my opinions.  I hate spam.




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