date:20100317

Dear Joakim Tjernlund,

In message 
off4ab0804.be309218-onc12576e9.003a69df-c12576e9.003b4...@transmode.se you 
wrote:

 hmm, I recently discovered that normal user space headers always define
 both __LITTLE_ENDIAN and __BIG_ENDIAN so therefore a
 # ifdef __LITTLE_ENDIAN
 #  define DO_CRC(x) crc = tab[(crc ^ (x))  255] ^ (crc  8)
 # else
 #  define DO_CRC(x) crc = tab[((crc  24) ^ (x))  255] ^ (crc  8)
 # endif
 
 Wont work. One have to use
  #if __BYTE_ORDER == __LITTLE_ENDIAN
 instead.

Wenn...

3ee8c120 (Joakim Tjernlund 2009-11-19 13:44:16 +0100 166) # 
ifdef __LITTLE_ENDIAN
3ee8c120 (Joakim Tjernlund 2009-11-19 13:44:16 +0100 167) #  
define DO_CRC(x) crc = tab[(crc ^ (x))  255] ^ (crc  8)
3ee8c120 (Joakim Tjernlund 2009-11-19 13:44:16 +0100 168) # else
3ee8c120 (Joakim Tjernlund 2009-11-19 13:44:16 +0100 169) #  
define DO_CRC(x) crc = tab[((crc  24) ^ (x))  255] ^ (crc  8)
3ee8c120 (Joakim Tjernlund 2009-11-19 13:44:16 +0100 170) # 
endif


commit 3ee8c12071f0e3bdda25125b63c9d3fd54a7c9d8
Author: Joakim Tjernlund joakim.tjernl...@transmode.se
Date:   Thu Nov 19 13:44:16 2009 +0100

crc32: Impl. linux optimized crc32()

Ported over the more efficient linux crc32() function.
A quick comparsion on ppc:
After changing the old crc32 to do 4 bytes in the
inner loop to be able to compare with new version one can note:
- old inner loop has 61 insn, new has 19 insn.
- new crc32 does one 32 bit load of data to crc while
  the old does four 8 bits loads.
- size is bit bigger for the new crc32:
  1392(old) 1416(new) of text. The is because the new version
  shares code with crc32_no_comp() instead of duplicating code.
- about 33% faster on ppc:
  New  crc 0 0xfff - 39 secs
  Old  crc 0 0xfff - 60 secs

Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se


Looks as if this were your very own commit. Do you have a fix in the
works?

Best regards,

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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[U-Boot] [PATCH] [ARM] Convert at91 watchdog driver to new SoC access

2010-03-17 Thread Achim Ehrlich

This converts the at91 watchdog driver to new c structure
type to access registers of the SoC

Signed-off-by: Achim Ehrlich aehrl...@taskit.de
---
 drivers/watchdog/at91sam9_wdt.c |   21 +++--
 1 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index 5bb8b77..25afae7 100644
--- a/drivers/watchdog/at91sam9_wdt.c
+++ b/drivers/watchdog/at91sam9_wdt.c
@@ -42,11 +42,10 @@
 static int at91_wdt_settimeout(unsigned int timeout)
 {
unsigned int reg;
-   unsigned int mr;
+   at91_wdt_t *wd  = (at91_wdt_t *) AT91_WDT_BASE;
 
/* Check if disabled */
-   mr = at91_sys_read(AT91_WDT_MR);
-   if (mr  AT91_WDT_WDDIS) {
+   if (readl(wd-mr)  AT91_WDT_MR_WDDIS) {
printf(sorry, watchdog is disabled\n);
return -1;
}
@@ -57,19 +56,21 @@ static int at91_wdt_settimeout(unsigned int timeout)
 * Since WDV is a 12-bit counter, the maximum period is
 * 4096 / 256 = 16 seconds.
 */
-   reg = AT91_WDT_WDRSTEN  /* causes watchdog reset */
-   /* | AT91_WDT_WDRPROC   causes processor reset only */
-   | AT91_WDT_WDDBGHLT /* disabled in debug mode */
-   | AT91_WDT_WDD  /* restart at any time */
-   | (timeout  AT91_WDT_WDV); /* timer value */
-   at91_sys_write(AT91_WDT_MR, reg);
+
+   reg = AT91_WDT_MR_WDRSTEN   /* causes watchdog reset */
+   | AT91_WDT_MR_WDDBGHLT  /* disabled in debug mode */
+   | AT91_WDT_MR_WDD(0xfff)/* restart at any time */
+   | AT91_WDT_MR_WDV(timeout); /* timer value */
+
+   writel(reg, wd-mr);
 
return 0;
 }
 
 void hw_watchdog_reset(void)
 {
-   at91_sys_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
+   at91_wdt_t *wd  = (at91_wdt_t *) AT91_WDT_BASE;
+   writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, wd-cr);
 }
 
 void hw_watchdog_init(void)
-- 
1.6.4.4

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[U-Boot] [PATCH v3] TI: Davinci: NAND Driver Cleanup

2010-03-17 Thread Cyril Chemparathy

Modified to use IO accessor routines consistently.  Eliminated volatile usage
to keep checkpatch.pl happy.

Signed-off-by: Cyril Chemparathy cy...@ti.com
---
Minor formatting

 board/davinci/da830evm/da830evm.c|2 +-
 drivers/mtd/nand/davinci_nand.c  |  128 --
 include/asm-arm/arch-davinci/emif_defs.h |   77 --
 3 files changed, 106 insertions(+), 101 deletions(-)

diff --git a/board/davinci/da830evm/da830evm.c 
b/board/davinci/da830evm/da830evm.c
index ed668af..6385443 100644
--- a/board/davinci/da830evm/da830evm.c
+++ b/board/davinci/da830evm/da830evm.c
@@ -150,7 +150,7 @@ int board_init(void)
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(2) |
DAVINCI_ABCR_ASIZE_8BIT),
-  davinci_emif_regs-AB2CR);
+  davinci_emif_regs-ab2cr);
 #endif
 
/* arch number of the board */
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index bfc2acf..4ca738e 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -57,8 +57,6 @@
 #define ECC_STATE_ERR_CORR_COMP_P  0x2
 #define ECC_STATE_ERR_CORR_COMP_N  0x3
 
-static emif_registers *const emif_regs = (void *) 
DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
 /*
  * Exploit the little endianness of the ARM to do multi-byte transfers
  * per device read. This can perform over twice as quickly as individual
@@ -93,7 +91,7 @@ static void nand_davinci_read_buf(struct mtd_info *mtd, 
uint8_t *buf, int len)
 
/* copy aligned data */
while (len = 4) {
-   *(u32 *)buf = readl(nand);
+   *(u32 *)buf = __raw_readl(nand);
buf += 4;
len -= 4;
}
@@ -138,7 +136,7 @@ static void nand_davinci_write_buf(struct mtd_info *mtd, 
const uint8_t *buf,
 
/* copy aligned data */
while (len = 4) {
-   writel(*(u32 *)buf, nand);
+   __raw_writel(*(u32 *)buf, nand);
buf += 4;
len -= 4;
}
@@ -156,7 +154,8 @@ static void nand_davinci_write_buf(struct mtd_info *mtd, 
const uint8_t *buf,
}
 }
 
-static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int 
ctrl)
+static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
+   unsigned int ctrl)
 {
struct  nand_chip *this = mtd-priv;
u_int32_t   IO_ADDR_W = (u_int32_t)this-IO_ADDR_W;
@@ -164,9 +163,9 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, 
int cmd, unsigned int c
if (ctrl  NAND_CTRL_CHANGE) {
IO_ADDR_W = ~(MASK_ALE|MASK_CLE);
 
-   if ( ctrl  NAND_CLE )
+   if (ctrl  NAND_CLE)
IO_ADDR_W |= MASK_CLE;
-   if ( ctrl  NAND_ALE )
+   if (ctrl  NAND_ALE)
IO_ADDR_W |= MASK_ALE;
this-IO_ADDR_W = (void __iomem *) IO_ADDR_W;
}
@@ -181,24 +180,26 @@ static void nand_davinci_enable_hwecc(struct mtd_info 
*mtd, int mode)
 {
u_int32_t   val;
 
-   (void)readl((emif_regs-NANDFECC[CONFIG_SYS_NAND_CS - 2]));
+   (void)__raw_readl((davinci_emif_regs-nandfecc[
+   CONFIG_SYS_NAND_CS - 2]));
 
-   val = readl(emif_regs-NANDFCR);
+   val = __raw_readl(davinci_emif_regs-nandfcr);
val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
-   writel(val, emif_regs-NANDFCR);
+   __raw_writel(val, davinci_emif_regs-nandfcr);
 }
 
 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
 {
u_int32_t   ecc = 0;
 
-   ecc = readl((emif_regs-NANDFECC[region - 1]));
+   ecc = __raw_readl((davinci_emif_regs-nandfecc[region - 1]));
 
-   return(ecc);
+   return ecc;
 }
 
-static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, 
u_char *ecc_code)
+static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+   u_char *ecc_code)
 {
u_int32_t   tmp;
const int region = 1;
@@ -232,7 +233,8 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, 
const u_char *dat, u
return 0;
 }
 
-static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char 
*read_ecc, u_char *calc_ecc)
+static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
+   u_char *read_ecc, u_char *calc_ecc)
 {
struct nand_chip *this = mtd-priv;
u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1]  8) |
@@ -268,7 +270,7 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, 
u_char *dat, u_char *
return -1;
}
}
-   return(0);
+   return 0;
 }
 #endif /* CONFIG_SYS_NAND_HW_ECC */
 
@@ -315,15 +317,15 @@ static void nand_davinci_4bit_enable_hwecc(struct 
mtd_info *mtd,

Re: [U-Boot] [PATCH v2 1/1] TI: Davinci: NAND Driver Cleanup

2010-03-17 Thread Chemparathy, Cyril

Hi Nick,

 I didn't check, but I would assume checkpatch would complain about the
 spaces that have crept in here?

Interestingly checkpatch complains only if it finds 8 or more spaces at the 
beginning of the line (below).  For some reason, vim cindent inserted 7 spaces 
in there, and that kept checkpatch from complaining.

...
# at the beginning of a line any tabs must come first and anything
# more than 8 must use tabs.
if ($rawline =~ /^\+\s* \t\s*\S/ ||
$rawline =~ /^\+\s*\s*/) {
my $herevet = $here\n . cat_vet($rawline) . \n;
ERROR(code indent should use tabs where possible\n . 
$herevet);
}
...

 If you haven't already done so, it would be a good idea to run
 checkpatch to check for any other formatting violations.

Thanks, resubmitted.

Regards
Cyril.

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Re: [U-Boot] cross compiling fw_printenv on big endian

2010-03-17 Thread Joakim Tjernlund



Wolfgang Denk w...@denx.de wrote on 2010/03/17 12:57:31:

 Dear Joakim Tjernlund,

 In message OFF4AB0804.BE309218-ONC12576E9.003A69DF-C12576E9.
 003b4...@transmode.se you wrote:
 
  hmm, I recently discovered that normal user space headers always define
  both __LITTLE_ENDIAN and __BIG_ENDIAN so therefore a
  # ifdef __LITTLE_ENDIAN
  #  define DO_CRC(x) crc = tab[(crc ^ (x))  255] ^ (crc  8)
  # else
  #  define DO_CRC(x) crc = tab[((crc  24) ^ (x))  255] ^ (crc  8)
  # endif
 
  Wont work. One have to use
   #if __BYTE_ORDER == __LITTLE_ENDIAN
  instead.

 Wenn...


 Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se


 Looks as if this were your very own commit. Do you have a fix in the
 works?

I know, but I don't have anything ATM. I am too busy debugging serious
customer problems.

 Jocke

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[U-Boot] Uboot debugging clarification!

2010-03-17 Thread Ramalingam C

Hi!

I am working on iMX515 processor in our project. Our evaluation board is 
iMX51EVK. We are using the uboot. 

For our board we have designed the NAND as storage device! But for our 
NAND chip we dont have the Advanced toolkit (freescale s/w) support! So we 

have to load the uboot binary to DDR2 through JTAG emulator and boot the 
uboot!.

When we are trying this on iMX51EVK board by removing the SD card, control 

is going to a infinite loop. The same binary is working if we store in the 

SD card of EVK board and boot!
If we get the uboot running then we can store the uboot to NAND and 
proceed with our testing!

It will be really helpful if you can help us in modifying the uboot such a 
way that it will boot from 
DDR2 itself.


Thanks  Regards,
Ramalingam C.

Larsen  Toubro Ltd,
Embedded System  Software (EmSyS),
Mysore Complex, KIADB Industrial Area,
Hebbal-Hootagalli,
Mysore, Karnataka, 
India - 570018.

Mobile : +91 9611417479
Mail : ramalinga...@lntemsys.com

LT EmSyS Proprietary LT EmSyS Confidential LT EmSyS Internal Use LT 
EmSyS General Business

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Re: [U-Boot] EABI 4.2

2010-03-17 Thread Praveen G K

On Wed, Mar 17, 2010 at 2:48 AM, Simon Kagstrom
simon.kagst...@netinsight.net wrote:
 (Sorry if this has already been taken up, I've not been following the
 discussion closely)

 On Thu, 11 Mar 2010 11:11:09 +0100
 Martin Krause martin.kra...@tqs.de wrote:

  Does this mean, my toolchain is broken? I use ELDK4.2 for ARM.
 
  I belive so, how many bytes is in dirent.namelen? alloca can not

 I compiled the original code with VLA with ELDK4.1 and there
 everything works. And also the '__builtin_alloca' Version works
 with ELDK4.1.

 I had a similar problem a few months ago, which turned out to be a
 stack alignment issue:

  http://www.mail-archive.com/u-boot@lists.denx.de/msg23202.html

 the behavior was pretty similar, with code built with some compilers
 working (by chance) and some others breaking.

Great! This does work when added to cpu/arm1176/start.S
Is there any specific reason why this was not added to the arm11 stream?

 (The patch above is in U-boot since november something I think)

 // Simon

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Re: [U-Boot] cross compiling fw_printenv on big endian

2010-03-17 Thread Jeff Angielski

Joakim Tjernlund wrote:
 
 Wolfgang Denk w...@denx.de wrote on 2010/03/17 12:57:31:
 Dear Joakim Tjernlund,

 In message OFF4AB0804.BE309218-ONC12576E9.003A69DF-C12576E9.
 003b4...@transmode.se you wrote:
 hmm, I recently discovered that normal user space headers always define
 both __LITTLE_ENDIAN and __BIG_ENDIAN so therefore a
 # ifdef __LITTLE_ENDIAN
 #  define DO_CRC(x) crc = tab[(crc ^ (x))  255] ^ (crc  8)
 # else
 #  define DO_CRC(x) crc = tab[((crc  24) ^ (x))  255] ^ (crc  8)
 # endif

 Wont work. One have to use
  #if __BYTE_ORDER == __LITTLE_ENDIAN
 instead.
 Wenn...
 
 Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se


 Looks as if this were your very own commit. Do you have a fix in the
 works?
 
 I know, but I don't have anything ATM. I am too busy debugging serious
 customer problems.
 
  Jocke

This appears to work for me on my big endian PowerPC target.  Perhaps 
somebody with a little endian target can verify it does not break their 
env tools.

diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c
index 468b397..27335a3 100644
--- a/lib_generic/crc32.c
+++ b/lib_generic/crc32.c
@@ -163,7 +163,7 @@ const uint32_t * ZEXPORT get_crc_table()
  #endif

  /* 
= */
-# ifdef __LITTLE_ENDIAN
+# if __BYTE_ORDER == __LITTLE_ENDIAN
  #  define DO_CRC(x) crc = tab[(crc ^ (x))  255] ^ (crc  8)
  # else
  #  define DO_CRC(x) crc = tab[((crc  24) ^ (x))  255] ^ (crc  8)



Jeff Angielski
The PTR Group
www.theptrgroup.com
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Re: [U-Boot] EABI 4.2

2010-03-17 Thread Simon Kagstrom

On Wed, 17 Mar 2010 09:53:36 -0500
Praveen G K praveen...@gmail.com wrote:

  I had a similar problem a few months ago, which turned out to be a
  stack alignment issue:
 
   http://www.mail-archive.com/u-boot@lists.denx.de/msg23202.html
 
  the behavior was pretty similar, with code built with some compilers
  working (by chance) and some others breaking.
 
 Great! This does work when added to cpu/arm1176/start.S
 Is there any specific reason why this was not added to the arm11 stream?

Well, none other than that I didn't realise it affected other platforms
as well. Looking at the tip, it seems like pretty much all ARM
platforms are susceptible to this issue. So a mass-fix would probably
be in place.

// Simon
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[U-Boot] u-boot stack overwrites end ramdisk

2010-03-17 Thread Norbert van Bolhuis


before I send a patch or whatsoever I'll explain what's wrong first,
maybe I overlook something.

I'm using u-boot v2008.10, customized for our PPC MPC8313 based board.
When booting a kernel (including ramdisk and dtb) space for cmdline
and board info is reserved (by arch_lmb_reserve-lmb_reserve) in unused
memory, unused as in far enough below the current stack ptr.
far enough is implemented here as stack-ptr minus 1k.
Btw. arch_lmb_reserve is called from do_bootm-bootm_start.

In my case the 1k hard-coded in arch_lmb_reserve isn't enough. This
is because a little later that same do_bootm calls 
bootm_load_os-gunzip-inflate
to decompress the linux kernel. In my case inflate alone already uses
1328 bytes of stack space, this is more than the stack-usage of
bootm_start and arch_lmb_reserve together (40 + 32 bytes) + 1k.

Again a little later do_bootm calls 
do_bootm_linux-boot_body_linux-boot_ramdisk_high.
The ramdisk address in memory (aligned on 0x1000 boundary) is determined here,
boot_ramdisk_high calls lmb_alloc_base and it places the ramdisk as close to 
and below
the arch_lmb_reserve stack-ptr minus 1k.


This is what happens:

bootargs=mem=252M
initrd_high=0x0fc0
autoload=no
ethact=TSEC0
.
.
.
 
## Booting kernel from Legacy Image at 2020 ...
Image Name:   Linux-2.6.28
Created:  2010-03-12   9:06:20 UTC
Image Type:   PowerPC Linux Kernel Image (gzip compressed)
Data Size:1459866 Bytes =  1.4 MB
Load Address: 
Entry Point:  
Version:  0x01003120 (16789792)
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 2050 ...
Image Name:   uboot initramfs
Created:  2010-03-12  10:17:54 UTC
Image Type:   PowerPC Linux RAMDisk Image (gzip compressed)
Data Size:2411044 Bytes =  2.3 MB
Load Address: 
Entry Point:  
Version:  0x01003120 (16789792)
Verifying Checksum ... OK
## Flattened Device Tree blob at 204e
Booting using the fdt blob at 0x204e
Uncompressing Kernel Image ... OK
Loading Ramdisk to 0f8c, end 0fb0ca24 ... OK
Loading Device Tree to 00ffa000, end 00fff593 ... OK
.
.
.
checking if image is initramfs...it isn't (invalid compressed format (err=1)); 
looks like an initrd
.
.
.
RAMDISK: Compressed image found at block 0
RAMDISK: ran out of compressed data
invalid compressed format (err=1)
List of all partitions:
1f001792 mtdblock0 (driver?)
1f01 128 mtdblock1 (driver?)
1f02 128 mtdblock2 (driver?)
1f032944 mtdblock3 (driver?)
1f04 128 mtdblock4 (driver?)
1f054096 mtdblock5 (driver?)
1f062944 mtdblock6 (driver?)
1f07 128 mtdblock7 (driver?)
1f084096 mtdblock8 (driver?)
1f094096 mtdblock9 (driver?)
1f0a2048 mtdblock10 (driver?)
1f0b4096 mtdblock11 (driver?)
1f0c2048 mtdblock12 (driver?)
1f0d8192 mtdblock13 (driver?)
1f0e   65536 mtdblock14 (driver?)
1f0f  159744 mtdblock15 (driver?)
No filesystem could mount root, tried:  iso9660
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(1,0)
Rebooting in 180 seconds..



The lowest used stack address by u-boot was 0x0fb0c370. This overwrites
the end of the ramdisk (which ends at 0fb0ca24)

Depending of the rate of compression of the ramdisk and the env setting
initrd_high and how aligning to 0x1000 turns out this problem does
or does not occur.

So, how about raising the 1k space to 8k, that seems safe enough ?

---
N. van Bolhuis.

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Re: [U-Boot] cross compiling fw_printenv on big endian

2010-03-17 Thread Joakim Tjernlund

Jeff Angielski j...@theptrgroup.com wrote on 2010/03/17 16:10:50:

 Joakim Tjernlund wrote:
 
  Wolfgang Denk w...@denx.de wrote on 2010/03/17 12:57:31:
  Dear Joakim Tjernlund,
 
  In message OFF4AB0804.BE309218-ONC12576E9.003A69DF-C12576E9.
  003b4...@transmode.se you wrote:
  hmm, I recently discovered that normal user space headers always define
  both __LITTLE_ENDIAN and __BIG_ENDIAN so therefore a
  # ifdef __LITTLE_ENDIAN
  #  define DO_CRC(x) crc = tab[(crc ^ (x))  255] ^ (crc  8)
  # else
  #  define DO_CRC(x) crc = tab[((crc  24) ^ (x))  255] ^ (crc  8)
  # endif
 
  Wont work. One have to use
   #if __BYTE_ORDER == __LITTLE_ENDIAN
  instead.
  Wenn...
 
  Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
 
 
  Looks as if this were your very own commit. Do you have a fix in the
  works?
 
  I know, but I don't have anything ATM. I am too busy debugging serious
  customer problems.
 
   Jocke

 This appears to work for me on my big endian PowerPC target.  Perhaps
 somebody with a little endian target can verify it does not break their
 env tools.

 diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c
 index 468b397..27335a3 100644
 --- a/lib_generic/crc32.c
 +++ b/lib_generic/crc32.c
 @@ -163,7 +163,7 @@ const uint32_t * ZEXPORT get_crc_table()
   #endif

   /*
 = */
 -# ifdef __LITTLE_ENDIAN
 +# if __BYTE_ORDER == __LITTLE_ENDIAN
   #  define DO_CRC(x) crc = tab[(crc ^ (x))  255] ^ (crc  8)
   # else
   #  define DO_CRC(x) crc = tab[((crc  24) ^ (x))  255] ^ (crc  8)


I THINK this will work. Looking at include/linux/byteorder/big_endian.h it says:
#define __BYTE_ORDER__BIG_ENDIAN
so it seems like the __BYTE_ORDER logic is in place in u-boot.
Someone with a LE CPU should confirm this.

Mind doing a proper patch?

   Jocke

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Re: [U-Boot] Instructions in TEXT section can not load data from other section

2010-03-17 Thread Scott Wood

On Wed, Mar 17, 2010 at 09:49:15AM +, jrjr wrote:
 
 Because I want to use LED controlled by OR3 to debug the code,so I don't want 
 to clear OR0.

It's temporary; you can use bank 3 after BRn/ORn are set to their final
values (confusingly named PRELIM) in cpu_init_f().

-Scott
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Re: [U-Boot] Uboot debugging clarification!

Dear Ramalingam C,

In message 
of04b24567.651e9130-on652576e9.004fb606-652576e9.004ff...@lntemsys.com you 
wrote:

 I am working on iMX515 processor in our project. Our evaluation board is 
 iMX51EVK. We are using the uboot. 
 
 For our board we have designed the NAND as storage device! But for our 
 NAND chip we dont have the Advanced toolkit (freescale s/w) support! So we 
 have to load the uboot binary to DDR2 through JTAG emulator and boot the 
 uboot!.

Is! there! any! specific! reason! for! ending! evary! sentence! in!
an! exclamation! mark!?   Why are you shouting at us?


 When we are trying this on iMX51EVK board by removing the SD card, control 
 is going to a infinite loop. The same binary is working if we store in the 
 SD card of EVK board and boot!

Then you obviously are doing something wrong or missing some
initialization, or both.

 If we get the uboot running then we can store the uboot to NAND and 
 proceed with our testing!

Please see http://www.catb.org/%7eesr/faqs/smart-questions.html#urgent
There is a number of companies providing commercial support for
U-Boot, so if your project is stuck you might consider contacting
these.

 It will be really helpful if you can help us in modifying the uboot such a 
 way that it will boot from 
 DDR2 itself.

You cannot boot from DDR2, because the DDR2 needs to be initialized
first, and to do so so need information (and eventually code) from
the boot device.


Best regards,

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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only the losers who have glorious victories.
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[U-Boot] uboot on microblaze, compilation error

2010-03-17 Thread Horst Gall

Hi,

I try to compile an actual version of u-boot for xilinx microblaze.
The linker ends with the error-message:

... mb-ld.real:u-boot.lds:1: parse error

In u-boot main-directory I found the file 'u-boot.lds':

OUTPUT_ARCH(1)
ENTRY(_start)
...
cpu/1/start.o (.text)
...

When I change the 1 to microblaze it works:

OUTPUT_ARCH(microblaze)
ENTRY(_start)
...
cpu/microblaze/start.o (.text)
...


After make ...config my modification is overwritten.
How can I fix this problem?


Best regards
Horst Gall
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Re: [U-Boot] uboot on microblaze, compilation error

Dear Horst Gall,

In message 001701cac601$5a380c50$c801a...@xeon you wrote:
 
 I try to compile an actual version of u-boot for xilinx microblaze.
 The linker ends with the error-message:
 
 ... mb-ld.real:u-boot.lds:1: parse error
 
 In u-boot main-directory I found the file 'u-boot.lds':
 
 OUTPUT_ARCH(1)
 ENTRY(_start)
 ...
 cpu/1/start.o (.text)
 ...
 
 When I change the 1 to microblaze it works:

The linker script is run through the C preprocessor. Obviously your
toolchain auto-defines microblaze as 1.

 How can I fix this problem?

Fix your toolchain. microblaze is not a reserved identified, and
your toolchain is not supposed to mess with it.

Best regards,

Wolfgang Denk

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] cross compiling fw_printenv on big endian

2010-03-17 Thread Jeff Angielski


Joakim Tjernlund wrote:

Jeff Angielski j...@theptrgroup.com wrote on 2010/03/17 16:10:50:

Joakim Tjernlund wrote:

Wolfgang Denk w...@denx.de wrote on 2010/03/17 12:57:31:

Dear Joakim Tjernlund,

In message OFF4AB0804.BE309218-ONC12576E9.003A69DF-C12576E9.
003b4...@transmode.se you wrote:

hmm, I recently discovered that normal user space headers always define
both __LITTLE_ENDIAN and __BIG_ENDIAN so therefore a
# ifdef __LITTLE_ENDIAN
#  define DO_CRC(x) crc = tab[(crc ^ (x))  255] ^ (crc  8)
# else
#  define DO_CRC(x) crc = tab[((crc  24) ^ (x))  255] ^ (crc  8)
# endif

Wont work. One have to use
 #if __BYTE_ORDER == __LITTLE_ENDIAN
instead.

Wenn...
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se


Looks as if this were your very own commit. Do you have a fix in the
works?

I know, but I don't have anything ATM. I am too busy debugging serious
customer problems.

 Jocke

This appears to work for me on my big endian PowerPC target.  Perhaps
somebody with a little endian target can verify it does not break their
env tools.

diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c
index 468b397..27335a3 100644
--- a/lib_generic/crc32.c
+++ b/lib_generic/crc32.c
@@ -163,7 +163,7 @@ const uint32_t * ZEXPORT get_crc_table()
  #endif

  /*
= */
-# ifdef __LITTLE_ENDIAN
+# if __BYTE_ORDER == __LITTLE_ENDIAN
  #  define DO_CRC(x) crc = tab[(crc ^ (x))  255] ^ (crc  8)
  # else
  #  define DO_CRC(x) crc = tab[((crc  24) ^ (x))  255] ^ (crc  8)



I THINK this will work. Looking at include/linux/byteorder/big_endian.h it says:
#define __BYTE_ORDER__BIG_ENDIAN
so it seems like the __BYTE_ORDER logic is in place in u-boot.
Someone with a LE CPU should confirm this.

Mind doing a proper patch?



See attached file.




--
Jeff Angielski
The PTR Group
www.theptrgroup.com
From 45c007e857990bd01f13c5dbbe61e6f9fc75f390 Mon Sep 17 00:00:00 2001
From: Jeff Angielski j...@theptrgroup.com
Date: Wed, 17 Mar 2010 15:09:26 -0400
Subject: [PATCH] env: fix endian ordering in crc table

The crc table was being built as little endian for big endian
targets.  This would cause fw_printenv to always fail with
Warning: Bad CRC, using default environment messages.
Signed-off-by: Jeff Angielski j...@theptrgroup.com
---
 lib_generic/crc32.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c
index 468b397..27335a3 100644
--- a/lib_generic/crc32.c
+++ b/lib_generic/crc32.c
@@ -163,7 +163,7 @@ const uint32_t * ZEXPORT get_crc_table()
 #endif
 
 /* = */
-# ifdef __LITTLE_ENDIAN
+# if __BYTE_ORDER == __LITTLE_ENDIAN
 #  define DO_CRC(x) crc = tab[(crc ^ (x))  255] ^ (crc  8)
 # else
 #  define DO_CRC(x) crc = tab[((crc  24) ^ (x))  255] ^ (crc  8)
-- 
1.6.3.3

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Re: [U-Boot] at91sam9g45ekes SDHC/MMC

2010-03-17 Thread Henry Súcart

Hi Albin,

Thanks for all the help :).

After doing some research i found out that I the configuration I need is
!CONFIG_ATMEL_MCI1 since I the interface I'm trying to use is MCI0. When I
try it out it does seem like it's trying to read from it (it immediately
returns with an -EIO if I remove the SD card) and I guess the problem is
with the response.

In the for loop in sd_init_card() it should break out of the loop if either
there is a return value for mmc_acmd() (which only happens when there's an
error) or when (resp[0]  0x8000) which I guess is that we read
something successfully. When I run mmc init 0 it never breaks out of that
loop. I'm guessing that the response should be something like 0x8,
then. Am I right? The responses I'm getting are:

mmc: CMD55 0x0 (flags 0x1040)
mmc: status 0x0c25
mmc: response: 0120
mmc: CMD41 0x10 (flags 0x41)
mmc: status 0x0c040025
mmc: response: 00ff8000

What does this number mean? Am I right in my assumption?

Thanks,
Henry

On Tue, Mar 16, 2010 at 6:08 PM, Henry Súcart henry.suc...@gmail.comwrote:

 I put the printf you asked for in sd_init_card, right after the for loop.
 Here's the output:

 With #define CONFIG_ATMEL_MCI1  1


 U-Boot mmc init 0
 mmc: setting clock 15 Hz, block size 512

 mmc: clock 15 too low; setting CLKDIV to 255
 mmc: CMD0 0x0 (flags 0x0)
 mmc: status 0x0c25

 mmc: CMD0 0x0 (flags 0x100)
 mmc: status 0x0c25

 mmc: CMD55 0x0 (flags 0x1040)
 mmc: status 0x0c25
 mmc: response: 

 HJS: MMCI_CR = 0
 HJS: sd_init_card() mmc_acmd after for loop. ret: -19, resp[0] = 0x6B200020

 mmc: CMD0 0x0 (flags 0x0)
 mmc: status 0x0c25

 mmc: CMD0 0x0 (flags 0x100)
 mmc: status 0x0c25

 mmc: CMD1 0x10 (flags 0x841)
 mmc: status 0x0c25
 mmc: response: 


 ...This keeps going for a while and at the end...

 mmc: CMD1 0x10 (flags 0x841)
 mmc: status 0x0c25
 mmc: response: 
 No MMC card found

 With #define CONFIG_ATMEL_MCI1  0

 U-Boot mmc init 0
 mmc: setting clock 15 Hz, block size 512

 mmc: clock 15 too low; setting CLKDIV to 255
 mmc: CMD0 0x0 (flags 0x0)
 mmc: status 0x0c25

 mmc: CMD0 0x0 (flags 0x100)
 mmc: status 0x0c25

 mmc: CMD55 0x0 (flags 0x1040)
 mmc: status 0x0c25
 mmc: response: 

 HJS: MMCI_CR = 0
 HJS: sd_init_card() mmc_acmd after for loop. ret: -19, resp[0] = 0x6B200020

 mmc: CMD0 0x0 (flags 0x0)
 mmc: status 0x0c25

 mmc: CMD0 0x0 (flags 0x100)
 mmc: status 0x0c25

 mmc: CMD1 0x10 (flags 0x841)
 mmc: status 0x0c25
 mmc: response: 
 mmc: CMD1 0x10 (flags 0x841)
 mmc: status 0x0c25
 mmc: response: 
 mmc: CMD1 0x10 (flags 0x841)
 mmc: status 0x0c25
 mmc: response: 
 mmc: CMD1 0x10 (flags 0x841)
 mmc: status 0x0c25
 mmc: response: 
 mmc: CMD1 0x10 (flags 0x841)
 mmc: status 0x0c25
 mmc: response: 

 ...This keeps going for a while and at the end...

 mmc: CMD1 0x10 (flags 0x841)
 mmc: status 0x0c25
 mmc: response: 
 No MMC card found

 If i take out the #define CONFIG_ATMEL_MCI1


 U-Boot mmc init 0
 mmc: setting clock 15 Hz, block size 512

 mmc: clock 15 too low; setting CLKDIV to 255
 mmc: CMD0 0x0 (flags 0x0)
 mmc: status 0x0c25

 mmc: CMD0 0x0 (flags 0x100)
 mmc: status 0x0c25

 mmc: CMD55 0x0 (flags 0x1040)
 mmc: status 0x0c25
 mmc: response: 0120
 mmc: CMD41 0x10 (flags 0x41)
 mmc: status 0x0c040025
 mmc: response: 00ff8000
 mmc: CMD55 0x0 (flags 0x1040)
 mmc: status 0x0c25
 mmc: response: 0120
 mmc: CMD41 0x10 (flags 0x41)
 mmc: status 0x0c040025
 mmc: response: 00ff8000

 ... Goes on for a while...

 HJS: MMCI_CR = 0
 HJS: sd_init_card() mmc_acmd for loop ret: -110, resp[0] = 0x00FF8000

 mmc: CMD0 0x0 (flags 0x0)
 mmc: status 0x0c25

 mmc: CMD0 0x0 (flags 0x100)
 mmc: status 0x0c25

 mmc: CMD1 0x10 (flags 0x841)
 mmc: status 0x0c100025

 mmc: command 1 failed (status: 0x0c100025)
 HJS: error_flags: 0x005B, status  error_flags: 0x0010
 HJS: mmc_init_card() ret = -5
 HJS: mmc_init_card failed
 No MMC card found

 In all of them I used the slot J6. I tried it with J5 too but it did the
 same thing.


 On Tue, Mar 16, 2010 at 4:36 PM, Albin Tonnerre 
 albin.tonne...@free-electrons.com wrote:

 On Tue, 16 Mar 2010 08:30 -0400, Henry Súcart wrote :
  Here's the command I'm using and the output. I put a debugging statement
 in
  sd_init_card() after the for loop (HJS:).
 
  U-Boot mmc init 0
  mmc: clock 15 too low; setting CLKDIV to 255
  HJS: sd_init_card() mmc_acmd for loop finished. ret = -19, resp[0] =
  0x6B200020
  No MMC card found

 Err, well, that's weird. I have to admit I can't even guess whether it's
 trying to read the right slot. Could you please:

 1/ add a #define DEBUG at the top of drivers/mmc/atmel_mci.c
 2/ get the output of mmc init (0 or 1 doesn't matter) for both
 CONFIG_ATMEL_MCI1
 and !CONFIG_ATMEL_MCI1 (with the SD card staying in the

[U-Boot] Can physical flash initramfs cpio address be given to bootm?

2010-03-17 Thread Brian Hutchinson

Can I use the physical flash address of a initramfs with the u-boot
bootm command?  The kernel doesn't appear to like it  see below.

I'm not sure if the problem I've having is a kernel or u-boot issue.
I posted on the ARM linux list too so forgive me if you are on both
lists.

I need a initial ram filesystem and don't want it built into the
kernel so I've built an external initramfs cpio.gz.

I'm currently loading my cpio initramfs into u-boot via tftp and then
providing the initrd= bootarg which works.

I've tried to wrap the cpio with mkimage both with -a 0x0 -e 0x0 and a
RAM address such as -a 0x400 -e 0x400 (the location I tftp the
initramfs to)

With boths types if mkimage's mentioned above, when I do a bootm
0x2008 (physical flash location of kernel)
0x2028 (mkimage of cpio.gz made with -T ramdisk) the cpio is
loaded into ram but the physical
flash address of the initramfs gets passed to kernel via ATAGS and the
kernel doesn't like it:

INITRD: 0x20280040+0x00c8bdb6 extends beyond physical memory - disabling initrd

I thought I saw a patch that allowed initramfs to come from physical
media (flash) but it looks like I currently have to copy the initramfs
to ram right now and provide the initrd= which I would like to get
away from since I don't want to have to touch u-boot env vars every
time the cpio changes.

I don't know if I'm heading in the weeds but my thought were to either
modify kernel to allow initramfs to come from outside external ram
(the patch I mentioned) which would be my NOR flash, or modify my
u-boot so the ATAGS passed to the kernel would include the -a or -e
address from the mkimage header.

How do you all load a initramfs from flash???

I'm using 2.6.28 kernel and u-boot 1.1.6.

Regards,

Brian
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Re: [U-Boot] [PATCH] add new board pm9g45

2010-03-17 Thread RONETIX - Asen Dimov


Hello Wolfgang,

in the message 20100316190012.84ca750...@gemini.denx.de form 
16.03.2010 at 09:00 PM

+#ifdef CONFIG_LCD
+/*
+ * LCD name TX09D50VM1CCA
+ */
+vidinfo_t panel_info = {
+   vl_col: 240,
+   vl_row: 320,
+   vl_clk: 4965000,
+   vl_sync:ATMEL_LCDC_INVLINE_NORMAL |
+   ATMEL_LCDC_INVFRAME_NORMAL,
+   vl_bpix:3,
+   vl_tft: 1,
+   vl_hsync_len:   5,
+   vl_left_margin: 1,
+   vl_right_margin:33,
+   vl_vsync_len:   1,
+   vl_upper_margin:1,
+   vl_lower_margin:0,
+   mmio:   AT91SAM9G45_LCDC_BASE,
+};



This information should not be board-specific. The panel information
is generic and should moved to a separate header file that is not part
of the board code.


  
In the boards (at91sam9263ek and at91sam9m10g45ek, and some more 
at91sam9 based boards) I am looking at, the panel_info is in the board 
specific code.
There are some lcd.c files with panel_info structures: 
drivers/video/mx3fb.c, cpu/pxa/pxafb.c and  cpu/mpc8xx/lcd.c .


Where should be the proper place for panel_info which is somehow 
architecture dependent?


Regards,
Asen




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Re: [U-Boot] Can physical flash initramfs cpio address be given to bootm?

Dear Brian Hutchinson,

In message 3d1967ab1003171233g5dc9cc20me150066bf64f5...@mail.gmail.com you
wrote:
Can I use the physical flash address of a initramfs with the u-boot
bootm command? The kernel doesn't appear to like it see below.

As far as U-Boot is concerned: yes, you can.

In my understanding any sane kernel implementation shoul dbe able to
deal with this.

I'm not sure if the problem I've having is a kernel or u-boot issue.
I posted on the ARM linux list too so forgive me if you are on both
lists.

Indeed ARM is one architecture which is well-known for NOT supporting
such a boot mode - for reasons I still fail to understand.

Patches to fix this have been posted several times on the ARM kernel
list - and been rejected because such a feature is not needed.

I need a initial ram filesystem and don't want it built into the
kernel so I've built an external initramfs cpio.gz.

I understand your situation. You have basicly 3 options:

- accept the additional, useless copy of the file system image to RAM
- convince the ARM maintainers that this is a useful feature
- live with out-of-tree patches like this one:

http://git.denx.de/?p=linux-2.6-denx.git;a=commit;h=4f112fe89c1ca9ad7853304bd93d39aeedbb06f9

Best regards,

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Microsoft Multimedia:
You have nice graphics, sound and animations when the system crashes.
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Re: [U-Boot] Uboot debugging clarification!

2010-03-17 Thread stefano babic

Ramalingam C wrote:
 Hi!
 

Hi Ramalingam,

 When we are trying this on iMX51EVK board by removing the SD card, control 
 
 is going to a infinite loop. The same binary is working if we store in the 
 
 SD card of EVK board and boot!

Which kind of u-boot have you tested ? If you use the u-boot you find on
the actual mainline, you get what you want. You will get a u-boot.imx
image that you can write into the SD card, setting the DDR. After that,
you will able to load a new u-boot image with a jtag debugger into the
RAM because the DDR is already setup.
There is no need of the SD card anymore - until obviously you do not
reboot the system and you need to setup the DDR again.

 If we get the uboot running then we can store the uboot to NAND and 
 proceed with our testing!

u-boot runs on the mx51evk. There is no NAND support because the board
has no NAND at all

 
 It will be really helpful if you can help us in modifying the uboot such a 
 way that it will boot from 
 DDR2 itself.

I do not understand the question. The processor must setup the DDR
before running from RAM. This is what is done with the SD card.
You need only to stop your board after a reset and load your new image
with the jtag debugger. That is it.

Best regargs,
Stefano Babic

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=
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Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: off...@denx.de
=
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[U-Boot] soft_spi.c crash while saveenv

2010-03-17 Thread Horst Gall


Hi Wolfgang,

I used the soft_spi - driver for saving the u-boot-environment.

When I started saveenv u-boot hang - no output.
I located the problem in soft_spi.c in function spi_xfer().
This function writes every byte received from the spi-device to the pointer 
dout.
In case of writing to the spi-device the returned bytes are also written to 
the dout-pointer.


The function spi_flash_cmd() in drivers/mtd/spi/spi_flash.c calls now 
this function with

a NULL-pointer.

I fiexed the problem in soft_spi.c and attached the file.


Best regards
Horst Gall 


soft_spi.c
Description: Binary data
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[U-Boot] Environmentvar. ipaddr - microblaze

2010-03-17 Thread Horst Gall

Hi Wolfgang,

in lib_microblaze/board.c  board_init() the function env_relocate() 
should be called before getenv_IPaddr()
otherwise there is no chance to save an ip-address in the environment (like 
in lib_ppc/board.c).

Best regards
Horst Gall 

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Re: [U-Boot] [PATCH] add new board pm9g45

Dear RONETIX - Asen Dimov,

In message 4ba1363b.7010...@ronetix.at you wrote:

  This information should not be board-specific. The panel information
  is generic and should moved to a separate header file that is not part
  of the board code.
 

 In the boards (at91sam9263ek and at91sam9m10g45ek, and some more 
 at91sam9 based boards) I am looking at, the panel_info is in the board 
 specific code.

Indeed. Patches to clean this up are welcome.

 There are some lcd.c files with panel_info structures: 
 drivers/video/mx3fb.c, cpu/pxa/pxafb.c and  cpu/mpc8xx/lcd.c .
 
 Where should be the proper place for panel_info which is somehow 
 architecture dependent?

I'm not an expert in this area. In Linux there has been discussion to
put this type of information into the device tree. Either in the form
of (new, to be defined) specific bindings, or as EDID data.

I wonder if we could / should do something similar here?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Man is the best computer we can put aboard a spacecraft ...  and  the
only one that can be mass produced with unskilled labor.
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Re: [U-Boot] uboot on microblaze, compilation error

2010-03-17 Thread Mike Frysinger

On Wednesday 17 March 2010 14:36:38 Horst Gall wrote:
 Hi,
 
 I try to compile an actual version of u-boot for xilinx microblaze.
 The linker ends with the error-message:
 
 ... mb-ld.real:u-boot.lds:1: parse error
 
 In u-boot main-directory I found the file 'u-boot.lds':
 
 OUTPUT_ARCH(1)
 ENTRY(_start)
 ...
 cpu/1/start.o (.text)
 ...
 
 When I change the 1 to microblaze it works:
 
 OUTPUT_ARCH(microblaze)
 ENTRY(_start)
 ...
 cpu/microblaze/start.o (.text)
 ...
 
 
 After make ...config my modification is overwritten.
 How can I fix this problem?

add #undef microblaze to the top of board/xilinx/microblaze-generic/u-
boot.lds
-mike


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[U-Boot] [PATCH] env: fix endian ordering in crc table

2010-03-17 Thread Jeff Angielski


The crc table was being built as little endian for big endian
targets.  This would cause fw_printenv to always fail with
Warning: Bad CRC, using default environment messages.

Signed-off-by: Jeff Angielski j...@theptrgroup.com
---
  lib_generic/crc32.c |2 +-
  1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c
index 468b397..27335a3 100644
--- a/lib_generic/crc32.c
+++ b/lib_generic/crc32.c
@@ -163,7 +163,7 @@ const uint32_t * ZEXPORT get_crc_table()
  #endif

  /* 
= */
-# ifdef __LITTLE_ENDIAN
+# if __BYTE_ORDER == __LITTLE_ENDIAN
  #  define DO_CRC(x) crc = tab[(crc ^ (x))  255] ^ (crc  8)
  # else
  #  define DO_CRC(x) crc = tab[((crc  24) ^ (x))  255] ^ (crc  8)
-- 
1.6.3.3

-- 
Jeff Angielski
The PTR Group
www.theptrgroup.com
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Re: [U-Boot] Can physical flash initramfs cpio address be given to bootm?

2010-03-17 Thread Brian Hutchinson

On Wed, Mar 17, 2010 at 4:48 PM, Wolfgang Denk w...@denx.de wrote:
As far as U-Boot is concerned: yes, you can.

In my understanding any sane kernel implementation shoul dbe able to
deal with this.

Thanks Wolfgang! I sure do thank the Lord for your diligence over the
past 10+ years!

Indeed ARM is one architecture which is well-known for NOT supporting
such a boot mode - for reasons I still fail to understand.

Patches to fix this have been posted several times on the ARM kernel
list - and been rejected because such a feature is not needed.

Yes sir, I've seen those posts and the discussion around them; patch
in question being rejected which I didn't understand the grounds for.
You have two options for initramfs, built into the kernel and loaded
external. This method replaces the old way of doing it with a ext2
filesystem and a fake block device so if you need a ramdisk ...
initramfs is the more efficient way to do it (thanks to Linus)
but then I was puzzled as to why I couldn't get this to work and
consulted the ARM kernel archives which left me even more confused
about this not being needed.

I need a initial ram filesystem and don't want it built into the
kernel so I've built an external initramfs cpio.gz.

I understand your situation. You have basicly 3 options:

- accept the additional, useless copy of the file system image to RAM
can't, will not, it just doesn't make sense (at least to me).

- convince the ARM maintainers that this is a useful feature
I don't think I'm worthy of being able to do that. Russell did save
my bacon recently ... I couldn't load my initramfs due to using
discontig mem model and he suggested I switch to sparse mem which
fixed my problem so props to him.

- live with out-of-tree patches like this one:
http://git.denx.de/?p=linux-2.6-denx.git;a=commit;h=4f112fe89c1ca9ad7853304bd93d39aeedbb06f9

Thanks again for checking my sanity (again) and now that I know I'm
not crazy (well mostly) I'll look for a patch that will not make the
kernel balk at locations outside of physical ram.

On a different topic, may I ask what happened to mini_fo in the git
repository? Doesn't look like it has been touched in a long time. I
needed a squashfs + union so I ended up finding patches for a 2.6.30+
kernel on the OpenWRT site and back ported them to my 2.6.28 kernel to
get around iget etc. being removed.

Is there a golden repository of this anymore?

Regards,

Brian
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[U-Boot] [PATCH 01/13] ColdFire: Correct bit definition

Use correct definition for _MASK and _UNMASK. It was combined in
the previous used and causes confusion.

Signed-off-by: TsiChung Liew tsicl...@gmail.com
---
 board/freescale/m54455evb/m54455evb.c |2 +-
 cpu/mcf5227x/cpu_init.c   |   12 ++--
 cpu/mcf52x2/cpu_init.c|   14 ++--
 cpu/mcf532x/cpu_init.c|   12 ++--
 cpu/mcf532x/speed.c   |2 +-
 cpu/mcf5445x/cpu_init.c   |4 +-
 include/asm-m68k/m520x.h  |   89 +-
 include/asm-m68k/m5227x.h |  108 +++
 include/asm-m68k/m5235.h  |4 +-
 include/asm-m68k/m5301x.h |  112 
 include/asm-m68k/m5445x.h |   56 
 11 files changed, 206 insertions(+), 209 deletions(-)

diff --git a/board/freescale/m54455evb/m54455evb.c 
b/board/freescale/m54455evb/m54455evb.c
index 293b5b0..866694f 100644
--- a/board/freescale/m54455evb/m54455evb.c
+++ b/board/freescale/m54455evb/m54455evb.c
@@ -107,7 +107,7 @@ int ide_preinit(void)
 {
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-   gpio-par_fec |= (gpio-par_fec  GPIO_PAR_FEC_FEC1_MASK) | 0x10;
+   gpio-par_fec |= (gpio-par_fec  GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
gpio-par_feci2c |=
(gpio-par_feci2c  0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
   GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c
index e160ee1..d336857 100644
--- a/cpu/mcf5227x/cpu_init.c
+++ b/cpu/mcf5227x/cpu_init.c
@@ -133,19 +133,19 @@ void uart_port_conf(void)
switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio-par_uart =
-   (GPIO_PAR_UART_U0TXD_MASK  GPIO_PAR_UART_U0RXD_MASK);
+   (GPIO_PAR_UART_U0TXD_UNMASK  GPIO_PAR_UART_U0RXD_UNMASK);
gpio-par_uart |=
(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
break;
case 1:
gpio-par_uart =
-   (GPIO_PAR_UART_U1TXD_MASK  GPIO_PAR_UART_U1RXD_MASK);
+   (GPIO_PAR_UART_U1TXD_UNMASK  GPIO_PAR_UART_U1RXD_UNMASK);
gpio-par_uart |=
(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
break;
case 2:
gpio-par_dspi =
-   (GPIO_PAR_DSPI_SIN_MASK  GPIO_PAR_DSPI_SOUT_MASK);
+   (GPIO_PAR_DSPI_SIN_UNMASK  GPIO_PAR_DSPI_SOUT_UNMASK);
gpio-par_dspi =
(GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
break;
@@ -175,11 +175,11 @@ int cfspi_claim_bus(uint bus, uint cs)
 
switch (cs) {
case 0:
-   gpio-par_dspi = ~GPIO_PAR_DSPI_PCS0_MASK;
+   gpio-par_dspi = ~GPIO_PAR_DSPI_PCS0_UNMASK;
gpio-par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
break;
case 2:
-   gpio-par_timer = GPIO_PAR_TIMER_T2IN_MASK;
+   gpio-par_timer = GPIO_PAR_TIMER_T2IN_UNMASK;
gpio-par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
break;
}
@@ -199,7 +199,7 @@ void cfspi_release_bus(uint bus, uint cs)
gpio-par_dspi = ~GPIO_PAR_DSPI_PCS0_PCS0;
break;
case 2:
-   gpio-par_timer = GPIO_PAR_TIMER_T2IN_MASK;
+   gpio-par_timer = GPIO_PAR_TIMER_T2IN_UNMASK;
break;
}
 }
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 5b06930..747c1cf 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -142,29 +142,29 @@ void uart_port_conf(void)
/* Setup Ports: */
switch (CONFIG_SYS_UART_PORT) {
case 0:
-   gpio-par_uart = GPIO_PAR_UART0_MASK;
+   gpio-par_uart = GPIO_PAR_UART0_UNMASK;
gpio-par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
break;
case 1:
-   gpio-par_uart = GPIO_PAR_UART0_MASK;
+   gpio-par_uart = GPIO_PAR_UART0_UNMASK;
gpio-par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
break;
case 2:
 #ifdef CONFIG_SYS_UART2_PRI_GPIO
gpio-par_timer =
-   (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK);
+   (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK);
gpio-par_timer |=
(GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
 #endif
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
gpio-par_feci2c =
-   (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK);
+   (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK);
gpio-par_feci2c |=
(GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
 #endif
 #ifdef

[U-Boot] [PATCH 02/13] ColdFire: Update processors' serial port configuration

Provide parameter passing to uart_port_config(). Update port
configuration - un-mask it before enable the bits.

Signed-off-by: TsiChung Liew tsicl...@gmail.com
---
 cpu/mcf5227x/cpu_init.c   |4 +-
 cpu/mcf523x/cpu_init.c|   26 +-
 cpu/mcf52x2/cpu_init.c|   61 ++---
 cpu/mcf532x/cpu_init.c|   29 ++-
 cpu/mcf5445x/cpu_init.c   |   32 +++---
 cpu/mcf547x_8x/cpu_init.c |4 +-
 include/asm-m68k/immap_5253.h |1 +
 7 files changed, 106 insertions(+), 51 deletions(-)

diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c
index d336857..beb78f5 100644
--- a/cpu/mcf5227x/cpu_init.c
+++ b/cpu/mcf5227x/cpu_init.c
@@ -125,12 +125,12 @@ int cpu_init_r(void)
return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
/* Setup Ports: */
-   switch (CONFIG_SYS_UART_PORT) {
+   switch (port) {
case 0:
gpio-par_uart =
(GPIO_PAR_UART_U0TXD_UNMASK  GPIO_PAR_UART_U0RXD_UNMASK);
diff --git a/cpu/mcf523x/cpu_init.c b/cpu/mcf523x/cpu_init.c
index 3c04fd4..0f299f0 100644
--- a/cpu/mcf523x/cpu_init.c
+++ b/cpu/mcf523x/cpu_init.c
@@ -130,21 +130,32 @@ int cpu_init_r(void)
return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
/* Setup Ports: */
-   switch (CONFIG_SYS_UART_PORT) {
+   switch (port) {
case 0:
-   gpio-par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+   gpio-par_uart = ~(GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+   gpio-par_uart |= (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
break;
case 1:
-   gpio-par_uart =
-   (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
+   gpio-par_uart =
+   ~(GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
+   gpio-par_uart |=
+   (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
break;
case 2:
-   gpio-par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+   gpio-par_uart = ~(GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+   gpio-par_uart |= (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
+   gpio-feci2c =
+   ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
+   gpio-feci2c |=
+   (GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
+#endif
break;
}
 }
@@ -156,7 +167,8 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 
if (setclear) {
gpio-par_feci2c |=
-   (GPIO_PAR_FECI2C_EMDC_FECEMDC | 
GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
+   (GPIO_PAR_FECI2C_EMDC_FECEMDC |
+GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
} else {
gpio-par_feci2c =
~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 747c1cf..170bbfc 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -135,12 +135,12 @@ int cpu_init_r(void)
return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
/* Setup Ports: */
-   switch (CONFIG_SYS_UART_PORT) {
+   switch (port) {
case 0:
gpio-par_uart = GPIO_PAR_UART0_UNMASK;
gpio-par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
@@ -247,15 +247,19 @@ int cpu_init_r(void)
return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
+   volatile u32 *par = (u32 *) MMAP_PAR;
+
/* Setup Ports: */
-   switch (CONFIG_SYS_UART_PORT) {
-   case 0:
-   break;
+   switch (port) {
case 1:
+   *par = 0xFFE7;
+   *par |= 0x0018;
break;
case 2:
+   *par = 0xFFFC;
+   *par = 0x0003;
break;
}
 }
@@ -291,21 +295,26 @@ int cpu_init_r(void)
return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
+   u16 temp;
+
/* Setup Ports: */
-   switch (CONFIG_SYS_UART_PORT) {
+   switch (port) {
case 0:
-   mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
-   MCF_GPIO_PAR_UART_U0RXD);
+   temp = mbar_readShort(MCF_GPIO_PAR_UART)  0xFFF3;
+   temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD);
+   mbar_writeShort(MCF_GPIO_PAR_UART, temp);
break;

[U-Boot] [PATCH 04/13] ColdFire: Relocate vector table - mcf5445x

Newer ColdFire processors family boot from address 0 instead of
0xFFnn_. When the boot flash base chip select is set at new
location instead of 0, an un-predictable error will occur if
there is an vector being trigger and refer it to an invalid
address or the vector table handler is not existed at address
0.

Signed-off-by: TsiChung Liew tsicl...@gmail.com
---
 cpu/mcf5445x/cpu_init.c |9 +
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c
index 00e0ca6..8d51d35 100644
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -28,6 +28,7 @@
 #include common.h
 #include watchdog.h
 #include asm/immap.h
+#include asm/processor.h
 #include asm/rtc.h
 
 #if defined(CONFIG_CMD_NET)
@@ -105,6 +106,14 @@ void cpu_init_f(void)
fbcs-csmr5 = CONFIG_SYS_CS5_MASK;
 #endif
 
+   /*
+* now the flash base address is no longer at 0 (Newer ColdFire family
+* boot at address 0 instead of 0xFFnn_). The vector table must
+* also move to the new location.
+*/
+   if (CONFIG_SYS_CS0_BASE != 0)
+   setvbr(CONFIG_SYS_CS0_BASE);
+
 #ifdef CONFIG_FSL_I2C
gpio-par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
 #endif
-- 
1.6.2.5

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[U-Boot] [PATCH 05/13] ColdFire: Update M5253DEMO configuration file

Fix incorrect default environment for flash erase or protect
range. Change offset from 0 to 0xff80. Change default
ethernet setup.

Signed-off-by: TsiChung Liew tsicl...@gmail.com
---
 include/configs/M5253DEMO.h |   12 ++--
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 5e86e4c..051e194 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -96,10 +96,10 @@
 #  undef CONFIG_DM9000_DEBUG
 
 #  define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
-#  define CONFIG_IPADDR10.82.121.249
-#  define CONFIG_NETMASK   255.255.252.0
-#  define CONFIG_SERVERIP  10.82.120.80
-#  define CONFIG_GATEWAYIP 10.82.123.254
+#  define CONFIG_IPADDR192.168.1.2
+#  define CONFIG_NETMASK   255.255.255.0
+#  define CONFIG_SERVERIP  192.168.1.1
+#  define CONFIG_GATEWAYIP 192.168.1.1
 #  define CONFIG_OVERWRITE_ETHADDR_ONCE
 
 #  define CONFIG_EXTRA_ENV_SETTINGS\
@@ -109,8 +109,8 @@
u-boot=u-boot.bin\0   \
load=tftp ${loadaddr) ${u-boot}\0 \
upd=run load; run prog\0  \
-   prog=prot off 0 2;\
-   era 0 2;  \
+   prog=prot off 0xff80 0xff82;  \
+   era 0xff80 0xff82;\
cp.b ${loadaddr} 0 ${filesize};   \
save\0\

-- 
1.6.2.5

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[U-Boot] [PATCH 06/13] ColdFire: M5271EVB DRAM Bring up issue

Fix proper portsize: The register for portsize is either 00b, 01b,
or 1xb. The value that previous assigned is 32d.
Fix DRAM bring up: insert asm(nop) for every DRAM register setup

Signed-off-by: TsiChung Liew tsicl...@gmail.com
---
 board/freescale/m5271evb/m5271evb.c |   12 ++--
 1 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/board/freescale/m5271evb/m5271evb.c 
b/board/freescale/m5271evb/m5271evb.c
index 5505cc4..446f102 100644
--- a/board/freescale/m5271evb/m5271evb.c
+++ b/board/freescale/m5271evb/m5271evb.c
@@ -47,6 +47,7 @@ phys_size_t initdram (int board_type) {
MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
MCF_GPIO_SDRAM_SDCS_11);
+   asm( nop);
 
/*
 * Check to see if the SDRAM has already been initialized
@@ -55,8 +56,9 @@ phys_size_t initdram (int board_type) {
if (!(mbar_readLong(MCF_SDRAMC_DACR0)  MCF_SDRAMC_DACRn_RE)) {
/* Initialize DRAM Control Register: DCR */
mbar_writeShort(MCF_SDRAMC_DCR,
-   MCF_SDRAMC_DCR_RTIM(0x01)
-   | MCF_SDRAMC_DCR_RC(0x30));
+   MCF_SDRAMC_DCR_RTIM(2)
+   | MCF_SDRAMC_DCR_RC(0x2E));
+   asm( nop);
 
/*
 * Initialize DACR0
@@ -70,15 +72,18 @@ phys_size_t initdram (int board_type) {
| MCF_SDRAMC_DACRn_CASL(1)
| MCF_SDRAMC_DACRn_CBM(3)
| MCF_SDRAMC_DACRn_PS(0));
+   asm( nop);
 
/* Initialize DMR0 */
mbar_writeLong(MCF_SDRAMC_DMR0,
MCF_SDRAMC_DMRn_BAM_16M
| MCF_SDRAMC_DMRn_V);
+   asm( nop);
 
/* Set IP bit in DACR */
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
| MCF_SDRAMC_DACRn_IP);
+   asm( nop);
 
/* Wait at least 20ns to allow banks to precharge */
for (i = 0; i  5; i++)
@@ -86,6 +91,7 @@ phys_size_t initdram (int board_type) {
 
/* Write to this block to initiate precharge */
*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
+   asm( nop);
 
/* Set RE bit in DACR */
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
@@ -98,6 +104,7 @@ phys_size_t initdram (int board_type) {
/* Finish the configuration by issuing the MRS */
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
| MCF_SDRAMC_DACRn_MRS);
+   asm( nop);
 
/*
 * Write to the SDRAM Mode Register A0-A11 = 0x400
@@ -109,6 +116,7 @@ phys_size_t initdram (int board_type) {
 * Burst Length = 1
 */
*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
+   asm( nop);
}
 
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-- 
1.6.2.5

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[U-Boot] [PATCH 08/13] ColdFire: Add CPU compile flag for mcf5301x and mcf532x

Add CPU compile flag -mcpu=53015 in cpu/config.mk

Signed-off-by: TsiChung Liew tsicl...@gmail.com
---
 cpu/mcf532x/config.mk |   12 
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/cpu/mcf532x/config.mk b/cpu/mcf532x/config.mk
index 0cb90ac..b783444 100644
--- a/cpu/mcf532x/config.mk
+++ b/cpu/mcf532x/config.mk
@@ -24,8 +24,20 @@
 #
 
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+
+cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 
's/.*\(configs.*\)/\1/')
+is5301x:=$(shell grep CONFIG_MCF5301x $(TOPDIR)/include/$(cfg))
+is532x:=$(shell grep CONFIG_MCF532x $(TOPDIR)/include/$(cfg))
+
 ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
+
+ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x)))
+PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC
+endif
+ifneq (,$(findstring CONFIG_MCF532x,$(is532x)))
 PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC
+endif
+
 else
 PLATFORM_CPPFLAGS += -m5307 -fPIC
 endif
-- 
1.6.2.5

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[U-Boot] [PATCH 07/13] ColdFire: Update Extra environment Data for M5275EVB

Provide extra environment Data and default network address

Signed-off-by: TsiChung Liew tsicl...@gmail.com
---
 include/configs/M5275EVB.h |   28 +++-
 1 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index b380159..f733a4d 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -121,11 +121,6 @@
 #define CONFIG_SYS_I2C_PINMUX_CLR  (0xFFF0)
 #define CONFIG_SYS_I2C_PINMUX_SET  (0x000F)
 
-#ifdef CONFIG_MCFFEC
-#define CONFIG_ETHADDR 00:06:3b:01:41:55
-#define CONFIG_ETH1ADDR00:0e:0c:bc:e5:60
-#endif
-
 #define CONFIG_SYS_PROMPT  - 
 #define CONFIG_SYS_LONGHELP/* undef to save memory */
 
@@ -145,6 +140,29 @@
 #define CONFIG_SYS_MEMTEST_START   0x400
 #define CONFIG_SYS_MEMTEST_END 0x38
 
+#ifdef CONFIG_MCFFEC
+#  define CONFIG_NET_RETRY_COUNT   5
+#  define CONFIG_ETHADDR   00:06:3b:01:41:55
+#  define CONFIG_ETH1ADDR  00:0e:0c:bc:e5:60
+#  define CONFIG_IPADDR192.162.1.2
+#  define CONFIG_NETMASK   255.255.255.0
+#  define CONFIG_SERVERIP  192.162.1.1
+#  define CONFIG_GATEWAYIP 192.162.1.1
+#  define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* FEC_ENET */
+
+#define CONFIG_EXTRA_ENV_SETTINGS  \
+   netdev=eth0\0 \
+   loadaddr=1\0  \
+   uboot=u-boot.bin\0\
+   load=tftp ${loadaddr} ${uboot}\0  \
+   upd=run load; run prog\0  \
+   prog=prot off ffe0 ffe3;  \
+   era ffe0 ffe3;\
+   cp.b ${loadaddr} ffe0 ${filesize};\
+   save\0\
+   
+
 #define CONFIG_SYS_HZ  1000
 #define CONFIG_SYS_CLK 15000
 
-- 
1.6.2.5

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[U-Boot] [PATCH 09/13] ColdFire: Misc update for M53017

Reside Ethernet buffer descriptors in SRAM instead of DRAM. Add
CONFIG_SYS_TX_ETH_BUFFER in platform configuration file. Update
DRAM control and SRAM control register setting. Update cache
setting where size does not write to proper region.

Signed-off-by: TsiChung Liew tsicl...@gmail.com
Signed-off-by: Jason Jin jason@freescale.com
---
 cpu/mcf532x/start.S |2 +-
 include/configs/M53017EVB.h |6 --
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S
index 5b134aa..5abd944 100644
--- a/cpu/mcf532x/start.S
+++ b/cpu/mcf532x/start.S
@@ -284,7 +284,7 @@ _int_handler:
 icache_enable:
move.l  #0x0100, %d0/* Invalidate cache cmd */
movec   %d0, %CACR  /* Invalidate cache */
-   move.l  #(CONFIG_SYS_SDRAM_BASE + 0xc000 + ((CONFIG_SYS_SDRAM_SIZE  
0x1fe0)  11)), %d0
+   move.l  #(CONFIG_SYS_SDRAM_BASE + 0xc000 + ((CONFIG_SYS_SDRAM_SIZE  
0x1fe0 - 1)  16)), %d0
movec   %d0, %ACR0  /* Enable cache */
 
move.l  #0x8200, %d0/* Setup cache mask */
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 30855bd..c351d41 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -69,6 +69,8 @@
 #  define CONFIG_MII_INIT  1
 #  define CONFIG_SYS_DISCOVER_PHY
 #  define CONFIG_SYS_RX_ETH_BUFFER 8
+#  define CONFIG_SYS_TX_ETH_BUFFER 8
+#  define CONFIG_SYS_FEC_BUF_USE_SRAM
 #  define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #  define CONFIG_HAS_ETH1
 
@@ -166,7 +168,7 @@
  */
 #define CONFIG_SYS_INIT_RAM_ADDR   0x8000
 #define CONFIG_SYS_INIT_RAM_END0x2 /* End of used area in 
internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL   0x21
+#define CONFIG_SYS_INIT_RAM_CTRL   0x221
 #define CONFIG_SYS_GBL_DATA_SIZE   128 /* size in bytes reserved for 
initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - 
CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
@@ -180,7 +182,7 @@
 #define CONFIG_SYS_SDRAM_SIZE  64  /* SDRAM size in MB */
 #define CONFIG_SYS_SDRAM_CFG1  0x43711630
 #define CONFIG_SYS_SDRAM_CFG2  0x5667
-#define CONFIG_SYS_SDRAM_CTRL  0xE1002000
+#define CONFIG_SYS_SDRAM_CTRL  0xE1092000
 #define CONFIG_SYS_SDRAM_EMOD  0x8001
 #define CONFIG_SYS_SDRAM_MODE  0x00CD
 
-- 
1.6.2.5

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[U-Boot] [PATCH 10/13] ColdFire: Fix SDRAM size on M5208evb rev E

The proper SDRAM size is 32MB not 64MB

Signed-off-by: Jingchang Lu b22...@freescale.com
---
 include/configs/M5208EVBE.h |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 32123d2..3cc259f 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -158,7 +158,7 @@
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE  0x4000
-#define CONFIG_SYS_SDRAM_SIZE  64  /* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_SIZE  32  /* SDRAM size in MB */
 #define CONFIG_SYS_SDRAM_CFG1  0x43711630
 #define CONFIG_SYS_SDRAM_CFG2  0x5667
 #define CONFIG_SYS_SDRAM_CTRL  0xE1002000
-- 
1.6.2.5

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[U-Boot] [PATCH 12/13] ColdFire: Fix incorrect M5253DEMO default environment

The flash location is at 0xff80, not 0

Signed-off-by: TsiChung Liew tsicl...@gmail.com
---
 include/configs/M5253DEMO.h |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 2d2e056..1eff44c 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -112,7 +112,7 @@
upd=run load; run prog\0  \
prog=prot off 0xff80 0xff82;  \
era 0xff80 0xff82;\
-   cp.b ${loadaddr} 0 ${filesize};   \
+   cp.b ${loadaddr} 0xff80 ${filesize};  \
save\0\

 #endif
-- 
1.6.2.5

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[U-Boot] [PATCH 11/13] ColdFire: Cache update for all platforms

The CF will call cache functions in lib_m68/cache.c and the
cache settings are defined in platform configuration file.

Signed-off-by: TsiChung Liew tsicl...@gmail.com
---
 cpu/mcf5227x/start.S |  100 ++-
 cpu/mcf523x/start.S  |   75 +-
 cpu/mcf52x2/start.S  |  176 ++--
 cpu/mcf532x/start.S  |   72 +
 cpu/mcf5445x/start.S |  123 ++-
 cpu/mcf547x_8x/start.S   |   83 +---
 include/asm-m68k/cache.h |  210 ++
 include/configs/EB+MCF-EV123.h   |   12 ++
 include/configs/M5208EVBE.h  |   13 +++
 include/configs/M52277EVB.h  |   13 +++
 include/configs/M5235EVB.h   |   12 ++
 include/configs/M5249EVB.h   |   15 +++
 include/configs/M5253DEMO.h  |   15 +++
 include/configs/M5253EVBE.h  |   15 +++
 include/configs/M5271EVB.h   |   14 +++
 include/configs/M5272C3.h|   14 +++
 include/configs/M5275EVB.h   |   14 +++
 include/configs/M5282EVB.h   |   13 +++
 include/configs/M53017EVB.h  |   11 ++
 include/configs/M5329EVB.h   |   11 ++
 include/configs/M5373EVB.h   |   11 ++
 include/configs/M54451EVB.h  |   15 +++
 include/configs/M54455EVB.h  |   17 +++-
 include/configs/M5475EVB.h   |   16 +++
 include/configs/M5485EVB.h   |   16 +++
 include/configs/TASREG.h |   11 ++
 include/configs/astro_mcf5373l.h |   11 ++
 include/configs/cobra5272.h  |   13 +++
 include/configs/idmr.h   |   13 +++
 lib_m68k/cache.c |  123 ++-
 30 files changed, 658 insertions(+), 599 deletions(-)
 create mode 100644 include/asm-m68k/cache.h

diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S
index 0c9c89c..30428f1 100644
--- a/cpu/mcf5227x/start.S
+++ b/cpu/mcf5227x/start.S
@@ -24,16 +24,12 @@
 #include config.h
 #include timestamp.h
 #include version.h
+#include asm/cache.h
 
 #ifndef CONFIG_IDENT_STRING
 #define CONFIG_IDENT_STRING 
 #endif
 
-/* last three long word reserved for cache status */
-#define ICACHE_STATUS  (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
-#define DCACHE_STATUS  (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
-#define CACR_STATUS(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
-
 #define _START _start
 #define _FAULT _fault
 
@@ -378,21 +374,19 @@ _start:
movec   %d0, %RAMBAR1
 #endif
 
+   /* invalidate and disable cache */
+   move.l  #CF_CACR_CINV, %d0  /* Invalidate cache cmd */
+   movec   %d0, %CACR  /* Invalidate cache */
+   move.l  #0, %d0
+   movec   %d0, %ACR0
+   movec   %d0, %ACR1
+
/* initialize general use internal ram */
move.l #0, %d0
move.l #(ICACHE_STATUS), %a1/* icache */
move.l #(DCACHE_STATUS), %a2/* icache */
-   move.l #(CACR_STATUS), %a3  /* CACR */
move.l %d0, (%a1)
move.l %d0, (%a2)
-   move.l %d0, (%a3)
-
-   /* invalidate and disable cache */
-   move.l  #0x0100, %d0/* Invalidate cache cmd */
-   movec   %d0, %CACR  /* Invalidate cache */
-   move.l  #0, %d0
-   movec   %d0, %ACR0
-   movec   %d0, %ACR1
 
/* set stackpointer to end of internal ram to get some stackspace for
   the first c-code */
@@ -510,84 +504,6 @@ _int_handler:
RESTORE_ALL
 
 
/*--*/
-/* cache functions */
-   .globl  icache_enable
-icache_enable:
-   move.l  #0x0120, %d0/* Invalid cache */
-   movec   %d0, %CACR
-
-   move.l  #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0
-   movec   %d0, %ACR0
-
-   move.l  #0x81600610, %d0/* Enable cache */
-   movec   %d0, %CACR
-
-   move.l  #(ICACHE_STATUS), %a1
-   moveq   #1, %d0
-   move.l  %d0, (%a1)
-   rts
-
-   .globl  icache_disable
-icache_disable:
-   move.l  #0x01F0, %d0/* Setup cache mask */
-   movec   %d0, %CACR  /* Invalidate icache */
-   clr.l   %d0
-   movec   %d0, %ACR0
-   movec   %d0, %ACR1
-
-   move.l  #(ICACHE_STATUS), %a1
-   moveq   #0, %d0
-   move.l  %d0, (%a1)
-   rts
-
-   .globl  icache_status
-icache_status:
-   move.l  #(ICACHE_STATUS), %a1
-   move.l  (%a1), %d0
-   rts
-
-   .globl  icache_invalid
-icache_invalid:
-   move.l  #0x80600610, %d0/* Invalidate icache */
-   movec   %d0, %CACR  /* Enable and invalidate cache */
-   rts
-
-   .globl  dcache_enable
-dcache_enable:
-   move.l  #0x0120, %d0/* Invalid cache */
-   movec   %d0, %CACR
-
-   move.l  #0x81300610, %d0
-   movec   %d0, %CACR
-
-   move.l  #(DCACHE_STATUS), %a1
-   moveq   #1, %d0
-   move.l  %d0, (%a1)
-   rts
-
-

[U-Boot] [PATCH 13/13] ColdFire: Fix m54455EVB save environment bug

The ATMEL flash does not have buffer write feature. Assgined
buffer_size = 1, so that when there is a write to the flash
will not use buffer write function.

Signed-off-by: TsiChung Liew tsicl...@gmail.com
---
 board/freescale/m54455evb/m54455evb.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/board/freescale/m54455evb/m54455evb.c 
b/board/freescale/m54455evb/m54455evb.c
index 866694f..2a84514 100644
--- a/board/freescale/m54455evb/m54455evb.c
+++ b/board/freescale/m54455evb/m54455evb.c
@@ -185,7 +185,7 @@ ulong board_flash_get_legacy (ulong base, int banknum, 
flash_info_t * info)
info-flash_id  = 0x0100;
info-portwidth = 1;
info-chipwidth = 1;
-   info-buffer_size   = 32;
+   info-buffer_size   = 1;
info-erase_blk_tout= 16384;
info-write_tout= 2;
info-buffer_write_tout = 5;
-- 
1.6.2.5

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[U-Boot] [PATCH 2/8] Nomadik: move gpio driver to drivers/gpio

The Nomadik GPIO driver will also be used on the U8500 SoC, so move it
out of platform-specific code.

Acked-by: Alessandro Rubini rub...@unipv.it
Acked-by: Michael Brandt michael.bra...@stericsson.com
Signed-off-by: Rabin Vincent rabin.vinc...@stericsson.com
---
 board/st/nhk8815/nhk8815.c |2 +-
 cpu/arm926ejs/nomadik/Makefile |1 -
 drivers/gpio/Makefile  |1 +
 .../nomadik/gpio.c = drivers/gpio/nomadik_gpio.c  |2 +-
 include/configs/nhk8815.h  |7 +--
 .../arch-nomadik/gpio.h = nomadik_gpio.h} |0
 6 files changed, 8 insertions(+), 5 deletions(-)
 rename cpu/arm926ejs/nomadik/gpio.c = drivers/gpio/nomadik_gpio.c (98%)
 rename include/{asm-arm/arch-nomadik/gpio.h = nomadik_gpio.h} (100%)

diff --git a/board/st/nhk8815/nhk8815.c b/board/st/nhk8815/nhk8815.c
index faef810..4f5f94f 100644
--- a/board/st/nhk8815/nhk8815.c
+++ b/board/st/nhk8815/nhk8815.c
@@ -28,7 +28,7 @@
 #include common.h
 #include netdev.h
 #include asm/io.h
-#include asm/arch/gpio.h
+#include nomadik_gpio.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/cpu/arm926ejs/nomadik/Makefile b/cpu/arm926ejs/nomadik/Makefile
index 180db8b..35550d7 100644
--- a/cpu/arm926ejs/nomadik/Makefile
+++ b/cpu/arm926ejs/nomadik/Makefile
@@ -25,7 +25,6 @@ include $(TOPDIR)/config.mk
 
 LIB= $(obj)lib$(SOC).a
 
-COBJS  = gpio.o
 SOBJS  = reset.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index d966082..d84f81e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -28,6 +28,7 @@ LIB   := $(obj)libgpio.a
 COBJS-$(CONFIG_AT91_GPIO)  += at91_gpio.o
 COBJS-$(CONFIG_KIRKWOOD_GPIO)  += kw_gpio.o
 COBJS-$(CONFIG_MX31_GPIO)  += mx31_gpio.o
+COBJS-$(CONFIG_NOMADIK_GPIO)   += nomadik_gpio.o
 COBJS-$(CONFIG_PCA953X)+= pca953x.o
 
 COBJS  := $(COBJS-y)
diff --git a/cpu/arm926ejs/nomadik/gpio.c b/drivers/gpio/nomadik_gpio.c
similarity index 98%
rename from cpu/arm926ejs/nomadik/gpio.c
rename to drivers/gpio/nomadik_gpio.c
index 62a375b..e8a7bca 100644
--- a/cpu/arm926ejs/nomadik/gpio.c
+++ b/drivers/gpio/nomadik_gpio.c
@@ -22,7 +22,7 @@
 
 #include common.h
 #include asm/io.h
-#include asm/arch/gpio.h
+#include nomadik_gpio.h
 
 static unsigned long gpio_base[4] = {
NOMADIK_GPIO0_BASE,
diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h
index 4dd391e..8ba1e5e 100644
--- a/include/configs/nhk8815.h
+++ b/include/configs/nhk8815.h
@@ -99,6 +99,9 @@
 #define CONFIG_SYS_TIMERBASE   0x101E2000
 #define CONFIG_NOMADIK_MTU
 
+/* GPIO */
+#define CONFIG_NOMADIK_GPIO
+
 /* serial port (PL011) configuration */
 #define CONFIG_PL011_SERIAL
 #define CONFIG_CONS_INDEX  1
@@ -110,9 +113,9 @@
 #define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
 #define CONFIG_PL011_CLOCK 4800
 
-/* i2c, for the port extenders (uses gpio.c in board directory) */
+/* i2c, for the port extenders (uses drivers/gpio/nomadik_gpio.c) */
 #ifndef __ASSEMBLY__
-#include asm/arch/gpio.h
+#include nomadik_gpio.h
 #define CONFIG_CMD_I2C
 #define CONFIG_SOFT_I2C
 #define CONFIG_SYS_I2C_SPEED   40
diff --git a/include/asm-arm/arch-nomadik/gpio.h b/include/nomadik_gpio.h
similarity index 100%
rename from include/asm-arm/arch-nomadik/gpio.h
rename to include/nomadik_gpio.h
-- 
1.7.0

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[U-Boot] [PATCH 1/8] Nomadik: move timer code to drivers/misc

The Nomadik MTU driver will also be used on the U8500 SoC, so move it
out of platform-specific code.

Acked-by: Alessandro Rubini rub...@unipv.it
Acked-by: Michael Brandt michael.bra...@stericsson.com
Signed-off-by: Rabin Vincent rabin.vinc...@stericsson.com
---
 cpu/arm926ejs/nomadik/Makefile |2 +-
 drivers/misc/Makefile  |1 +
 .../nomadik/timer.c = drivers/misc/nomadik_mtu.c  |2 +-
 include/configs/nhk8815.h  |1 +
 .../{asm-arm/arch-nomadik/mtu.h = nomadik_mtu.h}  |0
 5 files changed, 4 insertions(+), 2 deletions(-)
 rename cpu/arm926ejs/nomadik/timer.c = drivers/misc/nomadik_mtu.c (98%)
 rename include/{asm-arm/arch-nomadik/mtu.h = nomadik_mtu.h} (100%)

diff --git a/cpu/arm926ejs/nomadik/Makefile b/cpu/arm926ejs/nomadik/Makefile
index 0fc9f2a..180db8b 100644
--- a/cpu/arm926ejs/nomadik/Makefile
+++ b/cpu/arm926ejs/nomadik/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB= $(obj)lib$(SOC).a
 
-COBJS  = timer.o gpio.o
+COBJS  = gpio.o
 SOBJS  = reset.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index f6df60f..5c0c6f3 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -28,6 +28,7 @@ LIB   := $(obj)libmisc.a
 COBJS-$(CONFIG_ALI152X) += ali512x.o
 COBJS-$(CONFIG_DS4510)  += ds4510.o
 COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
+COBJS-$(CONFIG_NOMADIK_MTU) += nomadik_mtu.o
 COBJS-$(CONFIG_NS87308) += ns87308.o
 COBJS-$(CONFIG_STATUS_LED) += status_led.o
 COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
diff --git a/cpu/arm926ejs/nomadik/timer.c b/drivers/misc/nomadik_mtu.c
similarity index 98%
rename from cpu/arm926ejs/nomadik/timer.c
rename to drivers/misc/nomadik_mtu.c
index 1d98ef3..b9c0fb1 100644
--- a/cpu/arm926ejs/nomadik/timer.c
+++ b/drivers/misc/nomadik_mtu.c
@@ -22,7 +22,7 @@
 
 #include common.h
 #include asm/io.h
-#include asm/arch/mtu.h
+#include nomadik_mtu.h
 
 /*
  * The timer is a decrementer, we'll left it free running at 2.4MHz.
diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h
index 2b640dc..4dd391e 100644
--- a/include/configs/nhk8815.h
+++ b/include/configs/nhk8815.h
@@ -97,6 +97,7 @@
 /* timing informazion */
 #define CONFIG_SYS_HZ  1000 /* Mandatory... */
 #define CONFIG_SYS_TIMERBASE   0x101E2000
+#define CONFIG_NOMADIK_MTU
 
 /* serial port (PL011) configuration */
 #define CONFIG_PL011_SERIAL
diff --git a/include/asm-arm/arch-nomadik/mtu.h b/include/nomadik_mtu.h
similarity index 100%
rename from include/asm-arm/arch-nomadik/mtu.h
rename to include/nomadik_mtu.h
-- 
1.7.0

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[U-Boot] [PATCH 0/8] ST-Ericsson Ux500 support

This series adds base support for ST-Ericsson's Ux500 series of Cortex-A9 based
SoCs.  Several peripherals are shared with the Nomadik family, for which
support already exists in U-Boot.

Note: The series must be applied on top of the patch [PATCH V4] Nomadik: fix
reset_timer() posted by Alessandro Rubini on 2009-11-25:
http://lists.denx.de/pipermail/u-boot/2009-November/064800.html
Cc: Alessandro Rubini rub...@unipv.it

Rabin Vincent (8):
  Nomadik: move timer code to drivers/misc
  Nomadik: move gpio driver to drivers/gpio
  nomadik_gpio: get base address from platform code
  nomadik_mtu: support configurable clock rates
  ARM Cortex A8: ifdef code calling lowlevel init
  ux500: add SoC-specific code
  pl01x: add support for Ux500 variant of pl011
  mop500: add board-specific files

 MAINTAINERS|4 +
 MAKEALL|1 +
 Makefile   |3 +
 board/st/nhk8815/nhk8815.c |9 ++-
 board/stericsson/mop500/Makefile   |   54 ++
 board/stericsson/mop500/config.mk  |   23 
 board/stericsson/mop500/mop500.c   |   72 +
 cpu/arm926ejs/nomadik/Makefile |1 -
 cpu/arm_cortexa8/start.S   |4 +-
 cpu/arm_cortexa8/ux500/Makefile|   45 
 .../gpio.h = cpu/arm_cortexa8/ux500/clock.c   |   48 ++---
 .../gpio.h = cpu/arm_cortexa8/ux500/cpu.c |   41 +---
 drivers/gpio/Makefile  |1 +
 .../nomadik/gpio.c = drivers/gpio/nomadik_gpio.c  |   11 +--
 drivers/misc/Makefile  |1 +
 .../nomadik/timer.c = drivers/misc/nomadik_mtu.c  |   24 +++--
 drivers/serial/serial_pl01x.c  |8 ++
 drivers/serial/serial_pl01x.h  |1 +
 include/asm-arm/arch-ux500/clock.h |   72 +
 include/asm-arm/arch-ux500/hardware.h  |   78 ++
 include/configs/mop500.h   |  107 
 include/configs/nhk8815.h  |   11 ++-
 .../arch-nomadik/gpio.h = nomadik_gpio.h} |2 +
 .../{asm-arm/arch-nomadik/mtu.h = nomadik_mtu.h}  |0
 24 files changed, 563 insertions(+), 58 deletions(-)
 create mode 100644 board/stericsson/mop500/Makefile
 create mode 100644 board/stericsson/mop500/config.mk
 create mode 100644 board/stericsson/mop500/mop500.c
 create mode 100644 cpu/arm_cortexa8/ux500/Makefile
 copy include/asm-arm/arch-nomadik/gpio.h = cpu/arm_cortexa8/ux500/clock.c 
(52%)
 copy include/asm-arm/arch-nomadik/gpio.h = cpu/arm_cortexa8/ux500/cpu.c (58%)
 rename cpu/arm926ejs/nomadik/gpio.c = drivers/gpio/nomadik_gpio.c (92%)
 rename cpu/arm926ejs/nomadik/timer.c = drivers/misc/nomadik_mtu.c (81%)
 create mode 100644 include/asm-arm/arch-ux500/clock.h
 create mode 100644 include/asm-arm/arch-ux500/hardware.h
 create mode 100644 include/configs/mop500.h
 rename include/{asm-arm/arch-nomadik/gpio.h = nomadik_gpio.h} (97%)
 rename include/{asm-arm/arch-nomadik/mtu.h = nomadik_mtu.h} (100%)

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Re: [U-Boot] [PATCH 05/13] ColdFire: Update M5253DEMO configuration file

2010-03-17 Thread Ben Warren

TsiChung,

On Wed, Mar 17, 2010 at 6:39 PM, TsiChung Liew tsicl...@gmail.com wrote:

 Fix incorrect default environment for flash erase or protect
 range. Change offset from 0 to 0xff80. Change default
 ethernet setup.

 Signed-off-by: TsiChung Liew tsicl...@gmail.com
 ---
  include/configs/M5253DEMO.h |   12 ++--
  1 files changed, 6 insertions(+), 6 deletions(-)

 diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
 index 5e86e4c..051e194 100644
 --- a/include/configs/M5253DEMO.h
 +++ b/include/configs/M5253DEMO.h
 @@ -96,10 +96,10 @@
  #  undef CONFIG_DM9000_DEBUG

  #  define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
 -#  define CONFIG_IPADDR10.82.121.249
 -#  define CONFIG_NETMASK   255.255.252.0
 -#  define CONFIG_SERVERIP  10.82.120.80
 -#  define CONFIG_GATEWAYIP 10.82.123.254
 +#  define CONFIG_IPADDR192.168.1.2
 +#  define CONFIG_NETMASK   255.255.255.0
 +#  define CONFIG_SERVERIP  192.168.1.1
 +#  define CONFIG_GATEWAYIP 192.168.1.1
  #  define CONFIG_OVERWRITE_ETHADDR_ONCE

 Again, please remove these completely.

  #  define CONFIG_EXTRA_ENV_SETTINGS\
 @@ -109,8 +109,8 @@
u-boot=u-boot.bin\0   \
load=tftp ${loadaddr) ${u-boot}\0 \
upd=run load; run prog\0  \
 -   prog=prot off 0 2;\
 -   era 0 2;  \
 +   prog=prot off 0xff80 0xff82;  \
 +   era 0xff80 0xff82;\
cp.b ${loadaddr} 0 ${filesize};   \
save\0\


 regards,
Ben
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Re: [U-Boot] [PATCH 07/13] ColdFire: Update Extra environment Data for M5275EVB

2010-03-17 Thread Ben Warren

TsiChung,

On Wed, Mar 17, 2010 at 6:39 PM, TsiChung Liew tsicl...@gmail.com wrote:

 Provide extra environment Data and default network address

 Signed-off-by: TsiChung Liew tsicl...@gmail.com
 ---
  include/configs/M5275EVB.h |   28 +++-
  1 files changed, 23 insertions(+), 5 deletions(-)

 diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
 index b380159..f733a4d 100644
 --- a/include/configs/M5275EVB.h
 +++ b/include/configs/M5275EVB.h
 @@ -121,11 +121,6 @@
  #define CONFIG_SYS_I2C_PINMUX_CLR  (0xFFF0)
  #define CONFIG_SYS_I2C_PINMUX_SET  (0x000F)

 -#ifdef CONFIG_MCFFEC
 -#define CONFIG_ETHADDR 00:06:3b:01:41:55
 -#define CONFIG_ETH1ADDR00:0e:0c:bc:e5:60
 -#endif
 -
  #define CONFIG_SYS_PROMPT  - 
  #define CONFIG_SYS_LONGHELP/* undef to save memory */

 @@ -145,6 +140,29 @@
  #define CONFIG_SYS_MEMTEST_START   0x400
  #define CONFIG_SYS_MEMTEST_END 0x38

 +#ifdef CONFIG_MCFFEC
 +#  define CONFIG_NET_RETRY_COUNT   5
 +#  define CONFIG_ETHADDR   00:06:3b:01:41:55
 +#  define CONFIG_ETH1ADDR  00:0e:0c:bc:e5:60
 +#  define CONFIG_IPADDR192.162.1.2
 +#  define CONFIG_NETMASK   255.255.255.0
 +#  define CONFIG_SERVERIP  192.162.1.1
 +#  define CONFIG_GATEWAYIP 192.162.1.1

Please get rid of all default MAC and IP addresses.  MAC addresses need to
be unique, and you're making probably invalid assumptions about the
end-user's network.

 +#  define CONFIG_OVERWRITE_ETHADDR_ONCE
 +#endif /* FEC_ENET */
 +
 +#define CONFIG_EXTRA_ENV_SETTINGS  \
 +   netdev=eth0\0 \
 +   loadaddr=1\0  \
 +   uboot=u-boot.bin\0\
 +   load=tftp ${loadaddr} ${uboot}\0  \
 +   upd=run load; run prog\0  \
 +   prog=prot off ffe0 ffe3;  \
 +   era ffe0 ffe3;\
 +   cp.b ${loadaddr} ffe0 ${filesize};\
 +   save\0\
 +   
 +
  #define CONFIG_SYS_HZ  1000
  #define CONFIG_SYS_CLK 15000

 regards,
Ben
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[U-Boot] [PATCH 4/8] nomadik_mtu: support configurable clock rates

Change the Nomadik MTU driver to get the clock rate and prescaler from
the config file.  Also remove the hardcoded divisors and do the
calculations based on the configured rate.

Acked-by: Alessandro Rubini rub...@unipv.it
Acked-by: Michael Brandt michael.bra...@stericsson.com
Signed-off-by: Rabin Vincent rabin.vinc...@stericsson.com
---
 drivers/misc/nomadik_mtu.c |   22 +-
 include/configs/nhk8815.h  |3 +++
 2 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/drivers/misc/nomadik_mtu.c b/drivers/misc/nomadik_mtu.c
index b9c0fb1..4ec75ad 100644
--- a/drivers/misc/nomadik_mtu.c
+++ b/drivers/misc/nomadik_mtu.c
@@ -22,25 +22,29 @@
 
 #include common.h
 #include asm/io.h
+#include div64.h
 #include nomadik_mtu.h
 
-/*
- * The timer is a decrementer, we'll left it free running at 2.4MHz.
- * We have 2.4 ticks per microsecond and an overflow in almost 30min
- */
-#define TIMER_CLOCK(24 * 100 * 1000)
-#define COUNT_TO_USEC(x)   ((x) * 5 / 12)  /* overflows at 6min */
-#define USEC_TO_COUNT(x)   ((x) * 12 / 5)  /* overflows at 6min */
+#define TIMER_CLOCKCONFIG_NOMADIK_MTU_CLOCK
 #define TICKS_PER_HZ   (TIMER_CLOCK / CONFIG_SYS_HZ)
 #define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
 
 /* macro to read the decrementing 32 bit timer as an increasing count */
 #define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
 
+static unsigned long usec_to_count(unsigned long long usec)
+{
+   unsigned long long count = usec * TIMER_CLOCK;
+
+   do_div(count, 100);
+
+   return count;
+}
+
 /* Configure a free-running, auto-wrap counter with no prescaler */
 int timer_init(void)
 {
-   writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
+   writel(MTU_CRn_ENA | CONFIG_NOMADIK_MTU_PRESCALE | MTU_CRn_32BITS,
   CONFIG_SYS_TIMERBASE + MTU_CR(0));
reset_timer();
return 0;
@@ -73,7 +77,7 @@ void __udelay(unsigned long usec)
ulong ini, end;
 
ini = READ_TIMER();
-   end = ini + USEC_TO_COUNT(usec);
+   end = ini + usec_to_count(usec);
while ((signed)(end - READ_TIMER())  0)
;
 }
diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h
index 8ba1e5e..d52f50c 100644
--- a/include/configs/nhk8815.h
+++ b/include/configs/nhk8815.h
@@ -98,6 +98,9 @@
 #define CONFIG_SYS_HZ  1000 /* Mandatory... */
 #define CONFIG_SYS_TIMERBASE   0x101E2000
 #define CONFIG_NOMADIK_MTU
+/* We have 2.4 ticks per microsecond and an overflow in almost 30min */
+#define CONFIG_NOMADIK_MTU_CLOCK   (24 * 100 * 1000)
+#define CONFIG_NOMADIK_MTU_PRESCALEMTU_CRn_PRESCALE_1
 
 /* GPIO */
 #define CONFIG_NOMADIK_GPIO
-- 
1.7.0

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[U-Boot] [PATCH 6/8] ux500: add SoC-specific code

Add the base SoC code for ST-Ericsson's Ux500 series of Cortex A9 based
SoCs.

Even though this is a Cortex A9, we put it under Cortex A8 to avoid code
duplication, since the CPU specific code can be used unmodified across
the two CPUs.

Acked-by: Michael Brandt michael.bra...@stericsson.com
Signed-off-by: Rabin Vincent rabin.vinc...@stericsson.com
---
 cpu/arm_cortexa8/ux500/Makefile   |   45 +++
 cpu/arm_cortexa8/ux500/clock.c|   56 +++
 cpu/arm_cortexa8/ux500/cpu.c  |   49 
 include/asm-arm/arch-ux500/clock.h|   72 ++
 include/asm-arm/arch-ux500/hardware.h |   78 +
 5 files changed, 300 insertions(+), 0 deletions(-)
 create mode 100644 cpu/arm_cortexa8/ux500/Makefile
 create mode 100644 cpu/arm_cortexa8/ux500/clock.c
 create mode 100644 cpu/arm_cortexa8/ux500/cpu.c
 create mode 100644 include/asm-arm/arch-ux500/clock.h
 create mode 100644 include/asm-arm/arch-ux500/hardware.h

diff --git a/cpu/arm_cortexa8/ux500/Makefile b/cpu/arm_cortexa8/ux500/Makefile
new file mode 100644
index 000..c671010
--- /dev/null
+++ b/cpu/arm_cortexa8/ux500/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB=  $(obj)lib$(SOC).a
+
+COBJS  += clock.o cpu.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:$(obj).depend $(LIB)
+
+$(LIB):$(OBJS)
+   $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/cpu/arm_cortexa8/ux500/clock.c b/cpu/arm_cortexa8/ux500/clock.c
new file mode 100644
index 000..6b67fe8
--- /dev/null
+++ b/cpu/arm_cortexa8/ux500/clock.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2010 ST-Ericsson SA
+ * Author: Rabin Vincent rabin.vinc...@stericsson.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct clkrst {
+   unsigned int pcken;
+   unsigned int pckdis;
+   unsigned int kcken;
+   unsigned int kckdis;
+};
+
+static unsigned int clkrst_base[] = {
+   U8500_CLKRST1_BASE,
+   U8500_CLKRST2_BASE,
+   U8500_CLKRST3_BASE,
+   0,
+   U8500_CLKRST5_BASE,
+   U8500_CLKRST6_BASE,
+   U8500_CLKRST7_BASE,
+};
+
+/* Turn on peripheral clock at PRCC level */
+void u8500_clock_enable(int periph, int kern, int cluster)
+{
+   struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1];
+
+   if (kern != -1)
+   writel(1  kern, clkrst-kcken);
+
+   if (cluster != -1)
+   writel(1  cluster, clkrst-pcken);
+}
diff --git a/cpu/arm_cortexa8/ux500/cpu.c b/cpu/arm_cortexa8/ux500/cpu.c
new file mode 100644
index 000..b3c66fa
--- /dev/null
+++ b/cpu/arm_cortexa8/ux500/cpu.c
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2010 ST-Ericsson SA
+ * Author: Rabin Vincent rabin.vinc...@stericsson.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License

[U-Boot] [PATCH 5/8] ARM Cortex A8: ifdef code calling lowlevel init

Conditionally compile the code calling lowlevel_init, to avoid the
following build error when CONFIG_SKIP_LOWLEVEL_INIT is defined:

  start.S:218: undefined reference to `lowlevel_init'

Acked-by: Michael Brandt michael.bra...@stericsson.com
Signed-off-by: Rabin Vincent rabin.vinc...@stericsson.com
---
 cpu/arm_cortexa8/start.S |4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/cpu/arm_cortexa8/start.S b/cpu/arm_cortexa8/start.S
index 29dae2f..70bfc5d 100644
--- a/cpu/arm_cortexa8/start.S
+++ b/cpu/arm_cortexa8/start.S
@@ -181,7 +181,7 @@ clbss_l:
 
 _start_armboot: .word start_armboot
 
-
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 /*
  *
  * CPU_init_critical registers
@@ -218,6 +218,8 @@ cpu_init_crit:
bl  lowlevel_init   @ go setup pll,mux,memory
mov lr, ip  @ restore link
mov pc, lr  @ back to my caller
+#endif
+
 /*
  *
  *
-- 
1.7.0

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[U-Boot] [PATCH 7/8] pl01x: add support for Ux500 variant of pl011

The Ux500 variants of the pl011 have separate LCRH registers for RX and
TX.  The TX register is at the same offset as the unmodified pl011, so
we need to additionally program only the RX register.

Acked-by: Michael Brandt michael.bra...@stericsson.com
Signed-off-by: Rabin Vincent rabin.vinc...@stericsson.com
---
I have used the style of the surrounding code here.

 drivers/serial/serial_pl01x.c |8 
 drivers/serial/serial_pl01x.h |1 +
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index c645cef..c819f1d 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -144,6 +144,14 @@ int serial_init (void)
IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH,
  (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN));
 
+#ifdef CONFIG_UX500
+   /*
+* On Ux500 variants, also set up the separate LCRH for RX.
+*/
+   IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH_RX,
+ (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN));
+#endif
+
/*
 ** Finally, enable the UART
 */
diff --git a/drivers/serial/serial_pl01x.h b/drivers/serial/serial_pl01x.h
index 5f20fdd..0ff6203 100644
--- a/drivers/serial/serial_pl01x.h
+++ b/drivers/serial/serial_pl01x.h
@@ -93,6 +93,7 @@
  *  PL011 definitions
  *
  */
+#define UART_PL011_LCRH_RX  0x1C
 #define UART_PL011_IBRD 0x24
 #define UART_PL011_FBRD 0x28
 #define UART_PL011_LCRH 0x2C
-- 
1.7.0

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Re: [U-Boot] Uboot debugging clarification!

2010-03-17 Thread Liu Hui-R64343

 -Original Message-
 From: u-boot-boun...@lists.denx.de 
 [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Ramalingam C
 Sent: 2010年3月17日 22:34
 To: U-Boot@lists.denx.de
 Subject: [U-Boot] Uboot debugging clarification!

 Hi!

 I am working on iMX515 processor in our project. Our 
 evaluation board is iMX51EVK. We are using the uboot. 

 For our board we have designed the NAND as storage device! 
 But for our NAND chip we dont have the Advanced toolkit 
 (freescale s/w) support! So we 

 have to load the uboot binary to DDR2 through JTAG emulator 
 and boot the uboot!.

 When we are trying this on iMX51EVK board by removing the SD 
 card, control 

 is going to a infinite loop. 
What kind of ininite loop? Where code place is it?
The same binary is working if we  store in the  
 SD card of EVK board and boot!
 If we get the uboot running then we can store the uboot to 
 NAND and proceed with our testing!

 It will be really helpful if you can help us in modifying the 
 uboot such a way that it will boot from
 DDR2 itself.
You mean boot uboot via JTAG?

 Thanks  Regards,
 Ramalingam C.

 Larsen  Toubro Ltd,
 Embedded System  Software (EmSyS),
 Mysore Complex, KIADB Industrial Area,
 Hebbal-Hootagalli,
 Mysore, Karnataka,
 India - 570018.

 Mobile : +91 9611417479
 Mail : ramalinga...@lntemsys.com

 LT EmSyS Proprietary LT EmSyS Confidential LT EmSyS 
 Internal Use LT EmSyS General Business

 Your attempt may fail, but never fail to make an attempt.. 

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[U-Boot] [PATCH 8/8] mop500: add board-specific files