Re: [PATCH 1/1] cmd/sbi: display new extensions
On Wed, Apr 12, 2023 at 10:38:16AM +0200, Heinrich Schuchardt wrote: > OpenSBI already implements some extensions that are not ratified yet: > > * Debug Console Extension (DBCN) > * System Suspend Extension (SUSP) > * Collaborative Processor Performance Control Extension (CPPC) > > Allow the sbi command to display these. > > Provide the FID definitions of the Debug Console Extension. We can use that > extension for an early debug console driver. > > Signed-off-by: Heinrich Schuchardt > --- > arch/riscv/include/asm/sbi.h | 9 + > cmd/riscv/sbi.c | 3 +++ > 2 files changed, 12 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH] board: starfive: Fixed errors reported when executing get_maintainer.pl
On Fri, Apr 28, 2023 at 09:28:20AM +0800, Yanhong Wang wrote: > Fixed errors reported when executing 'scripts/get_maintainer.pl -f > configs/starfive_visionfive2_defconfig'. > > Invalid MAINTAINERS address: 'startfive' > > Signed-off-by: Yanhong Wang > --- > board/starfive/visionfive2/MAINTAINERS | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 21/42] watchdog: ulp_wdog: guard reset_cpu with condition check
On 4/28/23 06:08, Peng Fan (OSS) wrote:
From: Peng Fan
There will be build error if CONFIG_SYSRESET is enabled, so guard
the reset_cpu with condition check here
Signed-off-by: Peng Fan
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/watchdog/ulp_wdog.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index c21aa3af55f..0eea04ed2c6 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -122,6 +122,7 @@ void hw_watchdog_init(void)
ulp_watchdog_init(wdog, CONFIG_WATCHDOG_TIMEOUT_MSECS);
}
+#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
@@ -159,6 +160,7 @@ void reset_cpu(void)
while (1);
}
+#endif
static int ulp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 00/42] imx: i.MX9 update
On 4/28/23 06:08, Peng Fan (OSS) wrote: From: Peng Fan This patchset includes updates mainly for i.MX9, such as Clock, Memory, Parts, Low drive mode, DDR, cpu driver, Variants The first patch is not about i.MX9, just include it here since it is a simple one for i.MX8ULP. For the watchdog reset_cpu, I will move it out from watchdog driver in future patches which would includes other changes. I include it here mainly for sysreset support. Good to hear, thanks for working on this. Thanks, Stefan This patchset depends on two patches from Marek: https://patchwork.ozlabs.org/project/uboot/patch/20230404192510.160819-1-ma...@denx.de/ https://patchwork.ozlabs.org/project/uboot/patch/20230404192510.160819-2-ma...@denx.de/ Jacky Bai (4): ddr: imx9: Change the saved ddr data base to 0x2051c000 ddr: imx93: Add 625M bypass clock support ddr: imx93: update the ddr init to support mult setpoints ddr: imx9: update the rank setting for multi fsp support Peng Fan (33): imx8ulp: build ahab imx: spl_imx_romapi: typo fix imx: move imx8 sci header file to include/firmware/imx imx: firmware: sci: add inline functions when IMX8 not enabled imx: imx8_cpu: use static for local functions imx: imx8_cpu: support i.MX9 imx: imx8_cpu: support get temperature for i.MX9 imx: imx8_cpu: print cpu grade temperature imx9: configure M33 systick to 24M imx9: add more PLL settings imx9: use parameter freq when set_arm_clk imx9: correct getting LPI2C clk imx9: simplify clk settings imx9: cut off OPTEE memory region from U-Boot imx9: imx93_evk: enable CPU_IMX imx9: imx93_evk: drop unused macro imx9: imx93_evk: select IMX_TMU imx9: imx93_evk: enable CONFIG_WDT watchdog: ulp_wdog: guard reset_cpu with condition check imx9: soc: support reset cause imx9: Get market segment and speed grading imx9: clock: clear HW_CTRL_SEL imx9: clock: add CONFIG_IMX9_LOW_DRIVE_MODE support imx9: clock: config arm alt root to 500mhz imx9: add i.MX93 variants support imx9: correct coding style imx9: use i.MX generic rom api function imx9: imx93_evk: add low drive mode support on 11x11 EVK arm: dts: imx93: sync device tree with Linux arm: dts: imx93: add tmu imx9: imx93_evk: Update spl stack & bss base address imx9: imx93_evk: update ddr timing file imx9: imx93_evk: enable sysreset Ye Li (5): thermal: imx_tmu: Update TMU driver to support iMX93 imx9: Change hard coded MAC to read from fuse imx9: allow to bootaux Mcore with input address ddr: imx9: Add workaround for DDRPHY rank-to-rank errata imx9: Calculate DDR size from DDRC setting arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 29 - arch/arm/dts/imx93-11x11-evk.dts | 385 +- arch/arm/dts/imx93-pinfunc.h | 194 +- arch/arm/dts/imx93.dtsi | 618 +-- arch/arm/include/asm/arch-imx/cpu.h |7 + arch/arm/include/asm/arch-imx8/power-domain.h |2 +- arch/arm/include/asm/arch-imx8/sci/sci.h | 138 - arch/arm/include/asm/arch-imx8/sys_proto.h|2 +- arch/arm/include/asm/arch-imx8m/ddr.h |2 +- arch/arm/include/asm/arch-imx9/clock.h|6 + arch/arm/include/asm/arch-imx9/ddr.h | 23 +- arch/arm/include/asm/arch-imx9/imx-regs.h |3 + arch/arm/include/asm/mach-imx/sys_proto.h | 12 +- arch/arm/mach-imx/cmd_dek.c |2 +- arch/arm/mach-imx/imx8/ahab.c |2 +- arch/arm/mach-imx/imx8/cpu.c |2 +- arch/arm/mach-imx/imx8/fdt.c |2 +- arch/arm/mach-imx/imx8/iomux.c|2 +- arch/arm/mach-imx/imx8/misc.c |2 +- arch/arm/mach-imx/imx8/snvs_security_sc.c |2 +- arch/arm/mach-imx/imx8ulp/Kconfig |5 + arch/arm/mach-imx/imx8ulp/Makefile|1 + arch/arm/mach-imx/imx9/Kconfig|5 + arch/arm/mach-imx/imx9/clock.c| 113 +- arch/arm/mach-imx/imx9/imx_bootaux.c | 10 +- arch/arm/mach-imx/imx9/soc.c | 384 +- arch/arm/mach-imx/parse-container.c |2 +- arch/arm/mach-imx/spl_imx_romapi.c|2 +- .../imx8qm_rom7720_a1/imx8qm_rom7720_a1.c |2 +- board/advantech/imx8qm_rom7720_a1/spl.c |2 +- board/congatec/cgtqmx8/cgtqmx8.c |2 +- board/freescale/imx8qm_mek/imx8qm_mek.c |2 +- board/freescale/imx8qxp_mek/imx8qxp_mek.c |2 +- board/freescale/imx8qxp_mek/spl.c |2 +- board/freescale/imx93_evk/MAINTAINERS |1 + board/freescale/imx93_evk/Makefile|4 + board/freescale/imx93_evk/lpddr4x_timing.c| 3361 ++--- board/freescale/imx93_evk/lpddr4x_timing_ld.c | 1496 board/freescale/imx93_evk/spl.c | 26 +- board/siemens/capricorn/board.c |2 +- board/tor
Re: [PATCH v3] doc:mmc:drop 0x prefixes in read/write examples
On 4/27/23 12:12, Alexander Shirokov wrote: The patch drops 0x prefixes because all numbers are interpreted as HEX by default. Also, it fixes the mismatch between input arguments and output at 'mmc write' example. Now it's 256 (0x100) blocks. Signed-off-by: Alexander Shirokov --- doc/usage/cmd/mmc.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/usage/cmd/mmc.rst b/doc/usage/cmd/mmc.rst index 55e3f9cf98..71a0303109 100644 --- a/doc/usage/cmd/mmc.rst +++ b/doc/usage/cmd/mmc.rst @@ -213,10 +213,10 @@ The 'mmc info' command displays device's capabilities: The raw data can be read/written via 'mmc read/write' command: :: -=> mmc read 0x4000 0x5000 0x100 +=> mmc read 4000 5000 100 MMC read: dev # 0, block # 20480, count 256 ... 256 blocks read: OK -=> mmc write 0x4000 0x5000 0x10 +=> mmc write 4000 5000 100 MMC write: dev # 0, block # 20480, count 256 ... 256 blocks written: OK The partition list can be shown via 'mmc part' command: Reviewed-by: Heinrich Schuchardt
Re: [PATCH v5 1/4] efi_loader: get version information from device tree
Am 28. April 2023 01:35:04 MESZ schrieb Simon Glass :
>Hi Masahisa,
>
>On Mon, 10 Apr 2023 at 03:07, Masahisa Kojima
> wrote:
>>
>> Current FMP->GetImageInfo() always return 0 for the firmware
>> version, user can not identify which firmware version is currently
>> running through the EFI interface.
>>
>> This commit gets the version information from device tree,
>> then fills the firmware version, lowest supported version
>> in FMP->GetImageInfo().
>>
>> Now FMP->GetImageInfo() and ESRT have the meaningful version number.
>>
>> Signed-off-by: Masahisa Kojima
>> ---
>> Changes in v5:
>> - newly implement a device tree based versioning
>>
>> .../firmware/firmware-version.txt | 25
>> lib/efi_loader/efi_firmware.c | 63 +--
>> 2 files changed, 84 insertions(+), 4 deletions(-)
>> create mode 100644 doc/device-tree-bindings/firmware/firmware-version.txt
>>
>> diff --git a/doc/device-tree-bindings/firmware/firmware-version.txt
>> b/doc/device-tree-bindings/firmware/firmware-version.txt
>> new file mode 100644
>> index 00..6112de4a1d
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/firmware/firmware-version.txt
>> @@ -0,0 +1,25 @@
>> +firmware-version bindings
>> +---
>> +
>> +Required properties:
>> +- image-type-id: guid for image blob type
>> +- image-index : image index
>> +- fw-version : firmware version
>> +- lowest-supported-version : lowest supported version
>> +
>> +Example:
>> +
>> + firmware-version {
>> + image1 {
>> + image-type-id =
>> "09D7CF52-0720-4710-91D1-08469B7FE9C8";
>
>Nit: please use lower-case hex and add a decoder to uuid.c so we can
>look it up when debugging.
The GUIDs are board specific. No, we should not clutter uuid.c with strings for
dozens of boards. Our development aim is to keep U-Boot small and these GUIDs
are not printed anywhere.
Instead we should define a string per firmware image. We already have a field
for it:
fw_array[i].fw_name
Best regards
Heinrich
>
>> + image-index = <1>;
>> + fw-version = <5>;
>> + lowest-supported-version = <3>;
>> + };
>> + image2 {
>> + image-type-id =
>> "5A7021F5-FEF2-48B4-AABA-832E777418C0";
>> + image-index = <2>;
>> + fw-version = <10>;
>> + lowest-supported-version = <7>;
>> + };
>> + };
>[..]
>
>Regards,
>Simon
Re: [PATCH 16/18] arm: dts: fsl-ls1088a: copy all missing bindings from Linux
On 4/12/2023 3:38 PM, Mathew McBride wrote:
This is effectively:
cp linux/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi \
u-boot/arch/arm/dts/fsl-ls1088a.dtsi
Tested working with Ten64 board (LS1088A) booting openSUSE Tumbleweed.
Signed-off-by: Mathew McBride
---
arch/arm/dts/fsl-ls1088a.dtsi | 320 --
1 file changed, 304 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index d5822520fb..e5fb137ac0 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -1,18 +1,27 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
I just relized that I overlooked this. Is it fine to update this？
I could drop this line change in my local if need to keep original license.
Regards,
Peng.
/*
- * NXP ls1088a SOC common device tree source
+ * Device Tree Include file for NXP Layerscape-1088A family SoC.
+ *
+ * Copyright 2017-2020 NXP
+ *
+ * Harninder Rai
*
- * Copyright 2017, 2020-2021, 2023 NXP
*/
-
#include
#include
+#include
+
/ {
compatible = "fsl,ls1088a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ crypto = &crypto;
+ rtc1 = &ftm_alarm0;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -121,12 +130,73 @@
};
};
+ thermal-zones {
+ core-cluster {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ core_cluster_alert: core-cluster-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ core-cluster-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&core_cluster_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
+ <&cpu4 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ soc {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 1>;
+
+ trips {
+ soc-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
-<1 14 0x8>, /* Physical Non-Secure PPI, active-low
*/
-<1 11 0x8>, /* Virtual PPI, active-low */
-<1 10 0x8>; /* Hypervisor PPI, active-low */
+ interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
+<1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure
PPI */
+<1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
+<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = ;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
};
sysclk: sysclk {
@@ -136,6 +206,13 @@
clock-output-names = "sysclk";
};
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&reset>;
+
Re: [PATCH 18/18] arm: dts: ten64: fix header typo and update copyright
On 4/12/2023 3:38 PM, Mathew McBride wrote: Somehow, I managed to typo our company name in the U-Boot and Linux kernel submissions. Fix this and update the copyright year at the same time. Signed-off-by: Mathew McBride Acked-by: Peng Fan
Re: [PATCH 17/18] arm: dts: ten64: syncronise device tree with Linux
On 4/12/2023 3:38 PM, Mathew McBride wrote: This synchronises the Linux device tree with U-Boot (cp linux//fsl-ls1088a-ten64.dts uboot//fsl-ls1088a-ten64.dts), as of Linux v6.2-rc5. Missing from the U-Boot copy previously was the Ethernet PCS definitions (required for linking with PHY in Linux but not used by U-Boot) and various upstream fixes and formatting changes. The board microcontroller (which doesn't have a Linux driver) has been moved to the -u-boot.dtsi, as well as the spi0 quadspi alias (used by U-boot 'sf' but not valid for Linux). Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
Re: [PATCH 16/18] arm: dts: fsl-ls1088a: copy all missing bindings from Linux
On 4/12/2023 3:38 PM, Mathew McBride wrote: This is effectively: cp linux/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi \ u-boot/arch/arm/dts/fsl-ls1088a.dtsi Tested working with Ten64 board (LS1088A) booting openSUSE Tumbleweed. Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
Re: [PATCH 15/18] arm: dts: fsl-ls1088a: move and sync existing bindings to be under /soc
On 4/12/2023 3:38 PM, Mathew McBride wrote: Our [U-Boot] copy of fsl-ls1088a.dtsi had all the hardware under the top level, until the DM_SERIAL implementation recently. In this commit, remove any remaining devices (that were in U-Boot, but not touched by previous patches in this series) to be under /soc, updating to their upstream (Linux) bindings. The bindings have been copied closest to their relative positions in the Linux version, so the eventual result is that the U-Boot and Linux fsl-ls1088a.dtsi will be identical. The next commit will add the hardware bindings that were not in U-Boot. Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
Re: [PATCH 14/18] arm: dts: fsl-ls1088a: syncronise fsl-mc definition with Linux
On 4/12/2023 3:38 PM, Mathew McBride wrote: This moves the fsl-mc device tree definition under the /soc node, as well as adding interrupt and IOMMU definitions that were not in U-Boot before. There are slight differences between the two bindings as we add a "simple-mfd" compatible to function under U-Boot's driver model. Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
Re: [PATCH 13/18] arm: dts: fsl-ls1088a: syncronise MDIO+PCS U-Boot definitions with Linux
On 4/12/2023 3:38 PM, Mathew McBride wrote: Synchronise the MDIO controller definitions with Linux, so the controllers will be usable when passing U-Boot's control FDT to Linux. This also adds the PCS (internal controller) definitions which are not used by U-Boot. Caveat: The kernel definition uses "fsl,fman-memac-mdio", as with other members of the Layerscape family, but U-Boot uses a different driver for the DPAA2 Family devices (LS1088/LS2088/LX2160). So we use "fsl,ls-mdio" as the first compatible string for these devices. Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
Re: [PATCH 12/18] arm: dts: fsl-ls1088a: sync usb controller nodes with Linux
On 4/12/2023 3:38 PM, Mathew McBride wrote: Synchronise the USB device tree definition with Linux, allowing the U-Boot control FDT to be used to boot a Linux system with working USB. An extra compatible string, "fsl,layerscape-dwc3" is needed for special handling in U-Boot, so has been added to the -u-boot.dtsi file. It might be better to add this to the Linux source bindings. Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
Re: [PATCH 12/18] arm: dts: fsl-ls1088a: sync usb controller nodes with Linux
On 4/12/2023 3:38 PM, Mathew McBride wrote: Synchronise the USB device tree definition with Linux, allowing the U-Boot control FDT to be used to boot a Linux system with working USB. An extra compatible string, "fsl,layerscape-dwc3" is needed for special handling in U-Boot, so has been added to the -u-boot.dtsi file. It might be better to add this to the Linux source bindings. Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
Re: [PATCH 11/18] arm: dts: fsl-ls1088a: move I2C nodes under "soc" and syncronize with Linux
On 4/12/2023 3:38 PM, Mathew McBride wrote: U-Boot's definition for the I2C controllers did not contain any clock information. This resulted in the I2C not functioning when the U-Boot control FDT was passed to Linux. Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
Re: [PATCH 10/18] arm: dts: fsl-ls1088a: move GPIO controller under "soc" per Linux
On 4/12/2023 3:38 PM, Mathew McBride wrote: Move the GPIO controller definitions under the "soc" and in the same relative position as the Linux kernel fsl-ls1088a.dtsi. Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
Re: [PATCH 09/18] arm: dts: fsl-ls1088a: import CPU definition from Linux kernel
On 4/12/2023 3:38 PM, Mathew McBride wrote: This is required for Linux to boot using the same FDT as U-Boot (such as passing the control FDT to bootefi). Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
Re: [PATCH 08/18] arm: dts: fsl-ls1088a: match Linux FDT by disabling PCIe by default
On 4/12/2023 3:38 PM, Mathew McBride wrote: The Linux kernel fsl-ls1088a.dtsi disables (status="disabled") all PCIe controllers by default, with the bootloader (i.e U-Boot) enabling the appropriate controllers (specified by the board reset control word/RCW) by FDT fixup. However, U-Boot needs these controllers to be enabled to be usable, which we can add in the u-boot only dtsi. Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
Re: [PATCH 07/18] arm: dts: fsl-ls1088a: sync PCIe controller definition with Linux
On 4/12/2023 3:38 PM, Mathew McBride wrote: This moves the PCIe controller definitions under /soc and adopts the same bindings (fsl,ls1088a-pcie) as Linux. Previously, the format was different between the two versions. Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
Re: [PATCH 06/18] arm: dts: fsl-ls1088a: import and sync full SMMU nodes with Linux
On 4/12/2023 3:38 PM, Mathew McBride wrote: To synchronise the device tree in U-Boot with Linux, the GIC (Interrupt Controller) and SMMU/IOMMU nodes need to be synchronised before changing any dependent components like PCIe and DPAA2/fsl-mc. Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
[PATCH 14/42] imx9: simplify clk settings
From: Peng Fan
Simplify the clk root settings with an array
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/clock.h | 6
arch/arm/mach-imx/imx9/clock.c | 38 +++---
2 files changed, 28 insertions(+), 16 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/clock.h
b/arch/arm/include/asm/arch-imx9/clock.h
index 336d8613181..1169ffd74d3 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -205,6 +205,12 @@ struct clk_root_map {
u32 mux_type;
};
+struct imx_clk_setting {
+ u32 clk_root;
+ enum ccm_clk_src src;
+ u32 div;
+};
+
int clock_init(void);
u32 get_clk_src_rate(enum ccm_clk_src source);
u32 get_lpuart_clk(void);
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index a0efee96e51..a5f95fbcb8a 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -680,36 +680,42 @@ void set_arm_clk(ulong freq)
#endif
-int clock_init(void)
-{
- int i;
-
+struct imx_clk_setting imx_clk_settings[] = {
/* Set A55 periphal to 333M */
- ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3);
+ {ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3},
/* Set A55 mtr bus to 133M */
- ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
-
+ {ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Sentinel to 200M */
- ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2);
+ {SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2},
/* Bus_wakeup to 133M */
- ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ {BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Bus_AON to 133M */
- ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ {BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* M33 to 200M */
- ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2);
+ {M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2},
/*
* WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for
* generating MII clock at 2.5M
*/
- ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2);
+ {WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2},
/* SWO TRACE to 133M */
- ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ {SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* M33 systetick to 24M */
- ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1);
+ {M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
/* NIC to 400M */
- ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2);
+ {NIC_CLK_ROOT, SYS_PLL_PFD1, 2},
/* NIC_APB to 133M */
- ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ {NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
+};
+
+int clock_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx_clk_settings); i++) {
+ ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
+imx_clk_settings[i].src,
imx_clk_settings[i].div);
+ }
/* allow for non-secure access */
for (i = 0; i < OSCPLL_END; i++)
--
2.40.0
Re: [PATCH 05/18] pci: layerscape: add support for kernel/official fsl,ls1088a-pcie binding
On 4/12/2023 3:38 PM, Mathew McBride wrote:
This allows the Layerscape PCIe RC driver to use the upstream
style binding (two "reg" entries instead of four).
It is similar to the previous commit e10da1f985ad
("pci: layerscape: add official ls1028a binding support")
which implemented this for the LS1028A.
Signed-off-by: Mathew McBride
Reviewed-by: Peng Fan
Re: [PATCH 04/18] arm: dts: fsl-ls1088a: move memory node into U-Boot specific file
On 4/12/2023 3:38 PM, Mathew McBride wrote: The top-level "memory" node does not exist in the Linux version of the fsl-ls1088a.dtsi file. Move it to the U-Boot "tweak" file, so we can have an identical copy of fsl-ls1088a.dtsi between the projects in the end. Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
Re: [PATCH 03/18] arm: dts: fsl-ls1088a: move u-boot bootph tags into u-boot only files
On 4/12/2023 3:38 PM, Mathew McBride wrote:
This moves the bootph-all tags that were added in commit a593c1fec579
("arch: arm: dts: fsl-ls1088a.dtsi: tag serial nodes with bootph-all")
into a u-boot only include.
Due to the way the U-Boot device tree "tweak" system is setup[1],
we need to have a per-board -u-boot.dtsi, which will
include the "fsl-ls1088a-u-boot.dtsi" tweaks.
By doing so, future updates to fsl-ls1088a.dtsi from upstream
(Linux kernel) can just be copied directly into the U-Boot tree,
without worrying about any extra data local to U-Boot.
Signed-off-by: Mathew McBride
Reviewed-by: Peng Fan
Re: [PATCH 02/18] configs: ten64: enable DM_SERIAL
On 4/12/2023 3:38 PM, Mathew McBride wrote: The recent series "Convert LS1088A and LX2160 to DM_SERIAL" from Ioana Ciornei provided the necessary support to enable DM_SERIAL on the Ten64 board (LS1088A). Signed-off-by: Mathew McBride Reviewed-by: Peng Fan
Re: [PATCH 01/18] armv8: fsl-layerscape: check for crypto node first in fdt_fixup_remove_jr
On 4/12/2023 3:38 PM, Mathew McBride wrote:
This a problem I found while updating the U-Boot fsl-ls1088a.dtsi
to match the Linux version.
fdt_fixup_remove_jr did not check whether there was a "crypto"
alias in the device tree before calling more fdt_* functions,
which resulted in a crash.
Fixes: a797f274
("ARMv8/sec_firmware : Update chosen/kaslr-seed with random number")
Signed-off-by: Mathew McBride
Reviewed-by: Peng Fan
---
arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 4f91db49ee..22ce699216 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -387,6 +387,10 @@ void fdt_fixup_remove_jr(void *blob)
u64 jr_offset, used_jr;
fdt32_t *reg;
+ /* Return if crypto node not found */
+ if (crypto_node < 0)
+ return;
+
used_jr = sec_firmware_used_jobring_offset();
fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL);
[PATCH 41/42] imx9: imx93_evk: update ddr timing file
From: Peng Fan
Update DDR timing file generated by DDR Config Tool
1. Dynamic refresh rate is set by default
2. The 3rd freq will be 625MTS based on power and performance better than
100MTS.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
board/freescale/imx93_evk/lpddr4x_timing.c | 3361 +++-
1 file changed, 1935 insertions(+), 1426 deletions(-)
diff --git a/board/freescale/imx93_evk/lpddr4x_timing.c
b/board/freescale/imx93_evk/lpddr4x_timing.c
index e34096fee1e..ffdf96b739f 100644
--- a/board/freescale/imx93_evk/lpddr4x_timing.c
+++ b/board/freescale/imx93_evk/lpddr4x_timing.c
@@ -1,11 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2022 NXP
+ * Copyright 2023 NXP
*
- * Generated code from NXP_DDR_tool
- *
- * Align with uboot version:
- * imx_v2019.04_5.4.x and above version
+ * Code generated with DDR Tool v2.0.0_5.3.
*/
#include
@@ -13,1443 +10,1939 @@
struct dram_cfg_param ddr_ddrc_cfg[] = {
/** Initialize DDRC registers **/
- { 0x4e300110, 0x44140001 },
- { 0x4e30, 0x8000ff },
- { 0x4e38, 0x0 },
- { 0x4e300080, 0x8512 },
- { 0x4e300084, 0x0 },
- { 0x4e300114, 0x2 },
- { 0x4e300260, 0x0 },
- { 0x4e30017c, 0x0 },
- { 0x4e300104, 0xaaee001b },
- { 0x4e300108, 0x626ee273 },
- { 0x4e30010c, 0x5c18b },
- { 0x4e300100, 0x25ab321b },
- { 0x4e300160, 0x9002 },
- { 0x4e30016c, 0x35f0 },
- { 0x4e300250, 0x2b },
- { 0x4e300254, 0x0 },
- { 0x4e30025c, 0x400 },
- { 0x4e300300, 0x16291314 },
- { 0x4e300304, 0x163110c },
- { 0x4e300308, 0xa200e3c },
- { 0x4e300170, 0x8b0b0608 },
- { 0x4e300124, 0x1c77071d },
- { 0x4e300f04, 0x80 },
+ {0x4e300110, 0x4411},
+ {0x4e30, 0x8000ff},
+ {0x4e38, 0x0},
+ {0x4e300080, 0x8512},
+ {0x4e300084, 0x0},
+ {0x4e300114, 0x1002},
+ {0x4e300260, 0x80},
+ {0x4e300f04, 0x80},
+ {0x4e300800, 0x43b30002},
+ {0x4e300804, 0x1f1f1f1f},
+ {0x4e301000, 0x0},
+ {0x4e301240, 0x0},
+ {0x4e301244, 0x0},
+ {0x4e301248, 0x0},
+ {0x4e30124c, 0x0},
+ {0x4e301250, 0x0},
+ {0x4e301254, 0x0},
+ {0x4e301258, 0x0},
+ {0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+ {
+ {
+ {0x4e300100, 0x24AB321B},
+ {0x4e300104, 0xF8EE001B},
+ {0x4e300108, 0x2F2EE233},
+ {0x4e30010C, 0x0005E18B},
+ {0x4e300124, 0x1C77},
+ {0x4e300160, 0x9102},
+ {0x4e30016C, 0x35F0},
+ {0x4e300170, 0x8B0B0608},
+ {0x4e300250, 0x0028},
+ {0x4e300254, 0x015B015B},
+ {0x4e300258, 0x0008},
+ {0x4e30025C, 0x0400},
+ {0x4e300300, 0x224F2213},
+ {0x4e300304, 0x015B2213},
+ {0x4e300308, 0x0A3C0E3C},
+ },
+ {
+ {0x01, 0xE4},
+ {0x02, 0x36},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x12552100},
+ {0x4e300104, 0xF877000E},
+ {0x4e300108, 0x1816B4AA},
+ {0x4e30010C, 0x005101E6},
+ {0x4e300124, 0x0E3C},
+ {0x4e300160, 0x9102},
+ {0x4e30016C, 0x3090},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x0014},
+ {0x4e300254, 0x00AA00AA},
+ {0x4e300258, 0x0008},
+ {0x4e30025C, 0x0400},
+ },
+ {
+ {0x01, 0xB4},
+ {0x02, 0x1B},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00061000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E62FA48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C5},
+ {0x4e300160, 0x9102},
+ {0x4e30016C, 0x3000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x0007},
+
[PATCH 35/42] imx9: imx93_evk: Update spl stack & bss base address
From: Peng Fan As the ddr timing info will be saved at the last 16KB of the OCRAM, spl stack & bss base should be updated to avoid conflict. Signed-off-by: Peng Fan --- configs/imx93_11x11_evk_defconfig| 4 ++-- configs/imx93_11x11_evk_ld_defconfig | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index c2709f8c66c..cf240baae5b 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -15,7 +15,7 @@ CONFIG_TARGET_IMX93_11X11_EVK=y CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK=0x2051ddd0 +CONFIG_SPL_STACK=0x20519dd0 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x8800 CONFIG_SPL_LOAD_IMX_CONTAINER=y @@ -30,7 +30,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2051e000 +CONFIG_SPL_BSS_START_ADDR=0x2051a000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig index caf17de3b10..ac8a23fcbf7 100644 --- a/configs/imx93_11x11_evk_ld_defconfig +++ b/configs/imx93_11x11_evk_ld_defconfig @@ -31,12 +31,12 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x2051e000 +CONFIG_SPL_BSS_START_ADDR=0x2051a000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x2051ddd0 +CONFIG_SPL_STACK=0x20519dd0 CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8320 -- 2.40.0
[PATCH 31/42] imx9: allow to bootaux Mcore with input address
From: Ye Li
Currently bootaux only supports to boot M33 core from TCM. Since ATF
has changed to use x2 parameter for M33 image address, update the
bootaux command to use input address, so we can support boot from
any possilbe address like TCM, DDR, Flexspi NOR.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/imx_bootaux.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c
b/arch/arm/mach-imx/imx9/imx_bootaux.c
index 3b6662aeb81..256e6fa1c54 100644
--- a/arch/arm/mach-imx/imx9/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx9/imx_bootaux.c
@@ -34,17 +34,13 @@ int arch_auxiliary_core_down(u32 core_id)
int arch_auxiliary_core_up(u32 core_id, ulong addr)
{
struct arm_smccc_res res;
- u32 stack, pc;
if (!addr)
return -EINVAL;
- stack = *(u32 *)addr;
- pc = *(u32 *)(addr + 4);
+ printf("## Starting auxiliary core addr = 0x%08lX...\n", addr);
- printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n",
stack, pc);
-
- arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0,
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, addr, 0,
0, 0, 0, 0, &res);
return 0;
@@ -129,5 +125,5 @@ U_BOOT_CMD(
"Start auxiliary core",
" []\n"
" - start auxiliary core [] (default 0),\n"
- " at address \n"
+ " at address of auxiliary core view\n"
);
--
2.40.0
[PATCH 30/42] imx9: imx93_evk: add low drive mode support on 11x11 EVK
From: Peng Fan
Add a static u-boot config for i.MX93 low drive mode support. When
low drive mode is enabled, VDD_SOC is set to 0.75V. Bus clocks,
A55 core clock (900Mhz), DDR clock (1866MTS), and some peripherals
clocks (USDHC/FLEXSPI/PDM/DISP_PIX/CAM_PIX) must decrease to meet
max frequencies in low drive mode.
Also set standby voltage for buck1
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
board/freescale/imx93_evk/MAINTAINERS |1 +
board/freescale/imx93_evk/Makefile|4 +
board/freescale/imx93_evk/lpddr4x_timing_ld.c | 1496 +
board/freescale/imx93_evk/spl.c | 26 +-
configs/imx93_11x11_evk_ld_defconfig | 121 ++
5 files changed, 1642 insertions(+), 6 deletions(-)
create mode 100644 board/freescale/imx93_evk/lpddr4x_timing_ld.c
create mode 100644 configs/imx93_11x11_evk_ld_defconfig
diff --git a/board/freescale/imx93_evk/MAINTAINERS
b/board/freescale/imx93_evk/MAINTAINERS
index 389f17ae1e4..8ca4646f20f 100644
--- a/board/freescale/imx93_evk/MAINTAINERS
+++ b/board/freescale/imx93_evk/MAINTAINERS
@@ -4,3 +4,4 @@ S: Maintained
F: board/freescale/imx93_evk/
F: include/configs/imx93_evk.h
F: configs/imx93_11x11_evk_defconfig
+ configs/imx93_11x11_evk_ld_defconfig
diff --git a/board/freescale/imx93_evk/Makefile
b/board/freescale/imx93_evk/Makefile
index 575f8e94604..17956d24bf7 100644
--- a/board/freescale/imx93_evk/Makefile
+++ b/board/freescale/imx93_evk/Makefile
@@ -8,5 +8,9 @@ obj-y += imx93_evk.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
+ifdef CONFIG_IMX9_LOW_DRIVE_MODE
+obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing_ld.o
+else
obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o
endif
+endif
diff --git a/board/freescale/imx93_evk/lpddr4x_timing_ld.c
b/board/freescale/imx93_evk/lpddr4x_timing_ld.c
new file mode 100644
index 000..f080322f112
--- /dev/null
+++ b/board/freescale/imx93_evk/lpddr4x_timing_ld.c
@@ -0,0 +1,1496 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Generated code from IMX_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ */
+
+#include
+#include
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x4e300110, 0x44140001 },
+ { 0x4e301000, 0x0 },
+ { 0x4e30, 0x8000ff },
+ { 0x4e38, 0x0 },
+ { 0x4e300080, 0x8512 },
+ { 0x4e300084, 0x0 },
+ { 0x4e300114, 0x2 },
+ { 0x4e300260, 0x0 },
+ { 0x4e30017c, 0x0 },
+ { 0x4e300f04, 0x80 },
+ { 0x4e300104, 0xaa77000e },
+ { 0x4e300108, 0x1816b1aa },
+ { 0x4e30010c, 0x5101e6 },
+ { 0x4e300100, 0x12552100 },
+ { 0x4e300160, 0x9002 },
+ { 0x4e30016c, 0x3090 },
+ { 0x4e300250, 0x14 },
+ { 0x4e300254, 0xaa00aa },
+ { 0x4e300258, 0x8 },
+ { 0x4e30025c, 0x400 },
+ { 0x4e300300, 0x11281109 },
+ { 0x4e300304, 0xaa110a },
+ { 0x4e300308, 0x620071e },
+ { 0x4e300170, 0x8a0a0508 },
+ { 0x4e300124, 0xe3c },
+ { 0x4e300804, 0x1f1f1f1f },
+ { 0x4e301240, 0x0 },
+ { 0x4e301244, 0x0 },
+ { 0x4e301248, 0x0 },
+ { 0x4e30124c, 0x0 },
+ { 0x4e301250, 0x0 },
+ { 0x4e301254, 0x0 },
+ { 0x4e301258, 0x0 },
+ { 0x4e30125c, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x4 },
+ { 0x100a1, 0x5 },
+ { 0x100a2, 0x6 },
+ { 0x100a3, 0x7 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x1 },
+ { 0x100a6, 0x2 },
+ { 0x100a7, 0x3 },
+ { 0x110a0, 0x3 },
+ { 0x110a1, 0x2 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x1 },
+ { 0x110a4, 0x7 },
+ { 0x110a5, 0x6 },
+ { 0x110a6, 0x4 },
+ { 0x110a7, 0x5 },
+ { 0x1005f, 0x5ff },
+ { 0x1015f, 0x5ff },
+ { 0x1105f, 0x5ff },
+ { 0x1115f, 0x5ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x200c5, 0xb },
+ { 0x2002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x20024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x2007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x20056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x10049, 0xe00 },
+ { 0x10149, 0xe00 },
+ { 0x11049, 0xe00 },
+ { 0x11149, 0xe00 },
+ { 0x43, 0x60 },
+ { 0x1043, 0x60 },
+ { 0x2043, 0x60 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x2009b, 0x2 },
+ { 0x20008, 0x1d3 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x10c },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x200fa, 0x2 },
+ { 0x20019, 0x1 },
+ { 0x200f0, 0x0 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x444
[PATCH 42/42] imx9: imx93_evk: enable sysreset
From: Peng Fan Enable sysreset for i.MX93 EVK. Signed-off-by: Peng Fan --- configs/imx93_11x11_evk_defconfig| 3 +++ configs/imx93_11x11_evk_ld_defconfig | 3 +++ 2 files changed, 6 insertions(+) diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index cf240baae5b..eb4674ddd47 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -112,6 +112,9 @@ CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CMD_POWEROFF=y +CONFIG_SYSRESET_PSCI=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y CONFIG_ULP_WATCHDOG=y diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig index ac8a23fcbf7..29d94316b33 100644 --- a/configs/imx93_11x11_evk_ld_defconfig +++ b/configs/imx93_11x11_evk_ld_defconfig @@ -114,6 +114,9 @@ CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CMD_POWEROFF=y +CONFIG_SYSRESET_PSCI=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y CONFIG_ULP_WATCHDOG=y -- 2.40.0
[PATCH 39/42] ddr: imx9: update the rank setting for multi fsp support
From: Jacky Bai
The rank setting flow should be updated to support multi
fsp config.
Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
---
drivers/ddr/imx/imx9/ddr_init.c | 178 +---
1 file changed, 116 insertions(+), 62 deletions(-)
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
index a2158094b28..7a333880e6b 100644
--- a/drivers/ddr/imx/imx9/ddr_init.c
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -145,68 +145,122 @@ void get_trained_CDD(u32 fsp)
g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max :
cdd_chb_ww_max;
}
-void update_umctl2_rank_space_setting(unsigned int pstat_num)
+static u32 ddrc_get_fsp_reg_setting(struct dram_cfg_param *ddrc_cfg, unsigned
int cfg_num, u32 reg)
{
- u32 tmp, tmp_t;
+ unsigned int i;
+
+ for (i = 0; i < cfg_num; i++) {
+ if (reg == ddrc_cfg[i].reg)
+ return ddrc_cfg[i].val;
+ }
- int wwt, rrt, wrt, rwt;
- int ext_wwt, ext_rrt, ext_wrt, ext_rwt;
- int max_wwt, max_rrt, max_wrt, max_rwt;
-
- /* read wwt, rrt, wrt, rwt fields from timing_cfg_0 */
- tmp = readl(REG_DDR_TIMING_CFG_0);
- wwt = (tmp >> 24) & 0x3;
- rrt = (tmp >> 26) & 0x3;
- wrt = (tmp >> 28) & 0x3;
- rwt = (tmp >> 30) & 0x3;
-
- /* read rxt_wwt, ext_rrt, ext_wrt, ext_rwt fields from timing_cfg_4 */
- tmp_t = readl(REG_DDR_TIMING_CFG_4);
- ext_wwt = (tmp >> 8) & 0x1;
- ext_rrt = (tmp >> 10) & 0x1;
- ext_wrt = (tmp >> 12) & 0x1;
- ext_rwt = (tmp >> 14) & 0x3;
-
- wwt = (ext_wwt << 2) | wwt;
- rrt = (ext_rrt << 2) | wwt;
- wrt = (ext_wrt << 2) | wrt;
- rwt = (ext_rwt << 2) | rwt;
-
- /* calculate the maximum between controller and cdd values */
- max_wwt = MAX(g_cdd_ww_max[0], wwt);
- max_rrt = MAX(g_cdd_rr_max[0], rrt);
- max_wrt = MAX(g_cdd_wr_max[0], wrt);
- max_rwt = MAX(g_cdd_rw_max[0], rwt);
-
- /* verify values to see if are bigger then 7 or 15 (3 bits or 4 bits) */
- if (max_wwt > 7)
- max_wwt = 7;
- if (max_rrt > 7)
- max_rrt = 7;
- if (max_wrt > 7)
- max_wrt = 7;
- if (max_rwt > 15)
- max_rwt = 15;
-
- /* recalculate timings for controller registers */
- wwt = max_wwt & 0x3;
- rrt = max_rrt & 0x3;
- wrt = max_wrt & 0x3;
- rwt = max_rwt & 0x3;
-
- ext_wwt = (max_wwt & 0x4) >> 2;
- ext_rrt = (max_rrt & 0x4) >> 2;
- ext_wrt = (max_wrt & 0x4) >> 2;
- ext_rwt = (max_rwt & 0xC) >> 2;
-
- /* update timing_cfg_0 and timing_cfg_4 */
- tmp = (tmp & 0x00ff) | (rwt << 30) | (wrt << 28) |
- (rrt << 26) | (wwt << 24);
- writel(tmp, REG_DDR_TIMING_CFG_0);
-
- tmp_t = (tmp_t & 0x2AFF) | (ext_rwt << 14) |
- (ext_wrt << 12) | (ext_rrt << 10) | (ext_wwt << 8);
- writel(tmp_t, REG_DDR_TIMING_CFG_4);
+ return 0;
+}
+
+static void ddrc_update_fsp_reg_setting(struct dram_cfg_param *ddrc_cfg, int
cfg_num,
+ u32 reg, u32 val)
+{
+ unsigned int i;
+
+ for (i = 0; i < cfg_num; i++) {
+ if (reg == ddrc_cfg[i].reg) {
+ ddrc_cfg[i].val = val;
+ return;
+ }
+ }
+}
+
+void update_umctl2_rank_space_setting(struct dram_timing_info *dram_timing,
unsigned int pstat_num)
+{
+ u32 tmp, tmp_t;
+ u32 wwt, rrt, wrt, rwt;
+ u32 ext_wwt, ext_rrt, ext_wrt, ext_rwt;
+ u32 max_wwt, max_rrt, max_wrt, max_rwt;
+ u32 i;
+
+ for (i = 0; i < pstat_num; i++) {
+ /* read wwt, rrt, wrt, rwt fields from timing_cfg_0 */
+ if (!dram_timing->fsp_cfg_num) {
+ tmp = ddrc_get_fsp_reg_setting(dram_timing->ddrc_cfg,
+
dram_timing->ddrc_cfg_num,
+ REG_DDR_TIMING_CFG_0);
+ } else {
+ tmp =
ddrc_get_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg,
+
ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg),
+ REG_DDR_TIMING_CFG_0);
+ }
+ wwt = (tmp >> 24) & 0x3;
+ rrt = (tmp >> 26) & 0x3;
+ wrt = (tmp >> 28) & 0x3;
+ rwt = (tmp >> 30) & 0x3;
+
+ /* read rxt_wwt, ext_rrt, ext_wrt, ext_rwt fields from
timing_cfg_4 */
+ if (!dram_timing->fsp_cfg_num) {
+ tmp_t = ddrc_get_fsp_reg_setting(dram_timing->ddrc_cfg,
+
dram_timing->ddrc_cfg_num,
+REG_DDR_TIMING_CFG_4);
+
[PATCH 40/42] imx9: Calculate DDR size from DDRC setting
From: Ye Li
To avoid using static setting for ECC enabled DDR size, switch
to calculate DDR size from DDRC setting
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
Reviewed-by: Jacky Bai
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 22152172169..f1c74550f3f 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -36,6 +36,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -327,14 +328,26 @@ void enable_caches(void)
__weak int board_phys_sdram_size(phys_size_t *size)
{
+ phys_size_t start, end;
+ phys_size_t val;
+
if (!size)
return -EINVAL;
- *size = PHYS_SDRAM_SIZE;
+ val = readl(REG_DDR_CS0_BNDS);
+ start = (val >> 16) << 24;
+ end = (val & 0x);
+ end = end ? end + 1 : 0;
+ end = end << 24;
+ *size = end - start;
+
+ val = readl(REG_DDR_CS1_BNDS);
+ start = (val >> 16) << 24;
+ end = (val & 0x);
+ end = end ? end + 1 : 0;
+ end = end << 24;
+ *size += end - start;
-#ifdef PHYS_SDRAM_2_SIZE
- *size += PHYS_SDRAM_2_SIZE;
-#endif
return 0;
}
--
2.40.0
[PATCH 37/42] ddr: imx93: Add 625M bypass clock support
From: Jacky Bai
Add 625M bypass clock that may be used DRAM 625M
bypass mode support.
Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/clock.c | 3 +++
drivers/ddr/imx/phy/ddrphy_utils.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 957f80fce2e..a7ecccaf879 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -648,6 +648,9 @@ void dram_pll_init(ulong pll_val)
void dram_enable_bypass(ulong clk_val)
{
switch (clk_val) {
+ case MHZ(625):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD2, 1);
+ break;
case MHZ(400):
ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2);
break;
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c
b/drivers/ddr/imx/phy/ddrphy_utils.c
index 6a8b6be42b2..fd8b4113b7b 100644
--- a/drivers/ddr/imx/phy/ddrphy_utils.c
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -148,6 +148,9 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
dram_pll_init(MHZ(167));
dram_disable_bypass();
break;
+ case 625:
+ dram_enable_bypass(MHZ(625));
+ break;
case 400:
dram_enable_bypass(MHZ(400));
break;
--
2.40.0
[PATCH 38/42] ddr: imx93: update the ddr init to support mult setpoints
From: Jacky Bai
Update the DDR init flow for multi-setpoint support on i.MX93. A new
fsp_cfg struct need to be added in the timing file to store the diff
part of the DDRC and DRAM MR register for each setpoint.
Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/ddr.h | 2 +-
arch/arm/include/asm/arch-imx9/ddr.h | 21 -
drivers/ddr/imx/imx9/ddr_init.c | 113 +-
drivers/ddr/imx/phy/helper.c | 5 +-
4 files changed, 134 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h
b/arch/arm/include/asm/arch-imx8m/ddr.h
index 2f76e7d69b9..c14855d177e 100644
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -709,7 +709,7 @@ int ddr_init(struct dram_timing_info *timing_info);
int ddr_cfg_phy(struct dram_timing_info *timing_info);
void load_lpddr4_phy_pie(void);
void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
-void dram_config_save(struct dram_timing_info *info, unsigned long base);
+void *dram_config_save(struct dram_timing_info *info, unsigned long base);
void board_dram_ecc_scrub(void);
void ddrc_inline_ecc_scrub(unsigned int start_address,
unsigned int range_address);
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h
b/arch/arm/include/asm/arch-imx9/ddr.h
index 8e4f946e5b0..2b22f3a5bea 100644
--- a/arch/arm/include/asm/arch-imx9/ddr.h
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -13,11 +13,21 @@
#define DDR_PHY_BASE 0x4E10
#define DDRMIX_BLK_CTRL_BASE 0x4E01
+#define REG_DDR_SDRAM_MD_CNTL (DDR_CTL_BASE + 0x120)
+#define REG_DDR_CS0_BNDS(DDR_CTL_BASE + 0x0)
+#define REG_DDR_CS1_BNDS(DDR_CTL_BASE + 0x8)
#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24)
#define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104)
#define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110)
#define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160)
#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)
+#define REG_DDR_SDRAM_CFG_3(DDR_CTL_BASE + 0x260)
+#define REG_DDR_SDRAM_CFG_4(DDR_CTL_BASE + 0x264)
+#define REG_DDR_SDRAM_MD_CNTL_2(DDR_CTL_BASE + 0x270)
+#define REG_DDR_SDRAM_MPR4 (DDR_CTL_BASE + 0x28C)
+#define REG_DDR_SDRAM_MPR5 (DDR_CTL_BASE + 0x290)
+
+#define REG_DDR_ERR_EN (DDR_CTL_BASE + 0x1000)
#define SRC_BASE_ADDR (0x4446)
#define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400)
@@ -52,6 +62,12 @@ struct dram_cfg_param {
unsigned int val;
};
+struct dram_fsp_cfg {
+ struct dram_cfg_param ddrc_cfg[20];
+ struct dram_cfg_param mr_cfg[10];
+ unsigned int bypass;
+};
+
struct dram_fsp_msg {
unsigned int drate;
enum fw_type fw_type;
@@ -63,6 +79,9 @@ struct dram_timing_info {
/* umctl2 config */
struct dram_cfg_param *ddrc_cfg;
unsigned int ddrc_cfg_num;
+ /* fsp config */
+ struct dram_fsp_cfg *fsp_cfg;
+ unsigned int fsp_cfg_num;
/* ddrphy config */
struct dram_cfg_param *ddrphy_cfg;
unsigned int ddrphy_cfg_num;
@@ -86,7 +105,7 @@ int ddr_init(struct dram_timing_info *timing_info);
int ddr_cfg_phy(struct dram_timing_info *timing_info);
void load_lpddr4_phy_pie(void);
void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
-void dram_config_save(struct dram_timing_info *info, unsigned long base);
+void *dram_config_save(struct dram_timing_info *info, unsigned long base);
void board_dram_ecc_scrub(void);
void ddrc_inline_ecc_scrub(unsigned int start_address,
unsigned int range_address);
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
index a1d953026f3..a2158094b28 100644
--- a/drivers/ddr/imx/imx9/ddr_init.c
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -71,14 +71,25 @@ void check_dfi_init_complete(void)
setbits_le32(REG_DDRDSR_2, BIT(2));
}
-void ddrc_config(struct dram_cfg_param *ddrc_config, int num)
+void ddrc_config(struct dram_timing_info *dram_timing)
{
+ u32 num = dram_timing->ddrc_cfg_num;
+ struct dram_cfg_param *ddrc_config;
int i = 0;
+ ddrc_config = dram_timing->ddrc_cfg;
for (i = 0; i < num; i++) {
writel(ddrc_config->val, (ulong)ddrc_config->reg);
ddrc_config++;
}
+
+ if (dram_timing->fsp_cfg) {
+ ddrc_config = dram_timing->fsp_cfg[0].ddrc_cfg;
+ while (ddrc_config->reg != 0) {
+ writel(ddrc_config->val, (ulong)ddrc_config->reg);
+ ddrc_config++;
+ }
+ }
}
static unsigned int look_for_max(unsigned int data[], unsigned int addr_start,
@@ -198,10 +209,85 @@ void update_umctl2_rank_space_setting(unsigned int
pstat_num)
writel(tmp_t, REG_DDR_TIMING_CFG_4);
}
+u3
[PATCH 32/42] arm: dts: imx93: sync device tree with Linux
From: Peng Fan
Sync device tree with next-20230426
Signed-off-by: Peng Fan
---
arch/arm/dts/imx93-11x11-evk-u-boot.dtsi| 29 -
arch/arm/dts/imx93-11x11-evk.dts| 385 +++--
arch/arm/dts/imx93-pinfunc.h| 194 ---
arch/arm/dts/imx93.dtsi | 572
include/dt-bindings/clock/imx93-clock.h | 17 +-
include/dt-bindings/power/fsl,imx93-power.h | 15 +
include/dt-bindings/power/imx93-power.h | 12 -
7 files changed, 552 insertions(+), 672 deletions(-)
create mode 100644 include/dt-bindings/power/fsl,imx93-power.h
delete mode 100644 include/dt-bindings/power/imx93-power.h
diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
index 89e64344c6d..5b465e2dbd9 100644
--- a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
@@ -10,25 +10,6 @@
bootph-pre-ram;
};
- aliases {
- usbgadget0 = &usbg1;
- usbgadget1 = &usbg2;
- };
-
- usbg1: usbg1 {
- compatible = "fsl,imx27-usb-gadget";
- dr_mode = "peripheral";
- chipidea,usb = <&usbotg1>;
- status = "okay";
- };
-
- usbg2: usbg2 {
- compatible = "fsl,imx27-usb-gadget";
- dr_mode = "peripheral";
- chipidea,usb = <&usbotg2>;
- status = "okay";
- };
-
firmware {
optee {
compatible = "linaro,optee-tz";
@@ -141,16 +122,6 @@
reset-deassert-us = <10>;
};
-&usbotg1 {
- status = "okay";
- extcon = <&ptn5110>;
-};
-
-&usbotg2 {
- status = "okay";
- extcon = <&ptn5110_2>;
-};
-
&s4muap {
bootph-pre-ram;
status = "okay";
diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts
index b3a5a3d71e2..4322cc3e11b 100644
--- a/arch/arm/dts/imx93-11x11-evk.dts
+++ b/arch/arm/dts/imx93-11x11-evk.dts
@@ -1,36 +1,25 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright 2021 NXP
+ * Copyright 2022 NXP
*/
/dts-v1/;
#include "imx93.dtsi"
-/{
+/ {
+ model = "NXP i.MX93 11X11 EVK board";
+ compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
+
chosen {
stdout-path = &lpuart1;
};
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- audio: audio@a412 {
- compatible = "shared-dma-pool";
- reg = <0 0xa412 0 0x10>;
- no-map;
- };
- };
-
- reg_can2_stby: regulator-can2-stby {
+ reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
- regulator-name = "can2-stby";
- regulator-min-microvolt = <330>;
- regulator-max-microvolt = <330>;
- gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>;
- enable-active-low;
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
@@ -43,81 +32,57 @@
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+};
- usdhc3_pwrseq: usdhc3_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>;
- };
-
- reg_vref_1v8: regulator-adc-vref {
- compatible = "regulator-fixed";
- regulator-name = "vref_1v8";
- regulator-min-microvolt = <180>;
- regulator-max-microvolt = <180>;
- };
+&adc1 {
+ vref-supply = <®_vref_1v8>;
+ status = "okay";
+};
+&mu1 {
+ status = "okay";
};
-&lpi2c1 {
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <40>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pinctrl_lpi2c1>;
- pinctrl-1 = <&pinctrl_lpi2c1>;
+&mu2 {
status = "okay";
+};
- ptn5110: tcpc@50 {
- compatible = "nxp,ptn5110";
- reg = <0x50>;
- interrupt-parent = <&pcal6524>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- status = "okay";
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy1>;
+ status = "okay";
- port {
- typec1_dr_sw: endpoint {
- remote-endpoint = <&usb1_drd_sw>;
- };
- };
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequen
[PATCH 36/42] ddr: imx9: Change the saved ddr data base to 0x2051c000
From: Jacky Bai change the ddr saved info to the last 16KB of the OCRAM. Signed-off-by: Jacky Bai Reviewed-by: Peng Fan Reviewed-by: Ye Li Signed-off-by: Peng Fan --- drivers/ddr/imx/imx9/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig index 123ad173cfc..b1795eec353 100644 --- a/drivers/ddr/imx/imx9/Kconfig +++ b/drivers/ddr/imx/imx9/Kconfig @@ -22,6 +22,6 @@ config SAVED_DRAM_TIMING_BASE help after DRAM is trained, need to save the dram related timming info into memory for low power use. - default 0x204DC000 + default 0x2051C000 endmenu -- 2.40.0
[PATCH 34/42] ddr: imx9: Add workaround for DDRPHY rank-to-rank errata
From: Ye Li
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap
specification does not include the Critical Delay Difference (CDD) to
properly define the required rank-to-rank read command spacing after
executing PHY training firmware.
Following the errata workaround, at the end of data training, we get
all CDD values through the MessageBlock, then re-configure the DDRC
timing of WWT/WRT/RRT/RWT with comparing MAX CDD values.
Signed-off-by: Ye Li
Acked-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/ddr.h | 2 +
drivers/ddr/imx/imx9/ddr_init.c | 122 +++
2 files changed, 124 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h
b/arch/arm/include/asm/arch-imx9/ddr.h
index 62e6f7dda53..8e4f946e5b0 100644
--- a/arch/arm/include/asm/arch-imx9/ddr.h
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -14,7 +14,9 @@
#define DDRMIX_BLK_CTRL_BASE 0x4E01
#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24)
+#define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104)
#define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110)
+#define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160)
#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)
#define SRC_BASE_ADDR (0x4446)
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
index 8b8ec7f8de3..a1d953026f3 100644
--- a/drivers/ddr/imx/imx9/ddr_init.c
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -12,6 +12,13 @@
#include
#include
+static unsigned int g_cdd_rr_max[4];
+static unsigned int g_cdd_rw_max[4];
+static unsigned int g_cdd_wr_max[4];
+static unsigned int g_cdd_ww_max[4];
+
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+
void ddrphy_coldreset(void)
{
/* dramphy_apb_n default 1 , assert -> 0, de_assert -> 1 */
@@ -74,8 +81,121 @@ void ddrc_config(struct dram_cfg_param *ddrc_config, int
num)
}
}
+static unsigned int look_for_max(unsigned int data[], unsigned int addr_start,
+unsigned int addr_end)
+{
+ unsigned int i, imax = 0;
+
+ for (i = addr_start; i <= addr_end; i++) {
+ if (((data[i] >> 7) == 0) && data[i] > imax)
+ imax = data[i];
+ }
+
+ return imax;
+}
+
void get_trained_CDD(u32 fsp)
{
+ unsigned int i, tmp;
+ unsigned int cdd_cha[12], cdd_chb[12];
+ unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max,
cdd_cha_ww_max;
+ unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max,
cdd_chb_ww_max;
+
+ for (i = 0; i < 6; i++) {
+ tmp = dwc_ddrphy_apb_rd(0x54013 + i);
+ cdd_cha[i * 2] = tmp & 0xff;
+ cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
+ }
+
+ for (i = 0; i < 7; i++) {
+ tmp = dwc_ddrphy_apb_rd(0x5402c + i);
+
+ if (i == 0) {
+ cdd_chb[0] = (tmp >> 8) & 0xff;
+ } else if (i == 6) {
+ cdd_chb[11] = tmp & 0xff;
+ } else {
+ cdd_chb[i * 2 - 1] = tmp & 0xff;
+ cdd_chb[i * 2] = (tmp >> 8) & 0xff;
+ }
+ }
+
+ cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1);
+ cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5);
+ cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9);
+ cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11);
+ cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1);
+ cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5);
+ cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9);
+ cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11);
+ g_cdd_rr_max[fsp] = cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max :
cdd_chb_rr_max;
+ g_cdd_rw_max[fsp] = cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max :
cdd_chb_rw_max;
+ g_cdd_wr_max[fsp] = cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max :
cdd_chb_wr_max;
+ g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max :
cdd_chb_ww_max;
+}
+
+void update_umctl2_rank_space_setting(unsigned int pstat_num)
+{
+ u32 tmp, tmp_t;
+
+ int wwt, rrt, wrt, rwt;
+ int ext_wwt, ext_rrt, ext_wrt, ext_rwt;
+ int max_wwt, max_rrt, max_wrt, max_rwt;
+
+ /* read wwt, rrt, wrt, rwt fields from timing_cfg_0 */
+ tmp = readl(REG_DDR_TIMING_CFG_0);
+ wwt = (tmp >> 24) & 0x3;
+ rrt = (tmp >> 26) & 0x3;
+ wrt = (tmp >> 28) & 0x3;
+ rwt = (tmp >> 30) & 0x3;
+
+ /* read rxt_wwt, ext_rrt, ext_wrt, ext_rwt fields from timing_cfg_4 */
+ tmp_t = readl(REG_DDR_TIMING_CFG_4);
+ ext_wwt = (tmp >> 8) & 0x1;
+ ext_rrt = (tmp >> 10) & 0x1;
+ ext_wrt = (tmp >> 12) & 0x1;
+ ext_rwt = (tmp >> 14) & 0x3;
+
+ wwt = (ext_wwt << 2) | wwt;
+ rrt = (ext_rrt << 2) | wwt;
+ wrt = (ext_wrt << 2) | wrt;
+ rwt = (ext_rwt << 2) | rwt;
+
+ /* calculate the maximum between controller and cdd values */
+
[PATCH 33/42] arm: dts: imx93: add tmu
From: Peng Fan
Add tmu nodes and thermal zone
Signed-off-by: Peng Fan
---
arch/arm/dts/imx93.dtsi | 48 +
1 file changed, 48 insertions(+)
diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi
index 73ecd953ec8..13cf32d4b27 100644
--- a/arch/arm/dts/imx93.dtsi
+++ b/arch/arm/dts/imx93.dtsi
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include "imx93-pinfunc.h"
@@ -116,6 +117,38 @@
interrupt-parent = <&gic>;
};
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <8>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu-crit {
+ temperature = <9>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&A55_0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
+ <&A55_1 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -309,6 +342,21 @@
reg = <0x4448 0x1>;
};
+ tmu: tmu@44482000 {
+ compatible = "fsl,imx93-tmu";
+ reg = <0x44482000 0x1000>;
+ clocks = <&clk IMX93_CLK_TMC_GATE>;
+ little-endian;
+ fsl,tmu-calibration = <0x000e 0x80da
+ 0x0029 0x80e9
+ 0x0056 0x8102
+ 0x00a2 0x812a
+ 0x0116 0x8166
+ 0x0195 0x81a7
+ 0x01b2 0x81b6>;
+ #thermal-sensor-cells = <1>;
+ };
+
adc1: adc@4453 {
compatible = "nxp,imx93-adc";
reg = <0x4453 0x1>;
--
2.40.0
[PATCH 27/42] imx9: add i.MX93 variants support
From: Peng Fan
According to datasheet, iMX93 has fused parts with CORE1 or NPU or
both disabled. So update code to support it, the kernel device tree
runtime update will be added in future patches.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx/cpu.h | 7 +++
arch/arm/include/asm/mach-imx/sys_proto.h | 12 ++-
arch/arm/mach-imx/imx9/soc.c | 25 ++-
drivers/cpu/imx8_cpu.c| 14 +
4 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h
b/arch/arm/include/asm/arch-imx/cpu.h
index a666271fc11..cbd2717f97c 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -61,6 +61,13 @@
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
#define MXC_CPU_IMX93 0xC1 /* dummy ID */
+#define MXC_CPU_IMX93510xC2 /* dummy ID */
+#define MXC_CPU_IMX93320xC3 /* dummy ID */
+#define MXC_CPU_IMX93310xC4 /* dummy ID */
+#define MXC_CPU_IMX93220xC5 /* dummy ID */
+#define MXC_CPU_IMX93210xC6 /* dummy ID */
+#define MXC_CPU_IMX93120xC7 /* dummy ID */
+#define MXC_CPU_IMX93110xC8 /* dummy ID */
#define MXC_SOC_MX60x60
#define MXC_SOC_MX70x70
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 2eacddb51f5..85d9ca60b14 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -82,7 +82,17 @@ struct bd_info;
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
-#define is_imx93() (is_cpu_type(MXC_CPU_IMX93))
+#define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331)
|| \
+ is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || \
+ is_cpu_type(MXC_CPU_IMX9322) || is_cpu_type(MXC_CPU_IMX9321) || \
+ is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311))
+#define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351))
+#define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332))
+#define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331))
+#define is_imx9322() (is_cpu_type(MXC_CPU_IMX9322))
+#define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321))
+#define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312))
+#define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311))
#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 363dd39fc41..074df1e73cf 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -159,11 +159,34 @@ static void set_cpu_info(struct sentinel_get_info_data
*info)
memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32));
}
+static u32 get_cpu_variant_type(u32 type)
+{
+ /* word 19 */
+ u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2));
+ u32 val2 = readl((ulong)FSB_BASE_ADDR + 0x8000 + (20 << 2));
+ bool npu_disable = !!(val & BIT(13));
+ bool core1_disable = !!(val & BIT(15));
+ u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
+
+ if ((val2 & pack_9x9_fused) == pack_9x9_fused)
+ type = MXC_CPU_IMX9322;
+
+ if (npu_disable && core1_disable)
+ return type + 3;
+ else if (npu_disable)
+ return type + 2;
+ else if (core1_disable)
+ return type + 1;
+
+ return type;
+}
+
u32 get_cpu_rev(void)
{
u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
- return (MXC_CPU_IMX93 << 12) | (CHIP_REV_1_0 + rev);
+ return (get_cpu_variant_type(MXC_CPU_IMX93) << 12) |
+ (CHIP_REV_1_0 + rev);
}
#define UNLOCK_WORD 0xD928C520 /* unlock word */
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 304d5e59013..98ff95f5ff5 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -39,6 +39,20 @@ static const char *get_imx_type_str(u32 imxtype)
return "8QM";
case MXC_CPU_IMX93:
return "93(52)";/* iMX93 Dual core with NPU */
+ case MXC_CPU_IMX9351:
+ return "93(51)";/* iMX93 Single core with NPU */
+ case MXC_CPU_IMX9332:
+ return "93(32)";/* iMX93 Dual core without NPU */
+ case MXC_CPU_IMX9331:
+ return "93(31)";/* iMX93 Single core without NPU */
+ case MXC_CPU_IMX9322:
+ return "93(22)";/* iMX93 9x9 Dual core */
+ case MXC_CPU_IMX9321:
+ return "93(21)";/* iMX93 9x9 Single core */
+ case MXC_CPU_IMX9312:
+ return "93(12)";/* iMX93 9x9 Dual core without NPU */
+ case MXC_CPU_IMX9311:
+ return "93(11)";/* iMX93 9x9 Single core without NPU */
default:
return "??";
}
--
2.
[PATCH 29/42] imx9: use i.MX generic rom api function
From: Peng Fan
There is no need to save gd with using the generic rom api function, so
simplify code.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index f91f838e41a..22152172169 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -49,15 +49,12 @@ __weak int board_mmc_get_env_dev(int devno)
int mmc_get_env_dev(void)
{
- volatile gd_t *pgd = gd;
int ret;
u32 boot;
u16 boot_type;
u8 boot_instance;
- ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
- ((uintptr_t)&boot) ^ QUERY_BT_DEV);
- set_gd(pgd);
+ ret = rom_api_query_boot_infor(QUERY_BT_DEV, &boot);
if (ret != ROM_API_OKAY) {
puts("ROMAPI: failure at query_boot_info\n");
--
2.40.0
[PATCH 28/42] imx9: correct coding style
From: Peng Fan
The end brace should be in a new line
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 074df1e73cf..f91f838e41a 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -44,7 +44,8 @@ struct rom_api *g_rom_api = (struct rom_api *)0x1980;
#ifdef CONFIG_ENV_IS_IN_MMC
__weak int board_mmc_get_env_dev(int devno)
{
- return devno; }
+ return devno;
+}
int mmc_get_env_dev(void)
{
--
2.40.0
[PATCH 26/42] imx9: clock: config arm alt root to 500mhz
From: Peng Fan
Config the A55 alt root clock to 500MHz(LD mode frequency)
by default. Normally, this clock root is only used as an
intermediate clock soure for A55 core/dsu when change the
ARM PLL frequency.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/clock.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 3faab0685f7..957f80fce2e 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -727,6 +727,12 @@ struct imx_clk_setting imx_clk_settings[] = {
};
#else
struct imx_clk_setting imx_clk_settings[] = {
+ /*
+* Set A55 clk to 500M. This clock root is normally used as intermediate
+* clock source for A55 core/DSU when doing ARM PLL reconfig. set it to
+* 500MHz(LD mode frequency) should be ok.
+*/
+ {ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2},
/* Set A55 periphal to 333M */
{ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3},
/* Set A55 mtr bus to 133M */
--
2.40.0
[PATCH 25/42] imx9: clock: add CONFIG_IMX9_LOW_DRIVE_MODE support
From: Peng Fan
Add CONFIG_IMX9_LOW_DRIVE_MODE in imx9 clk, later we will
add board support
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/Kconfig | 5
arch/arm/mach-imx/imx9/clock.c | 55 +++---
2 files changed, 56 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index c06102bae07..c51f80f311a 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -5,6 +5,11 @@ config AHAB_BOOT
help
This option enables the support for AHAB secure boot.
+config IMX9_LOW_DRIVE_MODE
+bool "Configure to i.MX9 low drive mode"
+help
+This option enables the settings for iMX9 low drive mode.
+
config IMX9
bool
select HAS_CAAM
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 38e4cbbcc37..3faab0685f7 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -601,21 +601,27 @@ void init_uart_clk(u32 index)
void init_clk_usdhc(u32 index)
{
- /* 400 Mhz */
+ u32 div;
+
+ if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+ div = 3; /* 266.67 Mhz */
+ else
+ div = 2; /* 400 Mhz */
+
switch (index) {
case 0:
ccm_lpcg_on(CCGR_USDHC1, 0);
- ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, 2);
+ ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, div);
ccm_lpcg_on(CCGR_USDHC1, 1);
break;
case 1:
ccm_lpcg_on(CCGR_USDHC2, 0);
- ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, 2);
+ ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, div);
ccm_lpcg_on(CCGR_USDHC2, 1);
break;
case 2:
ccm_lpcg_on(CCGR_USDHC3, 0);
- ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, 2);
+ ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, div);
ccm_lpcg_on(CCGR_USDHC3, 1);
break;
default:
@@ -681,8 +687,45 @@ void set_arm_clk(ulong freq)
ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL);
}
+void set_arm_core_max_clk(void)
+{
+ /* Increase ARM clock to max rate according to speed grade */
+ u32 speed = get_cpu_speed_grade_hz();
+
+ set_arm_clk(speed);
+}
+
#endif
+#if IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)
+struct imx_clk_setting imx_clk_settings[] = {
+ /* Set A55 clk to 500M */
+ {ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2},
+ /* Set A55 periphal to 200M */
+ {ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD1, 4},
+ /* Set A55 mtr bus to 133M */
+ {ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
+
+ /* Sentinel to 133M */
+ {SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
+ /* Bus_wakeup to 133M */
+ {BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
+ /* Bus_AON to 133M */
+ {BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
+ /* M33 to 133M */
+ {M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
+ /* WAKEUP_AXI to 200M */
+ {WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD1, 4},
+ /* SWO TRACE to 133M */
+ {SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
+ /* M33 systetick to 24M */
+ {M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
+ /* NIC to 250M */
+ {NIC_CLK_ROOT, SYS_PLL_PFD0, 4},
+ /* NIC_APB to 133M */
+ {NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
+};
+#else
struct imx_clk_setting imx_clk_settings[] = {
/* Set A55 periphal to 333M */
{ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3},
@@ -710,6 +753,7 @@ struct imx_clk_setting imx_clk_settings[] = {
/* NIC_APB to 133M */
{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
};
+#endif
int clock_init(void)
{
@@ -720,6 +764,9 @@ int clock_init(void)
imx_clk_settings[i].src,
imx_clk_settings[i].div);
}
+ if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+ set_arm_clk(MHZ(900));
+
/* allow for non-secure access */
for (i = 0; i < OSCPLL_END; i++)
ccm_clk_src_tz_access(i, true, false, false);
--
2.40.0
[PATCH 24/42] imx9: clock: clear HW_CTRL_SEL
From: Peng Fan The HW_CTRL_SEL should be cleared when configuring PLL to avoid potential glitch Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx9/clock.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index a5f95fbcb8a..38e4cbbcc37 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -206,6 +206,9 @@ int configure_intpll(enum ccm_clk_src pll, u32 freq) return -EPERM; } + /* Clear PLL HW CTRL SEL */ + setbits_le32(®->ctrl.reg_clr, PLL_CTRL_HW_CTRL_SEL); + /* Bypass the PLL to ref */ writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_set); -- 2.40.0
[PATCH 23/42] imx9: Get market segment and speed grading
From: Peng Fan
Get the chip's market segment and speed grading from fuse and print
them in boot log as other i.MX series.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 3 +
arch/arm/mach-imx/imx9/soc.c | 81 ++-
2 files changed, 83 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 065fd1f96de..76d241eab09 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -48,6 +48,9 @@
#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII(0x1 << 1)
#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN(0x1 << 0)
+#define MARKETING_GRADING_MASK GENMASK(5, 4)
+#define SPEED_GRADING_MASK GENMASK(11, 6)
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include
#include
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index dcabfe34aca..363dd39fc41 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -26,12 +26,15 @@
#include
#include
#include
+#include
#include
+#include
+#include
+#include
#include
#include
#include
#include
-#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -73,6 +76,82 @@ int mmc_get_env_dev(void)
}
#endif
+/*
+ * SPEED_GRADE[5:4]SPEED_GRADE[3:0]MHz
+ * xx 2300
+ * xx 00012200
+ * xx 00102100
+ * xx 00112000
+ * xx 01001900
+ * xx 01011800
+ * xx 01101700
+ * xx 01111600
+ * xx 10001500
+ * xx 10011400
+ * xx 10101300
+ * xx 10111200
+ * xx 11001100
+ * xx 11011000
+ * xx 1110900
+ * xx 800
+ */
+u32 get_cpu_speed_grade_hz(void)
+{
+ u32 speed, max_speed;
+ u32 val;
+
+ fuse_read(2, 3, &val);
+ val = FIELD_GET(SPEED_GRADING_MASK, val) & 0xF;
+
+ speed = MHZ(2300) - val * MHZ(100);
+
+ if (is_imx93())
+ max_speed = MHZ(1700);
+
+ /* In case the fuse of speed grade not programmed */
+ if (speed > max_speed)
+ speed = max_speed;
+
+ return speed;
+}
+
+/*
+ * `00` - Consumer 0C to 95C
+ * `01` - Ext. Consumer -20C to 105C
+ * `10` - Industrial -40C to 105C
+ * `11` - Automotive -40C to 125C
+ */
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+ u32 val;
+
+ fuse_read(2, 3, &val);
+ val = FIELD_GET(MARKETING_GRADING_MASK, val);
+
+ if (minc && maxc) {
+ if (val == TEMP_AUTOMOTIVE) {
+ *minc = -40;
+ *maxc = 125;
+ } else if (val == TEMP_INDUSTRIAL) {
+ *minc = -40;
+ *maxc = 105;
+ } else if (val == TEMP_EXTCOMMERCIAL) {
+ if (is_imx93()) {
+ /* imx93 only has extended industrial*/
+ *minc = -40;
+ *maxc = 125;
+ } else {
+ *minc = -20;
+ *maxc = 105;
+ }
+ } else {
+ *minc = 0;
+ *maxc = 95;
+ }
+ }
+ return val;
+}
+
static void set_cpu_info(struct sentinel_get_info_data *info)
{
gd->arch.soc_rev = info->soc;
--
2.40.0
[PATCH 22/42] imx9: soc: support reset cause
From: Peng Fan
Support print reset cause. Since SRSR is not accessible from non-secure
world, so first save it to grp0, then read it in non-secure world.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 59
1 file changed, 59 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index e4e9eca101e..dcabfe34aca 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -19,6 +19,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -408,6 +410,18 @@ void get_board_serial(struct tag_serialnr *serialnr)
}
#endif
+static void save_reset_cause(void)
+{
+ struct src_general_regs *src = (struct src_general_regs
*)SRC_GLOBAL_RBASE;
+ u32 srsr = readl(&src->srsr);
+
+ /* clear srsr in sec mode */
+ writel(srsr, &src->srsr);
+
+ /* Save value to GPR1 to pass to nonsecure */
+ writel(srsr, &src->gpr[0]);
+}
+
int arch_cpu_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
@@ -417,6 +431,9 @@ int arch_cpu_init(void)
clock_init();
trdc_early_init();
+
+ /* Save SRC SRSR to GPR1 and clear it */
+ save_reset_cause();
}
return 0;
@@ -650,3 +667,45 @@ int m33_prepare(void)
return 0;
}
+
+int psci_sysreset_get_status(struct udevice *dev, char *buf, int size)
+{
+ static const char *reset_cause[] = {
+ "POR ",
+ "JTAG ",
+ "IPP USER ",
+ "WDOG1 ",
+ "WDOG2 ",
+ "WDOG3 ",
+ "WDOG4 ",
+ "WDOG5 ",
+ "TEMPSENSE ",
+ "CSU ",
+ "JTAG_SW ",
+ "M33_REQ ",
+ "M33_LOCKUP ",
+ "UNK ",
+ "UNK ",
+ "UNK "
+ };
+
+ struct src_general_regs *src = (struct src_general_regs
*)SRC_GLOBAL_RBASE;
+ u32 srsr;
+ u32 i;
+ int res;
+
+ srsr = readl(&src->gpr[0]);
+
+ for (i = ARRAY_SIZE(reset_cause); i > 0; i--) {
+ if (srsr & (BIT(i - 1)))
+ break;
+ }
+
+ res = snprintf(buf, size, "Reset Status: %s\n", i ? reset_cause[i - 1]
: "unknown reset");
+ if (res < 0) {
+ dev_err(dev, "Could not write reset status message (err =
%d)\n", res);
+ return -EIO;
+ }
+
+ return 0;
+}
--
2.40.0
[PATCH 15/42] imx9: cut off OPTEE memory region from U-Boot
From: Peng Fan
OPTEE memory region is set secure access only in ATF with configuration
to TRDC, and need to remove it from U-Boot, otherwise U-Boot and Kernel
may crash when accessing the memory
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 149 ++-
1 file changed, 148 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index a16e22ea6bb..a27262492e7 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -180,13 +180,160 @@ static struct mm_region imx93_mem_map[] = {
struct mm_region *mem_map = imx93_mem_map;
+static unsigned int imx9_find_dram_entry_in_mem_map(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx93_mem_map); i++)
+ if (imx93_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
+ return i;
+
+ hang(); /* Entry not found, this must never happen. */
+}
+
+void enable_caches(void)
+{
+ /* If OPTEE runs, remove OPTEE memory from MMU table to avoid
speculative prefetch
+* If OPTEE does not run, still update the MMU table according to dram
banks structure
+* to set correct dram size from board_phys_sdram_size
+*/
+ int i = 0;
+ /*
+* please make sure that entry initial value matches
+* imx93_mem_map for DRAM1
+*/
+ int entry = imx9_find_dram_entry_in_mem_map();
+ u64 attrs = imx93_mem_map[entry].attrs;
+
+ while (i < CONFIG_NR_DRAM_BANKS &&
+ entry < ARRAY_SIZE(imx93_mem_map)) {
+ if (gd->bd->bi_dram[i].start == 0)
+ break;
+ imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start;
+ imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start;
+ imx93_mem_map[entry].size = gd->bd->bi_dram[i].size;
+ imx93_mem_map[entry].attrs = attrs;
+ debug("Added memory mapping (%d): %llx %llx\n", entry,
+ imx93_mem_map[entry].phys, imx93_mem_map[entry].size);
+ i++; entry++;
+ }
+
+ icache_enable();
+ dcache_enable();
+}
+
+__weak int board_phys_sdram_size(phys_size_t *size)
+{
+ if (!size)
+ return -EINVAL;
+
+ *size = PHYS_SDRAM_SIZE;
+
+#ifdef PHYS_SDRAM_2_SIZE
+ *size += PHYS_SDRAM_2_SIZE;
+#endif
+ return 0;
+}
+
int dram_init(void)
{
- gd->ram_size = PHYS_SDRAM_SIZE;
+ phys_size_t sdram_size;
+ int ret;
+
+ ret = board_phys_sdram_size(&sdram_size);
+ if (ret)
+ return ret;
+
+ /* rom_pointer[1] contains the size of TEE occupies */
+ if (rom_pointer[1])
+ gd->ram_size = sdram_size - rom_pointer[1];
+ else
+ gd->ram_size = sdram_size;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ int bank = 0;
+ int ret;
+ phys_size_t sdram_size;
+ phys_size_t sdram_b1_size, sdram_b2_size;
+
+ ret = board_phys_sdram_size(&sdram_size);
+ if (ret)
+ return ret;
+
+ /* Bank 1 can't cross over 4GB space */
+ if (sdram_size > 0x8000) {
+ sdram_b1_size = 0x8000;
+ sdram_b2_size = sdram_size - 0x8000;
+ } else {
+ sdram_b1_size = sdram_size;
+ sdram_b2_size = 0;
+ }
+
+ gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+ if (rom_pointer[1]) {
+ phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
+ phys_size_t optee_size = (size_t)rom_pointer[1];
+
+ gd->bd->bi_dram[bank].size = optee_start -
gd->bd->bi_dram[bank].start;
+ if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
+ if (++bank >= CONFIG_NR_DRAM_BANKS) {
+ puts("CONFIG_NR_DRAM_BANKS is not enough\n");
+ return -1;
+ }
+
+ gd->bd->bi_dram[bank].start = optee_start + optee_size;
+ gd->bd->bi_dram[bank].size = PHYS_SDRAM +
+ sdram_b1_size - gd->bd->bi_dram[bank].start;
+ }
+ } else {
+ gd->bd->bi_dram[bank].size = sdram_b1_size;
+ }
+
+ if (sdram_b2_size) {
+ if (++bank >= CONFIG_NR_DRAM_BANKS) {
+ puts("CONFIG_NR_DRAM_BANKS is not enough for
SDRAM_2\n");
+ return -1;
+ }
+ gd->bd->bi_dram[bank].start = 0x1UL;
+ gd->bd->bi_dram[bank].size = sdram_b2_size;
+ }
return 0;
}
+phys_size_t get_effective_memsize(void)
+{
+ int ret;
+ phys_size_t sdram_size;
+ phys_size_t sdram_b1_size;
+
+ ret = board_phys_sdram_size(&sdram_size);
+ if (!ret) {
+ /* Bank 1 can't cross over 4GB space */
+ if (sdram_size > 0x80
[PATCH 16/42] imx9: Change hard coded MAC to read from fuse
From: Ye Li
The MAC addresses are hard coded for bring up. Change it to support
reading from fuse.
Reviewed-by: Jacky Bai
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 49 +++-
1 file changed, 43 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index a27262492e7..e4e9eca101e 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -336,12 +337,48 @@ phys_size_t get_effective_memsize(void)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
- mac[0] = 0x1;
- mac[1] = 0x2;
- mac[2] = 0x3;
- mac[3] = 0x4;
- mac[4] = 0x5;
- mac[5] = 0x6;
+ u32 val[2] = {};
+ int ret;
+
+ if (dev_id == 0) {
+ ret = fuse_read(39, 3, &val[0]);
+ if (ret)
+ goto err;
+
+ ret = fuse_read(39, 4, &val[1]);
+ if (ret)
+ goto err;
+
+ mac[0] = val[1] >> 8;
+ mac[1] = val[1];
+ mac[2] = val[0] >> 24;
+ mac[3] = val[0] >> 16;
+ mac[4] = val[0] >> 8;
+ mac[5] = val[0];
+
+ } else {
+ ret = fuse_read(39, 5, &val[0]);
+ if (ret)
+ goto err;
+
+ ret = fuse_read(39, 4, &val[1]);
+ if (ret)
+ goto err;
+
+ mac[0] = val[1] >> 24;
+ mac[1] = val[1] >> 16;
+ mac[2] = val[0] >> 24;
+ mac[3] = val[0] >> 16;
+ mac[4] = val[0] >> 8;
+ mac[5] = val[0];
+ }
+
+ debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
+ __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ return;
+err:
+ memset(mac, 0, 6);
+ printf("%s: fuse read err: %d\n", __func__, ret);
}
int print_cpuinfo(void)
--
2.40.0
[PATCH 18/42] imx9: imx93_evk: drop unused macro
From: Peng Fan Drop unused macro Signed-off-by: Peng Fan --- include/configs/imx93_evk.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 7b7bef3ca75..2705587a015 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -131,8 +131,6 @@ #define PHYS_SDRAM 0x8000 #define PHYS_SDRAM_SIZE0x8000 /* 2GB DDR */ -#define CFG_SYS_FSL_USDHC_NUM 2 - /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG3_BASE_ADDR -- 2.40.0
[PATCH 21/42] watchdog: ulp_wdog: guard reset_cpu with condition check
From: Peng Fan
There will be build error if CONFIG_SYSRESET is enabled, so guard
the reset_cpu with condition check here
Signed-off-by: Peng Fan
---
drivers/watchdog/ulp_wdog.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index c21aa3af55f..0eea04ed2c6 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -122,6 +122,7 @@ void hw_watchdog_init(void)
ulp_watchdog_init(wdog, CONFIG_WATCHDOG_TIMEOUT_MSECS);
}
+#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
@@ -159,6 +160,7 @@ void reset_cpu(void)
while (1);
}
+#endif
static int ulp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
--
2.40.0
[PATCH 19/42] imx9: imx93_evk: select IMX_TMU
From: Peng Fan Select thermal config to print current temperature Signed-off-by: Peng Fan --- configs/imx93_11x11_evk_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index f116d52a655..9f376d39c03 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -112,6 +112,8 @@ CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y CONFIG_ULP_WATCHDOG=y CONFIG_LZO=y CONFIG_BZIP2=y -- 2.40.0
[PATCH 20/42] imx9: imx93_evk: enable CONFIG_WDT
From: Peng Fan Without this config, there is boot error: Error binding ulp_wdt driver Signed-off-by: Peng Fan --- configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 9f376d39c03..c2709f8c66c 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -115,5 +115,6 @@ CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y CONFIG_LZO=y CONFIG_BZIP2=y -- 2.40.0
[PATCH 17/42] imx9: imx93_evk: enable CPU_IMX
From: Peng Fan select CONFIG_CPU_IMX to display cpu info Signed-off-by: Peng Fan --- configs/imx93_11x11_evk_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 4f8777161e4..f116d52a655 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -81,6 +81,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_CPU_IMX=y CONFIG_IMX_RGPIO2P=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -- 2.40.0
[PATCH 13/42] imx9: correct getting LPI2C clk
From: Peng Fan LPI2C_CLK_ROOT should be used instead of LPUART_CLK_ROOT for i2c Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx9/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index f6021502b3d..a0efee96e51 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -574,7 +574,7 @@ u32 imx_get_i2cclk(u32 i2c_num) if (i2c_num > 7) return -EINVAL; - return ccm_clk_root_get_rate(LPUART1_CLK_ROOT + i2c_num); + return ccm_clk_root_get_rate(LPI2C1_CLK_ROOT + i2c_num); } u32 get_lpuart_clk(void) -- 2.40.0
[PATCH 11/42] imx9: add more PLL settings
From: Peng Fan
Add more PLL settings for A55 and Display
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/clock.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 51aa259aa05..7d3a4c01333 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -26,6 +26,7 @@ static struct anatop_reg *ana_regs = (struct anatop_reg
*)ANATOP_BASE_ADDR;
static struct imx_intpll_rate_table imx9_intpll_tbl[] = {
INT_PLL_RATE(18U, 1, 150, 2), /* 1.8Ghz */
INT_PLL_RATE(17U, 1, 141, 2), /* 1.7Ghz */
+ INT_PLL_RATE(15U, 1, 125, 2), /* 1.5Ghz */
INT_PLL_RATE(14U, 1, 175, 3), /* 1.4Ghz */
INT_PLL_RATE(10U, 1, 166, 4), /* 1000Mhz */
INT_PLL_RATE(9U, 1, 150, 4), /* 900Mhz */
@@ -35,8 +36,11 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
FRAC_PLL_RATE(10U, 1, 166, 4, 2, 3), /* 1000Mhz */
FRAC_PLL_RATE(93300U, 1, 155, 4, 1, 2), /* 933Mhz */
FRAC_PLL_RATE(7U, 1, 145, 5, 5, 6), /* 700Mhz */
+ FRAC_PLL_RATE(48400U, 1, 121, 6, 0, 1),
+ FRAC_PLL_RATE(44533U, 1, 167, 9, 0, 1),
FRAC_PLL_RATE(46600U, 1, 155, 8, 1, 3), /* 466Mhz */
FRAC_PLL_RATE(4U, 1, 200, 12, 0, 1), /* 400Mhz */
+ FRAC_PLL_RATE(3U, 1, 150, 12, 0, 1),
};
/* return in khz */
--
2.40.0
[PATCH 12/42] imx9: use parameter freq when set_arm_clk
From: Peng Fan
The freq parameter was ignored, should use it when configuring ARM PLL
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/clock.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 7d3a4c01333..f6021502b3d 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -674,7 +674,7 @@ void set_arm_clk(ulong freq)
{
/* Increase ARM clock to 1.7Ghz */
ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM);
- configure_intpll(ARM_PLL_CLK, 17);
+ configure_intpll(ARM_PLL_CLK, freq);
ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL);
}
--
2.40.0
[PATCH 08/42] imx: imx8_cpu: support get temperature for i.MX9
From: Peng Fan
Use CONFIG_DM_THERMAL to make the temperature function could be reused
by i.MX8 and i.MX9
Signed-off-by: Peng Fan
---
drivers/cpu/imx8_cpu.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 2d3df419f1c..4da7a99bf30 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -89,15 +89,19 @@ static void set_core_data(struct udevice *dev)
}
}
-#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
+#if IS_ENABLED(CONFIG_DM_THERMAL)
static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
{
struct udevice *thermal_dev;
int cpu_tmp, ret;
int idx = 1; /* use "cpu-thermal0" device */
- if (plat->cpu_rsrc == SC_R_A72)
- idx = 2; /* use "cpu-thermal1" device */
+ if (IS_ENABLED(CONFIG_IMX8)) {
+ if (plat->cpu_rsrc == SC_R_A72)
+ idx = 2; /* use "cpu-thermal1" device */
+ } else {
+ idx = 1;
+ }
ret = uclass_get_device(UCLASS_THERMAL, idx, &thermal_dev);
if (!ret) {
@@ -128,7 +132,7 @@ static int cpu_imx_get_desc(const struct udevice *dev, char
*buf, int size)
ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz",
plat->type, plat->rev, plat->name, plat->freq_mhz);
- if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
+ if (IS_ENABLED(CONFIG_DM_THERMAL)) {
temp = cpu_imx_get_temp(plat);
buf = buf + ret;
size = size - ret;
--
2.40.0
[PATCH 10/42] imx9: configure M33 systick to 24M
From: Peng Fan The M33 systick should be 24M per reference mannual, so correct it. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx9/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 04f3116fd1c..51aa259aa05 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -700,8 +700,8 @@ int clock_init(void) ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2); /* SWO TRACE to 133M */ ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); - /* M33 systetick to 133M */ - ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 systetick to 24M */ + ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1); /* NIC to 400M */ ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2); /* NIC_APB to 133M */ -- 2.40.0
[PATCH 07/42] imx: imx8_cpu: support i.MX9
From: Peng Fan
Add CPU_IMX Kconfig
Support imx8_cpu driver for i.MX9
Signed-off-by: Peng Fan
---
drivers/cpu/Kconfig| 6 +++
drivers/cpu/Makefile | 1 +
drivers/cpu/imx8_cpu.c | 83 --
3 files changed, 62 insertions(+), 28 deletions(-)
diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
index 3bf04105e5e..1c3c810651e 100644
--- a/drivers/cpu/Kconfig
+++ b/drivers/cpu/Kconfig
@@ -7,6 +7,12 @@ config CPU
they can work correctly in the OS. This provides a framework for
finding out information about available CPUs and making changes.
+config CPU_IMX
+ bool "Enable i.MX CPU driver"
+ depends on CPU && ARM64
+ help
+ Support CPU cores for SoCs of the i.MX series.
+
config CPU_MPC83XX
bool "Enable MPC83xx CPU driver"
depends on CPU && MPC83xx
diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
index 3b38ba9c589..d4bbf6fa5e0 100644
--- a/drivers/cpu/Makefile
+++ b/drivers/cpu/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o
obj-$(CONFIG_ARCH_AT91) += at91_cpu.o
obj-$(CONFIG_ARCH_MEDIATEK) += mtk_cpu.o
+obj-$(CONFIG_CPU_IMX) += imx8_cpu.o
obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
obj-$(CONFIG_CPU_MICROBLAZE) += microblaze_cpu.o
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index e7f45e60dbd..2d3df419f1c 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -27,30 +28,43 @@ struct cpu_imx_plat {
u32 mpidr;
};
-static const char *get_imx8_type(u32 imxtype)
+static const char *get_imx_type_str(u32 imxtype)
{
switch (imxtype) {
case MXC_CPU_IMX8QXP:
case MXC_CPU_IMX8QXP_A0:
- return "QXP";
+ return "8QXP";
case MXC_CPU_IMX8QM:
- return "QM";
+ return "8QM";
+ case MXC_CPU_IMX93:
+ return "93(52)";/* iMX93 Dual core with NPU */
default:
return "??";
}
}
-static const char *get_imx8_rev(u32 rev)
+static const char *get_imx_rev_str(u32 rev)
{
- switch (rev) {
- case CHIP_REV_A:
- return "A";
- case CHIP_REV_B:
- return "B";
- case CHIP_REV_C:
- return "C";
- default:
- return "?";
+ static char revision[4];
+
+ if (IS_ENABLED(CONFIG_IMX8)) {
+ switch (rev) {
+ case CHIP_REV_A:
+ return "A";
+ case CHIP_REV_B:
+ return "B";
+ case CHIP_REV_C:
+ return "C";
+ default:
+ return "?";
+ }
+ } else {
+ revision[0] = '1' + (((rev & 0xf0) - CHIP_REV_1_0) >> 4);
+ revision[1] = '.';
+ revision[2] = '0' + (rev & 0xf);
+ revision[3] = '\0';
+
+ return revision;
}
}
@@ -67,6 +81,8 @@ static void set_core_data(struct udevice *dev)
} else if (device_is_compatible(dev, "arm,cortex-a72")) {
plat->cpu_rsrc = SC_R_A72;
plat->name = "A72";
+ } else if (device_is_compatible(dev, "arm,cortex-a55")) {
+ plat->name = "A55";
} else {
plat->cpu_rsrc = SC_R_A53;
plat->name = "?";
@@ -109,7 +125,7 @@ static int cpu_imx_get_desc(const struct udevice *dev, char
*buf, int size)
if (size < 100)
return -ENOSPC;
- ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
+ ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz",
plat->type, plat->rev, plat->name, plat->freq_mhz);
if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
@@ -174,7 +190,7 @@ static int cpu_imx_is_current(struct udevice *dev)
return 0;
}
-static const struct cpu_ops cpu_imx8_ops = {
+static const struct cpu_ops cpu_imx_ops = {
.get_desc = cpu_imx_get_desc,
.get_info = cpu_imx_get_info,
.get_count = cpu_imx_get_count,
@@ -182,21 +198,32 @@ static const struct cpu_ops cpu_imx8_ops = {
.is_current = cpu_imx_is_current,
};
-static const struct udevice_id cpu_imx8_ids[] = {
+static const struct udevice_id cpu_imx_ids[] = {
{ .compatible = "arm,cortex-a35" },
{ .compatible = "arm,cortex-a53" },
+ { .compatible = "arm,cortex-a55" },
{ .compatible = "arm,cortex-a72" },
{ }
};
-static ulong imx8_get_cpu_rate(struct udevice *dev)
+static ulong imx_get_cpu_rate(struct udevice *dev)
{
struct cpu_imx_plat *plat = dev_get_plat(dev);
+ struct clk clk;
ulong rate;
int ret;
- ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU,
-
[PATCH 09/42] imx: imx8_cpu: print cpu grade temperature
From: Peng Fan
Support print out cpu grade temperature
Signed-off-by: Peng Fan
---
drivers/cpu/imx8_cpu.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 4da7a99bf30..304d5e59013 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
@@ -121,10 +122,17 @@ static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
}
#endif
+__weak u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+ return 0;
+}
+
static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
{
struct cpu_imx_plat *plat = dev_get_plat(dev);
+ const char *grade;
int ret, temp;
+ int minc, maxc;
if (size < 100)
return -ENOSPC;
@@ -132,6 +140,27 @@ static int cpu_imx_get_desc(const struct udevice *dev,
char *buf, int size)
ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz",
plat->type, plat->rev, plat->name, plat->freq_mhz);
+ if (IS_ENABLED(CONFIG_IMX9)) {
+ switch (get_cpu_temp_grade(&minc, &maxc)) {
+ case TEMP_AUTOMOTIVE:
+ grade = "Automotive temperature grade ";
+ break;
+ case TEMP_INDUSTRIAL:
+ grade = "Industrial temperature grade ";
+ break;
+ case TEMP_EXTCOMMERCIAL:
+ grade = "Extended Consumer temperature grade ";
+ break;
+ default:
+ grade = "Consumer temperature grade ";
+ break;
+ }
+
+ buf = buf + ret;
+ size = size - ret;
+ ret = snprintf(buf, size, "\nCPU: %s (%dC to %dC)", grade,
minc, maxc);
+ }
+
if (IS_ENABLED(CONFIG_DM_THERMAL)) {
temp = cpu_imx_get_temp(plat);
buf = buf + ret;
--
2.40.0
[PATCH 06/42] imx: imx8_cpu: use static for local functions
From: Peng Fan
For local functions, use static for function.
Signed-off-by: Peng Fan
---
drivers/cpu/imx8_cpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index dc060513b38..e7f45e60dbd 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -27,7 +27,7 @@ struct cpu_imx_plat {
u32 mpidr;
};
-const char *get_imx8_type(u32 imxtype)
+static const char *get_imx8_type(u32 imxtype)
{
switch (imxtype) {
case MXC_CPU_IMX8QXP:
@@ -40,7 +40,7 @@ const char *get_imx8_type(u32 imxtype)
}
}
-const char *get_imx8_rev(u32 rev)
+static const char *get_imx8_rev(u32 rev)
{
switch (rev) {
case CHIP_REV_A:
@@ -101,7 +101,7 @@ static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
}
#endif
-int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
+static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
{
struct cpu_imx_plat *plat = dev_get_plat(dev);
int ret, temp;
--
2.40.0
[PATCH 05/42] imx: firmware: sci: add inline functions when IMX8 not enabled
From: Peng Fan
Since we might reuse some drivers for other platforms, while the drivers
have sci firmware api, so to avoid build failure add inline functions
Signed-off-by: Peng Fan
---
include/firmware/imx/sci/sci.h | 241 +
1 file changed, 241 insertions(+)
diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h
index dafe892aa4d..61c8211b443 100644
--- a/include/firmware/imx/sci/sci.h
+++ b/include/firmware/imx/sci/sci.h
@@ -57,6 +57,7 @@ static inline int sc_err_to_linux(sc_err_t err)
return ret;
}
+#if IS_ENABLED(CONFIG_IMX8)
/* PM API*/
int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode);
@@ -134,5 +135,245 @@ int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8
access, u32 *data);
int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access,
u32 *data0, u32 *data1, u32 *data2, u32 *data3,
u32 *data4, u8 size);
+#else
+/* PM API*/
+static inline int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t
resource,
+ sc_pm_power_mode_t mode)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t
resource,
+ sc_pm_power_mode_t *mode)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk,
+ sc_pm_clock_rate_t *rate)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk,
+ sc_pm_clock_rate_t *rate)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk,
+sc_bool_t enable, sc_bool_t autog)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk,
+sc_pm_clk_parent_t parent)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t
enable,
+ sc_faddr_t address)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt)
+{
+ return false;
+}
+
+static inline int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource)
+{
+ return -EOPNOTSUPP;
+}
+
+/* MISC API */
+static inline int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
sc_ctrl_t ctrl, u32 val)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource,
sc_ctrl_t ctrl, u32 *val)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev)
+{
+}
+
+static inline void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t
status)
+{
+}
+
+static inline int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit)
+{
+}
+
+static inline int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource,
sc_misc_temp_t temp,
+ s16 *celsius, s8 *tenths)
+{
+ return -EOPNOTSUPP;
+}
+
+/* RM API */
+static inline sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
+{
+ return true;
+}
+
+static inline int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t
addr_start,
+ sc_faddr_t addr_end)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
sc_rm_pt_t pt,
+ sc_rm_perm_t perm)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
sc_faddr_t *addr_start,
+ sc_faddr_t *addr_end)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t
resource)
+{
+ return true;
+}
+
+static inline int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt,
sc_bool_t secure,
+ sc_bool_t isolated, sc_bool_t
restricted,
+ sc_bool_t grant, sc_bool_t coherent)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t
pt_parent)
+{
+ return -EOPNOTSUPP;
+}
+
+stat
[PATCH 04/42] imx: move imx8 sci header file to include/firmware/imx
From: Peng Fan
Move imx8 sci header file to include/firmware/imx, then we could
use build macro to reuse some i.MX8 drivers for i.MX9, such as
drivers/cpu/imx8_cpu.c.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8/power-domain.h | 2 +-
arch/arm/include/asm/arch-imx8/sys_proto.h| 2 +-
arch/arm/mach-imx/cmd_dek.c | 2 +-
arch/arm/mach-imx/imx8/ahab.c | 2 +-
arch/arm/mach-imx/imx8/cpu.c | 2 +-
arch/arm/mach-imx/imx8/fdt.c | 2 +-
arch/arm/mach-imx/imx8/iomux.c| 2 +-
arch/arm/mach-imx/imx8/misc.c | 2 +-
arch/arm/mach-imx/imx8/snvs_security_sc.c | 2 +-
arch/arm/mach-imx/parse-container.c | 2 +-
.../imx8qm_rom7720_a1/imx8qm_rom7720_a1.c | 2 +-
board/advantech/imx8qm_rom7720_a1/spl.c | 2 +-
board/congatec/cgtqmx8/cgtqmx8.c | 2 +-
board/freescale/imx8qm_mek/imx8qm_mek.c | 2 +-
board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +-
board/freescale/imx8qxp_mek/spl.c | 2 +-
board/siemens/capricorn/board.c | 2 +-
board/toradex/apalis-imx8/apalis-imx8.c | 2 +-
board/toradex/colibri-imx8x/colibri-imx8x.c | 2 +-
drivers/clk/imx/clk-imx8.c| 2 +-
drivers/clk/imx/clk-imx8qm.c | 2 +-
drivers/clk/imx/clk-imx8qxp.c | 2 +-
drivers/cpu/imx8_cpu.c| 2 +-
drivers/cpu/imx9_cpu.c| 224 ++
drivers/misc/imx8/fuse.c | 2 +-
drivers/misc/imx8/scu.c | 2 +-
drivers/misc/imx8/scu_api.c | 2 +-
drivers/pinctrl/nxp/pinctrl-scu.c | 2 +-
.../power/domain/imx8-power-domain-legacy.c | 2 +-
drivers/power/domain/imx8-power-domain.c | 2 +-
drivers/thermal/imx_scu_thermal.c | 2 +-
.../firmware/imx}/sci/rpc.h | 0
.../firmware/imx}/sci/sci.h | 14 +-
.../firmware/imx}/sci/svc/misc/api.h | 0
.../firmware/imx}/sci/svc/pad/api.h | 0
.../firmware/imx}/sci/svc/pm/api.h| 0
.../firmware/imx}/sci/svc/rm/api.h| 2 +-
.../firmware/imx}/sci/svc/seco/api.h | 2 +-
.../firmware/imx}/sci/types.h | 0
39 files changed, 263 insertions(+), 39 deletions(-)
create mode 100644 drivers/cpu/imx9_cpu.c
rename {arch/arm/include/asm/arch-imx8 => include/firmware/imx}/sci/rpc.h
(100%)
rename {arch/arm/include/asm/arch-imx8 => include/firmware/imx}/sci/sci.h (94%)
rename {arch/arm/include/asm/arch-imx8 =>
include/firmware/imx}/sci/svc/misc/api.h (100%)
rename {arch/arm/include/asm/arch-imx8 =>
include/firmware/imx}/sci/svc/pad/api.h (100%)
rename {arch/arm/include/asm/arch-imx8 =>
include/firmware/imx}/sci/svc/pm/api.h (100%)
rename {arch/arm/include/asm/arch-imx8 =>
include/firmware/imx}/sci/svc/rm/api.h (98%)
rename {arch/arm/include/asm/arch-imx8 =>
include/firmware/imx}/sci/svc/seco/api.h (96%)
rename {arch/arm/include/asm/arch-imx8 => include/firmware/imx}/sci/types.h
(100%)
diff --git a/arch/arm/include/asm/arch-imx8/power-domain.h
b/arch/arm/include/asm/arch-imx8/power-domain.h
index 1db86a1209b..bdb0baa9844 100644
--- a/arch/arm/include/asm/arch-imx8/power-domain.h
+++ b/arch/arm/include/asm/arch-imx8/power-domain.h
@@ -6,7 +6,7 @@
#ifndef _ASM_ARCH_IMX8_POWER_DOMAIN_H
#define _ASM_ARCH_IMX8_POWER_DOMAIN_H
-#include
+#include
struct imx8_power_domain_plat {
sc_rsrc_t resource_id;
diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h
b/arch/arm/include/asm/arch-imx8/sys_proto.h
index d38f606e07e..e7625c42985 100644
--- a/arch/arm/include/asm/arch-imx8/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -3,7 +3,7 @@
* Copyright 2018 NXP
*/
-#include
+#include
#include
#include
#include
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index b65bf874b83..69ed57537b3 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -17,7 +17,7 @@
#include
#include
#ifdef CONFIG_IMX_SECO_DEK_ENCAP
-#include
+#include
#include
#endif
#include
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index 5a4d39cdaad..9addb824b6d 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -9,7 +9,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index be1f4edded1..894a8c14fe9 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -19,7 +19,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c
index a132ce2e6a3..02b3ee5c111 100644
--- a/arch/arm/mach-imx/imx8/fdt.c
+++ b/arch/arm/ma
[PATCH 03/42] imx: spl_imx_romapi: typo fix
From: Peng Fan
Unknow->Unknown
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/spl_imx_romapi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/spl_imx_romapi.c
b/arch/arm/mach-imx/spl_imx_romapi.c
index 830d5d12c25..9164045115f 100644
--- a/arch/arm/mach-imx/spl_imx_romapi.c
+++ b/arch/arm/mach-imx/spl_imx_romapi.c
@@ -367,7 +367,7 @@ int board_return_to_bootrom(struct spl_image_info
*spl_image,
printf("USB boot\n");
break;
default:
- printf("Unknow (0x%x)\n", bstage);
+ printf("Unknown (0x%x)\n", bstage);
}
if (is_boot_from_stream_device(boot))
--
2.40.0
[PATCH 02/42] thermal: imx_tmu: Update TMU driver to support iMX93
From: Ye Li
The TMU used on iMX93 is IP revision 2.1 which is different with previous
revision used on iMX8MQ. So add a new FLAG V4 for this revision to
distinguish the operations.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
drivers/thermal/Kconfig | 6 +--
drivers/thermal/imx_tmu.c | 101 ++
2 files changed, 104 insertions(+), 3 deletions(-)
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 97d4163e8ed..681b621760d 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -27,10 +27,10 @@ config IMX_SCU_THERMAL
trip is crossed
config IMX_TMU
-bool "Thermal Management Unit driver for NXP i.MX8M"
-depends on ARCH_IMX8M
+bool "Thermal Management Unit driver for NXP i.MX8M and iMX93"
+depends on ARCH_IMX8M || IMX93
help
- Support for Temperature sensors on NXP i.MX8M.
+ Support for Temperature sensors on NXP i.MX8M and iMX93.
It supports one critical trip point and one passive trip point.
The boot is hold to the cool device to throttle CPUs when the
passive trip is crossed
diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
index eb5605590fd..97efc550443 100644
--- a/drivers/thermal/imx_tmu.c
+++ b/drivers/thermal/imx_tmu.c
@@ -25,6 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define SITES_MAX 16
#define FLAGS_VER2 0x1
#define FLAGS_VER3 0x2
+#define FLAGS_VER4 0x4
#define TMR_DISABLE0x0
#define TMR_ME 0x8000
@@ -76,6 +77,45 @@ struct imx_tmu_regs {
u32 ttr3cr; /* Temperature Range 3 Control Register */
};
+struct imx_tmu_regs_v4 {
+ u32 tmr;/* Mode Register */
+ u32 tsr;/* Status Register */
+ u32 tmsr; /* Monitor Site Register */
+ u32 tmtmir; /* Temperature measurement interval Register */
+ u8 res0[0x10];
+ u32 tier; /* Interrupt Enable Register */
+ u32 tidr; /* Interrupt Detect Register */
+ u8 res1[0x8];
+ u32 tiiscr; /* Interrupt Immediate Site Capture Register */
+ u32 tiascr; /* Interrupt Average Site Capture Register */
+ u32 ticscr; /* Interrupt Critical Site Capture Register */
+ u8 res2[0x4];
+ u32 tmhtcr; /* Monitor High Temperature Capture Register */
+ u32 tmltcr; /* MonitorLow Temperature Capture Register */
+ u32 tmrtrcr; /* Monitor Rising Temperature Rate Capture Register */
+ u32 tmftrcr; /* Monitor Falling Temperature Rate Capture Register */
+ u32 tmhtitr; /* Monitor High Temperature Immediate Threshold */
+ u32 tmhtatr; /* Monitor High Temperature Average Threshold */
+ u32 tmhtactr; /* Monitor High Temperature Average Crit Threshold */
+ u8 res3[0x4];
+ u32 tmltitr; /* Monitor Low Temperature Immediate Threshold */
+ u32 tmltatr; /* Monitor Low Temperature Average Threshold */
+ u32 tmltactr; /* Monitor Low Temperature Average Crit Threshold */
+ u8 res4[0x4];
+ u32 tmrtrctr; /* Monitor Rising Temperature Rate Critical Threshold
Register */
+ u32 tmftrctr; /* Monitor Falling Temperature Rate Critical Threshold
Register */
+ u8 res5[0x8];
+ u32 ttcfgr; /* Temperature Configuration Register */
+ u32 tscfgr; /* Sensor Configuration Register */
+ u8 res6[0x78];
+ u32 tritsr0; /* Immediate Temperature Site Register */
+ u32 tratsr0; /* Average Temperature Site Register */
+ u8 res7[0xdf8];
+ u32 tcmcfg; /* Central Module Configuration */
+ u8 res8[0xc];
+ u32 ttrcr[16]; /* Temperature Range Control Register */
+};
+
struct imx_tmu_regs_v2 {
u32 ter;/* TMU enable Register */
u32 tsr;/* Status Register */
@@ -115,6 +155,7 @@ union tmu_regs {
struct imx_tmu_regs regs_v1;
struct imx_tmu_regs_v2 regs_v2;
struct imx_tmu_regs_v3 regs_v3;
+ struct imx_tmu_regs_v4 regs_v4;
};
struct imx_tmu_plat {
@@ -148,6 +189,9 @@ static int read_temperature(struct udevice *dev, int *temp)
* only reflects the RAW uncalibrated data
*/
valid = ((val & 0xff) < 10 || (val & 0xff) > 125) ? 0
: 1;
+ } else if (drv_data & FLAGS_VER4) {
+ val = readl(&pdata->regs->regs_v4.tritsr0);
+ valid = val & 0x8000;
} else {
val =
readl(&pdata->regs->regs_v1.site[pdata->id].tritsr);
valid = val & 0x8000;
@@ -165,6 +209,13 @@ static int read_temperature(struct udevice *dev, int *temp)
return -EINVAL;
*temp *= 1000;
+ } else if (drv_data & FLAGS_VER4) {
+ *temp = (val & 0x1ff) * 1000;
+ if (val & 0x200)
[PATCH 00/42] imx: i.MX9 update
From: Peng Fan This patchset includes updates mainly for i.MX9, such as Clock, Memory, Parts, Low drive mode, DDR, cpu driver, Variants The first patch is not about i.MX9, just include it here since it is a simple one for i.MX8ULP. For the watchdog reset_cpu, I will move it out from watchdog driver in future patches which would includes other changes. I include it here mainly for sysreset support. This patchset depends on two patches from Marek: https://patchwork.ozlabs.org/project/uboot/patch/20230404192510.160819-1-ma...@denx.de/ https://patchwork.ozlabs.org/project/uboot/patch/20230404192510.160819-2-ma...@denx.de/ Jacky Bai (4): ddr: imx9: Change the saved ddr data base to 0x2051c000 ddr: imx93: Add 625M bypass clock support ddr: imx93: update the ddr init to support mult setpoints ddr: imx9: update the rank setting for multi fsp support Peng Fan (33): imx8ulp: build ahab imx: spl_imx_romapi: typo fix imx: move imx8 sci header file to include/firmware/imx imx: firmware: sci: add inline functions when IMX8 not enabled imx: imx8_cpu: use static for local functions imx: imx8_cpu: support i.MX9 imx: imx8_cpu: support get temperature for i.MX9 imx: imx8_cpu: print cpu grade temperature imx9: configure M33 systick to 24M imx9: add more PLL settings imx9: use parameter freq when set_arm_clk imx9: correct getting LPI2C clk imx9: simplify clk settings imx9: cut off OPTEE memory region from U-Boot imx9: imx93_evk: enable CPU_IMX imx9: imx93_evk: drop unused macro imx9: imx93_evk: select IMX_TMU imx9: imx93_evk: enable CONFIG_WDT watchdog: ulp_wdog: guard reset_cpu with condition check imx9: soc: support reset cause imx9: Get market segment and speed grading imx9: clock: clear HW_CTRL_SEL imx9: clock: add CONFIG_IMX9_LOW_DRIVE_MODE support imx9: clock: config arm alt root to 500mhz imx9: add i.MX93 variants support imx9: correct coding style imx9: use i.MX generic rom api function imx9: imx93_evk: add low drive mode support on 11x11 EVK arm: dts: imx93: sync device tree with Linux arm: dts: imx93: add tmu imx9: imx93_evk: Update spl stack & bss base address imx9: imx93_evk: update ddr timing file imx9: imx93_evk: enable sysreset Ye Li (5): thermal: imx_tmu: Update TMU driver to support iMX93 imx9: Change hard coded MAC to read from fuse imx9: allow to bootaux Mcore with input address ddr: imx9: Add workaround for DDRPHY rank-to-rank errata imx9: Calculate DDR size from DDRC setting arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 29 - arch/arm/dts/imx93-11x11-evk.dts | 385 +- arch/arm/dts/imx93-pinfunc.h | 194 +- arch/arm/dts/imx93.dtsi | 618 +-- arch/arm/include/asm/arch-imx/cpu.h |7 + arch/arm/include/asm/arch-imx8/power-domain.h |2 +- arch/arm/include/asm/arch-imx8/sci/sci.h | 138 - arch/arm/include/asm/arch-imx8/sys_proto.h|2 +- arch/arm/include/asm/arch-imx8m/ddr.h |2 +- arch/arm/include/asm/arch-imx9/clock.h|6 + arch/arm/include/asm/arch-imx9/ddr.h | 23 +- arch/arm/include/asm/arch-imx9/imx-regs.h |3 + arch/arm/include/asm/mach-imx/sys_proto.h | 12 +- arch/arm/mach-imx/cmd_dek.c |2 +- arch/arm/mach-imx/imx8/ahab.c |2 +- arch/arm/mach-imx/imx8/cpu.c |2 +- arch/arm/mach-imx/imx8/fdt.c |2 +- arch/arm/mach-imx/imx8/iomux.c|2 +- arch/arm/mach-imx/imx8/misc.c |2 +- arch/arm/mach-imx/imx8/snvs_security_sc.c |2 +- arch/arm/mach-imx/imx8ulp/Kconfig |5 + arch/arm/mach-imx/imx8ulp/Makefile|1 + arch/arm/mach-imx/imx9/Kconfig|5 + arch/arm/mach-imx/imx9/clock.c| 113 +- arch/arm/mach-imx/imx9/imx_bootaux.c | 10 +- arch/arm/mach-imx/imx9/soc.c | 384 +- arch/arm/mach-imx/parse-container.c |2 +- arch/arm/mach-imx/spl_imx_romapi.c|2 +- .../imx8qm_rom7720_a1/imx8qm_rom7720_a1.c |2 +- board/advantech/imx8qm_rom7720_a1/spl.c |2 +- board/congatec/cgtqmx8/cgtqmx8.c |2 +- board/freescale/imx8qm_mek/imx8qm_mek.c |2 +- board/freescale/imx8qxp_mek/imx8qxp_mek.c |2 +- board/freescale/imx8qxp_mek/spl.c |2 +- board/freescale/imx93_evk/MAINTAINERS |1 + board/freescale/imx93_evk/Makefile|4 + board/freescale/imx93_evk/lpddr4x_timing.c| 3361 ++--- board/freescale/imx93_evk/lpddr4x_timing_ld.c | 1496 board/freescale/imx93_evk/spl.c | 26 +- board/siemens/capricorn/board.c |2 +- board/toradex/apalis-imx8/apalis-imx8.c |2 +- board/toradex/colibri-imx8x/colibri-imx8x.c |2 +- configs/imx93_11x11_evk_defconfig | 12 +- configs/imx93_11x11_evk_
[PATCH 01/42] imx8ulp: build ahab
From: Peng Fan The ahab was missed to be compiled, so add it back. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/Kconfig | 5 + arch/arm/mach-imx/imx8ulp/Makefile | 1 + 2 files changed, 6 insertions(+) diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig index c1c1aa08c52..49ea25250a3 100644 --- a/arch/arm/mach-imx/imx8ulp/Kconfig +++ b/arch/arm/mach-imx/imx8ulp/Kconfig @@ -1,5 +1,10 @@ if ARCH_IMX8ULP +config AHAB_BOOT + bool "Support i.MX8ULP AHAB features" + help + This option enables the support for AHAB secure boot. + config IMX8ULP bool diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile index 2c9938fcdf0..f7692cf3a78 100644 --- a/arch/arm/mach-imx/imx8ulp/Makefile +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -5,6 +5,7 @@ obj-y += lowlevel_init.o obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o +obj-$(CONFIG_AHAB_BOOT) += ahab.o ifeq ($(CONFIG_SPL_BUILD),y) obj-y += upower/ -- 2.40.0
[PATCH v3 11/11] configs: starfive: Enable ID EEPROM configuration
Enabled ID_EEPROM and I2C configuration for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
configs/starfive_visionfive2_defconfig | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
index dbd42e78d0..47559070c2 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -11,6 +11,7 @@ CONFIG_SPL_TEXT_BASE=0x800
CONFIG_SYS_PROMPT="StarFive #"
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x818
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -21,6 +22,7 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
+# CONFIG_OF_BOARD_FIXUP is not set
CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_BOOT=y
@@ -32,6 +34,8 @@ CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr
${fdtcontroladdr};"
CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_ID_EEPROM=y
+CONFIG_SYS_EEPROM_BUS_NUM=5
CONFIG_SPL_MAX_SIZE=0x4
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_BSS_START_ADDR=0x804
@@ -43,21 +47,34 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8000
CONFIG_SYS_SPL_MALLOC_SIZE=0x40
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
+CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_SIZE=512
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_TFTPPUT=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_JH7110=y
-# CONFIG_I2C is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0X50
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
--
2.17.1
[PATCH v3 10/11] configs: starfive: Enable ethernet configuration for StarFive VisionFive2
Enable DWC_ETH_QOS and PHY_MOTORCOMM configuration to support ethernet
function for StarFive VisionFive 2 board,including versions 1.2A and
1.3B.
Signed-off-by: Yanhong Wang
---
configs/starfive_visionfive2_defconfig | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
index 550d0ff3ab..dbd42e78d0 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b"
+CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2"
CONFIG_SPL_TEXT_BASE=0x800
CONFIG_SYS_PROMPT="StarFive #"
CONFIG_DM_RESET=y
@@ -21,15 +21,15 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
-CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
+CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SPL_MAX_SIZE=0x4
@@ -52,6 +52,8 @@ CONFIG_SYS_BOOTM_LEN=0x400
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_TFTPPUT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_JH7110=y
@@ -65,6 +67,13 @@ CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_STARFIVE=y
+CONFIG_RGMII=y
+CONFIG_RMII=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
--
2.17.1
[PATCH v3 09/11] doc: board: starfive: Reword the make defconfig information
The defconfig file name for StarFive VisionFive2 has been changed, and
the documentation description has also changed.
Signed-off-by: Yanhong Wang
---
doc/board/starfive/visionfive2.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/doc/board/starfive/visionfive2.rst
b/doc/board/starfive/visionfive2.rst
index 22d2a31ff5..a2374486b5 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -60,7 +60,7 @@ Now build the U-Boot SPL and U-Boot proper
.. code-block:: console
cd
- make starfive_visionfive2_13b_defconfig
+ make starfive_visionfive2_defconfig
make
OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
@@ -111,7 +111,7 @@ Program the SD card
sudo cp u-boot.itb /mnt/
sudo cp Image.gz /mnt/
sudo cp initramfs.cpio.gz /mnt/
- sudo cp jh7110-starfive-visionfive-2-v1.3b.dtb /mnt/
+ sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
sudo umount /mnt
Booting
@@ -255,7 +255,7 @@ Sample boot log from StarFive VisionFive2 board
StarFive #fatload mmc 1:3 ${kernel_addr_r} Image.gz
6429424 bytes read in 394 ms (15.6 MiB/s)
- StarFive #fatload mmc 1:3 ${fdt_addr_r}
jh7110-starfive-visionfive-2-v1.3b.dtb
+ StarFive #fatload mmc 1:3 ${fdt_addr_r} jh7110-starfive-visionfive-2.dtb
11285 bytes read in 5 ms (2.2 MiB/s)
StarFive #fatload mmc 1:3 ${ramdisk_addr_r} initramfs.cpio.gz
152848495 bytes read in 9271 ms (15.7 MiB/s)
--
2.17.1
[PATCH v3 08/11] riscv: dts: starfive: Add support eeprom device tree node
Add support "atmel,24c04" eeprom for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
.../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 14 ++
arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 8 +++-
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 2afcec30b8..13f69da31e 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -67,6 +67,20 @@
};
};
+&i2c5_pins {
+ bootph-pre-ram;
+ i2c-pins {
+ bootph-pre-ram;
+ };
+};
+
+&i2c5 {
+ bootph-pre-ram;
+ eeprom@50 {
+ bootph-pre-ram;
+ };
+};
+
&binman {
itb {
fit {
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index 0272369b24..710b082766 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -120,6 +120,12 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
};
&i2c6 {
@@ -350,4 +356,4 @@
reg = <0>;
};
};
-};
\ No newline at end of file
+};
--
2.17.1
[PATCH v3 07/11] riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B
The difference between 1.2A and 1.3B is dynamically configured according
to the PCB version, and there is no difference on the board device tree,
so the same DT file can be used.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/Makefile | 3 +-
... jh7110-starfive-visionfive-2-u-boot.dtsi} | 25 ++-
.../jh7110-starfive-visionfive-2-v1.2a.dts| 12
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 ---
...b.dts => jh7110-starfive-visionfive-2.dts} | 3 +-
5 files changed, 26 insertions(+), 86 deletions(-)
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi =>
jh7110-starfive-visionfive-2-u-boot.dtsi} (66%)
delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
delete mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts =>
jh7110-starfive-visionfive-2.dts} (65%)
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 79a58694f5..7940fe466d 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,8 +7,7 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.3b.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.2a.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
similarity index 66%
rename from arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
rename to arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 3c322c5c97..2afcec30b8 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
*/
#include "binman.dtsi"
@@ -67,3 +67,26 @@
};
};
+&binman {
+ itb {
+ fit {
+ images {
+ fdt-1 {
+ description = "NAME";
+ load = <0x4040>;
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ conf-1 {
+ fdt = "fdt-1";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
deleted file mode 100644
index b9d26d7af7..00
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-/dts-v1/;
-#include "jh7110-starfive-visionfive-2.dtsi"
-
-/ {
- model = "StarFive VisionFive 2 v1.2A";
- compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
-};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
deleted file mode 100644
index 3c322c5c97..00
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-#include "binman.dtsi"
-#include "jh7110-u-boot.dtsi"
-/ {
- chosen {
- bootph-pre-ram;
- };
-
- firmware {
- spi0 = &qspi;
- bootph-pre-ram;
- };
-
- config {
- bootph-pre-ram;
- u-boot,spl-payload-offset = <0x10>;
- };
-
- memory@4000 {
- bootph-pre-ram;
- };
-};
-
-&uart0 {
- bootph-pre-ram;
-};
-
-&mmc0 {
- bootph-pre-ram;
-};
-
-&mmc1 {
- bootph-pre-ram;
-};
-
-&qspi {
- bootph-pre-ram;
-
- nor-flash@0 {
- bootph-pre-ram;
- };
-};
-
-&sysgpio {
- bootph-pre-ram;
-};
-
-&mmc0_pins {
- bootph-pre-ram;
- mmc0-pins-rest {
- bootph-pre-ram;
- };
-};
-
-&mmc1_pins {
- bootph-pre-ram;
- mmc1-pins0 {
-
[PATCH v3 06/11] riscv: dts: jh7110: Add ethernet device tree nodes
Add ethernet device tree node to support StarFive ethernet driver for
the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
---
.../dts/jh7110-starfive-visionfive-2.dtsi | 34 +
arch/riscv/dts/jh7110.dtsi| 69 +++
2 files changed, 103 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..0272369b24 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -17,6 +17,8 @@
i2c2 = &i2c2;
i2c5 = &i2c5;
i2c6 = &i2c6;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
};
chosen {
@@ -317,3 +319,35 @@
assigned-clock-parents = <&osc>;
assigned-clock-rates = <0>;
};
+
+&gmac0 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&gmac1 {
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+ };
+};
\ No newline at end of file
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..58e332e9d7 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -235,6 +235,13 @@
#clock-cells = <0>;
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,lpi_en;
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <4>;
+ snps,blen = <256 128 64 32 0 0 0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -539,6 +546,68 @@
status = "disabled";
};
+ gmac0: ethernet@1603 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x1603 0x0 0x1>;
+ clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
+<&aoncrg JH7110_AONCLK_GMAC0_AHB>,
+<&syscrg JH7110_SYSCLK_GMAC0_PTP>,
+<&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
+<&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
+<&aoncrg JH7110_AONRST_GMAC0_AHB>;
+ reset-names = "stmmaceth", "ahb";
+ interrupts = <7>, <6>, <5>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <8>;
+ rx-fifo-depth = <2048>;
+ tx-fifo-depth = <2048>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,tso;
+ snps,en-tx-lpi-clockgating;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ starfive,syscon = <&aon_syscon 0xc 0x12>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@1604 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x1604 0x0 0x1>;
+ clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
+<&syscrg JH7110_SYSCLK_GMAC1_AHB>,
+<&syscrg JH7110_SYSCLK_GMAC1_PTP>,
+<&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
+<&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
+<&syscrg JH7110_SYSRST_GMAC1_AHB>;
+ reset-names = "stmmaceth", "ahb";
+ interrupts = <78>, <77>, <76>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-f
[PATCH v3 05/11] board: starfive: Dynamic configuration of DT for 1.2A and 1.3B
The main difference between StarFive VisionFive 2 1.2A and 1.3B is gmac.
You can read the PCB version of the current board by
get_pcb_revision_from_eeprom(), and then dynamically configure the
difference of gmac in spl_perform_fixups() according to different PCB
versions, so that one DT and one defconfig can support both 1.2A and
1.3B versions, which is more user-friendly.
Signed-off-by: Yanhong Wang
---
board/starfive/visionfive2/spl.c | 157 ++
.../visionfive2/starfive_visionfive2.c| 13 ++
2 files changed, 170 insertions(+)
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index db0b4cb433..7acd3995aa 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -5,16 +5,173 @@
*/
#include
+#include
#include
#include
#include
+#include
+#include
+#include
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
#define JH7110_CLK_CPU_ROOT_SHIFT 24
#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
+struct starfive_vf2_pro {
+ const char *path;
+ const char *name;
+ const char *value;
+};
+
+static const struct starfive_vf2_pro starfive_vera[] = {
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0", "rx-internal-delay-ps",
+ "1900"},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0", "tx-internal-delay-ps",
+ "1350"}
+};
+
+static const struct starfive_vf2_pro starfive_verb[] = {
+ {"/soc/ethernet@1603", "starfive,tx-use-rgmii-clk", NULL},
+ {"/soc/ethernet@1604", "starfive,tx-use-rgmii-clk", NULL},
+
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-1000-inverted", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "rx-internal-delay-ps", "1900"},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "tx-internal-delay-ps", "1500"},
+
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ { "/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "rx-internal-delay-ps", "0"},
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "tx-internal-delay-ps", "0"},
+};
+
+void spl_fdt_fixup_version_a(void *fdt)
+{
+ u32 phandle;
+ u8 i;
+ int offset;
+ int ret;
+
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+ "StarFive VisionFive 2 v1.2A");
+
+ offset = fdt_path_offset(fdt, "/soc/clock-controller@1302");
+ phandle = fdt_get_phandle(fdt, offset);
+ offset = fdt_path_offset(fdt, "/soc/ethernet@1604");
+
+ fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks",
JH7110_SYSCLK_GMAC1_TX);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks",
JH7110_SYSCLK_GMAC1_RX);
+
+ fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_SYSCLK_GMAC1_RMII_RTX);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_SYSCLK_GMAC1_RMII_RTX);
+
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@1604"),
+ "phy-mode", "rmii");
+
+ for (i = 0; i < ARRAY_SIZE(starfive_vera); i++) {
+ offset = fdt_path_offset(fdt, starfive_vera[i].path);
+
+ if (starfive_vera[i].value)
+ ret = fdt_setprop_u32(fdt, offset,
starfive_vera[i].name,
+ dectoul(starfive_vera[i].value,
NULL));
+ else
+ ret = fdt_setprop_empty(fdt, offset,
starfive_vera[i].name);
+
+ if (ret) {
+ pr_err("%s set prop %s fail.\n", __func__,
starfive_vera[i].name);
+ break;
+ }
+ }
+}
+
+void spl_fdt_fixup_version_b(void *fdt)
+{
+ u32 phandle;
+ u8 i;
+ int offset;
+ int ret;
+
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+ "StarFive VisionFive 2 v1.3B");
+
+ /* gmac0 */
+ offset = fdt_path_offset(fdt, "/soc/clock-controller@1700");
+ phandle = fdt_get_phandle(fdt, offset);
+ offset = fdt_path_off
[PATCH v3 03/11] eeprom: starfive: Enable ID EEPROM configuration
Enabled ID_EEPROM configuration for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
arch/riscv/include/asm/arch-jh7110/eeprom.h | 13 +
board/starfive/visionfive2/Makefile | 1 +
.../visionfive2/visionfive2-i2c-eeprom.c | 560 ++
3 files changed, 574 insertions(+)
create mode 100644 arch/riscv/include/asm/arch-jh7110/eeprom.h
create mode 100644 board/starfive/visionfive2/visionfive2-i2c-eeprom.c
diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h
b/arch/riscv/include/asm/arch-jh7110/eeprom.h
new file mode 100644
index 00..f354d5c60c
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#ifndef _ASM_RISCV_EEPROM_H
+#define _ASM_RISCV_EEPROM_H
+
+u8 get_pcb_revision_from_eeprom(void);
+u32 get_ddr_size_from_eeprom(void);
+
+#endif /* _ASM_RISCV_EEPROM_H */
diff --git a/board/starfive/visionfive2/Makefile
b/board/starfive/visionfive2/Makefile
index 66c854df39..c7ba4f7ed6 100644
--- a/board/starfive/visionfive2/Makefile
+++ b/board/starfive/visionfive2/Makefile
@@ -5,3 +5,4 @@
obj-y := starfive_visionfive2.o
obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_ID_EEPROM) += visionfive2-i2c-eeprom.o
diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
new file mode 100644
index 00..2d92ee52b6
--- /dev/null
+++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
@@ -0,0 +1,560 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define FORMAT_VERSION 0x2
+#define PCB_VERSION0xB1
+#define BOM_VERSION'A'
+/*
+ * BYTES_PER_EEPROM_PAGE: the 24FC04H datasheet says that data can
+ * only be written in page mode, which means 16 bytes at a time:
+ * 16-Byte Page Write Buffer
+ */
+#define BYTES_PER_EEPROM_PAGE 16
+
+/*
+ * EEPROM_WRITE_DELAY_MS: the 24FC04H datasheet says it takes up to
+ * 5ms to complete a given write:
+ * Write Cycle Time (byte or page) ro Page Write Time 5 ms, Maximum
+ */
+#define EEPROM_WRITE_DELAY_MS 5000
+/*
+ * StarFive OUI. Registration Date is 20xx-xx-xx
+ */
+#define STARFIVE_OUI_PREFIX"6C:CF:39:"
+#define STARFIVE_DEFAULT_MAC0 "6C:CF:39:6C:DE:AD"
+#define STARFIVE_DEFAULT_MAC1 "6C:CF:39:6C:DE:AE"
+
+/* Magic number at the first four bytes of EEPROM HATs */
+#define STARFIVE_EEPROM_HATS_SIG "SFVF" /* StarFive VisionFive */
+
+#define STARFIVE_EEPROM_HATS_SIZE_MAX 256 /* Header + Atom1&4(v1) */
+#define STARFIVE_EEPROM_WP_OFFSET 0 /* Read only field */
+#define STARFIVE_EEPROM_ATOM1_PSTR "VF7110A1-2228-D008E000-0001\0"
+#define STARFIVE_EEPROM_ATOM1_PSTR_SIZE32
+#define STARFIVE_EEPROM_ATOM1_SN_OFFSET23
+#define STARFIVE_EEPROM_ATOM1_VSTR "StarFive Technology Co., Ltd.\0\0\0"
+#define STARFIVE_EEPROM_ATOM1_VSTR_SIZE32
+
+#define MAGIC_NUMBER_BYTES 4
+#define MAC_ADDR_BYTES 6
+#define MAC_ADDR_STRLEN17
+
+/*
+ * Atom Types
+ * 0x = invalid
+ * 0x0001 = vendor info
+ * 0x0002 = GPIO map
+ * 0x0003 = Linux device tree blob
+ * 0x0004 = manufacturer custom data
+ * 0x0005-0xfffe = reserved for future use
+ * 0x = invalid
+ */
+
+#define HATS_ATOM_INVALID 0x
+#define HATS_ATOM_VENDOR 0x0001
+#define HATS_ATOM_GPIO 0x0002
+#define HATS_ATOM_DTB 0x0003
+#define HATS_ATOM_CUSTOM 0x0004
+#define HATS_ATOM_INVALID_END 0x
+
+struct eeprom_header {
+ char signature[MAGIC_NUMBER_BYTES]; /* ASCII table signature */
+ u8 version; /* EEPROM data format version */
+ /* (0x00 reserved, 0x01 = first version) */
+ u8 reversed;/* 0x00, Reserved field */
+ u16 numatoms; /* total atoms in EEPROM */
+ u32 eeplen; /* total length in bytes of all eeprom data */
+ /* (including this header) */
+};
+
+struct eeprom_atom_header {
+ u16 type;
+ u16 count;
+ u32 dlen;
+};
+
+struct eeprom_atom1_data {
+ u8 uuid[16];
+ u16 pid;
+ u16 pver;
+ u8 vslen;
+ u8 pslen;
+ uchar vstr[STARFIVE_EEPROM_ATOM1_VSTR_SIZE];
+ uchar pstr[STARFIVE_EEPROM_ATOM1_PSTR_SIZE]; /* product SN */
+};
+
+struct starfive_eeprom_atom1 {
+ struct eeprom_atom_header header;
+ struct eeprom_atom1_data data;
+ u16 crc;
+};
+
+struct eeprom_atom4_data {
+ u16 version;
+ u8 pcb_revision;/* PCB version */
+ u8 bom_revision;/* BOM version */
+ u8 mac0_addr[MAC_ADDR_BYTES]; /* Ethernet0 MAC */
+ u8 mac1_addr[MAC_ADDR_BYTES]; /
[PATCH v3 04/11] ram: starfive: Read memory size information from EEPROM
StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of
DDR capacity includes 2G/4G/8G, a DT can not support multiple
capacities, so the capacity size information is recorded to EEPROM, when
DDR initialization required capacity size information is read from
EEPROM.
If there is no information in EEPROM, it is initialized with the default
size defined in DT.
Signed-off-by: Yanhong Wang
---
arch/riscv/cpu/jh7110/spl.c | 32 -
drivers/ram/starfive/starfive_ddr.c | 2 --
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 104f0fe949..72adcefa0e 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -3,19 +3,49 @@
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Author: Yanhong Wang
*/
-
+#include
+#include
#include
#include
#include
+#include
#include
+#include
#define CSR_U74_FEATURE_DISABLE0x7c1
#define L2_LIM_MEM_END 0x81FUL
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool check_ddr_size(phys_size_t size)
+{
+ switch (size) {
+ case SZ_2:
+ case SZ_4:
+ case SZ_8:
+ case SZ_16:
+ return true;
+ default:
+ return false;
+ }
+}
+
int spl_soc_init(void)
{
int ret;
struct udevice *dev;
+ phys_size_t size;
+
+ ret = fdtdec_setup_mem_size_base();
+ if (ret)
+ return ret;
+
+ /* Read the definition of the DDR size from eeprom, and if not,
+* use the definition in DT
+*/
+ size = (get_ddr_size_from_eeprom() >> 16) & 0xFF;
+ if (check_ddr_size(size))
+ gd->ram_size = size << 30;
/* DDR init */
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
diff --git a/drivers/ram/starfive/starfive_ddr.c
b/drivers/ram/starfive/starfive_ddr.c
index 553f2ce6f4..a0a3d6b33d 100644
--- a/drivers/ram/starfive/starfive_ddr.c
+++ b/drivers/ram/starfive/starfive_ddr.c
@@ -72,8 +72,6 @@ static int starfive_ddr_probe(struct udevice *dev)
u64 rate;
int ret;
- /* Read memory base and size from DT */
- fdtdec_setup_mem_size_base();
priv->info.base = gd->ram_base;
priv->info.size = gd->ram_size;
--
2.17.1
[PATCH v3 02/11] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.
Signed-off-by: Yanhong Wang
---
drivers/net/Kconfig| 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c | 249 +
5 files changed, 264 insertions(+)
create mode 100644 drivers/net/dwc_eth_qos_starfive.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 09039a283e..5540f0ea18 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -249,6 +249,13 @@ config DWC_ETH_QOS_QCOM
The Synopsys Designware Ethernet QOS IP block with specific
configuration used in Qcom QCS404 SoC.
+config DWC_ETH_QOS_STARFIVE
+ bool "Synopsys DWC Ethernet QOS device support for STARFIVE"
+ depends on DWC_ETH_QOS
+ help
+ The Synopsys Designware Ethernet QOS IP block with specific
+ configuration used in STARFIVE JH7110 soc.
+
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 46a40e2ed9..d4af253b6f 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
+obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index ec58697b31..8060a4e782 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1713,6 +1713,12 @@ static const struct udevice_id eqos_ids[] = {
.data = (ulong)&eqos_qcom_config
},
#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
+ {
+ .compatible = "starfive,jh7110-dwmac",
+ .data = (ulong)&eqos_jh7110_config
+ },
+#endif
{ }
};
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index fddbe9336c..a6b719af80 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -289,3 +289,4 @@ int eqos_null_ops(struct udevice *dev);
extern struct eqos_config eqos_imx_config;
extern struct eqos_config eqos_qcom_config;
+extern struct eqos_config eqos_jh7110_config;
diff --git a/drivers/net/dwc_eth_qos_starfive.c
b/drivers/net/dwc_eth_qos_starfive.c
new file mode 100644
index 00..5be8ac0f1a
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_starfive.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dwc_eth_qos.h"
+
+#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
+#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
+#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
+
+struct starfive_platform_data {
+ struct regmap *regmap;
+ struct reset_ctl_bulk resets;
+ struct clk_bulk clks;
+ phy_interface_t interface;
+ u32 offset;
+ u32 shift;
+ bool tx_use_rgmii_clk;
+};
+
+static int eqos_interface_init_jh7110(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data = pdata->priv_pdata;
+ struct ofnode_phandle_args args;
+ unsigned int mode;
+ int ret;
+
+ switch (data->interface) {
+ case PHY_INTERFACE_MODE_RMII:
+ mode = STARFIVE_DWMAC_PHY_INFT_RMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
+2, 0, &args);
+ if (ret)
+ return ret;
+
+ if (args.args_count != 2)
+ return -EINVAL;
+
+ data->offset = args.args[0];
+ data->shift = args.args[1];
+ data->regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
+ if (IS_ERR(data->regmap)) {
+ ret = PTR_ERR(data->regmap);
+ pr_err("Failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ return regmap_update_bits(data->regmap, data->offset,
+ STARFIVE_DWMAC_PHY_INFT_FIELD << data->shift,
+ mode << data->shift);
+}
+
+static int eqos_set_tx_clk_speed_jh7110(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+
[PATCH v3 01/11] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have verified the driver on StarFive VisionFive2 board. Signed-off-by: Yanhong Wang Reviewed-by: Ramon Fried --- drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile| 1 + drivers/net/phy/motorcomm.c | 437 3 files changed, 444 insertions(+) create mode 100644 drivers/net/phy/motorcomm.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 24158776f5..0c3c39a550 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -220,6 +220,12 @@ config PHY_MICREL_KSZ8XXX endif # PHY_MICREL +config PHY_MOTORCOMM + tristate "Motorcomm PHYs" + help + Enables support for Motorcomm network PHYs. + Currently supports the YT8531 Gigabit Ethernet PHYs. + config PHY_MSCC bool "Microsemi Corp Ethernet PHYs support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 85d17f109c..2487f366e1 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o +obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c new file mode 100644 index 00..e822fd76f2 --- /dev/null +++ b/drivers/net/phy/motorcomm.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Motorcomm 8531 PHY driver. + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include + +#define PHY_ID_YT8531 0x4f51e91b +#define PHY_ID_MASKGENMASK(31, 0) + +/* Extended Register's Address Offset Register */ +#define YTPHY_PAGE_SELECT 0x1E + +/* Extended Register's Data Register */ +#define YTPHY_PAGE_DATA0x1F + +#define YTPHY_SYNCE_CFG_REG0xA012 + +#define YTPHY_DTS_OUTPUT_CLK_DIS 0 +#define YTPHY_DTS_OUTPUT_CLK_25M 2500 +#define YTPHY_DTS_OUTPUT_CLK_125M 12500 + +#define YT8531_SCR_SYNCE_ENABLEBIT(6) +/* 1b0 output 25m clock *default* + * 1b1 output 125m clock + */ +#define YT8531_SCR_CLK_FRE_SEL_125MBIT(4) +#define YT8531_SCR_CLK_SRC_MASKGENMASK(3, 1) +#define YT8531_SCR_CLK_SRC_PLL_125M0 +#define YT8531_SCR_CLK_SRC_UTP_RX 1 +#define YT8531_SCR_CLK_SRC_SDS_RX 2 +#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 +#define YT8531_SCR_CLK_SRC_REF_25M 4 +#define YT8531_SCR_CLK_SRC_SSC_25M 5 + +/* 1b0 use original tx_clk_rgmii *default* + * 1b1 use inverted tx_clk_rgmii. + */ +#define YT8531_RC1R_TX_CLK_SEL_INVERTEDBIT(14) +#define YT8531_RC1R_RX_DELAY_MASK GENMASK(13, 10) +#define YT8531_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) +#define YT8531_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) +#define YT8531_RC1R_RGMII_0_000_NS 0 +#define YT8531_RC1R_RGMII_0_150_NS 1 +#define YT8531_RC1R_RGMII_0_300_NS 2 +#define YT8531_RC1R_RGMII_0_450_NS 3 +#define YT8531_RC1R_RGMII_0_600_NS 4 +#define YT8531_RC1R_RGMII_0_750_NS 5 +#define YT8531_RC1R_RGMII_0_900_NS 6 +#define YT8531_RC1R_RGMII_1_050_NS 7 +#define YT8531_RC1R_RGMII_1_200_NS 8 +#define YT8531_RC1R_RGMII_1_350_NS 9 +#define YT8531_RC1R_RGMII_1_500_NS 10 +#define YT8531_RC1R_RGMII_1_650_NS 11 +#define YT8531_RC1R_RGMII_1_800_NS 12 +#define YT8531_RC1R_RGMII_1_950_NS 13 +#define YT8531_RC1R_RGMII_2_100_NS 14 +#define YT8531_RC1R_RGMII_2_250_NS 15 + +/* Phy gmii clock gating Register */ +#define YT8531_CLOCK_GATING_REG0xC +#define YT8531_CGR_RX_CLK_EN BIT(12) + +/* Specific Status Register */ +#define YTPHY_SPECIFIC_STATUS_REG 0x11 +#define YTPHY_DUPLEX_MASK BIT(13) +#define YTPHY_DUPLEX_SHIFT 13 +#define YTPHY_SPEED_MODE_MASK GENMASK(15, 14) +#define YTPHY_SPEED_MODE_SHIFT 14 + +#define YT8531_EXTREG_SLEEP_CONTROL1_REG 0x27 +#define YT8531_ESC1R_SLEEP_SW BIT(15) +#define YT8531_ESC1R_PLLON_SLP BIT(14) + +#define YT8531_RGMII_CONFIG1_REG 0xA003 + +#define YT8531_CHIP_CONFIG_REG 0xA001 +#define YT8531_CCR_SW_RST BIT(15) +/* 1b0 disable 1.9ns rxc clock delay *default* + * 1b1 enable 1.9ns rxc clock delay + */ +#define YT8531_CCR_RXC_DLY_EN
[PATCH v3 00/11] Add ethernet driver for StarFive JH7110 SoC
This series of patches base on the latest branch/master,and
adds ethernet support for the StarFive JH7110 RISC-V SoC.
The series includes EEPROM, PHY and MAC drivers. The PHY model is
YT8531 (from Motorcomm Inc), and the MAC version is dwmac-5.20
(from Synopsys DesignWare).
The implementation of the phy driver is ported from linux, but it
has been adjusted for the u-boot framework.
EEPROM stores board-related information, such as DDR capacity,
PCB version, MAC address, etc.
The main difference between StarFive VisionFive 2 1.2A and 1.3B is
gmac, but the difference in gmac is not defined in DT, but reads the
PCB version from EEPROM, and then dynamically configures the difference
of gmac according to different PCB versions, which is compatible
with 1.2A and 1.3B versions, which is more user-friendly.
The PHY and MAC driver has been tested on the StarFive VisionFive 2 1.2A
and 1.3B boards and works normally.
For more information and support,you can visit RVspace wiki[1].
[1] https://wiki.rvspace.org/
v3:
- Added EEPROM support.
- Combine the board device tree of 1.2A and 1.3B into one.
- Removed the delay configuration of gmac phy clock from DT.
- Dynamically configure gmac differences of 1.2A and 1.3B to DT according to
the PCB version.
- DDR capacity information is read from EEPROM first, if not, it is defined by
default in DT.
v2:
- Reworded the phy driver. Added platform private data struct to save the
configuration data read from dts.
- Reworded the MAC driver. Added platform private data struct to save the
configuration data read from dts.
Previous versions:
v1 -
https://patchwork.ozlabs.org/project/uboot/cover/20230317010536.17860-1-yanhong.w...@starfivetech.com/
v2 -
https://patchwork.ozlabs.org/project/uboot/cover/20230329102720.25439-1-yanhong.w...@starfivetech.com/
Yanhong Wang (11):
net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
net: dwc_eth_qos: Add StarFive ethernet driver glue layer
eeprom: starfive: Enable ID EEPROM configuration
ram: starfive: Read memory size information from EEPROM
board: starfive: Dynamic configuration of DT for 1.2A and 1.3B
riscv: dts: jh7110: Add ethernet device tree nodes
riscv: dts: jh7110: Combine the board device tree files of 1.2A and
1.3B
riscv: dts: starfive: Add support eeprom device tree node
doc: board: starfive: Reword the make defconfig information
configs: starfive: Enable ethernet configuration for StarFive
VisionFive2
configs: starfive: Enable ID EEPROM configuration
arch/riscv/cpu/jh7110/spl.c | 32 +-
arch/riscv/dts/Makefile | 3 +-
... jh7110-starfive-visionfive-2-u-boot.dtsi} | 39 +-
.../jh7110-starfive-visionfive-2-v1.2a.dts| 12 -
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 ---
...b.dts => jh7110-starfive-visionfive-2.dts} | 3 +-
.../dts/jh7110-starfive-visionfive-2.dtsi | 40 ++
arch/riscv/dts/jh7110.dtsi| 69 +++
arch/riscv/include/asm/arch-jh7110/eeprom.h | 13 +
board/starfive/visionfive2/Makefile | 1 +
board/starfive/visionfive2/spl.c | 157 +
.../visionfive2/starfive_visionfive2.c| 13 +
.../visionfive2/visionfive2-i2c-eeprom.c | 560 ++
configs/starfive_visionfive2_defconfig| 34 +-
doc/board/starfive/visionfive2.rst| 6 +-
drivers/net/Kconfig | 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c| 249
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/motorcomm.c | 437 ++
drivers/ram/starfive/starfive_ddr.c | 2 -
24 files changed, 1665 insertions(+), 96 deletions(-)
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi =>
jh7110-starfive-visionfive-2-u-boot.dtsi} (58%)
delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
delete mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts =>
jh7110-starfive-visionfive-2.dts} (65%)
create mode 100644 arch/riscv/include/asm/arch-jh7110/eeprom.h
create mode 100644 board/starfive/visionfive2/visionfive2-i2c-eeprom.c
create mode 100644 drivers/net/dwc_eth_qos_starfive.c
create mode 100644 drivers/net/phy/motorcomm.c
base-commit: c9c2c95d4cd27fe0cd41fe13a863899d268f973c
prerequisite-patch-id: dee366bfbaa4e2bebd4b874d187d267b427a812d
--
2.17.1
[PATCH] board: starfive: Fixed errors reported when executing get_maintainer.pl
Fixed errors reported when executing 'scripts/get_maintainer.pl -f configs/starfive_visionfive2_defconfig'. Invalid MAINTAINERS address: 'startfive' Signed-off-by: Yanhong Wang --- board/starfive/visionfive2/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS index c5369086d8..600ff9575b 100644 --- a/board/starfive/visionfive2/MAINTAINERS +++ b/board/starfive/visionfive2/MAINTAINERS @@ -1,5 +1,5 @@ STARFIVE JH7110 VISIONFIVE2 BOARD -M: startfive +M: Yanhong Wang S: Maintained F: arch/riscv/include/asm/arch-jh7110/ F: board/starfive/visionfive2/ -- 2.17.1
Re: [PATCH 1/1] doc: Indicate required OpenSBI release for VisionFive 2
On Thu, Apr 27, 2023 at 11:56:58AM +0200, Heinrich Schuchardt wrote: > Support for the VisionFive 2 board is not contained in the most recent > OpenSBI release (v1.2). > > Signed-off-by: Heinrich Schuchardt > --- > doc/board/starfive/visionfive2.rst | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Leo Yu-Chi Liang
[PATCH v1] arm64: dts: rockchip: Add Radxa ROCK 4C Plus support
rk3399-rock-4c-plus.dts and rk3399-t-opp.dtsi were imported from Linux
6.3.
Signed-off-by: Denis 'GNUtoo' Carikli
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 6 +
arch/arm/dts/rk3399-rock-4c-plus.dts | 709 +++
arch/arm/dts/rk3399-t-opp.dtsi | 114 +++
board/rockchip/evb_rk3399/MAINTAINERS| 2 +
configs/rock-4c-plus-rk3399_defconfig| 97 +++
doc/board/rockchip/rockchip.rst | 1 +
7 files changed, 930 insertions(+)
create mode 100644 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-rock-4c-plus.dts
create mode 100644 arch/arm/dts/rk3399-t-opp.dtsi
create mode 100644 configs/rock-4c-plus-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3385948d22..c4db3753bb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -160,6 +160,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-rock-pi-4a.dtb \
rk3399-rock-pi-4b.dtb \
rk3399-rock-pi-4c.dtb \
+ rk3399-rock-4c-plus.dtb \
rk3399-rock960.dtb \
rk3399-rockpro64.dtb \
rk3399pro-rock-pi-n10.dtb
diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
new file mode 100644
index 00..85ee5770ad
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rk3399-rock-pi-4-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts
b/arch/arm/dts/rk3399-rock-4c-plus.dts
new file mode 100644
index 00..028eb508ae
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock-4c-plus.dts
@@ -0,0 +1,709 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2019 Radxa Limited
+ * Copyright (c) 2022 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include
+#include "rk3399.dtsi"
+#include "rk3399-t-opp.dtsi"
+
+/ {
+ model = "Radxa ROCK 4C+";
+ compatible = "radxa,rock-4c-plus", "rockchip,rk3399";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led1 &user_led2>;
+
+ /* USER_LED1 */
+ led-0 {
+ function = LED_FUNCTION_POWER;
+ color = ;
+ gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ };
+
+ /* USER_LED2 */
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = ;
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_3v3: vcc-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_phy1: vcc3v3-phy1-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_phy1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vcc_3v3>;
+ };
+
+ vcc5v0_host1: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host1";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_host0_s0>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_s
Re: [PATCH] Kconfig: Remove an impossible condition
On Sun, 22 Jan 2023 11:23:51 -0600 Samuel Holland wrote: > ARCH_SUNXI selects BINMAN, so the condition "!BINMAN && ARCH_SUNXI" > is impossible to satisfy. Indeed the generic ARCH_SUNXI entry in arch/arm/Kconfig selects BINMAN, so that looks fine. The same seems to be true for ARCH_ROCKCHIP, btw. Anyway, for that patch: > Signed-off-by: Samuel Holland Acked-by: Andre Przywara Queued for sunxi/master. Cheers, Andre > --- > > Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Kconfig b/Kconfig > index a75cce7e28..f810646e8a 100644 > --- a/Kconfig > +++ b/Kconfig > @@ -459,7 +459,7 @@ config BUILD_TARGET > default "u-boot-with-spl.kwb" if ARMADA_32BIT && SPL > default "u-boot-elf.srec" if RCAR_GEN3 > default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \ > - ARCH_SUNXI || RISCV || ARCH_ZYNQMP) > + RISCV || ARCH_ZYNQMP) > default "u-boot.kwb" if (ARCH_KIRKWOOD || ARMADA_32BIT) && !SPL > default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 > && SPL > default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
Re: [PATCH 3/3] gpio: axp/sunxi: Remove virtual VBUS detection GPIO
On Sun, 22 Jan 2023 17:46:22 -0600
Samuel Holland wrote:
> Now that this functionality is modeled using the device tree and
> regulator uclass, the named GPIO is not referenced anywhere. Remove it.
>
> Signed-off-by: Samuel Holland
There is indeed no config left that would set AXP0-VBUS-DETECT, so this
code is indeed no longer needed:
Reviewed-by: Andre Przywara
Queued for sunxi/master.
Cheers,
Andre
> ---
>
> arch/arm/include/asm/arch-sunxi/gpio.h | 1 -
> drivers/gpio/axp_gpio.c| 21 -
> drivers/gpio/sunxi_gpio.c | 6 +-
> include/axp209.h | 1 -
> include/axp221.h | 1 -
> include/axp809.h | 1 -
> include/axp818.h | 1 -
> 7 files changed, 5 insertions(+), 27 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
> b/arch/arm/include/asm/arch-sunxi/gpio.h
> index 437e86479c..6eaeece4e2 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -209,7 +209,6 @@ enum sunxi_gpio_number {
>
> /* Virtual AXP0 GPIOs */
> #define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
> -#define SUNXI_GPIO_AXP0_VBUS_DETECT 4
> #define SUNXI_GPIO_AXP0_VBUS_ENABLE 5
> #define SUNXI_GPIO_AXP0_GPIO_COUNT 6
>
> diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c
> index 35585dc8ac..49672193ff 100644
> --- a/drivers/gpio/axp_gpio.c
> +++ b/drivers/gpio/axp_gpio.c
> @@ -36,18 +36,11 @@ static int axp_gpio_direction_input(struct udevice *dev,
> unsigned pin)
> {
> u8 reg;
>
> - switch (pin) {
> -#ifndef CONFIG_AXP152_POWER /* NA on axp152 */
> - case SUNXI_GPIO_AXP0_VBUS_DETECT:
> - return 0;
> -#endif
> - default:
> - reg = axp_get_gpio_ctrl_reg(pin);
> - if (reg == 0)
> - return -EINVAL;
> + reg = axp_get_gpio_ctrl_reg(pin);
> + if (reg == 0)
> + return -EINVAL;
>
> - return pmic_bus_write(reg, AXP_GPIO_CTRL_INPUT);
> - }
> + return pmic_bus_write(reg, AXP_GPIO_CTRL_INPUT);
> }
>
> static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
> @@ -83,12 +76,6 @@ static int axp_gpio_get_value(struct udevice *dev,
> unsigned pin)
> int ret;
>
> switch (pin) {
> -#ifndef CONFIG_AXP152_POWER /* NA on axp152 */
> - case SUNXI_GPIO_AXP0_VBUS_DETECT:
> - ret = pmic_bus_read(AXP_POWER_STATUS, &val);
> - mask = AXP_POWER_STATUS_VBUS_PRESENT;
> - break;
> -#endif
> #ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
> /* Only available on later PMICs */
> case SUNXI_GPIO_AXP0_VBUS_ENABLE:
> diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
> index 1e85db179a..f0b42e4fdb 100644
> --- a/drivers/gpio/sunxi_gpio.c
> +++ b/drivers/gpio/sunxi_gpio.c
> @@ -117,11 +117,7 @@ int sunxi_name_to_gpio(const char *name)
> #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
> char lookup[8];
>
> - if (strcasecmp(name, "AXP0-VBUS-DETECT") == 0) {
> - sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
> - SUNXI_GPIO_AXP0_VBUS_DETECT);
> - name = lookup;
> - } else if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
> + if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
> sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
> SUNXI_GPIO_AXP0_VBUS_ENABLE);
> name = lookup;
> diff --git a/include/axp209.h b/include/axp209.h
> index 414f88a32c..d8bf44f1fa 100644
> --- a/include/axp209.h
> +++ b/include/axp209.h
> @@ -77,7 +77,6 @@ enum axp209_reg {
> #ifdef CONFIG_AXP209_POWER
> #define AXP_POWER_STATUS 0x00
> #define AXP_POWER_STATUS_ALDO_IN BIT(0)
> -#define AXP_POWER_STATUS_VBUS_PRESENTBIT(5)
> #define AXP_GPIO0_CTRL 0x90
> #define AXP_GPIO1_CTRL 0x92
> #define AXP_GPIO2_CTRL 0x93
> diff --git a/include/axp221.h b/include/axp221.h
> index 8dfcc5b5a2..32b988f3a9 100644
> --- a/include/axp221.h
> +++ b/include/axp221.h
> @@ -53,7 +53,6 @@
> #ifdef CONFIG_AXP221_POWER
> #define AXP_POWER_STATUS 0x00
> #define AXP_POWER_STATUS_ALDO_IN BIT(0)
> -#define AXP_POWER_STATUS_VBUS_PRESENTBIT(5)
> #define AXP_VBUS_IPSOUT 0x30
> #define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
> #define AXP_MISC_CTRL0x8f
> diff --git a/include/axp809.h b/include/axp809.h
> index 8082e402e2..71a7cb2aaa 100644
> --- a/include/axp809.h
> +++ b/include/axp809.h
> @@ -47,7 +47,6 @@
> #ifdef CONFIG_AXP809_POWER
> #define AXP_POWER_STATUS 0x00
> #define AXP_POWER_STATUS_ALDO_IN BIT(0)
> -#define AXP_POWER_STATUS_VBUS_PRESENTBIT(5)
> #define AXP_VBUS_IPSOUT 0x30
> #define AXP_VBUS_IPSOUT_DRIVEBUS
Re: [PATCH 2/3] sunxi: Switch to PMIC USB power supply VBUS detection
On Sun, 22 Jan 2023 17:46:21 -0600 Samuel Holland wrote: > Update boards to use the USB power supply driver, as referenced in the > device tree, instead of a virtual GPIO. This removes the need for some > DM-incompatible special cases in the GPIO driver. Confirmed that it replaces AXP0-VBUS-DETECT with CONFIG_REGULATOR_AXP_USB_POWER for all 23 boards affected. Reviewed-by: Andre Przywara Queued for sunxi/master. Cheers, Andre > The following five boards used AXP0-VBUS-DETECT in their config, but are > missing the "usb0_vbus_power-supply" property in their device tree: > - Ainol_AW1_defconfig / sun7i-a20-ainol-aw1 > - Cubieboard4_defconfig / sun9i-a80-cubieboard4 > - Merrii_A80_Optimus_defconfig / sun9i-a80-optimus > - Yones_Toptech_BD1078_defconfig / sun7i-a20-yones-toptech-bd1078 > - Yones_Toptech_BS1078_V2_defconfig / >sun6i-a31s-yones-toptech-bs1078-v2 > > None of those five boards have the MUSB controller (USB OTG) enabled in > their device trees, so this change should not break anything for them. > > Additionally, the following board intentionally omits the property > because VBUS is always enabled: > - Nintendo_NES_Classic_Edition_defconfig / >sun8i-r16-nintendo-nes-classic > > The PHY driver already assumes VBUS is enabled when no detection method > is available, so again this will not cause any problems. > > Signed-off-by: Samuel Holland > --- > > configs/A33-OLinuXino_defconfig| 2 +- > configs/Ainol_AW1_defconfig| 2 +- > configs/Cubieboard4_defconfig | 3 ++- > configs/Cubietruck_plus_defconfig | 2 +- > configs/MSI_Primo81_defconfig | 2 +- > configs/Merrii_A80_Optimus_defconfig | 3 ++- > configs/Nintendo_NES_Classic_Edition_defconfig | 2 +- > configs/Sinovoip_BPI_M3_defconfig | 2 +- > configs/Wexler_TAB7200_defconfig | 2 +- > configs/Yones_Toptech_BD1078_defconfig | 2 +- > configs/Yones_Toptech_BS1078_V2_defconfig | 2 +- > configs/colorfly_e708_q1_defconfig | 2 +- > configs/ga10h_v1_1_defconfig | 2 +- > configs/gt90h_v4_defconfig | 2 +- > configs/iNet_D978_rev2_defconfig | 2 +- > configs/inet86dz_defconfig | 2 +- > configs/inet_q972_defconfig| 2 +- > configs/polaroid_mid2407pxe03_defconfig| 2 +- > configs/polaroid_mid2809pxe04_defconfig| 2 +- > configs/q8_a23_tablet_800x480_defconfig| 2 +- > configs/q8_a33_tablet_1024x600_defconfig | 2 +- > configs/q8_a33_tablet_800x480_defconfig| 2 +- > configs/tbs_a711_defconfig | 2 +- > 23 files changed, 25 insertions(+), 23 deletions(-) > > diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig > index 351a454339..896ddbb95f 100644 > --- a/configs/A33-OLinuXino_defconfig > +++ b/configs/A33-OLinuXino_defconfig > @@ -8,7 +8,6 @@ CONFIG_DRAM_ZQ=15291 > CONFIG_DRAM_ODT_EN=y > CONFIG_MMC0_CD_PIN="PB4" > CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" > -CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" > CONFIG_USB0_ID_DET="PB3" > CONFIG_AXP_GPIO=y > > CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0" > @@ -16,5 +15,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 > CONFIG_VIDEO_LCD_BL_EN="PB2" > CONFIG_VIDEO_LCD_BL_PWM="PH0" > # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set > +CONFIG_REGULATOR_AXP_USB_POWER=y > CONFIG_AXP_DCDC1_VOLT=3300 > CONFIG_USB_MUSB_HOST=y > diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig > index 9a18af8c6e..ec0c216413 100644 > --- a/configs/Ainol_AW1_defconfig > +++ b/configs/Ainol_AW1_defconfig > @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=432 > CONFIG_DRAM_ZQ=123 > CONFIG_MMC0_CD_PIN="PH1" > CONFIG_USB0_VBUS_PIN="PB9" > -CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" > CONFIG_AXP_GPIO=y > > CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:4,le:87,ri:112,up:38,lo:141,hs:1,vs:1,sync:3,vmode:0" > CONFIG_VIDEO_LCD_POWER="PH8" > @@ -18,4 +17,5 @@ CONFIG_SPL_I2C=y > CONFIG_SYS_I2C_MVTWSI=y > CONFIG_SYS_I2C_SLAVE=0x7f > CONFIG_SYS_I2C_SPEED=40 > +CONFIG_REGULATOR_AXP_USB_POWER=y > CONFIG_USB_MUSB_HOST=y > diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig > index 04ed79afb6..82a8deac77 100644 > --- a/configs/Cubieboard4_defconfig > +++ b/configs/Cubieboard4_defconfig > @@ -7,10 +7,11 @@ CONFIG_DRAM_CLK=672 > CONFIG_MMC0_CD_PIN="PH18" > CONFIG_MMC_SUNXI_SLOT_EXTRA=2 > CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" > -CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" > CONFIG_USB0_ID_DET="PH16" > CONFIG_USB1_VBUS_PIN="PH14" > CONFIG_USB3_VBUS_PIN="PH15" > CONFIG_AXP_GPIO=y > CONFIG_SYS_I2C_SUN8I_RSB=y > +CONFIG_DM_REGULATOR=y > +CONFIG_REGULATOR_AXP_USB_POWER=y > CONFIG_AXP809_POWER=y > diff --git a/configs/Cubietruck_plus_defconfig > b/configs/Cubietruck_plus_defconfig > index 13f958977b..29f4df2b81
Re: [PATCH 1/3] power: regulator: Add a driver for the AXP USB power supply
On Sun, 22 Jan 2023 17:46:20 -0600
Samuel Holland wrote:
> This driver reports the presence/absence of voltage on the PMIC's USB
> VBUS pin. This information is used by the USB PHY driver. The
> corresponding Linux driver uses the power supply class, which does not
> exist in U-Boot. UCLASS_REGULATOR seems to be the closest match.
That's a quite clever and lean solution, since the USB PHY already
checks for such a regulator enable status. The bits match up, so:
Acked-by: Andre Przywara
queued for sunxi/master
Cheers,
Andre
> Signed-off-by: Samuel Holland
> ---
>
> drivers/power/regulator/Kconfig | 7
> drivers/power/regulator/Makefile| 1 +
> drivers/power/regulator/axp_usb_power.c | 49 +
> 3 files changed, 57 insertions(+)
> create mode 100644 drivers/power/regulator/axp_usb_power.c
>
> diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
> index c346d03507..eb5aa38c1c 100644
> --- a/drivers/power/regulator/Kconfig
> +++ b/drivers/power/regulator/Kconfig
> @@ -57,6 +57,13 @@ config SPL_REGULATOR_AXP
> Enable support in SPL for the regulators (DCDCs, LDOs) in the
> X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
>
> +config REGULATOR_AXP_USB_POWER
> + bool "Enable driver for X-Powers AXP PMIC USB power supply"
> + depends on DM_REGULATOR && PMIC_AXP
> + help
> + Enable support for reading the USB power supply status from
> + X-Powers AXP2xx and AXP8xx PMICs.
> +
> config DM_REGULATOR_BD71837
> bool "Enable Driver Model for ROHM BD71837/BD71847 regulators"
> depends on DM_REGULATOR && DM_PMIC_BD71837
> diff --git a/drivers/power/regulator/Makefile
> b/drivers/power/regulator/Makefile
> index 2d97e1033a..d9e0cd5949 100644
> --- a/drivers/power/regulator/Makefile
> +++ b/drivers/power/regulator/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
> obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
> obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
> obj-$(CONFIG_$(SPL_)REGULATOR_AXP) += axp_regulator.o
> +obj-$(CONFIG_$(SPL_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o
> obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o
> obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
> obj-$(CONFIG_DM_REGULATOR_NPCM8XX) += npcm8xx_regulator.o
> diff --git a/drivers/power/regulator/axp_usb_power.c
> b/drivers/power/regulator/axp_usb_power.c
> new file mode 100644
> index 00..f32fb6a92d
> --- /dev/null
> +++ b/drivers/power/regulator/axp_usb_power.c
> @@ -0,0 +1,49 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#define AXP_POWER_STATUS 0x00
> +#define AXP_POWER_STATUS_VBUS_PRESENTBIT(5)
> +
> +static int axp_usb_power_get_enable(struct udevice *dev)
> +{
> + int ret;
> +
> + ret = pmic_reg_read(dev->parent, AXP_POWER_STATUS);
> + if (ret < 0)
> + return ret;
> +
> + return !!(ret & AXP_POWER_STATUS_VBUS_PRESENT);
> +}
> +
> +static const struct dm_regulator_ops axp_usb_power_ops = {
> + .get_enable = axp_usb_power_get_enable,
> +};
> +
> +static int axp_usb_power_probe(struct udevice *dev)
> +{
> + struct dm_regulator_uclass_plat *uc_plat = dev_get_uclass_plat(dev);
> +
> + uc_plat->type = REGULATOR_TYPE_FIXED;
> +
> + return 0;
> +}
> +
> +static const struct udevice_id axp_usb_power_ids[] = {
> + { .compatible = "x-powers,axp202-usb-power-supply" },
> + { .compatible = "x-powers,axp221-usb-power-supply" },
> + { .compatible = "x-powers,axp223-usb-power-supply" },
> + { .compatible = "x-powers,axp813-usb-power-supply" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(axp_usb_power) = {
> + .name = "axp_usb_power",
> + .id = UCLASS_REGULATOR,
> + .of_match = axp_usb_power_ids,
> + .probe = axp_usb_power_probe,
> + .ops= &axp_usb_power_ops,
> +};
Re: [PATCH v5 1/3] regulator: implement basic reference counter
On Wed, Apr 19, 2023 at 6:45 AM Eugen Hristev
wrote:
>
> Some devices share a regulator supply, when the first one will request
> regulator disable, the second device will have it's supply cut off before
> graciously shutting down. Hence there will be timeouts and other failed
> operations.
> Implement a reference counter mechanism similar with what is done in
> Linux, to keep track of enable and disable requests, and only disable the
> regulator when the last of the consumers has requested shutdown.
>
> Signed-off-by: Eugen Hristev
> Reviewed-by: Simon Glass
> ---
> Changes in v5:
> - none
> Changes in v4:
> - add documentation for error codes
> Changes in v3:
> - add error return codes
> Changes in v2:
> - add info in header regarding the function
>
> drivers/power/regulator/regulator_common.c | 22 ++
> drivers/power/regulator/regulator_common.h | 21 +
> 2 files changed, 43 insertions(+)
>
> diff --git a/drivers/power/regulator/regulator_common.c
> b/drivers/power/regulator/regulator_common.c
> index 93d8196b381e..484a4fc31ef7 100644
> --- a/drivers/power/regulator/regulator_common.c
> +++ b/drivers/power/regulator/regulator_common.c
> @@ -73,6 +73,23 @@ int regulator_common_set_enable(const struct udevice *dev,
> return 0;
> }
>
> + /* If previously enabled, increase count */
> + if (enable && dev_pdata->enable_count > 0) {
> + dev_pdata->enable_count++;
> + return -EALREADY;
> + }
> +
> + if (!enable) {
> + if (dev_pdata->enable_count > 1) {
> + /* If enabled multiple times, decrease count */
> + dev_pdata->enable_count--;
> + return -EBUSY;
> + } else if (!dev_pdata->enable_count) {
> + /* If already disabled, do nothing */
> + return -EALREADY;
> + }
> + }
> +
Eugen,
Thank you for working on this series!
I wonder if instead of returning a failure you should print an error
here but return 0 in order to not break unbalanced regulator calls
(like what is done in clk_disable()). I see that you have another
patch in this series which handles htis for
regulator_set_enable_if_allowed() but that doesn't cover drivers that
call regulator_common_set_enable() directly such as
drivers/power/regulator/fixed.c and
drivers/power/regulator/gpio-regulator.c.
I know there is an unbalanced call currently on imx8mm that this patch
causes a failure where it previously did not:
u-boot=> usb start && usb tree
starting USB...
Bus usb@32e4: Bus usb@32e5: Error enabling VBUS supply (ret=-114)
probe failed, error -114
Best Regards,
Tim
Re: Question regarding CONFIG_SPL_OF_PLATDATA_INST usage
Hi Lukasz, On Thu, 27 Apr 2023 at 09:23, Lukasz Majewski wrote: > > Hi Simon, > > I'm trying to convert imx28 based XEA board to use CONFIG_DM_SERIAL. > This board uses SPL_OF_PLATDATA to have as small SPL as possible. > > It looks like the 'duart' description/driver is properly instantiated, > but serial console is configured too early -> apparently > serial_find_console_or_panic() from serial_init() at serial-uclass.c is > called before DM is setup in SPL. > > > To fix this problem - in the commit (SHA1: 5a1b25c2011) the > CONFIG_SPL_OF_PLATDATA_INST has been introduced; without it (after > commit SHA1: 1e9ced28f18ed75bef96df08e47baad27dd51829) uclass_get() > returns -EDEADLOCK. That is not the goal of the _INST feature. The goal is to drop the need for the device_bind() function, thus cutting down the code size of driver model by about 1KB. To get DM inited early you can call spl_early_init(). > > > Grepping the sources show that only two "boards" use it: > > 1. arch/x86/cpu/apollolake/Kconfig -> TPL_OF_PLATDATA_INST >(configs/chromebook_coral_defconfig and corresponding >./arch/x86/dts/chromebook_coral.dts) > > 2. configs/sandbox_spl_defconfig -> CONFIG_SPL_OF_PLATDATA_INST=y > > > > I would like to ask if: > > - Anybody managed to use CONFIG_SPL_OF_PLATDATA_INST=y on real HW? > > - Is it on purpose, that dtoc tool is not extracting structures > definitions from *.c files ? I don't understand that question, sorry. The docs is at [1] but I suppose you saw that. > > - Is the "coral" board (from point 1 above) using any extra > coral*-u-boot.dtsi to specify which parts of dts shall be included to > the in-TPL DTS? Or is it just using full-blown DTS support ins TPL? Yes it is using tags, since we don't want all the devices in TPL. It only has enough to use serial, SPI flash and some early pinmux stuff. You can build it and take a look. > > > I'm using cutting-edge mainline u-boot - SHA1: > 6a11fdf0536e02ac9cd4a3da0535a271c694715f > > Thanks in advance for any help. Regards, Simon [1] https://u-boot.readthedocs.io/en/latest/develop/driver-model/of-plat.html?highlight=of-platdata#build-time-instantiation
Re: [PATCH v5 1/4] efi_loader: get version information from device tree
Hi Masahisa,
On Mon, 10 Apr 2023 at 03:07, Masahisa Kojima
wrote:
>
> Current FMP->GetImageInfo() always return 0 for the firmware
> version, user can not identify which firmware version is currently
> running through the EFI interface.
>
> This commit gets the version information from device tree,
> then fills the firmware version, lowest supported version
> in FMP->GetImageInfo().
>
> Now FMP->GetImageInfo() and ESRT have the meaningful version number.
>
> Signed-off-by: Masahisa Kojima
> ---
> Changes in v5:
> - newly implement a device tree based versioning
>
> .../firmware/firmware-version.txt | 25
> lib/efi_loader/efi_firmware.c | 63 +--
> 2 files changed, 84 insertions(+), 4 deletions(-)
> create mode 100644 doc/device-tree-bindings/firmware/firmware-version.txt
>
> diff --git a/doc/device-tree-bindings/firmware/firmware-version.txt
> b/doc/device-tree-bindings/firmware/firmware-version.txt
> new file mode 100644
> index 00..6112de4a1d
> --- /dev/null
> +++ b/doc/device-tree-bindings/firmware/firmware-version.txt
> @@ -0,0 +1,25 @@
> +firmware-version bindings
> +---
> +
> +Required properties:
> +- image-type-id: guid for image blob type
> +- image-index : image index
> +- fw-version : firmware version
> +- lowest-supported-version : lowest supported version
> +
> +Example:
> +
> + firmware-version {
> + image1 {
> + image-type-id =
> "09D7CF52-0720-4710-91D1-08469B7FE9C8";
Nit: please use lower-case hex and add a decoder to uuid.c so we can
look it up when debugging.
> + image-index = <1>;
> + fw-version = <5>;
> + lowest-supported-version = <3>;
> + };
> + image2 {
> + image-type-id =
> "5A7021F5-FEF2-48B4-AABA-832E777418C0";
> + image-index = <2>;
> + fw-version = <10>;
> + lowest-supported-version = <7>;
> + };
> + };
[..]
Regards,
Simon
Re: [PATCH v2 0/7] introduce NVM XIP block storage emulation
On Mon, 17 Apr 2023 10:11:51 +0100, Abdellatif El Khlifi wrote: > Adding block storage emulation for NVM XIP flash devices. > > Some paltforms such as Corstone-1000 need to see NVM XIP raw flash > as a block storage device with read only capability. > > Here NVM flash devices are devices with addressable > memory (e.g: QSPI NOR flash). > > [...] Applied to u-boot/master, thanks! -- Tom
Re: [PATCH 1/3] arm: dts: imx8mm: Sync with Linux 6.3
On Thu, Apr 27, 2023 at 12:49 PM Fabio Estevam wrote:
>
> On Thu, Apr 27, 2023 at 4:44 PM Tim Harvey wrote:
>
> > Fabio,
> >
> > Sorry for the confusion.
> >
> > This imx8mm dt sync patch will hang on imx8mm boards that use 'both'
> > usbotg1 and usbotg2. You can reproduce this hang on your imx8mm-evk by
> > enabling usbotg2 in the dt (the board has it but it is not enabled due
> > to the gpio based usb 3.0 mux not being sorted out yet):
> > +&usbotg2 {
> > + dr_mode = "otg";
> > + status = "okay";
> > +};
> > +
> >
> > u-boot=> usb start && usb tree
> > starting USB...
> > Bus usb@32e4: Bus usb@32e5:
> > ^^^ imx8mm-evk hangs
>
> Yes, I can reproduce the hang, but it happens with or without the
> imx8mm dt sync.
>
Fabio,
I do 'not' see a hang on imx8mm-evk on 'usb start && usb tree' on
master (my other issue was on a 'usb stop' but only with usb
controllers in host mode).
> This hang is a separate issue, not dt related, as far as I understand.
>
> The imx8mm dts sync does solve the issue of running 'ums' after CTRL+C.
I don't agree. The hang 'is' related because all my imx8mm-venice-*
boards which use 'both' USB controllers hang with this patch on a 'usb
start' and don't hang without it. While a basic 'review' of the patch
looks good but actual product testing shows issues. As a maintainer
for ARM FREESCALE IMX you must have another imx8mm board which uses
both usbotg devices to test against and verify you see what I see?
Until we know what other fix is needed to go along with this:
Nacked-by: Tim Harvey
I've verified that it's the changes from Linux commit 4585c79ff477f
("arm64: dts: imx8mm: correct usb power domains") that causes the
hang, but I don't know why yet.
Why are we seeing different behavior on the imx8mm-evk? Are we on
different branches? My testing today is on caf0a88d9f31
Best Regards,
Tim
atmel_sdhci: SDMMC_CD pin still needed for card detection despite EMMC set to non-removable
Hardware: SAMA5D27 customized board, EMMC connected to SDMMC0. SDMMC0_CD pin
pulled-down for BootROM card detection, once booted it used as LED output.
Software: u-boot-at91 76f7f55
Issue:
U-Boot can't detect EMMC despite it set to non-removable in DT, unless
SDMMC0_CD pin is used (so this pin can't be used for other purpose)
sdmmc0: sdio-host@a000 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 =
<&pinctrl_sdmmc0_default>;
status = "okay";
non-removable;
no-1-8-v;
};
Workaround: I have to FCD bit of SDMMC_MC1R register.
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 766e4a6b0c..89ceeaf3c1 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -758,7 +758,12 @@ static int sdhci_get_cd(struct udevice *dev)
/* If nonremovable, assume that the card is always present. */
if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
+ {
+ value = sdhci_readb(host, SDHCI_HOST_MC1R);
+ sdhci_writeb(host, SDHCI_VENDOR_MC1R_FCD | value,
SDHCI_HOST_MC1R);
return 1;
+ }
+
/* If polling, assume that the card is always present. */
if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
return 1;
diff --git a/include/sdhci.h b/include/sdhci.h
index c718dd7206..61e7ebb2a1 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -223,6 +223,9 @@
#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
+#define SDHCI_HOST_MC1R0x204
+
+#define SDHCI_VENDOR_MC1R_FCD 0x80
/*
* End of controller registers.
*/
[RFC PATCH v1 7/7] cmd: clk: Remove __weak from soc_clk_dump
After introducing dump to clk_ops there is no need to override this
symbol anymore.
Signed-off-by: Igor Prusov
---
cmd/clk.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/cmd/clk.c b/cmd/clk.c
index 55fb96e631..54491ac577 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -59,7 +59,7 @@ static void show_clks(struct udevice *dev, int depth, int
last_flag)
}
}
-int __weak soc_clk_dump(void)
+int soc_clk_dump(void)
{
struct udevice *dev;
const struct clk_ops *ops;
@@ -81,7 +81,7 @@ int __weak soc_clk_dump(void)
return 0;
}
#else
-int __weak soc_clk_dump(void)
+int soc_clk_dump(void)
{
puts("Not implemented\n");
return 1;
--
2.34.1
[RFC PATCH v1 6/7] clk: treewide: switch to clock dump from clk_ops
Switch to using new dump operation in clock provider drivers instead of
overriding soc_clk_dump.
Signed-off-by: Igor Prusov
---
arch/mips/mach-pic32/cpu.c | 23 ---
drivers/clk/aspeed/clk_ast2600.c | 13 -
drivers/clk/clk_k210.c | 11 +++-
drivers/clk/clk_pic32.c| 39 ++
drivers/clk/clk_versal.c | 7 -
drivers/clk/clk_zynq.c | 19 -
drivers/clk/clk_zynqmp.c | 13 -
drivers/clk/imx/clk-imx8.c | 11 +++-
drivers/clk/mvebu/armada-37xx-periph.c | 5 +++-
drivers/clk/stm32/clk-stm32mp1.c | 29 ++-
10 files changed, 83 insertions(+), 87 deletions(-)
diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
index de449e3c6a..2875a1ec7c 100644
--- a/arch/mips/mach-pic32/cpu.c
+++ b/arch/mips/mach-pic32/cpu.c
@@ -148,26 +148,3 @@ const char *get_core_name(void)
return str;
}
#endif
-#ifdef CONFIG_CMD_CLK
-
-int soc_clk_dump(void)
-{
- int i;
-
- printf("PLL Speed: %lu MHz\n",
- CLK_MHZ(rate(PLLCLK)));
-
- printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK)));
-
- printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
-
- for (i = PB1CLK; i <= PB7CLK; i++)
- printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
- CLK_MHZ(rate(i)));
-
- for (i = REF1CLK; i <= REF5CLK; i++)
- printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
- CLK_MHZ(rate(i)));
- return 0;
-}
-#endif
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index b3cc8392fa..08db21d394 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -1109,6 +1109,7 @@ struct aspeed_clks {
const char *name;
};
+#if IS_ENABLED(CONFIG_CMD_CLK)
static struct aspeed_clks aspeed_clk_names[] = {
{ ASPEED_CLK_HPLL, "hpll" },
{ ASPEED_CLK_MPLL, "mpll" },
@@ -1123,18 +1124,12 @@ static struct aspeed_clks aspeed_clk_names[] = {
{ ASPEED_CLK_HUARTX, "huxclk" },
};
-int soc_clk_dump(void)
+int ast2600_clk_dump(struct udevice *dev)
{
- struct udevice *dev;
struct clk clk;
unsigned long rate;
int i, ret;
- ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(aspeed_scu),
- &dev);
- if (ret)
- return ret;
-
printf("Clk\t\tHz\n");
for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) {
@@ -1167,11 +1162,15 @@ int soc_clk_dump(void)
return 0;
}
+#endif
struct clk_ops ast2600_clk_ops = {
.get_rate = ast2600_clk_get_rate,
.set_rate = ast2600_clk_set_rate,
.enable = ast2600_clk_enable,
+#if IS_ENABLED(CONFIG_CMD_CLK)
+ .dump = ast2600_clk_dump,
+#endif
};
static int ast2600_clk_probe(struct udevice *dev)
diff --git a/drivers/clk/clk_k210.c b/drivers/clk/clk_k210.c
index 2f17152021..656d6f5610 100644
--- a/drivers/clk/clk_k210.c
+++ b/drivers/clk/clk_k210.c
@@ -1276,16 +1276,10 @@ static void show_clks(struct k210_clk_priv *priv, int
id, int depth)
}
}
-int soc_clk_dump(void)
+int k210_clk_dump(struct udevice *dev)
{
- int ret;
- struct udevice *dev;
struct k210_clk_priv *priv;
- ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(k210_clk),
- &dev);
- if (ret)
- return ret;
priv = dev_get_priv(dev);
puts(" Rate Enabled Name\n");
@@ -1304,6 +1298,9 @@ static const struct clk_ops k210_clk_ops = {
.set_parent = k210_clk_set_parent,
.enable = k210_clk_enable,
.disable = k210_clk_disable,
+#if IS_ENABLED(CONFIG_CMD_CLK)
+ .dump = k210_clk_dump,
+#endif
};
static int k210_clk_probe(struct udevice *dev)
diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c
index ef06a7fb9f..f756fc88f0 100644
--- a/drivers/clk/clk_pic32.c
+++ b/drivers/clk/clk_pic32.c
@@ -20,6 +20,8 @@
DECLARE_GLOBAL_DATA_PTR;
+#define CLK_MHZ(x) ((x) / 100)
+
/* Primary oscillator */
#define SYS_POSC_CLK_HZ2400
@@ -385,9 +387,46 @@ static ulong pic32_set_rate(struct clk *clk, ulong rate)
return rate;
}
+#if IS_ENABLED(CONFIG_CMD_CLK)
+static int pic32_dump(struct udevice *dev)
+{
+ int i;
+ struct clk clk;
+
+ clk.dev = dev;
+
+ clk.id = PLLCLK;
+ printf("PLL Speed: %lu MHz\n",
+ CLK_MHZ(pic32_get_rate(&clk)));
+
+ clk.id = PB7CLK;
+ printf("CPU Speed: %lu MHz\n", CLK_MHZ(pic32_get_rate(&clk)));
+
+ clk.id = MPLL;
+ printf("MPLL Speed: %lu MHz\n", CLK_MHZ(pic32_get_rate(&clk)));
+
+ for (i = PB1CLK; i <= PB7CLK; i++) {
+ clk.id = i;
+ printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
+
[RFC PATCH v1 5/7] cmd: clk: Use dump function from clk_ops
Add another loop to dump additional info from clock providers that
implement dump operation.
Signed-off-by: Igor Prusov
---
cmd/clk.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/cmd/clk.c b/cmd/clk.c
index ff7c7649a1..55fb96e631 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -62,6 +62,7 @@ static void show_clks(struct udevice *dev, int depth, int
last_flag)
int __weak soc_clk_dump(void)
{
struct udevice *dev;
+ const struct clk_ops *ops;
printf(" Rate Usecnt Name\n");
printf("--\n");
@@ -69,6 +70,14 @@ int __weak soc_clk_dump(void)
uclass_foreach_dev_probe(UCLASS_CLK, dev)
show_clks(dev, -1, 0);
+ uclass_foreach_dev_probe(UCLASS_CLK, dev) {
+ ops = dev_get_driver_ops(dev);
+ if (ops && ops->dump) {
+ printf("--\n");
+ ops->dump(dev);
+ }
+ }
+
return 0;
}
#else
--
2.34.1
[RFC PATCH v1 3/7] clk: k210: Move soc_clk_dump function
Move clock dump function to avoid forward declaration after switching to
dump in clk_ops.
Signed-off-by: Igor Prusov
---
drivers/clk/clk_k210.c | 92 +-
1 file changed, 46 insertions(+), 46 deletions(-)
diff --git a/drivers/clk/clk_k210.c b/drivers/clk/clk_k210.c
index c534cc07e0..2f17152021 100644
--- a/drivers/clk/clk_k210.c
+++ b/drivers/clk/clk_k210.c
@@ -1238,52 +1238,6 @@ static int k210_clk_request(struct clk *clk)
return 0;
}
-static const struct clk_ops k210_clk_ops = {
- .request = k210_clk_request,
- .set_rate = k210_clk_set_rate,
- .get_rate = k210_clk_get_rate,
- .set_parent = k210_clk_set_parent,
- .enable = k210_clk_enable,
- .disable = k210_clk_disable,
-};
-
-static int k210_clk_probe(struct udevice *dev)
-{
- int ret;
- struct k210_clk_priv *priv = dev_get_priv(dev);
-
- priv->base = dev_read_addr_ptr(dev_get_parent(dev));
- if (!priv->base)
- return -EINVAL;
-
- ret = clk_get_by_index(dev, 0, &priv->in0);
- if (ret)
- return ret;
-
- /*
-* Force setting defaults, even before relocation. This is so we can
-* set the clock rate for PLL1 before we relocate into aisram.
-*/
- if (!(gd->flags & GD_FLG_RELOC))
- clk_set_defaults(dev, CLK_DEFAULTS_POST_FORCE);
-
- return 0;
-}
-
-static const struct udevice_id k210_clk_ids[] = {
- { .compatible = "canaan,k210-clk" },
- { },
-};
-
-U_BOOT_DRIVER(k210_clk) = {
- .name = "k210_clk",
- .id = UCLASS_CLK,
- .of_match = k210_clk_ids,
- .ops = &k210_clk_ops,
- .probe = k210_clk_probe,
- .priv_auto = sizeof(struct k210_clk_priv),
-};
-
#if IS_ENABLED(CONFIG_CMD_CLK)
static char show_enabled(struct k210_clk_priv *priv, int id)
{
@@ -1342,3 +1296,49 @@ int soc_clk_dump(void)
return 0;
}
#endif
+
+static const struct clk_ops k210_clk_ops = {
+ .request = k210_clk_request,
+ .set_rate = k210_clk_set_rate,
+ .get_rate = k210_clk_get_rate,
+ .set_parent = k210_clk_set_parent,
+ .enable = k210_clk_enable,
+ .disable = k210_clk_disable,
+};
+
+static int k210_clk_probe(struct udevice *dev)
+{
+ int ret;
+ struct k210_clk_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev_get_parent(dev));
+ if (!priv->base)
+ return -EINVAL;
+
+ ret = clk_get_by_index(dev, 0, &priv->in0);
+ if (ret)
+ return ret;
+
+ /*
+* Force setting defaults, even before relocation. This is so we can
+* set the clock rate for PLL1 before we relocate into aisram.
+*/
+ if (!(gd->flags & GD_FLG_RELOC))
+ clk_set_defaults(dev, CLK_DEFAULTS_POST_FORCE);
+
+ return 0;
+}
+
+static const struct udevice_id k210_clk_ids[] = {
+ { .compatible = "canaan,k210-clk" },
+ { },
+};
+
+U_BOOT_DRIVER(k210_clk) = {
+ .name = "k210_clk",
+ .id = UCLASS_CLK,
+ .of_match = k210_clk_ids,
+ .ops = &k210_clk_ops,
+ .probe = k210_clk_probe,
+ .priv_auto = sizeof(struct k210_clk_priv),
+};
--
2.34.1
[RFC PATCH v1 4/7] clk: Add dump operation to clk_ops
This adds dump function to struct clk_ops which should replace
soc_clk_dump. It allows clock drivers to provide custom dump
implementation without overriding generic CCF dump function.
Signed-off-by: Igor Prusov
---
include/clk-uclass.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/clk-uclass.h b/include/clk-uclass.h
index 65ebff9ed2..f29f4c0d01 100644
--- a/include/clk-uclass.h
+++ b/include/clk-uclass.h
@@ -39,6 +39,9 @@ struct clk_ops {
int (*set_parent)(struct clk *clk, struct clk *parent);
int (*enable)(struct clk *clk);
int (*disable)(struct clk *clk);
+#if IS_ENABLED(CONFIG_CMD_CLK)
+ int (*dump)(struct udevice *dev);
+#endif
};
#if 0 /* For documentation only */
--
2.34.1
[RFC PATCH v1 1/7] clk: zynq: Move soc_clk_dump to Zynq clock driver
Move clock dump function in preparation for switching to dump function
in clk_ops.
Signed-off-by: Igor Prusov
---
arch/arm/mach-zynq/clk.c | 57 ---
drivers/clk/clk_zynq.c | 58
2 files changed, 58 insertions(+), 57 deletions(-)
diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c
index 1945f60e08..e6a67326dd 100644
--- a/arch/arm/mach-zynq/clk.c
+++ b/arch/arm/mach-zynq/clk.c
@@ -13,20 +13,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static const char * const clk_names[clk_max] = {
- "armpll", "ddrpll", "iopll",
- "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
- "ddr2x", "ddr3x", "dci",
- "lqspi", "smc", "pcap", "gem0", "gem1",
- "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
- "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma",
- "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper",
- "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper",
- "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
- "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper",
- "smc_aper", "swdt", "dbg_trc", "dbg_apb"
-};
-
/**
* set_cpu_clk_info() - Setup clock information
*
@@ -65,46 +51,3 @@ int set_cpu_clk_info(void)
return 0;
}
-
-/**
- * soc_clk_dump() - Print clock frequencies
- * Returns zero on success
- *
- * Implementation for the clk dump command.
- */
-int soc_clk_dump(void)
-{
- struct udevice *dev;
- int i, ret;
-
- ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_DRIVER_GET(zynq_clk), &dev);
- if (ret)
- return ret;
-
- printf("clk\t\tfrequency\n");
- for (i = 0; i < clk_max; i++) {
- const char *name = clk_names[i];
- if (name) {
- struct clk clk;
- unsigned long rate;
-
- clk.id = i;
- ret = clk_request(dev, &clk);
- if (ret < 0)
- return ret;
-
- rate = clk_get_rate(&clk);
-
- clk_free(&clk);
-
- if ((rate == (unsigned long)-ENOSYS) ||
- (rate == (unsigned long)-ENXIO))
- printf("%10s%20s\n", name, "unknown");
- else
- printf("%10s%20lu\n", name, rate);
- }
- }
-
- return 0;
-}
diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c
index e80500e382..be5226175f 100644
--- a/drivers/clk/clk_zynq.c
+++ b/drivers/clk/clk_zynq.c
@@ -454,6 +454,64 @@ static int dummy_enable(struct clk *clk)
return 0;
}
+static const char * const clk_names[clk_max] = {
+ "armpll", "ddrpll", "iopll",
+ "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
+ "ddr2x", "ddr3x", "dci",
+ "lqspi", "smc", "pcap", "gem0", "gem1",
+ "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+ "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma",
+ "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper",
+ "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper",
+ "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
+ "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper",
+ "smc_aper", "swdt", "dbg_trc", "dbg_apb"
+};
+
+/**
+ * soc_clk_dump() - Print clock frequencies
+ * Returns zero on success
+ *
+ * Implementation for the clk dump command.
+ */
+int soc_clk_dump(void)
+{
+ struct udevice *dev;
+ int i, ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(zynq_clk), &dev);
+ if (ret)
+ return ret;
+
+ printf("clk\t\tfrequency\n");
+ for (i = 0; i < clk_max; i++) {
+ const char *name = clk_names[i];
+
+ if (name) {
+ struct clk clk;
+ unsigned long rate;
+
+ clk.id = i;
+ ret = clk_request(dev, &clk);
+ if (ret < 0)
+ return ret;
+
+ rate = clk_get_rate(&clk);
+
+ clk_free(&clk);
+
+ if ((rate == (unsigned long)-ENOSYS) ||
+ (rate == (unsigned long)-ENXIO))
+ printf("%10s%20s\n", name, "unknown");
+ else
+ printf("%10s%20lu\n", name, rate);
+ }
+ }
+
+ return 0;
+}
+
static struct clk_ops zynq_clk_ops = {
.get_rate = zynq_clk_get_rate,
#ifndef CONFIG_SPL_BUILD
--
2.34.1
