Re: [PATCH next v2] rockchip: puma-rk3399: increase Ethernet PHY timeout to 30s
On 2024/6/19 23:44, Quentin Schulz wrote: From: Quentin Schulz On Puma v2.1 with a KSZ9031, the Ethernet PHY often doesn't detect the link in the 4-second default timeout. After some boot-loop test for about a thousand boots, 70% were below 10s, 90% below 15s and 100% below 30s. Let's play it safe and make it 30s so that hopefully all links that should be detected are. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- Changes in v2: - rebase on next - use Kconfig symbol instead of constant in include/configs/ - Link to v1: https://lore.kernel.org/r/20240619-puma-eth-timeout-v1-1-db5c17153...@cherry.de --- configs/puma-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 5319239f989..4293cf0ae44 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -69,6 +69,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_ANEG_TIMEOUT=3 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y --- base-commit: 01a5d7547ed3a51a8ac5837c31a150f85bc475f8 change-id: 20240619-puma-eth-timeout-41be9c243ed7 Best regards,
Re: [PATCH v2 2/3] configs: rockchip: sync ENV_MEM_LAYOUT_SETTINGS for rk3308, rk3328, and rk3399
On 2024/6/18 17:53, FUKAUMI Naoki wrote: - add support for compressed kernel for rk3308 - prepare support for fdtoverlay for rk3328 tested on ROCK Pi S 256MB, ROCK Pi E 2GB, and ROCK Pi 4A 4GB with linux-next-20240613 defconfig kernel. Signed-off-by: FUKAUMI Naoki Reviewed-by: Kever Yang Thanks, - Kever Changes in v2: - minor cosmetic change in commit message --- include/configs/rk3308_common.h | 12 include/configs/rk3328_common.h | 5 - include/configs/rk3399_common.h | 4 ++-- 3 files changed, 14 insertions(+), 7 deletions(-) diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 80113220e4..2de55538fd 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -15,11 +15,15 @@ #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x0050\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ "pxefile_addr_r=0x0060\0" \ - "fdt_addr_r=0x03e0\0" \ - "fdtoverlay_addr_r=0x03f0\0" \ - "kernel_addr_r=0x0068\0" \ - "ramdisk_addr_r=0x0400\0" + "fdt_addr_r=0x01e0\0" \ + "fdtoverlay_addr_r=0x01f0\0" \ + "kernel_addr_r=0x0208\0" \ + "ramdisk_addr_r=0x0600\0" \ + "kernel_comp_addr_r=0x0800\0" \ + "kernel_comp_size=0x200\0" #define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index f9e6634c5f..bd2bfe2910 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -15,8 +15,11 @@ #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x0050\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ "pxefile_addr_r=0x0060\0" \ - "fdt_addr_r=0x01f0\0" \ + "fdt_addr_r=0x01e0\0" \ + "fdtoverlay_addr_r=0x01f0\0" \ "kernel_addr_r=0x0208\0" \ "ramdisk_addr_r=0x0600\0" \ "kernel_comp_addr_r=0x0800\0" \ diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 62007c8b27..d652ae4ca3 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -24,8 +24,8 @@ "script_offset_f=0xffe000\0" \ "script_size_f=0x2000\0" \ "pxefile_addr_r=0x0060\0" \ - "fdt_addr_r=0x01f0\0" \ - "fdtoverlay_addr_r=0x0200\0" \ + "fdt_addr_r=0x01e0\0" \ + "fdtoverlay_addr_r=0x01f0\0" \ "kernel_addr_r=0x0208\0" \ "ramdisk_addr_r=0x0600\0" \ "kernel_comp_addr_r=0x0800\0" \
Re: [PATCH v2 1/3] configs: rockchip: reduce diff for rk3308, rk3328, rk3399, rk3568, and rk3588
On 2024/6/18 17:53, FUKAUMI Naoki wrote: this is cosmetic change. no functional change is intended. - remove redundant white spaces - replace white spaces with tab - align position of last letter/word - sort lines in CFG_EXTRA_ENV_SETTINGS - add comment after #endif Signed-off-by: FUKAUMI Naoki Reviewed-by: Kever Yang Thanks, - Kever Changes in v2: - rewrite whole commit message --- include/configs/rk3308_common.h | 26 ++--- include/configs/rk3328_common.h | 28 +++ include/configs/rk3399_common.h | 40 - include/configs/rk3568_common.h | 14 ++-- include/configs/rk3588_common.h | 12 +- 5 files changed, 60 insertions(+), 60 deletions(-) diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 861154fbeb..80113220e4 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -8,24 +8,24 @@ #include "rockchip-common.h" -#define CFG_IRAM_BASE 0xfff8 +#define CFG_IRAM_BASE 0xfff8 #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE0xff00 -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x0050\0" \ - "pxefile_addr_r=0x0060\0" \ - "fdt_addr_r=0x03e0\0" \ - "fdtoverlay_addr_r=0x03f0\0" \ - "kernel_addr_r=0x0068\0" \ +#define ENV_MEM_LAYOUT_SETTINGS\ + "scriptaddr=0x0050\0" \ + "pxefile_addr_r=0x0060\0" \ + "fdt_addr_r=0x03e0\0" \ + "fdtoverlay_addr_r=0x03f0\0" \ + "kernel_addr_r=0x0068\0" \ "ramdisk_addr_r=0x0400\0" -#define CFG_EXTRA_ENV_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - ENV_MEM_LAYOUT_SETTINGS \ - "partitions=" PARTS_DEFAULT \ - ROCKCHIP_DEVICE_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS\ "boot_targets=" BOOT_TARGETS "\0" -#endif +#endif /* __CONFIG_RK3308_COMMON_H */ diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 2c40674b22..f9e6634c5f 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -8,25 +8,25 @@ #include "rockchip-common.h" -#define CFG_IRAM_BASE 0xff09 +#define CFG_IRAM_BASE 0xff09 #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE0xff00 -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x0050\0" \ - "pxefile_addr_r=0x0060\0" \ - "fdt_addr_r=0x01f0\0" \ - "kernel_addr_r=0x0208\0" \ - "ramdisk_addr_r=0x0600\0" \ - "kernel_comp_addr_r=0x0800\0" \ +#define ENV_MEM_LAYOUT_SETTINGS\ + "scriptaddr=0x0050\0" \ + "pxefile_addr_r=0x0060\0" \ + "fdt_addr_r=0x01f0\0" \ + "kernel_addr_r=0x0208\0" \ + "ramdisk_addr_r=0x0600\0" \ + "kernel_comp_addr_r=0x0800\0" \ "kernel_comp_size=0x200\0" -#define CFG_EXTRA_ENV_SETTINGS \ - ENV_MEM_LAYOUT_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ - ROCKCHIP_DEVICE_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS\ "boot_targets=" BOOT_TARGETS "\0" -#endif +#endif /* __CONFIG_RK3328_COMMON_H */ diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 4e75771055..62007c8b27 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -8,36 +8,36 @@ #include "rockchip-common.h" -#define CFG_IRAM_BASE 0xff8c +#define CFG_IRAM_BASE 0xff8c #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE0xf800 #ifndef CONFIG_SPL_BUILD -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x0050\0" \ - "script_offset_f=0xffe000\0" \ - "script_size_f=0x2000\0" \ - "pxefile_addr_r=0x0060\0" \ - "fdt_addr_r=0x01f0\0" \ - "fdtoverlay_addr_r=0x0200\0" \ - "ker
Re: [PATCH] rockchip: include cru_rk3588.h and define rockchip_cru for RK3588
On 2024/6/19 03:30, FUKAUMI Naoki wrote:
fix following error found by clang:
CC arch/arm/mach-rockchip/cpu-info.o
arch/arm/mach-rockchip/cpu-info.c:23:13: error: incomplete definition of type
'struct rockchip_cru'
23 | switch (cru->glb_rst_st) {
| ~~~^
./arch/arm/include/asm/arch-rockchip/clock.h:181:8: note: forward declaration
of 'struct rockchip_cru'
181 | struct rockchip_cru;
|^
1 error generated.
Signed-off-by: FUKAUMI Naoki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/include/asm/arch-rockchip/cru.h| 2 ++
arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
b/arch/arm/include/asm/arch-rockchip/cru.h
index 9778790f34..c3259b8e7c 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -17,6 +17,8 @@
# include
#elif defined(CONFIG_ROCKCHIP_RK3568)
#include
+#elif defined(CONFIG_ROCKCHIP_RK3588)
+#include
#endif
/* CRU_GLB_RST_ST */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
index a0e54d3965..dad484813f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -92,6 +92,8 @@ struct rk3588_cru {
unsigned int pmuclkgate_con[9]; /* Address Offset: 0x0100 */
};
+#define rockchip_cru rk3588_cru
+
check_member(rk3588_cru, mode_con00, 0x280);
check_member(rk3588_cru, pmuclksel_con[1], 0x30304);
Re: [PATCH next 1/4] rockchip: ringneck-px30: disable broken USB gadget
Hi Quentin, On 2024/6/14 19:04, Quentin Schulz wrote: From: Quentin Schulz USB gadget simply doesn't work right now on PX30. Tested on PX30 EVB and PX30 Ringneck with Linux mainline and Rockchip 5.10 Linux as well as U-Boot. Do you mean for both U-Boot and kernel, including mainline version and rockchip version, and on both PX30 EVB and Ringneck board, all SW&HW have no USB gadget working? So when you test this, does the maskrom mode works? because it sounds like maybe the HOST PC is the one have issue at the moment. Thanks, - Kever We don't want to our users to assume that USB gadget is supported on Q7 USB P1 on Ringneck Haikou, so let's remove its support, which also removes the ums CLI command, fastboot and Android image booting support. Signed-off-by: Quentin Schulz --- configs/ringneck-px30_defconfig | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index 23204794205..2ec5f72e47a 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -15,7 +15,6 @@ CONFIG_DEBUG_UART_BASE=0xFF03 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y -# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y @@ -42,6 +41,7 @@ CONFIG_SPL_ATF=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set +CONFIG_CMD_BIND=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -49,7 +49,6 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y @@ -73,8 +72,6 @@ CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_FASTBOOT_BUF_ADDR=0x800800 -CONFIG_FASTBOOT_BUF_SIZE=0x0400 CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_ROCKCHIP_GPIO=y @@ -112,8 +109,6 @@ CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_LZO=y
Re: [PATCH next 3/3] rockchip: ringneck-px30: enable IO domain
On 2024/6/15 00:54, Quentin Schulz wrote: From: Quentin Schulz Enable the IO domain on Ringneck. Based on the current HW design, this should do nothing else than making sure vccio6 iodomain is controlled by the GRF and not GPIO0B6. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/ringneck-px30_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index e7594b7a67b..52a4c9710a9 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -80,6 +80,7 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_ROCKCHIP_OTP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y
Re: [PATCH next 2/3] rockchip: io-domain: add support for PX30
On 2024/6/15 00:54, Quentin Schulz wrote:
From: Quentin Schulz
Port the PX30 part of the Rockchip IO Domain driver from Linux.
This differs from linux version in that the io iodomain bit is enabled
in the write ops instead of in an init ops as in linux, this way we can
avoid keeping a full state of all supplies that have been configured.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/misc/rockchip-io-domain.c | 66 +++
1 file changed, 66 insertions(+)
diff --git a/drivers/misc/rockchip-io-domain.c
b/drivers/misc/rockchip-io-domain.c
index 04d4d07c412..cf4f7c3984c 100644
--- a/drivers/misc/rockchip-io-domain.c
+++ b/drivers/misc/rockchip-io-domain.c
@@ -27,6 +27,10 @@
#define MAX_VOLTAGE_1_8 198
#define MAX_VOLTAGE_3_3 360
+#define PX30_IO_VSEL 0x180
+#define PX30_IO_VSEL_VCCIO6_SRCBIT(0)
+#define PX30_IO_VSEL_VCCIO6_SUPPLY_NUM 1
+
#define RK3328_SOC_CON4 0x410
#define RK3328_SOC_CON4_VCCIO2BIT(7)
#define RK3328_SOC_VCCIO2_SUPPLY_NUM 1
@@ -99,6 +103,22 @@ static int rockchip_iodomain_write(struct regmap *grf, uint
offset, int idx, int
return regmap_write(grf, offset, val);
}
+static int px30_iodomain_write(struct regmap *grf, uint offset, int idx, int uV)
+{
+ int ret = rockchip_iodomain_write(grf, offset, idx, uV);
+
+ if (!ret && idx == PX30_IO_VSEL_VCCIO6_SUPPLY_NUM) {
+ /*
+* set vccio6 iodomain to also use this framework
+* instead of a special gpio.
+*/
+ u32 val = PX30_IO_VSEL_VCCIO6_SRC | (PX30_IO_VSEL_VCCIO6_SRC <<
16);
+ ret = regmap_write(grf, PX30_IO_VSEL, val);
+ }
+
+ return ret;
+}
+
static int rk3328_iodomain_write(struct regmap *grf, uint offset, int idx,
int uV)
{
int ret = rockchip_iodomain_write(grf, offset, idx, uV);
@@ -131,6 +151,44 @@ static int rk3399_pmu_iodomain_write(struct regmap *grf,
uint offset, int idx, i
return ret;
}
+static const struct rockchip_iodomain_soc_data soc_data_px30 = {
+ .grf_offset = 0x180,
+ .supply_names = {
+ NULL,
+ "vccio6-supply",
+ "vccio1-supply",
+ "vccio2-supply",
+ "vccio3-supply",
+ "vccio4-supply",
+ "vccio5-supply",
+ "vccio-oscgpi-supply",
+ },
+ .write = px30_iodomain_write,
+};
+
+static const struct rockchip_iodomain_soc_data soc_data_px30_pmu = {
+ .grf_offset = 0x100,
+ .supply_names = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "pmuio1-supply",
+ "pmuio2-supply",
+ },
+ .write = rockchip_iodomain_write,
+};
+
static const struct rockchip_iodomain_soc_data soc_data_rk3328 = {
.grf_offset = 0x410,
.supply_names = {
@@ -190,6 +248,14 @@ static const struct rockchip_iodomain_soc_data
soc_data_rk3568_pmu = {
};
static const struct udevice_id rockchip_iodomain_ids[] = {
+ {
+ .compatible = "rockchip,px30-io-voltage-domain",
+ .data = (ulong)&soc_data_px30,
+ },
+ {
+ .compatible = "rockchip,px30-pmu-io-voltage-domain",
+ .data = (ulong)&soc_data_px30_pmu,
+ },
{
.compatible = "rockchip,rk3328-io-voltage-domain",
.data = (ulong)&soc_data_rk3328,
Re: [PATCH next 1/3] rockchip: px30: bind sub-nodes for GRF (syscon)
On 2024/6/15 00:54, Quentin Schulz wrote:
From: Quentin Schulz
There are some sub-nodes under the grf DT nodes, so add bind callback
function in syscon_px30 driver to scan them recursively.
Fixes: e9ccb2f526ed ("rockchip: add px30 architecture core")
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/px30/syscon_px30.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-rockchip/px30/syscon_px30.c
b/arch/arm/mach-rockchip/px30/syscon_px30.c
index c9de57493d8..893a5234baa 100644
--- a/arch/arm/mach-rockchip/px30/syscon_px30.c
+++ b/arch/arm/mach-rockchip/px30/syscon_px30.c
@@ -18,6 +18,9 @@ static const struct udevice_id px30_syscon_ids[] = {
U_BOOT_DRIVER(syscon_px30) = {
.id = UCLASS_SYSCON,
.name = "px30_syscon",
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
.of_match = px30_syscon_ids,
};
Re: [PATCH next 3/4] rockchip: px30: imply ARMV8_CRYPTO
On 2024/6/14 19:04, Quentin Schulz wrote: From: Quentin Schulz PX30 supports ARMv8 Cryptography Extensions so let's enable it by default for all PX30 to make FIT verification when enabled much faster. While A35 shouldn't be impacted by ARMV8_SET_SMPEN cache coherency according to the Kconfig help text, let's enable it just in case since it exists in the documentation[1]. For u-boot part of the FIT image, it is now taking 5ms against currently 35ms. fdt-1 check lowered from 3ms to <1ms. atf-1 from 6ms to <1ms. [1] https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/cpu-extended-control-register--el1?lang=en Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- arch/arm/mach-rockchip/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 14b3ab1a572..2242ed9184b 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -16,6 +16,8 @@ config ROCKCHIP_PX30 select DEBUG_UART_BOARD_INIT imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD + imply ARMV8_CRYPTO + imply ARMV8_SET_SMPEN help The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35 including NEON and GPU, Mali-400 graphics, several DDR3 options
Re: [PATCH next 4/4] rockchip: puma-rk3399: add button support
On 2024/6/14 19:04, Quentin Schulz wrote: From: Quentin Schulz The Haikou Devkit exposes 4 buttons over GPIO so let's enable their support so their status can be queried from the `button` command from the CLI. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/puma-rk3399_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 5319239f989..bc9a79107e0 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -56,6 +56,8 @@ CONFIG_ENV_SPI_MAX_HZ=5000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_ROCKCHIP_GPIO=y
Re: [PATCH next 2/4] rockchip: ringneck-px30: enable FIT verification in SPL
On 2024/6/14 19:04, Quentin Schulz wrote: From: Quentin Schulz This enables FIT verification in SPL for its payload (bl31, u-boot.itb, ...). This makes PX30 Ringneck match what happens on other Theobroma boards. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/ringneck-px30_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index 2ec5f72e47a..e7594b7a67b 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -17,8 +17,10 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTSTD_FULL=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -111,6 +113,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y +# CONFIG_RSA is not set CONFIG_LZO=y CONFIG_ERRNO_STR=y # CONFIG_EFI_LOADER is not set
Re: [PATCH RFC v2 22/23] sysreset: rockchip: use fst reset for ARM64 SOC
On 2024/6/1 00:44, Jonas Karlman wrote:
Hi Anand and Kever,
On 2024-05-31 16:18, Anand Moon wrote:
From: Kever Yang
Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.
What is this trying to fix? And what SoCs is affected?
Both fst and snd softreset are available for SoCs, but the fst reset
more thing.
This commit msg is about: in some case the CPU entry may change after
system boot,
eg. the wakeup code for deep sleep mode(which may power off) is locate
at a different address;
with fst reset, the CPU entry is reset to the one bootRom used but the
snd reset can not.
All the mass produced product with ARM64 SoCs are using the first global
reset for warn reset now.
Thanks,
- Kever
My arm64 RK SoCs seem to reset using warm reset (second global reset).
Cc: Jagan Teki
Signed-off-by: Kever Yang
---
drivers/sysreset/sysreset_rockchip.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/sysreset/sysreset_rockchip.c
b/drivers/sysreset/sysreset_rockchip.c
index f353f9b4c7..17aa191349 100644
--- a/drivers/sysreset/sysreset_rockchip.c
+++ b/drivers/sysreset/sysreset_rockchip.c
@@ -22,7 +22,12 @@ int rockchip_sysreset_request(struct udevice *dev, enum
sysreset_t type)
switch (type) {
case SYSRESET_WARM:
+#ifdef CONFIG_ARM64
+ /* Rockchip 64bit SOC need fst reset for cpu reset entry */
+ writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
+#else
writel(0xeca8, cru_base + offset->glb_srst_snd_value);
+#endif
If this is needed maybe use something like this and let it fall through
to SYSRESET_COLD?
if (!IS_ENABLED(CONFIG_ARM64)) {
writel(0xeca8, cru_base + offset->glb_srst_snd_value);
break;
}
Regards,
Jonas
break;
case SYSRESET_COLD:
writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
Re: [PATCH 3/3] rockchip: tiger-rk3588: add PCIe support
On 2024/7/4 20:53, Quentin Schulz wrote: From: Quentin Schulz This enables PCIe support on Tiger as exposed on Q7_PCIE[0123]_[RT]X_[PN] signals and more specifically on the `PCI Express` connector on the Haikou devkit. This was tested with a PCIe to NVMe adapter (e.g. https://www.amazon.de/dp/B07RZZ3TJG). Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/tiger-rk3588_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig index 8fcdd063a3d..8eb1027e449 100644 --- a/configs/tiger-rk3588_defconfig +++ b/configs/tiger-rk3588_defconfig @@ -14,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0xfeb5 CONFIG_DEBUG_UART_CLOCK=2400 # CONFIG_DEBUG_UART_BOARD_INIT is not set CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -41,6 +42,7 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y # CONFIG_CMD_SF is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -89,6 +91,8 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_PHY_ROCKCHIP_USBDP=y
Re: [PATCH 2/3] rockchip: jaguar-rk3588: add PCIe M.2 M-KEY NVMe support
On 2024/7/4 20:53, Quentin Schulz wrote: From: Quentin Schulz Jaguar has an M.2 M-KEY slot for NVMes, connected to the PCIe3 4-lane PHY on RK3588. CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y is technically not necessary since it's required only for the M.2 E-KEY slot on the main PCB, but that is used typically for WiFi+BT modules, or on the mezzanine connector but the features exposed behind that connector aren't supported in U-Boot (no DT for it right now). However, if the PHY driver is missing, we get the following error message: pcie_dw_rockchip pcie@fe17: failed to get pcie phy (ret=-19) and you would need to know which PCIe controller that is before deciding to ignore it. While after enabling the PHY driver, we are greeted with: pcie_dw_rockchip pcie@fe17: PCIe-2 Link Fail which is a bit more acceptable (to me). The other option would be to disable the PCIe2 PHYs/controllers in the DT, which I'm not too fond of. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/jaguar-rk3588_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index 36bf34d97c8..18006467dde 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -13,6 +13,7 @@ CONFIG_TARGET_JAGUAR_RK3588=y CONFIG_DEBUG_UART_BASE=0xfeb5 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -40,6 +41,7 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y # CONFIG_CMD_SF is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -88,7 +90,10 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y
Re: [PATCH 1/3] arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar
On 2024/7/4 20:53, Quentin Schulz wrote:
From: Heiko Stuebner
The Jaguar SBC provides an M.2 slot connected to the pcie3 controller.
In contrast to a number of other boards the pcie-refclk is gpio-controlled,
so the necessary clock and is added to the list of pcie3 clocks.
Signed-off-by: Heiko Stuebner
Reviewed-by: Quentin Schulz
Link: https://lore.kernel.org/r/20240423074956.2622318-1-he...@sntech.de
Signed-off-by: Heiko Stuebner
Reviewed-by: Kever Yang
Thanks,
- Kever
[ upstream commit: 0ec7e1096332bc2b9bc881c21cfd234058f747b3 ]
(cherry picked from commit 76a89655ae740dddb57187b5b52071ed99187452)
---
dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts | 59 +++
1 file changed, 59 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
index 7d7303f8ecb..678ed8b4dcc 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
@@ -72,6 +72,27 @@
};
};
+ /*
+* 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
+* clock generator.
+* The clock output is gated via the OE pin on the clock generator.
+* This is modeled as a fixed-clock plus a gpio-gate-clock.
+*/
+ pcie_refclk_gen: pcie-refclk-gen-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ pcie_refclk: pcie-refclk-clock {
+ compatible = "gpio-gate-clock";
+ clocks = <&pcie_refclk_gen>;
+ #clock-cells = <0>;
+ enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /*
PCIE30X4_CLKREQN_M0 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x4_clkreqn_m0>;
+ };
+
pps {
compatible = "pps-gpio";
gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
@@ -353,6 +374,30 @@
status = "okay";
};
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ /*
+* The board has a gpio-controlled "pcie_refclk" generator,
+* so add it to the list of clocks.
+*/
+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
+<&pcie_refclk>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe",
+ "ref";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x4_waken_m0 &pcie30x4_perstn_m0>;
+ reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTN_M0 */
+ vpcie3v3-supply = <&vcc3v3_mdot2>;
+ status = "okay";
+};
+
&pinctrl {
emmc {
emmc_reset: emmc-reset {
@@ -371,6 +416,20 @@
rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ pcie30x4 {
+ pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie30x4_perstn_m0: pcie30x4-perstn-m0 {
+ rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie30x4_waken_m0: pcie30x4-waken-m0 {
+ rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>;
+ };
+ };
};
&saradc {
Re: [PATCH 4/4] phy: rockchip: snps-pcie3: Fix clearing PHP_GRF_PCIESEL_CON bits
On 2024/7/15 05:23, Sebastian Kropatsch wrote:
The pcie1ln_sel bits for the RK3588 are getting set but not cleared due
to an incorrect write mask.
Use a newly introduced constant for the write mask to fix this.
Also introduce a GENMASK-based constant for PCIE30_PHY_MODE.
This fix is adapted from the upstream Linux commit by Sebastian Reichel:
55491a5fa163 ("phy: rockchip-snps-pcie3: fix clearing PHP_GRF_PCIESEL_CON bits")
Fixes: 50e54e80679b ("phy: rockchip: snps-pcie3: Add support for RK3588")
Signed-off-by: Sebastian Kropatsch
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
index fadb77c25c..62b42d1805 100644
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -36,6 +36,8 @@
#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
#define RK3588_LANE_AGGREGATION BIT(2)
+#define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16)
+#define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16)
/**
* struct rockchip_p3phy_priv - RK DW PCIe PHY state
@@ -127,13 +129,13 @@ static int rockchip_p3phy_rk3588_init(struct phy *phy)
reg = mode;
regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
-(0x7 << 16) | reg);
+RK3588_PCIE30_PHY_MODE_EN | reg);
/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
- reg = mode & 3;
+ reg = mode & (RK3588_BIFURCATION_LANE_0_1 |
RK3588_BIFURCATION_LANE_2_3);
if (reg)
regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
-(reg << 16) | reg);
+RK3588_PCIE1LN_SEL_EN | reg);
reset_deassert(&priv->p30phy);
udelay(1);
Re: [PATCH 3/4] phy: rockchip: snps-pcie3: Fix bifurcation for RK3588
On 2024/7/15 05:23, Sebastian Kropatsch wrote:
Misconfigured `PHP_GRF_PCIESEL` values are causing bifurcation issues,
for example on the FriendlyElec CM3588 NAS board which uses bifurcation
on both PCIe PCIe ports (all four lanes) to enable four M.2 NVMe
sockets. Without this fix, NVMe devices do not get recognized.
Correct the `PHP_GRF_PCIESEL` register configuration and simplify the
bifurcation logic, enabling proper PCIe bifurcation based on the
data-lanes property.
This fix is adapted from the upstream Linux commit by Michal Tomek:
f8020dfb311d ("phy: rockchip-snps-pcie3: fix bifurcation on rk3588")
Fixes: 50e54e80679b ("phy: rockchip: snps-pcie3: Add support for RK3588")
Signed-off-by: Sebastian Kropatsch
Reviewed-by: Kever Yang
Thanks,
- Kever
---
.../phy/rockchip/phy-rockchip-snps-pcie3.c| 24 +++
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
index 1c94875aaa..fadb77c25c 100644
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -108,7 +108,7 @@ static int rockchip_p3phy_rk3588_init(struct phy *phy)
{
struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
u32 reg = 0;
- u8 mode = 0;
+ u8 mode = RK3588_LANE_AGGREGATION; /* Lane aggregation by default */
int ret;
/* Deassert PCIe PMA output clamp mode */
@@ -117,28 +117,20 @@ static int rockchip_p3phy_rk3588_init(struct phy *phy)
/* Set bifurcation if needed */
for (int i = 0; i < priv->num_lanes; i++) {
- if (!priv->lanes[i])
- mode |= (BIT(i) << 3);
-
if (priv->lanes[i] > 1)
- mode |= (BIT(i) >> 1);
- }
-
- if (!mode) {
- reg = RK3588_LANE_AGGREGATION;
- } else {
- if (mode & (BIT(0) | BIT(1)))
- reg |= RK3588_BIFURCATION_LANE_0_1;
-
- if (mode & (BIT(2) | BIT(3)))
- reg |= RK3588_BIFURCATION_LANE_2_3;
+ mode &= ~RK3588_LANE_AGGREGATION;
+ if (priv->lanes[i] == 3)
+ mode |= RK3588_BIFURCATION_LANE_0_1;
+ if (priv->lanes[i] == 4)
+ mode |= RK3588_BIFURCATION_LANE_2_3;
}
+ reg = mode;
regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
(0x7 << 16) | reg);
/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
- reg = (mode & (BIT(6) | BIT(7))) >> 6;
+ reg = mode & 3;
if (reg)
regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
(reg << 16) | reg);
Re: [PATCH 2/4] phy: rockchip: snps-pcie3: Fix "rockchip" spelling
On 2024/7/15 05:23, Sebastian Kropatsch wrote:
Several identifiers use "rochchip" instead of "rockchip".
Fix this by replacing every instance of "rochchip" with "rockchip".
Signed-off-by: Sebastian Kropatsch
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
index 2737bd81dd..1c94875aaa 100644
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -164,7 +164,7 @@ static const struct rockchip_p3phy_ops rk3588_ops = {
.phy_init = rockchip_p3phy_rk3588_init,
};
-static int rochchip_p3phy_init(struct phy *phy)
+static int rockchip_p3phy_init(struct phy *phy)
{
struct rockchip_p3phy_ops *ops =
(struct rockchip_p3phy_ops *)dev_get_driver_data(phy->dev);
@@ -185,7 +185,7 @@ static int rochchip_p3phy_init(struct phy *phy)
return ret;
}
-static int rochchip_p3phy_exit(struct phy *phy)
+static int rockchip_p3phy_exit(struct phy *phy)
{
struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
@@ -251,9 +251,9 @@ static int rockchip_p3phy_probe(struct udevice *dev)
return 0;
}
-static struct phy_ops rochchip_p3phy_ops = {
- .init = rochchip_p3phy_init,
- .exit = rochchip_p3phy_exit,
+static struct phy_ops rockchip_p3phy_ops = {
+ .init = rockchip_p3phy_init,
+ .exit = rockchip_p3phy_exit,
};
static const struct udevice_id rockchip_p3phy_of_match[] = {
@@ -272,7 +272,7 @@ U_BOOT_DRIVER(rockchip_pcie3phy) = {
.name = "rockchip_pcie3phy",
.id = UCLASS_PHY,
.of_match = rockchip_p3phy_of_match,
- .ops= &rochchip_p3phy_ops,
+ .ops= &rockchip_p3phy_ops,
.probe = rockchip_p3phy_probe,
.priv_auto = sizeof(struct rockchip_p3phy_priv),
};
Re: [PATCH 1/4] phy: rockchip: naneng-combphy: Fix "rockchip" spelling
On 2024/7/15 05:23, Sebastian Kropatsch wrote:
Replace "rochchip" by "rockchip" in two instances.
Signed-off-by: Sebastian Kropatsch
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 3ad339bccc..1b85cbcce8 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -225,7 +225,7 @@ static int rockchip_combphy_xlate(struct phy *phy, struct
ofnode_phandle_args *a
return 0;
}
-static const struct phy_ops rochchip_combphy_ops = {
+static const struct phy_ops rockchip_combphy_ops = {
.init = rockchip_combphy_init,
.exit = rockchip_combphy_exit,
.of_xlate = rockchip_combphy_xlate,
@@ -535,7 +535,7 @@ U_BOOT_DRIVER(rockchip_naneng_combphy) = {
.name = "naneng-combphy",
.id = UCLASS_PHY,
.of_match = rockchip_combphy_ids,
- .ops= &rochchip_combphy_ops,
+ .ops= &rockchip_combphy_ops,
.probe = rockchip_combphy_probe,
.priv_auto = sizeof(struct rockchip_combphy_priv),
};
Re: [PATCH v3 16/18] rockchip: Avoid #ifdefs in RK3399 SPL
Hi Simon,
On 2024/6/21 22:57, Simon Glass wrote:
Hi Jonas,
On Fri, 21 Jun 2024 at 00:45, Jonas Karlman wrote:
Hi Simon,
On 2024-06-21 01:06, Simon Glass wrote:
The code here is confusing due to large blocks which are #ifdefed out.
Add a function phase_sdram_init() which returns whether SDRAM init
should happen in the current phase, using that as needed to control the
code flow.
This increases code size by about 500 bytes in SPL when the cache is on,
since it must call the rather large rockchip_sdram_size() function.
Signed-off-by: Simon Glass
---
Changes in v3:
- Split out the refactoring into a separate patch
- Drop the non-dcache optimisation, since the cache should normally be on
drivers/ram/rockchip/sdram_rk3399.c | 47 -
1 file changed, 26 insertions(+), 21 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index 3c4e20f4e80..2f37dd712e7 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -63,8 +64,6 @@ struct chan_info {
};
struct dram_info {
-#if defined(CONFIG_TPL_BUILD) || \
- (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
u32 pwrup_srefresh_exit[2];
struct chan_info chan[2];
struct clk ddr_clk;
@@ -75,7 +74,6 @@ struct dram_info {
struct rk3399_pmusgrf_regs *pmusgrf;
struct rk3399_ddr_cic_regs *cic;
const struct sdram_rk3399_ops *ops;
-#endif
struct ram_info info;
struct rk3399_pmugrf_regs *pmugrf;
};
@@ -92,9 +90,6 @@ struct sdram_rk3399_ops {
struct rk3399_sdram_params *params);
};
-#if defined(CONFIG_TPL_BUILD) || \
- (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
-
struct rockchip_dmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_rockchip_rk3399_dmc dtplat;
@@ -191,6 +186,17 @@ struct io_setting {
},
};
+/**
+ * phase_sdram_init() - Check if this is the phase where SDRAM init happens
+ *
+ * Returns: true to do SDRAM init in this phase, false to not
+ */
+static bool phase_sdram_init(void)
+{
+ return spl_phase() == PHASE_TPL ||
+ (!IS_ENABLED(CONFIG_TPL) && !spl_in_proper());
+}
+
static struct io_setting *
lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
{
@@ -3024,7 +3030,7 @@ static int rk3399_dmc_of_to_plat(struct udevice *dev)
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
- if (!CONFIG_IS_ENABLED(OF_REAL))
+ if (!CONFIG_IS_ENABLED(OF_REAL) || !phase_sdram_init())
return 0;
ret = dev_read_u32_array(dev, "rockchip,sdram-params",
@@ -3138,22 +3144,24 @@ static int rk3399_dmc_init(struct udevice *dev)
return 0;
}
-#endif
static int rk3399_dmc_probe(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
-#if defined(CONFIG_TPL_BUILD) || \
- (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
- if (rk3399_dmc_init(dev))
- return 0;
-#endif
- priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
- debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
- priv->info.base = CFG_SYS_SDRAM_BASE;
- priv->info.size =
- rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
+ if (phase_sdram_init()) {
+ if (rk3399_dmc_init(dev))
+ return 0;
+ } else {
+ priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+ debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
+ }
+
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
This check should be dropped, this driver intent is to initialize dram
in first phase (normally TPL), and report the size to any other phase.
This whole patch can be dropped :-) Here I am just trying to avoid
code-size growth when the cache is off. But yes, it is not needed.
The main need for phase_sdram_init() and disable of DCACHE can probably
be avoided if bob/kevin can move to use separate TPL and SPL instead of
doing both dram init and everything else in SPL.
My best guess is that enabling of caches in SPL cause issue for bob and
kevin because they only use SPL not TPL+SPL like (if I am not mistaken)
all other Rockchip arm64 targets.
Using SPL-only was not something I tested when caches was enabled in SPL.
Maybe bob/kevin can be changed to also use TPL+SPL similar to all other
RK3399 boards?
How U-Boot works on these chromebooks is still a mystery to me.
When coreboot is involved it would only load U-Boot proper and SPL or
TPL+SPL would never be involved at all?
If I understand correctly SPL is only involved for bare metal boot, if
this is the case then using TPL + back-to-brom to load SPL should
probably work fine?, and would align all RK3399 boards to work in a
similar way and reduce the need for special care/handling in the co
Pull request: u-boot-rockchip-next-20240615
Hi Tom, Please pull the updates for next on rockchip platform: - New board: Theobroma Systems SOM-RK3588-Q7 Tiger, ArmSoM Sige7 Rk3588; - PX30 dts migrate to OF_UPSTREAM; - Some other update on board or config; CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/21113 Thanks, - Kever The following changes since commit 3db3a6ba7b0cb09757fc631ccc9d4445eb101dc7: Merge patch series "Enable OSPI boot for j721s2" (2024-06-13 08:20:30 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-next-20240615 for you to fetch changes up to ae4aaa44977cbe522e9f38f2ac2ac07a784bf867: rockchip: puma-rk3399: get closer to other Theobroma defconfigs (2024-06-14 17:35:45 +0800) Boris Brezillon (1): arm64: dts: rockchip: Add rk3588 GPU node Diederik de Haas (1): arm64: dts: rockchip: Fix ordering of nodes on rk3588s Heiko Stuebner (6): arm64: dts: rockchip: enable gpu on rk3588-tiger arm64: dts: rockchip: move uart2 pinmux to dtsi on rk3588-tiger arm64: dts: rockchip: fix pcie-refclk frequency on rk3588 tiger arm64: dts: rockchip: fix comment for upper usb3 port arm64: dts: rockchip: add usb-id extcon on rk3588 tiger arm64: dts: rockchip: add dual-role usb3 hosts to rk3588 Tiger-Haikou Jianfeng Liu (3): arm64: dts: rockchip: Add ArmSom Sige7 board rockchip: rk3588: Remove USB3 DRD nodes in u-boot.dtsi board: rockchip: add ArmSoM Sige7 Rk3588 board Jing Luo (1): arm64: dts: rockchip: correct gpio_pwrctrl1 typos on rk3588(s) boards Niklas Cassel (1): arm64: dts: rockchip: add rk3588 pcie and php IOMMUs Quentin Schulz (17): rockchip: evb-px30: Use common bss and stack addresses rockchip: firefly-px30: Use common bss and stack addresses rockchip: odroid-go2: Use common bss and stack addresses rockchip: px30-core-*: Use common bss and stack addresses rockchip: px30: make UART pinmux accessible to TPL/SPL DTB rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB rockchip: evb-px30: make UART5 the debug UART rockchip: px30/rk3326: migrate to OF_UPSTREAM rockchip: jaguar-rk3588: use default env size for Rockchip on MMC rockchip: rk3399-puma: remove default value from defconfig rockchip: rk3399-puma: remove unnecessary simple-bin:fit:offset override rockchip: px30-ringneck: Update SPL_PAD_TO Kconfig option power: rk8xx: properly print all supported PMICs name rockchip: ringneck-px30: fix TPL_MAX_SIZE rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module rockchip: ringneck-px30: get closer to other Theobroma defconfigs rockchip: puma-rk3399: get closer to other Theobroma defconfigs Sebastian Reichel (4): arm64: dts: rockchip: fix usb2phy nodename for rk3588 arm64: dts: rockchip: reorder usb2phy properties for rk3588 arm64: dts: rockchip: add USBDP phys on rk3588 arm64: dts: rockchip: add USB3 DRD controllers on rk3588 MAINTAINERS| 1 + arch/arm/dts/Makefile | 8 - arch/arm/dts/px30-engicam-common.dtsi | 129 arch/arm/dts/px30-engicam-ctouch2.dtsi | 30 - arch/arm/dts/px30-engicam-edimm2.2.dtsi| 66 -- .../dts/px30-engicam-px30-core-ctouch2-of10.dts| 77 --- arch/arm/dts/px30-engicam-px30-core-ctouch2.dts| 22 - arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts | 43 -- arch/arm/dts/px30-engicam-px30-core.dtsi | 241 --- arch/arm/dts/px30-evb.dts | 634 -- arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi | 8 - arch/arm/dts/px30-ringneck-haikou.dts | 232 --- arch/arm/dts/px30-ringneck.dtsi| 382 --- arch/arm/dts/px30-u-boot.dtsi | 16 + arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 15 + arch/arm/dts/rk3326-odroid-go2.dts | 642 -- arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi| 6 - arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi | 6 + arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi | 37 ++ arch/arm/dts/rk3588-u-boot.dtsi| 74 --- arch/arm/dts/rk3588s-u-boot.dtsi | 85 --- arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/rk3588/Kconfig | 57 ++ board/armsom/sige7-rk3588/Kconfig | 12 + board/armsom/sige7-rk3588/MAINTAINERS | 7 + board/theobroma-systems/tiger_rk3588/Kconfig | 16 + board/theobroma-systems/tiger_rk3588/MAINTAINERS | 13 + board/theobroma-systems/tiger_rk3588/Makefile | 10 + .../theobroma-systems/tiger_rk3588/tiger_rk3588.c | 53 ++ configs/evb-px30_defconfig
Pull request: u-boot-rockchip-20240614
Hi Tom, Please pull the fixex for rockchip platform: - pmic fix for rk8xx; - pinctrl fix for rk3188/rv1126/rk3588; - mkimage fix for rockcihp "-l" option; CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/2 Thanks, - Kever The following changes since commit ca6a992e09441d6cca73439c63c3735f86b36ea4: cmd: sound: fix help text (2024-06-13 09:31:56 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-20240614 for you to fetch changes up to 3f9a19befe9277db2a337552912c6ddbcc0c8b10: rockchip: mkimage: fix mkimage -l for header v1 (2024-06-14 17:07:59 +0800) Chris Morgan (2): Revert "board: rockchip: Add early ADC button detect for RGxx3" board: rockchip: rgxx3: Use sdmmc0 as first device Jonas Karlman (3): pinctrl: rockchip: rk3188: Fix support for IOMUX_GPIO_ONLY flag pinctrl: rockchip: rv1126: Fix support for IOMUX_L_SOURCE_PMU flag pinctrl: rockchip: rk3588: Fix support for rockchip_get_mux() Quentin Schulz (4): regulator: rk8xx: fix incorrect device used for _ldo_[sg]et_suspend_value regulator: rk8xx: pass pmic udevice instead of regulator to all internal functions regulator: rk8xx: clarify operator precedence rockchip: mkimage: fix mkimage -l for header v1 arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 2 +- board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 64 drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 40 --- drivers/power/regulator/rk8xx.c | 54 ++-- tools/rkcommon.c | 2 +- 5 files changed, 63 insertions(+), 99 deletions(-)
Re: [PATCH 2/2] rockchip: puma-rk3399: get closer to other Theobroma defconfigs
On 2024/6/12 22:40, Quentin Schulz wrote: From: Quentin Schulz Disable support for unused OSes as Linux is the primary target. Disable support for bootz as zImage isn't a format compatible with Aarch64 machines so it should never be attempted to be booted. Enable a bunch of commands: - erofs - gpio - squashfs that could be useful and are also found in Jaguar and Tiger defconfigs. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/puma-rk3399_defconfig | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 34a0b575991..3196b5e24b1 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -29,7 +29,12 @@ CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y -CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_VBE is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -41,6 +46,8 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EROFS=y +CONFIG_CMD_SQUASHFS=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_OVERWRITE=y
Re: [PATCH 1/2] rockchip: ringneck-px30: get closer to other Theobroma defconfigs
On 2024/6/12 22:40, Quentin Schulz wrote: From: Quentin Schulz RK3588 Jaguar and Tiger, and RK3399 Puma use standard boot with the full feature set, so let's do that as well for PX30 Ringneck. Disable support for unused OSes as Linux is the primary target. Enable a bunch of commands: - boot/bootd - erofs - gpio - iminfo - imxtract - itest - pmic - regulator - sleep - squashfs that could be useful and are also found in Jaguar and Tiger defconfigs. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/ringneck-px30_defconfig | 16 +++- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index dedf35d4347..a0c1fec0951 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -20,6 +20,7 @@ CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTD_FULL=y CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -34,12 +35,15 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set # CONFIG_TPL_SYS_MALLOC_SIMPLE is not set -# CONFIG_CMD_BOOTD is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_VBE is not set +# CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set @@ -47,9 +51,11 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_SLEEP is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EROFS=y +CONFIG_CMD_SQUASHFS=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
Re: [PATCH next v2 8/8] rockchip: px30/rk3326: migrate to OF_UPSTREAM
On 2024/5/24 17:23, Quentin Schulz wrote:
From: Quentin Schulz
Migrate PX30/RK3326 boards that exists in Linux v6.8 to use OF_UPSTREAM.
firefly-px30 is not migrated to OF_UPSTREAM because there's no Device
Tree in the Linux kernel.
Differences between U-Boot's Odroid-Go2 and Linux's are now moved to the
-u-boot.dtsi, though I have a gut feeling that the existing cru
overrides aren't necessary (anymore?).
The U-Boot GPIO led-0 is on GPIO0_C1 but such is the pin of PWM3 which
is used for Linux's PWM led-2 so keep Linux's.
I also doubt vcc_cam is actually used, though the Odroid-Go2 Black
Edition uses this dcdc regulator for WiFi, so let's just move it to the
-u-boot.dtsi to play it safe.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/Makefile | 8 -
arch/arm/dts/px30-engicam-common.dtsi | 129 -
arch/arm/dts/px30-engicam-ctouch2.dtsi | 30 -
arch/arm/dts/px30-engicam-edimm2.2.dtsi| 66 ---
.../dts/px30-engicam-px30-core-ctouch2-of10.dts| 77 ---
arch/arm/dts/px30-engicam-px30-core-ctouch2.dts| 22 -
arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts | 43 --
arch/arm/dts/px30-engicam-px30-core.dtsi | 241
arch/arm/dts/px30-evb.dts | 634
arch/arm/dts/px30-ringneck-haikou.dts | 232
arch/arm/dts/px30-ringneck.dtsi| 382
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 15 +
arch/arm/dts/rk3326-odroid-go2.dts | 642 -
arch/arm/mach-rockchip/Kconfig | 1 +
configs/evb-px30_defconfig | 2 +-
configs/firefly-px30_defconfig | 1 +
configs/odroid-go2_defconfig | 2 +-
configs/px30-core-ctouch2-of10-px30_defconfig | 2 +-
configs/px30-core-ctouch2-px30_defconfig | 2 +-
configs/px30-core-edimm2.2-px30_defconfig | 2 +-
configs/ringneck-px30_defconfig| 2 +-
21 files changed, 23 insertions(+), 2512 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f7032f1e175..198bc41223d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -53,14 +53,6 @@ dtb-$(CONFIG_MACH_S900) += \
dtb-$(CONFIG_MACH_S700) += \
s700-cubieboard7.dtb
-dtb-$(CONFIG_ROCKCHIP_PX30) += \
- px30-evb.dtb \
- px30-firefly.dtb \
- px30-engicam-px30-core-ctouch2.dtb \
- px30-engicam-px30-core-ctouch2-of10.dtb \
- px30-engicam-px30-core-edimm2.2.dtb \
- rk3326-odroid-go2.dtb
-
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
rk3036-sdk.dtb
diff --git a/arch/arm/dts/px30-engicam-common.dtsi b/arch/arm/dts/px30-engicam-common.dtsi
deleted file mode 100644
index 3429e124d95..000
--- a/arch/arm/dts/px30-engicam-common.dtsi
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-/ {
- aliases {
- mmc1 = &sdmmc;
- mmc2 = &sdio;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";/* +5V */
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&xin32k>;
- clock-names = "ext_clock";
- post-power-on-delay-ms = <80>;
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- };
-
- vcc3v3_btreg: vcc3v3-btreg {
- compatible = "regulator-gpio";
- enable-active-high;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_enable_h>;
- regulator-name = "btreg-gpio-supply";
- regulator-min-microvolt = <330>;
- regulator-max-microvolt = <330>;
- regulator-always-on;
- states = <330 0x0>;
- };
-
- vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_rf_aux_mod";
- regulator-min-microvolt = <330>;
- regulator-max-microvolt = <330>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
Re: [PATCH] rockchip: mkimage: fix mkimage -l for header v1
On 2024/6/6 19:44, Quentin Schulz wrote: From: Quentin Schulz There are two paths to reach this function, either through mkimage -l or through dumpimage -l. The latter passes a NULL imagename while the former passes an empty string. Therefore, let's make both tools behave the same by handling the empty string the same way as for NULL. Without this, the only way to get some information out of mkimage -l is to provide "-n rk3399" for example, which isn't documented in the usage of the tool. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- tools/rkcommon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 12c27b34eaa..3e52236b15a 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -470,7 +470,7 @@ int rkcommon_verify_header(unsigned char *buf, int size, * If no 'imagename' is specified via the commandline (e.g. if this is * 'dumpimage -l' w/o any further constraints), we accept any spl_info. */ - if (params->imagename == NULL) + if (params->imagename == NULL || !strlen(params->imagename)) return 0; /* Match the 'imagename' against the 'spl_hdr' found */ --- base-commit: 4b992573b34b1586e323e27b177680a6efec1c76 change-id: 20240606-rkcommon-dumpimage-mkimage-58610cf07340 Best regards,
Re: [PATCH 3/9] pinctrl: rockchip: rk3588: Fix support for rockchip_get_mux()
Hi Jonas,
On 2024/6/7 18:27, Kever Yang wrote:
On 2024/5/12 20:16, Jonas Karlman wrote:
GPIO IOMUX control is located at PMU2_IOC or BUS_IOC offset on RK3588.
Based on Linux commit fdc33eba11c5 ("pinctrl/rockchip: add rk3588
support").
Compared to the Linux commit, this include a fix so that the iomux of
GPIO0_B4-D7 is reported correctly.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
I have apply the first 3 patches of this patch for master, and please
rebase other patches for next.
Thanks,
- Kever
Thanks,
- Kever
---
The fix to report correct iomux for GPIO0_B4-D7 will be sent to Linux.
---
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 24 ++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index 973e6a4f6db9..efc2070d32d9 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -14,10 +14,10 @@
#include
#include "pinctrl-rockchip.h"
+#include
#define MAX_ROCKCHIP_PINS_ENTRIES 30
#define MAX_ROCKCHIP_GPIO_PER_BANK 32
-#define RK_FUNC_GPIO 0
static int rockchip_verify_config(struct udevice *dev, u32 bank,
u32 pin)
{
@@ -147,6 +147,28 @@ static int rockchip_get_mux(struct
rockchip_pin_bank *bank, int pin)
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
+ if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588)) {
+ if (bank->bank_num == 0) {
+ if (pin >= RK_PB4 && pin <= RK_PD7) {
+ u32 reg0 = 0;
+
+ reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
+ ret = regmap_read(regmap, reg0, &val);
+ if (ret)
+ return ret;
+
+ ret = ((val >> bit) & mask);
+ if (ret != 8)
+ return ret;
+
+ reg = reg + 0x8000; /* BUS_IOC_BASE */
+ regmap = priv->regmap_base;
+ }
+ } else if (bank->bank_num > 0) {
+ reg += 0x8000; /* BUS_IOC_BASE */
+ }
+ }
+
ret = regmap_read(regmap, reg, &val);
if (ret)
return ret;
Re: [PATCH next v3 8/8] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module
On 2024/6/10 21:13, Quentin Schulz wrote:
From: Quentin Schulz
The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3588.
It provides the following feature set:
* up to 16GB LPDDR4x
* on-module eMMC
* SD card (on a baseboard) via edge connector
* Gigabit Ethernet with on-module GbE PHY
* HDMI/eDP
* MIPI-DSI
* 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
* HDMI input over FPC connector
* CAN
* USB
- 1x USB 3.0 dual-role (direct connection)
- 2x USB 3.0 host + 1x USB 2.0 host
* PCIe
- 1x PCIe 2.1 Gen3, 4 lanes
- 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
* on-module ATtiny816 companion controller, implementing:
- low-power RTC functionality (ISL1208 emulation)
- fan controller (AMC6821 emulation)
* on-module Secure Element with Global Platform 2.2.1 compliant
JavaCard environment
The support is added for Tiger on Haikou devkit, similarly to RK3399
Puma and PX30 Ringneck.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
Tested-by: Heiko Stuebner
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi | 37 +++
arch/arm/mach-rockchip/rk3588/Kconfig | 31 ++
board/theobroma-systems/tiger_rk3588/Kconfig | 16 +++
board/theobroma-systems/tiger_rk3588/MAINTAINERS | 13 +++
board/theobroma-systems/tiger_rk3588/Makefile | 10 ++
.../theobroma-systems/tiger_rk3588/tiger_rk3588.c | 53 ++
configs/tiger-rk3588_defconfig | 113 +
doc/board/rockchip/rockchip.rst| 1 +
doc/board/theobroma-systems/index.rst | 1 +
doc/board/theobroma-systems/tiger_rk3588.rst | 102 +++
include/configs/tiger_rk3588.h | 15 +++
11 files changed, 392 insertions(+)
diff --git a/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
new file mode 100644
index 000..275ae6fdaea
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+ };
+};
+
+&emmc_pwrseq {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_reset {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdhci {
+ /* U-Boot currently cannot handle anything below HS200 for eMMC on
RK3588 */
+ /delete-property/ mmc-ddr-1_8v;
+ /delete-property/ cap-mmc-highspeed;
+};
+
+&uart2m2_xfer {
+ bootph-all;
+};
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig
b/arch/arm/mach-rockchip/rk3588/Kconfig
index 9f82e9f3371..9a35c7d9cc2 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -193,6 +193,36 @@ config TARGET_QUARTZPRO64_RK3588
Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board
Computer) by Pine64.
+config TARGET_TIGER_RK3588
+ bool "Theobroma Systems SOM-RK3588-Q7 (Tiger)"
+ select BOARD_LATE_INIT
+ help
+ The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
+ connector) system-on-module from Theobroma Systems, featuring the
+ Rockchip RK3588.
+
+ It provides the following feature set:
+ * up to 16GB LPDDR4x
+ * on-module eMMC
+ * SD card (on a baseboard) via edge connector
+ * Gigabit Ethernet with on-module GbE PHY
+ * HDMI/eDP
+ * MIPI-DSI
+ * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
+ * HDMI input over FPC connector
+ * CAN
+ * USB
+- 1x USB 3.0 dual-role (direct connection)
+- 2x USB 3.0 host + 1x USB 2.0 host
+ * PCIe
+- 1x PCIe 2.1 Gen3, 4 lanes
+- 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
+ * on-module ATtiny816 companion controller, implementing:
+- low-power RTC functionality (ISL1208 emulation)
+- fan controller (AMC6821 emulation)
+ * on-module Secure Element with Global Platform 2.2.1 compliant
+JavaCard environment
+
config TARGET_TURINGRK1_RK3588
bool "Turing Machines RK1 RK3588 board"
select BOARD_LATE_INIT
@@ -266,5 +296,6 @@ source "board/radxa/rock5b-rk3588/Kconfig"
source "board/rockchip/evb_rk3588/Kconfig"
source "board/rockchip/toybrick_rk3588/Kconfig"
source "board/theobroma-systems/jaguar_rk3588/Kconfig"
+source "board/theobroma-systems/tiger_rk3588/Kconfig"
endif
diff --git a/b
Re: [PATCH next v3 3/8] arm64: dts: rockchip: correct gpio_pwrctrl1 typos on rk3588(s) boards
On 2024/6/10 21:13, Quentin Schulz wrote:
From: Jing Luo
gpio_pwrctrl2 gets duplicated by both rk806_dvs1_null and rk806_dvs2_null
gpio_pwrctrl1 is unset. This typo appears in multiple files. Let's fix them.
Note: I haven't had the chance to test them all because I don't own all
of these boards (obviously). Please test if it's needed.
Signed-off-by: Jing Luo
Link: https://lore.kernel.org/r/20240420130355.639406-1-jing@jing.rocks
Signed-off-by: Heiko Stuebner
Reviewed-by: Kever Yang
Thanks,
- Kever
[ upstream commit: d7f2039e5321636069baa77ef2f1e5d22cb69a88 ]
(cherry picked from commit cb2b6d1d19ed10fcaec5f5859c08a3355d1c66e0)
---
dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi | 2 +-
dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi | 2 +-
dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts| 2 +-
dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi| 2 +-
dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi | 2 +-
dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts| 2 +-
dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts | 2 +-
dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts | 2 +-
dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts | 2 +-
9 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi
b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi
index 94ecb9b4f98..170501a879d 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi
@@ -357,7 +357,7 @@
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi
index c0d4a15323e..d9bf67525e8 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi
@@ -182,7 +182,7 @@
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
index 39d65002add..7d7303f8ecb 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
@@ -452,7 +452,7 @@
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
index 4984e36a8c2..29f8e536de1 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
@@ -401,7 +401,7 @@
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
index dc08da518a7..6b9206ce4a0 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
@@ -318,7 +318,7 @@
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts
index e037bf9db75..7f4d7bb9a07 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts
@@ -479,7 +479,7 @@
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip
Re: [PATCH v2 2/2] board: rockchip: Add FriendlyElec NanoPi R6S
On 2024/6/8 04:17, Sebastian Kropatsch wrote:
The NanoPi R6S is a SBC by FriendlyElec based on the Rockchip RK3588s.
It comes with 4GB or 8GB of RAM, a microSD card slot, 32GB eMMC storage,
one RTL8211F 1GbE and two RTL8125 2.5GbE Ethernet ports, one USB 2.0
Type-A and one USB 3.0 Type-A port, a HDMI port, a 12-pin GPIO FPC
connector, a fan connector, IR receiver as well as some buttons and LEDs.
Add initial support for this board using the upstream devicetree sources.
Kernel commit:
f1b11f43b3e9 ("arm64: dts: rockchip: Add support for NanoPi R6S")
Signed-off-by: Sebastian Kropatsch
Reviewed-by: Kever Yang
Thanks,
- Kever
---
The R6S is very similar to the R6C, the major difference being that
instead of the M.2 NVMe socket on the R6C, the R6S has a second RTL8125BG
Ethernet chip, which uses the same PCIe lanes that the R6C uses for its
M.2 socket. Other minor differences include:
- 12-pin GPIO FPC instead of 30-pin header
- IR receiver (pwm-based)
- 5V fan connector
Other than that, they are the same, which is why the difference in
U-Boot is only the missing NVME config option in the R6S defconfig.
Please note that I was not able to test this device. I only chose to
add it due to it being a very similar implementation to the R6C, like the
NanoPi R5C and R5S are similar. It should however boot just fine and even
both RTL8125 Ethernet ports should work in U-Boot since RTL8125 is the
same chip used in the R6C, using the rtl8169 driver.
If this is not how things should be done in U-Boot, please disregard
and drop this patch :) Thanks!
---
arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi | 3 +
arch/arm/mach-rockchip/rk3588/Kconfig | 12 +++
board/friendlyelec/nanopi-r6s-rk3588s/Kconfig | 12 +++
.../nanopi-r6s-rk3588s/MAINTAINERS| 7 ++
configs/nanopi-r6s-rk3588s_defconfig | 82 +++
doc/board/rockchip/rockchip.rst | 1 +
include/configs/nanopi-r6s-rk3588s.h | 12 +++
7 files changed, 129 insertions(+)
create mode 100644 arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi
create mode 100644 board/friendlyelec/nanopi-r6s-rk3588s/Kconfig
create mode 100644 board/friendlyelec/nanopi-r6s-rk3588s/MAINTAINERS
create mode 100644 configs/nanopi-r6s-rk3588s_defconfig
create mode 100644 include/configs/nanopi-r6s-rk3588s.h
diff --git a/arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi
b/arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi
new file mode 100644
index 00..853ed58cfe
--- /dev/null
+++ b/arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig
b/arch/arm/mach-rockchip/rk3588/Kconfig
index 4b7d751c6f..a9e400861a 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -90,6 +90,18 @@ config TARGET_NANOPI_R6C_RK3588S
Type-A port, a HDMI port, a 30-pin GPIO header as well as some
buttons and LEDs.
+config TARGET_NANOPI_R6S_RK3588S
+ bool "FriendlyElec NanoPi R6S"
+ select BOARD_LATE_INIT
+ help
+ The NanoPi R6S is a SBC by FriendlyElec based on the Rockchip
+ RK3588s.
+ It comes with 4GB or 8GB of RAM, a microSD card slot, 32GB eMMC
+ storage, one RTL8211F 1GbE and two RTL8125 2.5GbE Ethernet ports,
+ one USB 2.0 Type-A and one USB 3.0 Type-A port, a HDMI port, a
+ 12-pin GPIO FPC connector, a fan connector, IR receiver as well
+ as some buttons and LEDs.
+
config TARGET_NOVA_RK3588
bool "Indiedroid Nova RK3588"
select BOARD_LATE_INIT
diff --git a/board/friendlyelec/nanopi-r6s-rk3588s/Kconfig
b/board/friendlyelec/nanopi-r6s-rk3588s/Kconfig
new file mode 100644
index 00..4d579816b1
--- /dev/null
+++ b/board/friendlyelec/nanopi-r6s-rk3588s/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NANOPI_R6S_RK3588S
+
+config SYS_BOARD
+ default "nanopi-r6s-rk3588s"
+
+config SYS_VENDOR
+ default "friendlyelec"
+
+config SYS_CONFIG_NAME
+ default "nanopi-r6s-rk3588s"
+
+endif
diff --git a/board/friendlyelec/nanopi-r6s-rk3588s/MAINTAINERS
b/board/friendlyelec/nanopi-r6s-rk3588s/MAINTAINERS
new file mode 100644
index 00..76288b4320
--- /dev/null
+++ b/board/friendlyelec/nanopi-r6s-rk3588s/MAINTAINERS
@@ -0,0 +1,7 @@
+NANOPI-R6S
+M: Sebastian Kropatsch
+S: Maintained
+F: arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi
+F: board/friendlyelec/nanopi-r6s-rk3588s
+F: configs/nanopi-r6s-rk3588s_defconfig
+F: include/configs/nanopi-r6s-rk3588s.h
diff --git a/configs/nanopi-r6s-rk3588s_defconfig
b/configs/nanopi-r6s-rk3588s_defconfig
new file mode 100644
index 00..f7b364655f
--- /dev/null
+++ b/configs/nanopi-r6s-rk3588s_defconfig
@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACH
Re: [PATCH v2 1/2] board: rockchip: Add FriendlyElec NanoPi R6C
On 2024/6/8 04:17, Sebastian Kropatsch wrote:
The NanoPi R6C is a SBC by FriendlyElec based on the Rockchip RK3588s.
It comes with 4GB or 8GB of RAM, a microSD card slot, optional 32GB eMMC
storage, one M.2 M-Key connector, one RTL8211F 1GbE and one RTL8125
2.5GbE Ethernet port, one USB 2.0 Type-A and one USB 3.0 Type-A port, a
HDMI port, a 30-pin GPIO header as well as multiple buttons and LEDs.
Add initial support for this board using the upstream devicetree sources.
Tests in U-Boot proper:
- Booting from eMMC works
- 1GbE Ethernet works using the eth_eqos driver (tested by ping)
- 2.5GbE Ethernet works using the eth_rtl8169 driver (tested by ping),
but the status LEDs on this specific port currently aren't working
- NVMe SSD in M.2 socket does get recognized (tested with `nvme scan`
followed by `nvme details`)
Kernel commit:
d5f1d7437451 ("arm64: dts: rockchip: Add support for NanoPi R6C")
Signed-off-by: Sebastian Kropatsch
Reviewed-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes v1 -> v2:
- Add missing 'S' to 'RK3588S' symbols
- Add similar board NanoPi R6S (new patch)
- Collect r-b tag from Quentin Schulz for patch 1
- Link to v1:
https://lore.kernel.org/u-boot/20240605155413.226629-1-seb-...@mail.de/
Hello!
The Ethernet status LEDs which sit directly on the 2.5GbE port using the
RTL8169 driver don't light up when connected and I couldn't figure out
why. The other port with a RTL8211F has no problems with the LEDs.
Have there been occurrences like this in combination with the RTL8125?
I'm trying to figure out if this is something that could be solved in
the devicetree or if this is a potential driver bug.
Secondly, the default active network device in U-Boot is the 1GbE one.
I believe it would make sense to make the 2.5GbE device the default
active one since this one is labeled "LAN", whereas the 1GbE is labeled
"WAN". However, since the 2.5GbE device is PCIe-based, it only shows up
in U-Boot proper after using the `pci enum` command (shows up as in gets
listed in `net list` and `dm tree`).
Do you have any tips on the preferred approach to handle this switch of
the default active net device? Is this even a sensible thing to include
in U-Boot in your opinion?
Thanks for your feedback!
Cheers,
Sebastian
---
arch/arm/dts/rk3588s-nanopi-r6c-u-boot.dtsi | 3 +
arch/arm/mach-rockchip/rk3588/Kconfig | 13 +++
board/friendlyelec/nanopi-r6c-rk3588s/Kconfig | 12 +++
.../nanopi-r6c-rk3588s/MAINTAINERS| 7 ++
configs/nanopi-r6c-rk3588s_defconfig | 83 +++
doc/board/rockchip/rockchip.rst | 1 +
include/configs/nanopi-r6c-rk3588s.h | 12 +++
7 files changed, 131 insertions(+)
create mode 100644 arch/arm/dts/rk3588s-nanopi-r6c-u-boot.dtsi
create mode 100644 board/friendlyelec/nanopi-r6c-rk3588s/Kconfig
create mode 100644 board/friendlyelec/nanopi-r6c-rk3588s/MAINTAINERS
create mode 100644 configs/nanopi-r6c-rk3588s_defconfig
create mode 100644 include/configs/nanopi-r6c-rk3588s.h
diff --git a/arch/arm/dts/rk3588s-nanopi-r6c-u-boot.dtsi
b/arch/arm/dts/rk3588s-nanopi-r6c-u-boot.dtsi
new file mode 100644
index 00..853ed58cfe
--- /dev/null
+++ b/arch/arm/dts/rk3588s-nanopi-r6c-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig
b/arch/arm/mach-rockchip/rk3588/Kconfig
index 820e979abb..4b7d751c6f 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -78,6 +78,18 @@ config TARGET_NANOPCT6_RK3588
Power: 5.5*2.1mm DC Jack, 12VDC input
Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case)
+config TARGET_NANOPI_R6C_RK3588S
+ bool "FriendlyElec NanoPi R6C"
+ select BOARD_LATE_INIT
+ help
+ The NanoPi R6C is a SBC by FriendlyElec based on the Rockchip
+ RK3588s.
+ It comes with 4GB or 8GB of RAM, a microSD card slot, optional 32GB
+ eMMC storage, one M.2 M-Key connector, one RTL8211F 1GbE and one
+ RTL8125 2.5GbE Ethernet port, one USB 2.0 Type-A and one USB 3.0
+ Type-A port, a HDMI port, a 30-pin GPIO header as well as some
+ buttons and LEDs.
+
config TARGET_NOVA_RK3588
bool "Indiedroid Nova RK3588"
select BOARD_LATE_INIT
@@ -232,6 +244,7 @@ config TEXT_BASE
source "board/edgeble/neural-compute-module-6/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
+source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig"
source "board/indiedroid/nova/Kconfig"
source "board/pine64/quartzpro64-rk3588/Kconfig"
source "board/turing/turing-rk1-rk3588/Kconfig"
diff --git a/board/friendlyelec/nanopi-r6c-rk3588s/Kconfig
b/board/
Re: [PATCH 0/9] rockchip: pinctrl: Minor fixes and add support for pinmux status cmd
Hi Jonas, Could you spit this patch in two part, one with fixes only, which I can merge it for master directly, and another part for new feature and together with "Add gpio request" for next? Thanks, - Kever On 2024/5/12 20:16, Jonas Karlman wrote: This series includes some minor fixes, cleanup and add support for using the pinmux status cmd. Following is an example on a Radxa ROCK 5A (RK3588S): => pinmux dev pinctrl dev: pinctrl => pinmux status GPIO0_A0 : gpio GPIO0_A1 : func-2 GPIO0_A2 : gpio GPIO0_A3 : gpio GPIO0_A4 : func-1 GPIO0_A5 : func-2 GPIO0_A6 : gpio GPIO0_A7 : gpio GPIO0_B0 : gpio GPIO0_B1 : gpio GPIO0_B2 : gpio GPIO0_B3 : gpio GPIO0_B4 : gpio GPIO0_B5 : func-10 GPIO0_B6 : func-10 GPIO0_B7 : gpio [...] and on a ASUS TinkerBoard R2.0 (RK3288W): => pinmux dev pinctrl dev: pinctrl => pinmux status [...] GPIO2_C6 : gpio GPIO2_C7 : gpio GPIO2_D0 : unrouted GPIO2_D1 : unrouted GPIO2_D2 : unrouted GPIO2_D3 : unrouted GPIO2_D4 : unrouted GPIO2_D5 : unrouted GPIO2_D6 : unrouted GPIO2_D7 : unrouted GPIO3_A0 : func-2 GPIO3_A1 : func-2 [...] Patch 1-3 are minor fixes so that correct pinmux status is reported. Patch 4 refactor to use syscon_regmap_lookup_by_phandle() helper. Patch 6 refactor to get pinctrl device from gpio-ranges prop. Patch 5 and 7 change to use pinctrl pin offset instead of bank num to get current pinmux. Patch 8 add required ops for use of the pinmux status cmd. Patch 9 add gpio-ranges props for remaining RK SoCs, this is strictly not needed for pinmux status cmd to function. However, the change to not require the pin controller offset to be 32 aligned was required to add gpio-ranges props for RK3288. This series depends on the "rockchip: Add gpio request() ops and drop PCIe reset-gpios workaround" [1] series. [1]https://patchwork.ozlabs.org/cover/1934100/ Jonas Karlman (9): pinctrl: rockchip: rk3188: Fix support for IOMUX_GPIO_ONLY flag pinctrl: rockchip: rv1126: Fix support for IOMUX_L_SOURCE_PMU flag pinctrl: rockchip: rk3588: Fix support for rockchip_get_mux() pinctrl: rockchip: Use syscon_regmap_lookup_by_phandle() pinctrl: rockchip: Update get_gpio_mux() ops gpio: rockchip: Get pinctrl device from gpio-ranges prop gpio: rockchip: Use pinctrl pin offset to get_gpio_mux() pinctrl: rockchip: Add pinmux status related ops rockchip: gpio: Add gpio-ranges props arch/arm/dts/rk3036-u-boot.dtsi | 12 ++ arch/arm/dts/rk3066a-u-boot.dtsi | 3 +- arch/arm/dts/rk3128-u-boot.dtsi | 16 ++ arch/arm/dts/rk322x-u-boot.dtsi | 16 ++ arch/arm/dts/rk3288-u-boot.dtsi | 33 arch/arm/dts/rk3308-u-boot.dtsi | 20 +++ arch/arm/dts/rk3328-u-boot.dtsi | 13 ++ arch/arm/dts/rk3368-u-boot.dtsi | 16 ++ arch/arm/dts/rk3399-u-boot.dtsi | 20 +++ arch/arm/dts/rv1108-u-boot.dtsi | 16 ++ arch/arm/dts/rv1126-u-boot.dtsi | 14 ++ drivers/gpio/rk_gpio.c| 44 +++-- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 151 ++ 13 files changed, 322 insertions(+), 52 deletions(-)
Re: [PATCH 4/9] pinctrl: rockchip: Use syscon_regmap_lookup_by_phandle()
On 2024/5/12 20:16, Jonas Karlman wrote:
Use syscon_regmap_lookup_by_phandle() to simplify the code.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 39 ++-
1 file changed, 12 insertions(+), 27 deletions(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index efc2070d32d9..b7c08c23311f 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include "pinctrl-rockchip.h"
@@ -672,37 +673,21 @@ int rockchip_pinctrl_probe(struct udevice *dev)
{
struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
struct rockchip_pin_ctrl *ctrl;
- struct udevice *syscon;
- struct regmap *regmap;
- int ret = 0;
- /* get rockchip grf syscon phandle */
- ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
- &syscon);
- if (ret) {
- debug("unable to find rockchip,grf syscon device (%d)\n", ret);
- return ret;
+ priv->regmap_base =
+ syscon_regmap_lookup_by_phandle(dev, "rockchip,grf");
+ if (IS_ERR(priv->regmap_base)) {
+ debug("unable to find rockchip,grf regmap\n");
+ return PTR_ERR(priv->regmap_base);
}
- /* get grf-reg base address */
- regmap = syscon_get_regmap(syscon);
- if (!regmap) {
- debug("unable to find rockchip grf regmap\n");
- return -ENODEV;
- }
- priv->regmap_base = regmap;
-
- /* option: get pmu-reg base address */
- ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
- &syscon);
- if (!ret) {
- /* get pmugrf-reg base address */
- regmap = syscon_get_regmap(syscon);
- if (!regmap) {
- debug("unable to find rockchip pmu regmap\n");
- return -ENODEV;
+ if (dev_read_bool(dev, "rockchip,pmu")) {
+ priv->regmap_pmu =
+ syscon_regmap_lookup_by_phandle(dev, "rockchip,pmu");
+ if (IS_ERR(priv->regmap_pmu)) {
+ debug("unable to find rockchip,pmu regmap\n");
+ return PTR_ERR(priv->regmap_pmu);
}
- priv->regmap_pmu = regmap;
}
ctrl = rockchip_pinctrl_get_soc_data(dev);
Re: [PATCH 3/9] pinctrl: rockchip: rk3588: Fix support for rockchip_get_mux()
On 2024/5/12 20:16, Jonas Karlman wrote:
GPIO IOMUX control is located at PMU2_IOC or BUS_IOC offset on RK3588.
Based on Linux commit fdc33eba11c5 ("pinctrl/rockchip: add rk3588
support").
Compared to the Linux commit, this include a fix so that the iomux of
GPIO0_B4-D7 is reported correctly.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
The fix to report correct iomux for GPIO0_B4-D7 will be sent to Linux.
---
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 24 ++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index 973e6a4f6db9..efc2070d32d9 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -14,10 +14,10 @@
#include
#include "pinctrl-rockchip.h"
+#include
#define MAX_ROCKCHIP_PINS_ENTRIES 30
#define MAX_ROCKCHIP_GPIO_PER_BANK 32
-#define RK_FUNC_GPIO0
static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
{
@@ -147,6 +147,28 @@ static int rockchip_get_mux(struct rockchip_pin_bank
*bank, int pin)
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
+ if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588)) {
+ if (bank->bank_num == 0) {
+ if (pin >= RK_PB4 && pin <= RK_PD7) {
+ u32 reg0 = 0;
+
+ reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
+ ret = regmap_read(regmap, reg0, &val);
+ if (ret)
+ return ret;
+
+ ret = ((val >> bit) & mask);
+ if (ret != 8)
+ return ret;
+
+ reg = reg + 0x8000; /* BUS_IOC_BASE */
+ regmap = priv->regmap_base;
+ }
+ } else if (bank->bank_num > 0) {
+ reg += 0x8000; /* BUS_IOC_BASE */
+ }
+ }
+
ret = regmap_read(regmap, reg, &val);
if (ret)
return ret;
Re: [PATCH 2/9] pinctrl: rockchip: rv1126: Fix support for IOMUX_L_SOURCE_PMU flag
On 2024/5/12 20:16, Jonas Karlman wrote:
GPIO0_C0-C4 iomux is set using PMUGRF_GPIO0C_IOMUX_L reg on RV1126. This
is indicated using the IOMUX_L_SOURCE_PMU flag. Fix reading current mux
by fully adopting the IOMUX_L_SOURCE_PMU related code in Linux kernel.
Based on Linux commit fd4ea48688c6 ("pinctrl: rockchip: Add RV1126
pinctrl support").
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index b6e2ab474d0f..973e6a4f6db9 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -132,8 +132,12 @@ static int rockchip_get_mux(struct rockchip_pin_bank
*bank, int pin)
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
return RK_FUNC_GPIO;
- regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
- ? priv->regmap_pmu : priv->regmap_base;
+ if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ regmap = priv->regmap_pmu;
+ else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
+ regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base;
+ else
+ regmap = priv->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
@@ -563,12 +567,14 @@ static struct rockchip_pin_ctrl
*rockchip_pinctrl_get_soc_data(struct udevice *d
/* preset iomux offset value, set new start value */
if (iom->offset >= 0) {
- if (iom->type & IOMUX_SOURCE_PMU)
+ if ((iom->type & IOMUX_SOURCE_PMU) ||
+ (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs = iom->offset;
else
grf_offs = iom->offset;
} else { /* set current iomux offset */
- iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
+ iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
+ (iom->type &
IOMUX_L_SOURCE_PMU)) ?
pmu_offs : grf_offs;
}
Re: [PATCH 1/9] pinctrl: rockchip: rk3188: Fix support for IOMUX_GPIO_ONLY flag
On 2024/5/12 20:16, Jonas Karlman wrote:
GPIO0_A0-A7 on RK3188 is IOMUX_GPIO_ONLY, however, trying to set gpio
mux return an -ENOTSUPP error code. Fix this by validating using the mux
function type and not the iomux flag.
Based on Linux commit c4a532dee6b6 ("pinctrl: rockchip: handle first
half of rk3188-bank0 correctly").
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Based on the old Linux commit and TRM it looks like GPIO0_B0-B7 should
also be flagged as IOMUX_GPIO_ONLY.
---
drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index a423abcafb23..b6e2ab474d0f 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -189,7 +189,7 @@ static int rockchip_verify_mux(struct rockchip_pin_bank
*bank,
}
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
- if (mux != IOMUX_GPIO_ONLY) {
+ if (mux != RK_FUNC_GPIO) {
debug("pin %d only supports a gpio mux\n", pin);
return -ENOTSUPP;
}
Re: [PATCH 3/4] rockchip: rk3568-rock-3a: Drop PCIe reset-gpios workaround
Hi Jonas,
On 2024/5/11 19:28, Jonas Karlman wrote:
The GPIO2_D6 pin is changed to use func-4 using pcie30x2m1_pins during
probe of pcie3x2. This cause the device to lock-up when pci driver use
the reset-gpios unless the pin is first changed to use gpio pinmux.
The reset-gpio for PCIe is for sure to use this IO as GPIO instead of
function IO.
And also CLKREQ and WAKEN should work in GPIO mode.
So keep the all PCIe IO to pinmux to function IO should not be correct.
Could you try with something like this:
&pcie3x2 {
/delete-property/ pinctrl-names
/delete-property/ pinctrl-0;
};
Thanks,
- Kever
Drop the board u-boot.dtsi workaround now that the gpio and pinctrl
drivers automatically use gpio pinmux when a gpio is requested.
Signed-off-by: Jonas Karlman
---
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 12
1 file changed, 12 deletions(-)
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 9d18f5d0b364..f4e2dc91ddfb 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -6,18 +6,6 @@
#include "rk356x-u-boot.dtsi"
-&pcie3x2 {
- pinctrl-0 = <&pcie3x2_reset_h>;
-};
-
-&pinctrl {
- pcie {
- pcie3x2_reset_h: pcie3x2-reset-h {
- rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
&sdhci {
cap-mmc-highspeed;
mmc-hs200-1_8v;
Re: [PATCH next v2 2/6] rockchip: rk3399-puma: remove default value from defconfig
On 2024/6/5 23:56, Quentin Schulz wrote: From: Quentin Schulz CONFIG_ENV_OFFSET already defaults to 0x3F8000, however it is stored in lowercase hexdigits instead of uppercase like in the defconfig. No change in behavior intended. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/puma-rk3399_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 34a0b575991..42819102d70 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -6,7 +6,6 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_ENV_SIZE=0x3000 -CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-puma-haikou" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y
Re: [PATCH next v2 3/6] rockchip: rk3399-puma: remove unnecessary simple-bin:fit:offset override
On 2024/6/5 23:56, Quentin Schulz wrote:
From: Quentin Schulz
Since commit 6007b69d544e ("rockchip: rk3399-puma: Update SPL_PAD_TO
Kconfig option"), SPL_PAD_TO matches
(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512 and the default
value for simple-bin:fit:offset in rockchip-u-boot.dtsi is
SPL_PAD_TO, so let's remove this override.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
index 5a9bd320ec4..55895d0dd19 100644
--- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
@@ -33,12 +33,6 @@
};
&binman {
- simple-bin {
- fit {
- offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64)
* 512)>;
- };
- };
-
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
simple-bin-spi {
fit {
Re: [PATCH next v2 4/6] rockchip: px30-ringneck: Update SPL_PAD_TO Kconfig option
On 2024/6/5 23:56, Quentin Schulz wrote:
From: Quentin Schulz
On px30-ringneck the FIT payload is located at sector 0x200 compared to
the more Rockchip common sector 0x4000 offset:
SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
Because FIT payload is located at sector 0x200 and the TPL+SPL is
located at sector 64, the combined size of TPL+SPL cannot take up more
than 224KiB:
(0x200 - 64) x 512 = 0x38000 (224 KiB)
Adjust SPL_PAD_TO to match the used 0x200 sector offset.
While at it, update the px30-ringneck-u-boot.dtsi to remove the now
unnecessary override of simple-bin:fit:offset since SPL_PAD_TO matches
with the current formula.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi | 8
configs/ringneck-px30_defconfig | 2 +-
2 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi
b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi
index e04766ad09c..29ea2763636 100644
--- a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi
+++ b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi
@@ -15,14 +15,6 @@
};
};
-&binman {
- simple-bin {
- fit {
- offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64)
* 512)>;
- };
- };
-};
-
&emmc_clk {
bootph-all;
};
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index dedf35d4347..a22d25e0089 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -25,7 +25,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2
-CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_PAD_TO=0x38000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Re: [PATCH next v2 5/6] power: rk8xx: properly print all supported PMICs name
On 2024/6/5 23:56, Quentin Schulz wrote:
From: Quentin Schulz
The ID of the PMIC is stored in the 2 16b registers but the only part
that matters right now is the 3 MSB, which make the 3 digits (in hex) of
the part number.
Right now, only RK808 was properly displayed, with this all currently
supported PMICs should display the proper part number.
Additionally, when the PMIC variant is not found, print that value
instead of the masked unshifted value as all PMICs we support for now
have their LSB ignored to represent the actual part number.
Tested on RK806 (RK3588 Jaguar), RK808 (RK3399 Puma) and RK809 (PX30
Ringneck).
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/power/pmic/rk8xx.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c
index 12ff26a0855..4d07e630579 100644
--- a/drivers/power/pmic/rk8xx.c
+++ b/drivers/power/pmic/rk8xx.c
@@ -277,10 +277,9 @@ static int rk8xx_probe(struct udevice *dev)
return ret;
priv->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK;
- show_variant = priv->variant;
+ show_variant = bitfield_extract_by_mask(priv->variant, RK8XX_ID_MSK);
switch (priv->variant) {
case RK808_ID:
- show_variant = 0x808; /* RK808 hardware ID is 0 */
break;
case RK805_ID:
case RK816_ID:
@@ -311,7 +310,7 @@ static int rk8xx_probe(struct udevice *dev)
init_data_num = ARRAY_SIZE(rk806_init_reg);
break;
default:
- printf("Unknown PMIC: RK%x!!\n", priv->variant);
+ printf("Unknown PMIC: RK%x!!\n", show_variant);
return -EINVAL;
}
Re: [PATCH next v2 6/6] rockchip: ringneck-px30: fix TPL_MAX_SIZE
On 2024/6/5 23:56, Quentin Schulz wrote:
From: Quentin Schulz
Ringneck was mistakenly set to allow up to 128KiB for the TPL code size
while PX30 SoC only has 16KiB of SRAM.
Therefore, let's use the default value of TPL_MAX_SIZE from the SoC
(which is 10KiB) so that the max code size is actually checked and
useful.
Fixes: c925be73a0a8 ("rockchip: add support for PX30 Ringneck SoM on Haikou
Devkit")
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
configs/ringneck-px30_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index a22d25e0089..9965e55d611 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -14,7 +14,6 @@ CONFIG_SPL_DRIVERS_MISC=y
CONFIG_DEBUG_UART_BASE=0xFF03
CONFIG_DEBUG_UART_CLOCK=2400
CONFIG_SYS_LOAD_ADDR=0x800800
-CONFIG_TPL_MAX_SIZE=0x2
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
Re: [PATCH next v2 1/6] rockchip: jaguar-rk3588: use default env size for Rockchip on MMC
On 2024/6/5 23:56, Quentin Schulz wrote: From: Quentin Schulz The default env size is 0x8000 when building for Rockchip SoCs with support for environment stored in MMC. Jaguar hasn't entered mass production just yet, so it's a breaking change we can afford in the name of consistency. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/jaguar-rk3588_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index b69cf4cd057..36bf34d97c8 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_SF_DEFAULT_SPEED=2400 CONFIG_SF_DEFAULT_MODE=0x2000 -CONFIG_ENV_SIZE=0x1f000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-jaguar" CONFIG_ROCKCHIP_RK3588=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
Re: [PATCH v4 10/10] board: rockchip: add ArmSoM Sige7 Rk3588 board
On 2024/5/29 01:04, Jianfeng Liu wrote: ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) by ArmSoM. There are two variants depending on the DRAM size : 8G and 16G. Specification: Rockchip Rk3588 SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 8/16GB memory LPDDR4x Mali G610MC4 GPU 2x MIPI CSI 2 multiple lanes connector 64GB/128GB on board eMMC uSD slot 1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C 1x HDMI 2.1 output 2x 2.5 Gbps Ethernet port 40-pin IO header including UART, SPI and I2C USB PD over USB Type-C Size: 92mm x 62mm Kernel commit: 81c828a67c78 (arm64: dts: rockchip: Add ArmSom Sige7 board) Signed-off-by: Jianfeng Liu Reviewed-by: Kever Yang Thanks, - Kever --- Changes in v4: - Pick all commits of rk3588s.dtsi and rk3588.dtsi from v6.10-rc1-dts - Remove obsolete USB3 DRD nodes in u-boot.dtsi of rk3588s/rk3588 - Remove sdhci and usb nodes from rk3588-armsom-sige7-u-boot.dtsi Changes in v3: - Use update-dts-subtree.sh to pick upstream dts Changes in v2: - Fix alphabetical order of MAINTAINERS - Use arch/arm/dts/rk3588-armsom-sige7* in board MAINTAINERS - Remove spi flash related config - Move kernel dts to dts/upstream/src/arm64/rockchip/ MAINTAINERS | 1 + arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi | 6 ++ arch/arm/mach-rockchip/rk3588/Kconfig| 26 ++ board/armsom/sige7-rk3588/Kconfig| 12 +++ board/armsom/sige7-rk3588/MAINTAINERS| 7 ++ configs/sige7-rk3588_defconfig | 93 doc/board/rockchip/rockchip.rst | 1 + include/configs/sige7-rk3588.h | 15 8 files changed, 161 insertions(+) create mode 100644 arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi create mode 100644 board/armsom/sige7-rk3588/Kconfig create mode 100644 board/armsom/sige7-rk3588/MAINTAINERS create mode 100644 configs/sige7-rk3588_defconfig create mode 100644 include/configs/sige7-rk3588.h diff --git a/MAINTAINERS b/MAINTAINERS index 6c861b529df..fffcf898bf1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -534,6 +534,7 @@ F: arch/arm/include/asm/arch-rockchip/ F:arch/arm/mach-rockchip/ F:board/amarula/vyasa-rk3288/ F:board/anbernic/rgxx3_rk3566/ +F: board/armsom/sige7-rk3588/ F:board/chipspark/popmetal_rk3288 F:board/engicam/px30_core/ F:board/firefly/ diff --git a/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi new file mode 100644 index 000..af96d2fa8fb --- /dev/null +++ b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 ArmSoM Technology Co., Ltd. + */ + +#include "rk3588-u-boot.dtsi" diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 39049ab35a9..4c14b0be1eb 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -152,6 +152,31 @@ config TARGET_ROCK5B_RK3588 USB PD over USB Type-C Size: 100mm x 72mm (Pico-ITX form factor) +config TARGET_SIGE7_RK3588 + bool "ArmSoM Sige7 RK3588 board" + select BOARD_LATE_INIT + help + ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) + by ArmSoM. + + There are two variants depending on the DRAM size : 8G and 16G. + + Specification: + + Rockchip Rk3588 SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 8/16GB memory LPDDR4x + Mali G610MC4 GPU + 2x MIPI CSI 2 multiple lanes connector + 64GB/128GB on board eMMC + uSD slot + 1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C + 1x HDMI 2.1 output + 2x 2.5 Gbps Ethernet port + 40-pin IO header including UART, SPI and I2C + USB PD over USB Type-C + Size: 92mm x 62mm + config TARGET_QUARTZPRO64_RK3588 bool "Pine64 QuartzPro64 RK3588 board" select BOARD_LATE_INIT @@ -221,6 +246,7 @@ config ROCKCHIP_COMMON_STACK_ADDR config TEXT_BASE default 0x00a0 +source "board/armsom/sige7-rk3588/Kconfig" source "board/edgeble/neural-compute-module-6/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" source "board/pine64/quartzpro64-rk3588/Kconfig" diff --git a/board/armsom/sige7-rk3588/Kconfig b/board/armsom/sige7-rk3588/Kconfig new file mode 100644 index 000..793985f531b --- /dev/null +++ b/board/armsom/sige7-rk3588/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SIGE7_RK3588 + +config SYS_BOARD + default "sige7-rk3588" + +config SYS_VENDOR + default "armsom" + +config SYS_CONFIG_NAME + default "sige7-rk3588" + +endif diff --git a/board/armsom/sige7-rk3588/MAINTAINERS b/board/armsom/sige7-rk3
Re: [PATCH v4 09/10] rockchip: rk3588: Remove USB3 DRD nodes in u-boot.dtsi
On 2024/5/29 01:04, Jianfeng Liu wrote:
After we sync USB3 DRD nodes from v6.10-rc1, these obsolete nodes
can be removed.
Signed-off-by: Jianfeng Liu
Reviewed-by: Kever Yang
Thanks,
- Kever
---
(no changes since v1)
arch/arm/dts/rk3588-u-boot.dtsi | 74 ---
arch/arm/dts/rk3588s-u-boot.dtsi | 85
2 files changed, 159 deletions(-)
diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
index 4623580c610..bfe6645c30e 100644
--- a/arch/arm/dts/rk3588-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-u-boot.dtsi
@@ -4,77 +4,3 @@
*/
#include "rk3588s-u-boot.dtsi"
-
-/ {
- usb_host1_xhci: usb@fc40 {
- compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
- reg = <0x0 0xfc40 0x0 0x40>;
- interrupts = ;
- clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
-<&cru ACLK_USB3OTG1>;
- clock-names = "ref_clk", "suspend_clk", "bus_clk";
- dr_mode = "otg";
- phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- power-domains = <&power RK3588_PD_USB>;
- resets = <&cru SRST_A_USB3OTG1>;
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- status = "disabled";
- };
-
- usbdpphy1_grf: syscon@fd5cc000 {
- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
- reg = <0x0 0xfd5cc000 0x0 0x4000>;
- };
-
- usb2phy1_grf: syscon@fd5d4000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
- reg = <0x0 0xfd5d4000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy1: usb2phy@4000 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0x4000 0x10>;
- #clock-cells = <0>;
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy1";
- interrupts = ;
- resets = <&cru SRST_OTGPHY_U3_1>, <&cru
SRST_P_USB2PHY_U3_1_GRF0>;
- reset-names = "phy", "apb";
- status = "disabled";
-
- u2phy1_otg: otg-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
- usbdp_phy1: phy@fed9 {
- compatible = "rockchip,rk3588-usbdp-phy";
- reg = <0x0 0xfed9 0x0 0x1>;
- #phy-cells = <1>;
- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
-<&cru CLK_USBDP_PHY1_IMMORTAL>,
-<&cru PCLK_USBDPPHY1>,
-<&u2phy1>;
- clock-names = "refclk", "immortal", "pclk", "utmi";
- resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
-<&cru SRST_USBDP_COMBO_PHY1_CMN>,
-<&cru SRST_USBDP_COMBO_PHY1_LANE>,
-<&cru SRST_USBDP_COMBO_PHY1_PCS>,
-<&cru SRST_P_USBDPPHY1>;
- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
- rockchip,u2phy-grf = <&usb2phy1_grf>;
- rockchip,usb-grf = <&usb_grf>;
- rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
- rockchip,vo-grf = <&vo0_grf>;
- status = "disabled";
- };
-};
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index e9d38d5c83b..09d8b311cec 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -19,95 +19,10 @@
bootph-all;
};
- usb_host0_xhci: usb@fc00 {
- compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
- reg = <0x0 0xfc00 0x0 0x40>;
- interrupts = ;
-
Re: [PATCH v4 08/10] arm64: dts: rockchip: Add ArmSom Sige7 board
On 2024/5/29 01:04, Jianfeng Liu wrote:
Specification:
Rockchip Rk3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
8/16/32GB Memory LPDDR4/LPDDR4x
Mali G610MP4 GPU
2× MIPI-CSI Connector
1× MIPI-DSI Connector
1x M.2 Key M (PCIe 3.0 4-lanes)
2x RTL8125 2.5G Ethernet
Onboard AP6275P for WIFI6/BT5
32GB/64GB/128GB eMMC
MicroSD card slot
1x USB2.0, 1x USB3.0 Type-A, 1x US3.0 Type-C
1x HDMI Output, 1x type-C DP Output
Functions work normally:
USB2.0 Host
USB3.0 Type-A Host
M.2 Key M (PCIe 3.0 4-lanes)
2x RTL8125 2.5G Ethernet
eMMC
MicroSD card
More information can be obtained from the following website
https://docs.armsom.org/armsom-sige7
Signed-off-by: Jianfeng Liu
Reviewed-by: Weizhao Ouyang
Link:
https://lore.kernel.org/r/20240420034300.176920-4-liujianfeng1...@gmail.com
Signed-off-by: Heiko Stuebner
[ upstream commit: 81c828a67c78bb03ea75819c417c93c7f3d637b5 ]
(cherry picked from commit d427a11542bcf5364a5260280e077f0a2e030dcb)
Reviewed-by: Kever Yang
Thanks,
- Kever
---
(no changes since v1)
.../arm64/rockchip/rk3588-armsom-sige7.dts| 721 ++
1 file changed, 721 insertions(+)
create mode 100644 dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
new file mode 100644
index 000..98c622b2764
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
@@ -0,0 +1,721 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include
+#include
+#include "rk3588.dtsi"
+
+/ {
+ model = "ArmSoM Sige7";
+ compatible = "armsom,sige7", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ analog-sound {
+ compatible = "audio-graph-card";
+ dais = <&i2s0_8ch_p0>;
+ label = "rk3588-es8316";
+ hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_rgb_g>;
+
+ led_green: led-0 {
+ color = ;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led_red: led-1 {
+ color = ;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "none";
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 95 145 195 255>;
+ fan-supply = <&vcc5v0_sys>;
+ pwms = <&pwm1 0 5 0>;
+ #cooling-cells = <2>;
+ };
+
+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie2x1l2";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc3v3_pcie30";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-
Re: [PATCH v4 07/10] arm64: dts: rockchip: add rk3588 pcie and php IOMMUs
On 2024/5/29 01:04, Jianfeng Liu wrote:
From: Niklas Cassel
The mmu600_pcie is connected with the five PCIe controllers.
The mmu600_php is connected with the USB3 controller, the GMAC
controllers, and the SATA controllers.
See 8.2 Block Diagram, in rk3588 TRM (Technical Reference Manual).
The IOMMUs are disabled by default, as further patches are needed to
program the SID/SSIDs in to the IOMMUs.
iommu: Default domain type: Translated
iommu: DMA domain TLB invalidation policy: strict mode
arm-smmu-v3 fc90.iommu: ias 48-bit, oas 48-bit (features 0x001c1eaf)
arm-smmu-v3 fc90.iommu: allocated 65536 entries for cmdq
arm-smmu-v3 fc90.iommu: allocated 32768 entries for evtq
arm-smmu-v3 fc90.iommu: msi_domain absent - falling back to wired irqs
Additionally, the IOMMU correctly triggers an IOMMU fault when
a PCIe device performs a write (since the device hasn't been
assigned a SID/SSID):
arm-smmu-v3 fc90.iommu: event 0x02 received:
arm-smmu-v3 fc90.iommu: 0x0102
arm-smmu-v3 fc90.iommu: 0x
arm-smmu-v3 fc90.iommu: 0x
arm-smmu-v3 fc90.iommu: 0x
While this doesn't provide much value as is, having the devices as
disabled in the device tree will allow developers to see that the rk3588
actually has IOMMUs on the SoC.
Signed-off-by: Niklas Cassel
Link: https://lore.kernel.org/r/20240502140231.477049-2-cas...@kernel.org
Signed-off-by: Heiko Stuebner
[ upstream commit: cd81d3a0695cc54ad6ac0ef4bbb67a7c8f55d592 ]
(cherry picked from commit ea9a34aa0d786cbf4b87f1ba528e69b07219738f)
Signed-off-by: Jianfeng Liu
Reviewed-by: Kever Yang
Thanks,
- Kever
---
(no changes since v1)
dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index b0a59ec5183..6ac5ac8b48a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -579,6 +579,30 @@
status = "disabled";
};
+ mmu600_pcie: iommu@fc90 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0xfc90 0x0 0x20>;
+ interrupts = ,
+,
+,
+;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ mmu600_php: iommu@fcb0 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0xfcb0 0x0 0x20>;
+ interrupts = ,
+,
+,
+;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
pmu1grf: syscon@fd58a000 {
compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xfd58a000 0x0 0x1>;
Re: [PATCH v4 06/10] arm64: dts: rockchip: add USB3 DRD controllers on rk3588
On 2024/5/29 01:04, Jianfeng Liu wrote:
From: Sebastian Reichel
Add both USB3 dual-role controllers to the RK3588 devicetree.
Signed-off-by: Sebastian Reichel
Link:
https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reic...@collabora.com
Signed-off-by: Heiko Stuebner
[ upstream commit: 33f393a2a990e16f56931ca708295f31d2b44415 ]
(cherry picked from commit c7ed588e14f7dd04a92fb55f12680f94c7b14edf)
Signed-off-by: Jianfeng Liu
Reviewed-by: Kever Yang
Thanks,
- Kever
---
(no changes since v1)
dts/upstream/src/arm64/rockchip/rk3588.dtsi | 20 ++
dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 22
2 files changed, 42 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi
b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
index 4fdd047c9eb..5984016b5f9 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
@@ -7,6 +7,26 @@
#include "rk3588-pinctrl.dtsi"
/ {
+ usb_host1_xhci: usb@fc40 {
+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+ reg = <0x0 0xfc40 0x0 0x40>;
+ interrupts = ;
+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
+<&cru ACLK_USB3OTG1>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ dr_mode = "otg";
+ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG1>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ status = "disabled";
+ };
+
pcie30_phy_grf: syscon@fd5b8000 {
compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
reg = <0x0 0xfd5b8000 0x0 0x1>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 9063c0bb0f0..b0a59ec5183 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -492,6 +492,28 @@
};
};
+ usb_host0_xhci: usb@fc00 {
+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+ reg = <0x0 0xfc00 0x0 0x40>;
+ interrupts = ;
+ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
+<&cru ACLK_USB3OTG0>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ dr_mode = "otg";
+ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG0>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ status = "disabled";
+ };
+
usb_host0_ehci: usb@fc80 {
compatible = "rockchip,rk3588-ehci", "generic-ehci";
reg = <0x0 0xfc80 0x0 0x4>;
Re: [PATCH v4 05/10] arm64: dts: rockchip: add USBDP phys on rk3588
On 2024/5/29 01:04, Jianfeng Liu wrote:
From: Sebastian Reichel
Add both USB3-DisplayPort PHYs to RK3588 SoC DT.
Signed-off-by: Sebastian Reichel
Link:
https://lore.kernel.org/r/20240408225109.128953-7-sebastian.reic...@collabora.com
Signed-off-by: Heiko Stuebner
[ upstream commit: e18e5e8188f2671abf63abe7db5f21555705130f ]
(cherry picked from commit 5110caca9865718616cf7093ed4a9a1bc54780db)
Signed-off-by: Jianfeng Liu
Reviewed-by: Kever Yang
Thanks,
- Kever
---
(no changes since v1)
dts/upstream/src/arm64/rockchip/rk3588.dtsi | 52
dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 63
2 files changed, 115 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi
b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
index 5519c1430cb..4fdd047c9eb 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
@@ -17,6 +17,36 @@
reg = <0x0 0xfd5c 0x0 0x100>;
};
+ usbdpphy1_grf: syscon@fd5cc000 {
+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+ reg = <0x0 0xfd5cc000 0x0 0x4000>;
+ };
+
+ usb2phy1_grf: syscon@fd5d4000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
+ reg = <0x0 0xfd5d4000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy1: usb2phy@4000 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x4000 0x10>;
+ #clock-cells = <0>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy1";
+ interrupts = ;
+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru
SRST_P_USB2PHY_U3_1_GRF0>;
+ reset-names = "phy", "apb";
+ status = "disabled";
+
+ u2phy1_otg: otg-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -310,6 +340,28 @@
};
};
+ usbdp_phy1: phy@fed9 {
+ compatible = "rockchip,rk3588-usbdp-phy";
+ reg = <0x0 0xfed9 0x0 0x1>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+<&cru CLK_USBDP_PHY1_IMMORTAL>,
+<&cru PCLK_USBDPPHY1>,
+<&u2phy1>;
+ clock-names = "refclk", "immortal", "pclk", "utmi";
+ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
+<&cru SRST_USBDP_COMBO_PHY1_CMN>,
+<&cru SRST_USBDP_COMBO_PHY1_LANE>,
+<&cru SRST_USBDP_COMBO_PHY1_PCS>,
+<&cru SRST_P_USBDPPHY1>;
+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ rockchip,u2phy-grf = <&usb2phy1_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ status = "disabled";
+ };
+
combphy1_ps: phy@fee1 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee1 0x0 0x100>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 58d12969b7e..9063c0bb0f0 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -572,12 +572,23 @@
reg = <0x0 0xfd5a4000 0x0 0x2000>;
};
+ vo0_grf: syscon@fd5a6000 {
+ compatible = "rockchip,rk3588-vo-grf", "syscon";
+ reg = <0x0 0xfd5a6000 0x0 0x2000>;
+ clocks = <&cru PCLK_VO0GRF>;
+ };
+
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru PCLK_VO1GRF>;
};
+ usb_grf: syscon@fd5ac000 {
+
Re: [PATCH v4 04/10] arm64: dts: rockchip: reorder usb2phy properties for rk3588
On 2024/5/29 01:04, Jianfeng Liu wrote:
From: Sebastian Reichel
Reorder common DT properties alphabetically for usb2phy, according
to latest DT style rules.
Signed-off-by: Sebastian Reichel
Link:
https://lore.kernel.org/r/20240408225109.128953-6-sebastian.reic...@collabora.com
Signed-off-by: Heiko Stuebner
[ upstream commit: abe68e0ca71dddce0e5419e35507cb464d61870d ]
(cherry picked from commit f6835a60a8a28ff14ffb3dd80c99ce1c137d06c5)
Signed-off-by: Jianfeng Liu
Reviewed-by: Kever Yang
Thanks,
- Kever
---
(no changes since v1)
dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 87df0902273..58d12969b7e 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -602,13 +602,13 @@
u2phy2: usb2phy@8000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x8000 0x10>;
- interrupts = ;
- resets = <&cru SRST_OTGPHY_U2_0>, <&cru
SRST_P_USB2PHY_U2_0_GRF0>;
- reset-names = "phy", "apb";
+ #clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy2";
- #clock-cells = <0>;
+ interrupts = ;
+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru
SRST_P_USB2PHY_U2_0_GRF0>;
+ reset-names = "phy", "apb";
status = "disabled";
u2phy2_host: host-port {
@@ -627,13 +627,13 @@
u2phy3: usb2phy@c000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0xc000 0x10>;
- interrupts = ;
- resets = <&cru SRST_OTGPHY_U2_1>, <&cru
SRST_P_USB2PHY_U2_1_GRF0>;
- reset-names = "phy", "apb";
+ #clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy3";
- #clock-cells = <0>;
+ interrupts = ;
+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru
SRST_P_USB2PHY_U2_1_GRF0>;
+ reset-names = "phy", "apb";
status = "disabled";
u2phy3_host: host-port {
Re: [PATCH v4 03/10] arm64: dts: rockchip: fix usb2phy nodename for rk3588
On 2024/5/29 01:03, Jianfeng Liu wrote:
From: Sebastian Reichel
usb2-phy should be named usb2phy according to the DT binding,
so let's fix it up accordingly.
Signed-off-by: Sebastian Reichel
Link:
https://lore.kernel.org/r/20240408225109.128953-5-sebastian.reic...@collabora.com
Signed-off-by: Heiko Stuebner
[ upstream commit: 4e07a95f7402de092cd71b2cb96c69f85c98f251 ]
(cherry picked from commit 5a3e4638492497ae81b9bd4a8627f4727e312ccc)
Signed-off-by: Jianfeng Liu
Reviewed-by: Kever Yang
Thanks,
- Kever
---
(no changes since v1)
dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index ac5bd630f15..87df0902273 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -599,7 +599,7 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy2: usb2-phy@8000 {
+ u2phy2: usb2phy@8000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x8000 0x10>;
interrupts = ;
@@ -624,7 +624,7 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy3: usb2-phy@c000 {
+ u2phy3: usb2phy@c000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0xc000 0x10>;
interrupts = ;
Re: [PATCH v4 01/10] arm64: dts: rockchip: Add rk3588 GPU node
On 2024/5/29 01:03, Jianfeng Liu wrote:
From: Boris Brezillon
Add Mali GPU Node to the RK3588 SoC DT including GPU clock
operating points
Signed-off-by: Boris Brezillon
Signed-off-by: Sebastian Reichel
Link:
https://lore.kernel.org/r/20240326165232.73585-3-sebastian.reic...@collabora.com
Signed-off-by: Heiko Stuebner
[ upstream commit: 6fca4edb93d335f29f81e484936f38a5eed6a9b1 ]
(cherry picked from commit 3cd15354ea0c8668812bc0b3a4136606c10803e9)
Signed-off-by: Jianfeng Liu
Reviewed-by: Kever Yang
Thanks,
- Kever
---
(no changes since v1)
dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 56
1 file changed, 56 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 87b83c87bd5..89d40cff635 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -501,6 +501,62 @@
status = "disabled";
};
+ gpu: gpu@fb00 {
+ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
+ reg = <0x0 0xfb00 0x0 0x20>;
+ #cooling-cells = <2>;
+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
+ assigned-clock-rates = <2>;
+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
+<&cru CLK_GPU_STACKS>;
+ clock-names = "core", "coregroup", "stacks";
+ dynamic-power-coefficient = <2982>;
+ interrupts = ,
+,
+;
+ interrupt-names = "job", "mmu", "gpu";
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&power RK3588_PD_GPU>;
+ status = "disabled";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-3 {
+ opp-hz = /bits/ 64 <3>;
+ opp-microvolt = <675000 675000 85>;
+ };
+ opp-4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <675000 675000 85>;
+ };
+ opp-5 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <675000 675000 85>;
+ };
+ opp-6 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <675000 675000 85>;
+ };
+ opp-7 {
+ opp-hz = /bits/ 64 <7>;
+ opp-microvolt = <70 70 85>;
+ };
+ opp-8 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = <75 75 85>;
+ };
+ opp-9 {
+ opp-hz = /bits/ 64 <9>;
+ opp-microvolt = <80 80 85>;
+ };
+ opp-10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = <85 85 85>;
+ };
+ };
+ };
+
pmu1grf: syscon@fd58a000 {
compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xfd58a000 0x0 0x1>;
Re: [PATCH v4 02/10] arm64: dts: rockchip: Fix ordering of nodes on rk3588s
On 2024/5/29 01:03, Jianfeng Liu wrote:
From: Diederik de Haas
Fix the ordering of the main nodes by sorting them alphabetically and
then the ones with a memory address sequentially by that address.
Signed-off-by: Diederik de Haas
Link: https://lore.kernel.org/r/20240406172821.34173-1-didi.deb...@cknow.org
Signed-off-by: Heiko Stuebner
[ upstream commit: cbb97fe18e299ece1c0074924c630de6a19b320f ]
(cherry picked from commit bbf7c16f2f1208b96349f6f6648b69cfaa1a482b)
Signed-off-by: Jianfeng Liu
Reviewed-by: Kever Yang
Thanks,
- Kever
---
(no changes since v1)
dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 304 +--
1 file changed, 152 insertions(+), 152 deletions(-)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 89d40cff635..ac5bd630f15 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -347,6 +347,11 @@
};
};
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ };
+
firmware {
optee: optee {
compatible = "linaro,optee-tz";
@@ -394,11 +399,6 @@
#clock-cells = <0>;
};
- display_subsystem: display-subsystem {
- compatible = "rockchip,display-subsystem";
- ports = <&vop_out>;
- };
-
timer {
compatible = "arm,armv8-timer";
interrupts = ,
@@ -436,6 +436,62 @@
};
};
+ gpu: gpu@fb00 {
+ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
+ reg = <0x0 0xfb00 0x0 0x20>;
+ #cooling-cells = <2>;
+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
+ assigned-clock-rates = <2>;
+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
+<&cru CLK_GPU_STACKS>;
+ clock-names = "core", "coregroup", "stacks";
+ dynamic-power-coefficient = <2982>;
+ interrupts = ,
+,
+;
+ interrupt-names = "job", "mmu", "gpu";
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&power RK3588_PD_GPU>;
+ status = "disabled";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-3 {
+ opp-hz = /bits/ 64 <3>;
+ opp-microvolt = <675000 675000 85>;
+ };
+ opp-4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <675000 675000 85>;
+ };
+ opp-5 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <675000 675000 85>;
+ };
+ opp-6 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <675000 675000 85>;
+ };
+ opp-7 {
+ opp-hz = /bits/ 64 <7>;
+ opp-microvolt = <70 70 85>;
+ };
+ opp-8 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = <75 75 85>;
+ };
+ opp-9 {
+ opp-hz = /bits/ 64 <9>;
+ opp-microvolt = <80 80 85>;
+ };
+ opp-10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = <85 85 85>;
+ };
+ };
+ };
+
usb_host0_ehci: usb@fc80 {
compatible = "rockchip,rk3588-ehci", "generic-ehci";
reg = <0x0 0xfc80 0x0 0x4>;
@@ -501,62 +557,6 @@
status = "disabled";
};
- gpu: gpu@fb00 {
- compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
- reg = <
Re: [PATCH 3/3] regulator: rk8xx: clarify operator precedence
On 2024/6/5 17:33, Quentin Schulz wrote:
From: Quentin Schulz
My linter complains that the order isn't clear enough so let's put
parentheses around the ternary condition to make it happy.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/power/regulator/rk8xx.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c
index bd5a37e718f..3125835bc07 100644
--- a/drivers/power/regulator/rk8xx.c
+++ b/drivers/power/regulator/rk8xx.c
@@ -520,7 +520,7 @@ static int _buck_get_enable(struct udevice *pmic, int buck)
if (ret < 0)
return ret;
- return ret & mask ? true : false;
+ return (ret & mask) ? true : false;
}
static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable)
@@ -585,7 +585,7 @@ static int _buck_get_suspend_enable(struct udevice *pmic,
int buck)
val = pmic_reg_read(pmic, RK816_REG_DCDC_SLP_EN);
if (val < 0)
return val;
- ret = val & mask ? 1 : 0;
+ ret = (val & mask) ? 1 : 0;
break;
case RK806_ID:
{
@@ -608,7 +608,7 @@ static int _buck_get_suspend_enable(struct udevice *pmic,
int buck)
val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF1);
if (val < 0)
return val;
- ret = val & mask ? 0 : 1;
+ ret = (val & mask) ? 0 : 1;
break;
case RK809_ID:
case RK817_ID:
@@ -620,7 +620,7 @@ static int _buck_get_suspend_enable(struct udevice *pmic,
int buck)
val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0));
if (val < 0)
return val;
- ret = val & mask ? 1 : 0;
+ ret = (val & mask) ? 1 : 0;
break;
default:
ret = -EINVAL;
@@ -723,7 +723,7 @@ static int _ldo_get_enable(struct udevice *pmic, int ldo)
if (ret < 0)
return ret;
- return ret & mask ? true : false;
+ return (ret & mask) ? true : false;
}
static int _nldo_get_enable(struct udevice *pmic, int nldo)
@@ -980,7 +980,7 @@ static int _ldo_get_suspend_enable(struct udevice *pmic,
int ldo)
val = pmic_reg_read(pmic, RK816_REG_LDO_SLP_EN);
if (val < 0)
return val;
- ret = val & mask ? 1 : 0;
+ ret = (val & mask) ? 1 : 0;
break;
case RK808_ID:
case RK818_ID:
@@ -988,7 +988,7 @@ static int _ldo_get_suspend_enable(struct udevice *pmic,
int ldo)
val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF2);
if (val < 0)
return val;
- ret = val & mask ? 0 : 1;
+ ret = (val & mask) ? 0 : 1;
break;
case RK809_ID:
case RK817_ID:
@@ -997,13 +997,13 @@ static int _ldo_get_suspend_enable(struct udevice *pmic,
int ldo)
val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0));
if (val < 0)
return val;
- ret = val & mask ? 1 : 0;
+ ret = (val & mask) ? 1 : 0;
} else {
mask = 1 << ldo;
val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(1));
if (val < 0)
return val;
- ret = val & mask ? 1 : 0;
+ ret = (val & mask) ? 1 : 0;
}
break;
}
@@ -1438,7 +1438,7 @@ static int switch_get_enable(struct udevice *dev)
if (ret < 0)
return ret;
- return ret & mask ? true : false;
+ return (ret & mask) ? true : false;
}
static int switch_set_suspend_value(struct udevice *dev, int uvolt)
@@ -1493,21 +1493,21 @@ static int switch_get_suspend_enable(struct udevice
*dev)
val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1);
if (val < 0)
return val;
- ret = val & mask ? 0 : 1;
+ ret = (val & mask) ? 0 : 1;
break;
case RK809_ID:
mask = 1 << (sw + 6);
val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0));
if (val < 0)
return val;
- ret = val & mask ? 1 : 0;
+ ret = (val & mask) ? 1 : 0;
break;
case RK818_ID:
mask = 1 << 6;
val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1);
if (val < 0)
return val;
- ret = val & mask ? 0 : 1;
+ ret = (val & mask) ? 0 : 1;
break;
}
Re: [PATCH 2/3] regulator: rk8xx: pass pmic udevice instead of regulator to all internal functions
On 2024/6/5 17:33, Quentin Schulz wrote:
From: Quentin Schulz
For the sake of consistency, make all internal (starting with _)
functions expect a pmic udevice instead of a regulator udevice.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/power/regulator/rk8xx.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c
index cce3502f89c..bd5a37e718f 100644
--- a/drivers/power/regulator/rk8xx.c
+++ b/drivers/power/regulator/rk8xx.c
@@ -1134,14 +1134,14 @@ static int buck_get_enable(struct udevice *dev)
return _buck_get_enable(dev->parent, buck);
}
-static int _ldo_get_value(struct udevice *dev, const struct rk8xx_reg_info *info)
+static int _ldo_get_value(struct udevice *pmic, const struct rk8xx_reg_info
*info)
{
int mask = info->vsel_mask;
int ret, val;
if (info->vsel_reg == NA)
return -ENOSYS;
- ret = pmic_reg_read(dev->parent, info->vsel_reg);
+ ret = pmic_reg_read(pmic, info->vsel_reg);
if (ret < 0)
return ret;
val = ret & mask;
@@ -1154,7 +1154,7 @@ static int ldo_get_value(struct udevice *dev)
int ldo = dev->driver_data - 1;
const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
- return _ldo_get_value(dev, info);
+ return _ldo_get_value(dev->parent, info);
}
static int nldo_get_value(struct udevice *dev)
@@ -1162,7 +1162,7 @@ static int nldo_get_value(struct udevice *dev)
int nldo = dev->driver_data - 1;
const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, 0);
- return _ldo_get_value(dev, info);
+ return _ldo_get_value(dev->parent, info);
}
static int pldo_get_value(struct udevice *dev)
@@ -1170,10 +1170,10 @@ static int pldo_get_value(struct udevice *dev)
int pldo = dev->driver_data - 1;
const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, 0);
- return _ldo_get_value(dev, info);
+ return _ldo_get_value(dev->parent, info);
}
-static int _ldo_set_value(struct udevice *dev, const struct rk8xx_reg_info *info, int uvolt)
+static int _ldo_set_value(struct udevice *pmic, const struct rk8xx_reg_info
*info, int uvolt)
{
int mask = info->vsel_mask;
int val;
@@ -1189,7 +1189,7 @@ static int _ldo_set_value(struct udevice *dev, const
struct rk8xx_reg_info *info
debug("%s: volt=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
__func__, uvolt, info->vsel_reg, mask, val);
- return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val);
+ return pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
}
static int ldo_set_value(struct udevice *dev, int uvolt)
@@ -1197,7 +1197,7 @@ static int ldo_set_value(struct udevice *dev, int uvolt)
int ldo = dev->driver_data - 1;
const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo,
uvolt);
- return _ldo_set_value(dev, info, uvolt);
+ return _ldo_set_value(dev->parent, info, uvolt);
}
static int nldo_set_value(struct udevice *dev, int uvolt)
@@ -1205,7 +1205,7 @@ static int nldo_set_value(struct udevice *dev, int uvolt)
int nldo = dev->driver_data - 1;
const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo,
uvolt);
- return _ldo_set_value(dev, info, uvolt);
+ return _ldo_set_value(dev->parent, info, uvolt);
}
static int pldo_set_value(struct udevice *dev, int uvolt)
@@ -1213,7 +1213,7 @@ static int pldo_set_value(struct udevice *dev, int uvolt)
int pldo = dev->driver_data - 1;
const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo,
uvolt);
- return _ldo_set_value(dev, info, uvolt);
+ return _ldo_set_value(dev->parent, info, uvolt);
}
static int _ldo_set_suspend_value(struct udevice *pmic, const struct rk8xx_reg_info *info, int uvolt)
Re: [PATCH 1/3] regulator: rk8xx: fix incorrect device used for _ldo_[sg]et_suspend_value
On 2024/6/5 17:33, Quentin Schulz wrote:
From: Quentin Schulz
_ldo_get_suspend_value and _ldo_set_suspend_value get passed the parent
of the regulator (so the pmic) as first argument, therefore this udevice
should be used for pmic_* callbacks instead of using the parent of the
pmic.
To avoid further confusion, let's rename the argument to pmic instead of
dev, highlighting which kind of device we expect as argument.
Fixes: f047e4ab9762 ("regulator: rk8xx: add indirection level for some ldo
callbacks")
Reported-by: Simon Glass
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/power/regulator/rk8xx.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c
index 1bd4605d43a..cce3502f89c 100644
--- a/drivers/power/regulator/rk8xx.c
+++ b/drivers/power/regulator/rk8xx.c
@@ -1216,7 +1216,7 @@ static int pldo_set_value(struct udevice *dev, int uvolt)
return _ldo_set_value(dev, info, uvolt);
}
-static int _ldo_set_suspend_value(struct udevice *dev, const struct rk8xx_reg_info *info, int uvolt)
+static int _ldo_set_suspend_value(struct udevice *pmic, const struct
rk8xx_reg_info *info, int uvolt)
{
int mask = info->vsel_mask;
int val;
@@ -1232,7 +1232,7 @@ static int _ldo_set_suspend_value(struct udevice *dev,
const struct rk8xx_reg_in
debug("%s: volt=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
__func__, uvolt, info->vsel_sleep_reg, mask, val);
- return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val);
+ return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val);
}
static int ldo_set_suspend_value(struct udevice *dev, int uvolt)
@@ -1259,7 +1259,7 @@ static int pldo_set_suspend_value(struct udevice *dev,
int uvolt)
return _ldo_set_suspend_value(dev->parent, info, uvolt);
}
-static int _ldo_get_suspend_value(struct udevice *dev, const struct rk8xx_reg_info *info)
+static int _ldo_get_suspend_value(struct udevice *pmic, const struct
rk8xx_reg_info *info)
{
int mask = info->vsel_mask;
int val, ret;
@@ -1267,7 +1267,7 @@ static int _ldo_get_suspend_value(struct udevice *dev,
const struct rk8xx_reg_in
if (info->vsel_sleep_reg == NA)
return -ENOSYS;
- ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
+ ret = pmic_reg_read(pmic, info->vsel_sleep_reg);
if (ret < 0)
return ret;
Pull request: u-boot-rockchip-20240525
Hi Tom, Please pull the updates for rockchip platform: - new board: rk3566 Powkiddy X55, rk3588s Indiedroid Nova; - rv1126 migrate to OF_UPSTREAM; - Fix for px30 ringneck board; - Fix for rk3588 SPLL clock init; CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/20844 Thanks, - Kever The following changes since commit a7f0154c412859323396111dd0c09dbafbc153cb: Prepare v2024.07-rc3 (2024-05-20 10:05:16 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-20240525 for you to fetch changes up to 5c7caa95982c481cc0d6a0e9997629afb0d2ce10: board: rockchip: Add Indiedroid Nova (2024-05-25 10:28:19 +0800) Anand Moon (1): rockchip: rv1126: Migrate to OF_UPSTREAM Chris Morgan (2): board: rockchip: add Powkiddy X55 board: rockchip: Add Indiedroid Nova Fabio Estevam (1): rockchip: rv1108: Remove unneeded local rv1108-cru.h Heiko Stuebner (1): clk: rockchip: rk3588: Set SPLL frequency during SPL stage Quentin Schulz (3): rockchip: px30: default TPL_SYS_MALLOC_F_LEN to 0x600 on PX30 Kconfig level rockchip: Use common bss and stack addresses on PX30 rockchip: ringneck_px30: Use common bss and stack addresses arch/arm/dts/Makefile | 3 - arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi | 9 + arch/arm/dts/rv1126-edgeble-neu2-io.dts | 112 arch/arm/dts/rv1126-edgeble-neu2.dtsi | 345 arch/arm/dts/rv1126-pinctrl.dtsi | 341 arch/arm/dts/rv1126-sonoff-ihost.dts | 29 - arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404 -- arch/arm/dts/rv1126.dtsi | 623 - arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 4 + arch/arm/mach-rockchip/Kconfig| 1 + arch/arm/mach-rockchip/px30/Kconfig | 8 +- arch/arm/mach-rockchip/rk3568/Kconfig | 6 + arch/arm/mach-rockchip/rk3588/Kconfig | 10 + board/indiedroid/nova/Kconfig | 12 + board/indiedroid/nova/MAINTAINERS | 6 + board/powkiddy/x55/Kconfig| 15 + board/powkiddy/x55/MAINTAINERS| 7 + board/powkiddy/x55/Makefile | 6 + board/powkiddy/x55/x55.c | 39 ++ configs/evb-px30_defconfig| 1 - configs/firefly-px30_defconfig| 1 - configs/neu2-io-rv1126_defconfig | 2 +- configs/nova-rk3588s_defconfig| 69 +++ configs/odroid-go2_defconfig | 1 - configs/powkiddy-x55-rk3566_defconfig | 58 ++ configs/px30-core-ctouch2-of10-px30_defconfig | 1 - configs/px30-core-ctouch2-px30_defconfig | 1 - configs/px30-core-edimm2.2-px30_defconfig | 1 - configs/ringneck-px30_defconfig | 19 +- configs/sonoff-ihost-rv1126_defconfig | 2 +- doc/board/rockchip/rockchip.rst | 2 + drivers/clk/rockchip/clk_rk3588.c | 30 +- include/configs/nova-rk3588s.h| 15 + include/configs/powkiddy-x55-rk3566.h | 12 + include/dt-bindings/clock/rockchip,rv1126-cru.h | 632 -- include/dt-bindings/clock/rv1108-cru.h| 356 include/dt-bindings/power/rockchip,rv1126-power.h | 35 -- 37 files changed, 310 insertions(+), 2908 deletions(-) create mode 100644 arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2-io.dts delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2.dtsi delete mode 100644 arch/arm/dts/rv1126-pinctrl.dtsi delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi delete mode 100644 arch/arm/dts/rv1126.dtsi create mode 100644 board/indiedroid/nova/Kconfig create mode 100644 board/indiedroid/nova/MAINTAINERS create mode 100644 board/powkiddy/x55/Kconfig create mode 100644 board/powkiddy/x55/MAINTAINERS create mode 100644 board/powkiddy/x55/Makefile create mode 100644 board/powkiddy/x55/x55.c create mode 100644 configs/nova-rk3588s_defconfig create mode 100644 configs/powkiddy-x55-rk3566_defconfig create mode 100644 include/configs/nova-rk3588s.h create mode 100644 include/configs/powkiddy-x55-rk3566.h delete mode 100644 include/dt-bindings/clock/rockchip,rv1126-cru.h delete mode 100644 include/dt-bindings/clock/rv1108-cru.h delete mode 100644 include/dt-bindings/power/rockchip,rv1126-power.h
Re: [PATCH V4] board: rockchip: Add Indiedroid Nova
On 2024/5/25 00:48, Chris Morgan wrote:
From: Chris Morgan
The Indiedroid Nova is a Rockchip RK3588S based SBC from Indiedroid.
Specifications:
Rockchip RK3588S SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
Optional eMMC
2x USB 2.0, 2x USB 3.0, 1x USB 3.0 C port with DP Alt
1x MIPI-CSI Port (4-lane or 2x 2-lane)
1x MIPI-DSI 4-lane connector
1x Micro HDMI 2.1 output, 1x DP 1.4 output
Gigabit Ethernet
Realtek RTL8821CS WiFi
4 pin debug UART connector
40 pin GPIO header
Size: 85mm x 56mm (Raspberry Pi Form Factor)
Kernel commit:
3900160e164b ("arm64: dts: rockchip: Add Indiedroid Nova board")
Signed-off-by: Chris Morgan
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes since V3:
- Corrected another typo in the MAINTAINERS file. I think I got them
all this time.
Changes since V2:
- Corrected typo in the MAINTAINERS file.
- Removed OF_UPSTREAM since it is now defined for all RK3588 boards.
Changes since V1:
- Refactored to use the upstream Linux device tree now that that is
an option.
- Added board to doc/board/rockchip/rockchip.rst.
---
arch/arm/mach-rockchip/rk3588/Kconfig | 10
board/indiedroid/nova/Kconfig | 12 +
board/indiedroid/nova/MAINTAINERS | 6 +++
configs/nova-rk3588s_defconfig| 69 +++
doc/board/rockchip/rockchip.rst | 1 +
include/configs/nova-rk3588s.h| 15 ++
6 files changed, 113 insertions(+)
create mode 100644 board/indiedroid/nova/Kconfig
create mode 100644 board/indiedroid/nova/MAINTAINERS
create mode 100644 configs/nova-rk3588s_defconfig
create mode 100644 include/configs/nova-rk3588s.h
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig
b/arch/arm/mach-rockchip/rk3588/Kconfig
index 39049ab35a..820e979abb 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -78,6 +78,15 @@ config TARGET_NANOPCT6_RK3588
Power: 5.5*2.1mm DC Jack, 12VDC input
Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case)
+config TARGET_NOVA_RK3588
+ bool "Indiedroid Nova RK3588"
+ select BOARD_LATE_INIT
+ help
+ Indiedroid Nova is a Rockchip RK3588s based SBC by Indiedroid.
+ It comes in configurations from 4GB of RAM to 16GB of RAM,
+ includes socket for eMMC storage, an SDMMC slot, and a 40-pin
+ GPIO header for expansion.
+
config TARGET_RK3588_NEU6
bool "Edgeble Neural Compute Module 6(Neu6) SoM"
select BOARD_LATE_INIT
@@ -223,6 +232,7 @@ config TEXT_BASE
source "board/edgeble/neural-compute-module-6/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
+source "board/indiedroid/nova/Kconfig"
source "board/pine64/quartzpro64-rk3588/Kconfig"
source "board/turing/turing-rk1-rk3588/Kconfig"
source "board/radxa/rock5a-rk3588s/Kconfig"
diff --git a/board/indiedroid/nova/Kconfig b/board/indiedroid/nova/Kconfig
new file mode 100644
index 00..271d15a0ed
--- /dev/null
+++ b/board/indiedroid/nova/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NOVA_RK3588
+
+config SYS_BOARD
+ default "nova-rk3588s"
+
+config SYS_VENDOR
+ default "indiedroid"
+
+config SYS_CONFIG_NAME
+ default "nova-rk3588s"
+
+endif
diff --git a/board/indiedroid/nova/MAINTAINERS
b/board/indiedroid/nova/MAINTAINERS
new file mode 100644
index 00..db1f11551b
--- /dev/null
+++ b/board/indiedroid/nova/MAINTAINERS
@@ -0,0 +1,6 @@
+INDIEDROID-NOVA-RK3588
+M: Chris Morgan
+S: Maintained
+F: board/indiedroid/nova
+F: configs/nova-rk3588s_defconfig
+F: include/configs/nova-rk3588s.h
diff --git a/configs/nova-rk3588s_defconfig b/configs/nova-rk3588s_defconfig
new file mode 100644
index 00..a2e2440359
--- /dev/null
+++ b/configs/nova-rk3588s_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-indiedroid-nova"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_NOVA_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB5
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-indiedroid-nova.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is
Re: [PATCH V3] board: rockchip: Add Indiedroid Nova
Hi Tom,
This new boards has MAINTAINERS file, but the CI reports:
WARNING: no maintainers for 'nova-rk3588s'
Could you give advice for this?
Thanks,
- Kever
On 2024/5/21 23:33, Chris Morgan wrote:
From: Chris Morgan
The Indiedroid Nova is a Rockchip RK3588S based SBC from Indiedroid.
Specifications:
Rockchip RK3588S SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
Optional eMMC
2x USB 2.0, 2x USB 3.0, 1x USB 3.0 C port with DP Alt
1x MIPI-CSI Port (4-lane or 2x 2-lane)
1x MIPI-DSI 4-lane connector
1x Micro HDMI 2.1 output, 1x DP 1.4 output
Gigabit Ethernet
Realtek RTL8821CS WiFi
4 pin debug UART connector
40 pin GPIO header
Size: 85mm x 56mm (Raspberry Pi Form Factor)
Kernel commit:
3900160e164b ("arm64: dts: rockchip: Add Indiedroid Nova board")
Signed-off-by: Chris Morgan
---
Changes since V2:
- Corrected typo in the MAINTAINERS file.
- Removed OF_UPSTREAM since it is now defined for all RK3588 boards.
Changes since V1:
- Refactored to use the upstream Linux device tree now that that is
an option.
- Added board to doc/board/rockchip/rockchip.rst.
---
arch/arm/mach-rockchip/rk3588/Kconfig | 10
board/indiedroid/nova/Kconfig | 12 +
board/indiedroid/nova/MAINTAINERS | 6 +++
configs/nova-rk3588s_defconfig| 69 +++
doc/board/rockchip/rockchip.rst | 1 +
include/configs/nova-rk3588s.h| 15 ++
6 files changed, 113 insertions(+)
create mode 100644 board/indiedroid/nova/Kconfig
create mode 100644 board/indiedroid/nova/MAINTAINERS
create mode 100644 configs/nova-rk3588s_defconfig
create mode 100644 include/configs/nova-rk3588s.h
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig
b/arch/arm/mach-rockchip/rk3588/Kconfig
index 39049ab35a..820e979abb 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -78,6 +78,15 @@ config TARGET_NANOPCT6_RK3588
Power: 5.5*2.1mm DC Jack, 12VDC input
Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case)
+config TARGET_NOVA_RK3588
+ bool "Indiedroid Nova RK3588"
+ select BOARD_LATE_INIT
+ help
+ Indiedroid Nova is a Rockchip RK3588s based SBC by Indiedroid.
+ It comes in configurations from 4GB of RAM to 16GB of RAM,
+ includes socket for eMMC storage, an SDMMC slot, and a 40-pin
+ GPIO header for expansion.
+
config TARGET_RK3588_NEU6
bool "Edgeble Neural Compute Module 6(Neu6) SoM"
select BOARD_LATE_INIT
@@ -223,6 +232,7 @@ config TEXT_BASE
source "board/edgeble/neural-compute-module-6/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
+source "board/indiedroid/nova/Kconfig"
source "board/pine64/quartzpro64-rk3588/Kconfig"
source "board/turing/turing-rk1-rk3588/Kconfig"
source "board/radxa/rock5a-rk3588s/Kconfig"
diff --git a/board/indiedroid/nova/Kconfig b/board/indiedroid/nova/Kconfig
new file mode 100644
index 00..271d15a0ed
--- /dev/null
+++ b/board/indiedroid/nova/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NOVA_RK3588
+
+config SYS_BOARD
+ default "nova-rk3588s"
+
+config SYS_VENDOR
+ default "indiedroid"
+
+config SYS_CONFIG_NAME
+ default "nova-rk3588s"
+
+endif
diff --git a/board/indiedroid/nova/MAINTAINERS
b/board/indiedroid/nova/MAINTAINERS
new file mode 100644
index 00..db40adf9ad
--- /dev/null
+++ b/board/indiedroid/nova/MAINTAINERS
@@ -0,0 +1,6 @@
+INDIEDROID-NOVA-RK3588
+M: Chris Morgan
+S: Maintained
+F: board/indiedroid/nova
+F: include/configs/nova-rk3588s.h
+F: configs/indiedroid-nova-rk3588s_defconfig
diff --git a/configs/nova-rk3588s_defconfig b/configs/nova-rk3588s_defconfig
new file mode 100644
index 00..a2e2440359
--- /dev/null
+++ b/configs/nova-rk3588s_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-indiedroid-nova"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_NOVA_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB5
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-indiedroid-nova.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks
Re: [PATCH 09/10] rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB
On 2024/5/22 01:40, Quentin Schulz wrote: From: Quentin Schulz In order to be able to properly mux UART on PX30 EVB, the pinmux needs to be done at runtime, so let's not remove the pinctrl nodes from the SPL DTB. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/evb-px30_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 50ce1d7a9f3..a5833ad6d09 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -51,7 +51,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y
Re: [PATCH 10/10] rockchip: evb-px30: make UART5 the debug UART
On 2024/5/22 01:40, Quentin Schulz wrote: From: Quentin Schulz In the Device Tree, UART5 is the system UART, but in the defconfig it currently is UART2. Let's sync the two by making the defconfig use UART5 as well. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/evb-px30_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index a5833ad6d09..abe545625a5 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -10,7 +10,7 @@ CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_EVB_PX30=y # CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_DEBUG_UART_BASE=0xFF16 +CONFIG_DEBUG_UART_BASE=0xff178000 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y
Re: [PATCH 08/10] rockchip: px30: make UART pinmux accessible to TPL/SPL DTB
On 2024/5/22 01:40, Quentin Schulz wrote:
From: Quentin Schulz
This adds the default pinmux for UART2 and UART5 to the TPL/SPL DTB (if
not removed through the CONFIG_OF_SPL_REMOVE_PROPS symbol) as those two
controllers are always made available to all boards.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/px30-u-boot.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
index 046da022ffe..59fa9f43a97 100644
--- a/arch/arm/dts/px30-u-boot.dtsi
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -33,11 +33,27 @@
bootph-all;
};
+&uart2m0_xfer {
+ bootph-all;
+};
+
&uart5 {
clock-frequency = <2400>;
bootph-all;
};
+&uart5_cts {
+ bootph-all;
+};
+
+&uart5_rts {
+ bootph-all;
+};
+
+&uart5_xfer {
+ bootph-all;
+};
+
&sdmmc {
bootph-all;
Re: [PATCH 07/10] rockchip: px30-core-*: Use common bss and stack addresses
On 2024/5/22 01:40, Quentin Schulz wrote: From: Quentin Schulz U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them. Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/px30-core-ctouch2-of10-px30_defconfig | 18 +++--- configs/px30-core-ctouch2-px30_defconfig | 18 +++--- configs/px30-core-edimm2.2-px30_defconfig | 18 +++--- 3 files changed, 9 insertions(+), 45 deletions(-) diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index 87a39e115df..dd005f20ff8 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x0020 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10" -CONFIG_SPL_TEXT_BASE=0x CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x60 -CONFIG_SPL_STACK=0x40 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF16 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x2 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index 7162c117beb..f6559fbae3a 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x0020 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2" -CONFIG_SPL_TEXT_BASE=0x CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x60 -CONFIG_SPL_STACK=0x40 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF16 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x2 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index 1182f60358f..a099e9378c9 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x0020 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40 CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2" -CONFIG_SPL_TEXT_BASE=0x CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BO
Re: [PATCH 06/10] rockchip: odroid-go2: Use common bss and stack addresses
On 2024/5/22 01:39, Quentin Schulz wrote: From: Quentin Schulz U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them. Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/odroid-go2_defconfig | 18 +++--- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 3c1abb83ed9..f4c9b02e12f 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -2,29 +2,17 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x0020 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x4000 CONFIG_DEFAULT_DEVICE_TREE="rk3326-odroid-go2" -CONFIG_SPL_TEXT_BASE=0x CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_ODROID_GO2=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x60 -CONFIG_SPL_STACK=0x40 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF16 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -44,11 +32,11 @@ CONFIG_SPL_MAX_SIZE=0x2 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set
Re: [PATCH 04/10] rockchip: evb-px30: Use common bss and stack addresses
On 2024/5/22 01:39, Quentin Schulz wrote: From: Quentin Schulz U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them. Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/evb-px30_defconfig | 18 +++--- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 73a3c6120e0..50ce1d7a9f3 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -2,26 +2,14 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x0020 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40 CONFIG_DEFAULT_DEVICE_TREE="px30-evb" -CONFIG_SPL_TEXT_BASE=0x CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_EVB_PX30=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x60 -CONFIG_SPL_STACK=0x40 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF16 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -39,9 +27,9 @@ CONFIG_SPL_MAX_SIZE=0x2 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set
Re: [PATCH 03/10] rockchip: ringneck_px30: Use common bss and stack addresses
On 2024/5/22 01:39, Quentin Schulz wrote: From: Quentin Schulz U-Boot proper pre-reloc is currently running out of memory and it is thus impossible to boot into U-Boot CLI. Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/ringneck-px30_defconfig | 18 +++--- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index 0df1b8a59ac..94179dca3ae 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x0020 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40 CONFIG_DEFAULT_DEVICE_TREE="px30-ringneck-haikou" -CONFIG_SPL_TEXT_BASE=0x CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_RINGNECK_PX30=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x60 -CONFIG_SPL_STACK=0x40 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF03 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -41,11 +29,11 @@ CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set
Re: [PATCH 05/10] rockchip: firefly-px30: Use common bss and stack addresses
On 2024/5/22 01:39, Quentin Schulz wrote: From: Quentin Schulz U-Boot proper pre-reloc is currently running out of memory on PX30 Ringneck and it is thus impossible to boot into U-Boot CLI. It is assumed the same problem can be seen on other PX30 boards though I cannot guarantee it since I don't have access to them. Fix this by migrating to the common bss and stack addresses for PX30, which drastically increases the size of the pre-reloc allocation pool (8 times bigger now). The memory layout in SPL and U-Boot proper now match the other SoCs' using ROCKCHIP_COMMON_STACK_ADDR. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/firefly-px30_defconfig | 18 +++--- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 0a14b393667..063e4211fb7 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -2,27 +2,15 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x0020 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40 CONFIG_DEFAULT_DEVICE_TREE="px30-firefly" -CONFIG_SPL_TEXT_BASE=0x CONFIG_DM_RESET=y CONFIG_ROCKCHIP_PX30=y +# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set CONFIG_TARGET_EVB_PX30=y CONFIG_DEBUG_UART_CHANNEL=1 -CONFIG_TPL_LIBGENERIC_SUPPORT=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK_R_ADDR=0x60 -CONFIG_SPL_STACK=0x40 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400 -CONFIG_SPL_BSS_MAX_SIZE=0x4000 -CONFIG_SPL_STACK_R=y CONFIG_DEBUG_UART_BASE=0xFF16 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0x800800 @@ -40,9 +28,9 @@ CONFIG_SPL_MAX_SIZE=0x2 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set # CONFIG_TPL_BANNER_PRINT is not set # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set
Re: [PATCH 02/10] rockchip: Use common bss and stack addresses on PX30
On 2024/5/22 01:39, Quentin Schulz wrote:
From: Quentin Schulz
See commit 008ba0d56d00 ("rockchip: Add common default bss and stack
addresses") for memory layout. This migrates PX30 to use the new layout,
except for TPL. Indeed, PX30 is extremely limited in SRAM, so we need to
be extra careful about what goes into the TPL and how much we can
allocate there, so let's keep the current value for
TPL_SYS_MALLOC_F_LEN (already present in the PX30-specific Kconfig, from
an earlier commit).
This will allow us to use the same memory layout on one more Rockchip
SoC, which is always a nice thing. Additionally, this will make it
easier to fix U-Boot proper pre-reloc running out of memory on PX30 in a
subsequent commit.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/px30/Kconfig | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/px30/Kconfig
b/arch/arm/mach-rockchip/px30/Kconfig
index e39472604c3..dcf9eb8144b 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -68,8 +68,11 @@ config ROCKCHIP_STIMER_BASE
config SYS_SOC
default "px30"
+config ROCKCHIP_COMMON_STACK_ADDR
+ default y
+
config SYS_MALLOC_F_LEN
- default 0x400
+ default 0x400 if !SPL_SHARES_INIT_SP_ADDR
config SPL_SERIAL
default y
Re: [PATCH 01/10] rockchip: px30: default TPL_SYS_MALLOC_F_LEN to 0x600 on PX30 Kconfig level
On 2024/5/22 01:39, Quentin Schulz wrote: From: Quentin Schulz This is the kind of setting that typically doesn't need to be changed between boards based on the same SoC, so let's make it the default in PX30 Kconfig so we don't have to care about it in the defconfig if we don't want to. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- arch/arm/mach-rockchip/px30/Kconfig | 3 +++ configs/evb-px30_defconfig| 1 - configs/firefly-px30_defconfig| 1 - configs/odroid-go2_defconfig | 1 - configs/px30-core-ctouch2-of10-px30_defconfig | 1 - configs/px30-core-ctouch2-px30_defconfig | 1 - configs/px30-core-edimm2.2-px30_defconfig | 1 - configs/ringneck-px30_defconfig | 1 - 8 files changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 23f8f430c4a..e39472604c3 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -83,6 +83,9 @@ config TPL_TEXT_BASE config TPL_STACK default 0xff0e4fff +config TPL_SYS_MALLOC_F_LEN + default 0x600 + config DEBUG_UART_CHANNEL int "Mux channel to use for debug UART2/UART3" depends on DEBUG_UART_BOARD_INIT diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 07c56a45ec0..73a3c6120e0 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -16,7 +16,6 @@ CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_EVB_PX30=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x60 CONFIG_SPL_STACK=0x40 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index e5377dcdf3d..0a14b393667 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_TARGET_EVB_PX30=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x60 CONFIG_SPL_STACK=0x40 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 99d7149a44c..3c1abb83ed9 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -19,7 +19,6 @@ CONFIG_TARGET_ODROID_GO2=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x60 CONFIG_SPL_STACK=0x40 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index a2801ec7796..87a39e115df 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x60 CONFIG_SPL_STACK=0x40 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index cc33e275742..7162c117beb 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x60 CONFIG_SPL_STACK=0x40 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index 99e1b2fc7ae..1182f60358f 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y CONFIG_DEBUG_UART_CHANNEL=1 CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x60 CONFIG_SPL_STACK=0x40 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index 67a44eda684..0df1b8a59ac 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_RINGNECK_PX30=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_STACK_R_ADDR=0x60 CONFIG_SPL_STACK=0x40 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
Re: [PATCH 1/2 V2] Revert "board: rockchip: Add early ADC button detect for RGxx3"
On 2024/5/21 23:45, Chris Morgan wrote:
From: Chris Morgan
This reverts commit 41a60d0e5cef54a59596a58940fa7c9cf071034b.
On some of the supported devices the adc detect code always returns
that the button has been pushed, and as a result the device will
not boot normally.
Have you check the key input voltage with voltameter which can identify
is hardware issue or software issue.
Thanks,
- Kever
Signed-off-by: Chris Morgan
---
board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 64 --
1 file changed, 64 deletions(-)
diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
index 099eea60c3..5c57b902d1 100644
--- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
+++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
@@ -6,14 +6,12 @@
#include
#include
#include
-#include
#include
#include
#include
#include
#include
#include
-#include
#include
#include
#include
@@ -21,8 +19,6 @@
#include
#include
-#define BOOT_BROM_DOWNLOAD 0xef08a53c
-
#define GPIO0_BASE0xfdd6
#define GPIO4_BASE0xfe77
#define GPIO_SWPORT_DR_L 0x
@@ -36,14 +32,6 @@
#define GPIO_WRITEMASK(bits) ((bits) << 16)
-#define SARADC_BASE 0xfe72
-#define SARADC_DATA0x
-#define SARADC_STAS0x0004
-#define SARADC_ADC_STATUS BIT(0)
-#define SARADC_CTRL0x0008
-#define SARADC_INPUT_SRC_MSK 0x7
-#define SARADC_POWER_CTRL BIT(3)
-
#define DTB_DIR "rockchip/"
struct rg3xx_model {
@@ -169,64 +157,12 @@ static const struct rg353_panel rg353_panel_details[] = {
},
};
-/*
- * The device has internal eMMC, and while some devices have an exposed
- * clk pin you can ground to force a bypass not all devices do. As a
- * result it may be possible for some devices to become a perma-brick
- * if a corrupted TPL or SPL stage with a valid header is flashed to
- * the internal eMMC. Add functionality to read ADC channel 0 (the func
- * button) as early as possible in the boot process to provide some
- * protection against this. If we ever get an open TPL stage, we should
- * consider moving this function there.
- */
-void read_func_button(void)
-{
- int ret;
- u32 reg;
-
- /* Turn off SARADC to reset it. */
- writel(0, (SARADC_BASE + SARADC_CTRL));
-
- /* Enable channel 0 and power on SARADC. */
- writel(((0 & SARADC_INPUT_SRC_MSK) | SARADC_POWER_CTRL),
- (SARADC_BASE + SARADC_CTRL));
-
- /*
-* Wait for data to be ready. Use timeout of 2us from
-* rockchip_saradc driver.
-*/
- ret = readl_poll_timeout((SARADC_BASE + SARADC_STAS), reg,
-!(reg & SARADC_ADC_STATUS), 2);
- if (ret) {
- printf("ADC Timeout");
- return;
- }
-
- /* Read the data from the SARADC. */
- reg = readl((SARADC_BASE + SARADC_DATA));
-
- /* Turn the SARADC back off so it's ready to be used again. */
- writel(0, (SARADC_BASE + SARADC_CTRL));
-
- /*
-* If the value is less than 30 the button is being pressed.
-* Reset the device back into Rockchip download mode.
-*/
- if (reg <= 30) {
- printf("download key pressed, entering download mode...");
- writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
- do_reset(NULL, 0, 0, NULL);
- }
-};
-
/*
* Start LED very early so user knows device is on. Set color
* to red.
*/
void spl_board_init(void)
{
- read_func_button();
-
/* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */
writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \
(GPIO_C7 | GPIO_C6 | GPIO_C5),
Re: [PATCH 2/2 V2] board: rockchip: rgxx3: Use sdmmc0 as first device
On 2024/5/21 23:45, Chris Morgan wrote:
From: Chris Morgan
Some of the rgxx3 devices do not have a way to recover from a poor
flash of a bootloader to eMMC. Set the device to always attempt to boot
from sdmmc0 first which ensures that we can override the boot from
emmc if we have a card present with a valid fit signature. The
expectation is that this will protect from the very unlikely chance
we have a valid FIT signature on the eMMC but the U-Boot stage fails
for some other reason.
Signed-off-by: Chris Morgan
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
index 793ed4ae8a..c7e849816a 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
@@ -4,7 +4,7 @@
/ {
chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdmmc1, &sdmmc0;
+ u-boot,spl-boot-order = &sdmmc0, &sdhci;
};
};
Re: [PATCH 1/2 V2] Revert "board: rockchip: Add early ADC button detect for RGxx3"
On 2024/5/21 23:45, Chris Morgan wrote:
From: Chris Morgan
This reverts commit 41a60d0e5cef54a59596a58940fa7c9cf071034b.
On some of the supported devices the adc detect code always returns
that the button has been pushed, and as a result the device will
not boot normally.
Signed-off-by: Chris Morgan
Reviewed-by: Kever Yang
Thanks,
- Kever
---
board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 64 --
1 file changed, 64 deletions(-)
diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
index 099eea60c3..5c57b902d1 100644
--- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
+++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
@@ -6,14 +6,12 @@
#include
#include
#include
-#include
#include
#include
#include
#include
#include
#include
-#include
#include
#include
#include
@@ -21,8 +19,6 @@
#include
#include
-#define BOOT_BROM_DOWNLOAD 0xef08a53c
-
#define GPIO0_BASE0xfdd6
#define GPIO4_BASE0xfe77
#define GPIO_SWPORT_DR_L 0x
@@ -36,14 +32,6 @@
#define GPIO_WRITEMASK(bits) ((bits) << 16)
-#define SARADC_BASE 0xfe72
-#define SARADC_DATA0x
-#define SARADC_STAS0x0004
-#define SARADC_ADC_STATUS BIT(0)
-#define SARADC_CTRL0x0008
-#define SARADC_INPUT_SRC_MSK 0x7
-#define SARADC_POWER_CTRL BIT(3)
-
#define DTB_DIR "rockchip/"
struct rg3xx_model {
@@ -169,64 +157,12 @@ static const struct rg353_panel rg353_panel_details[] = {
},
};
-/*
- * The device has internal eMMC, and while some devices have an exposed
- * clk pin you can ground to force a bypass not all devices do. As a
- * result it may be possible for some devices to become a perma-brick
- * if a corrupted TPL or SPL stage with a valid header is flashed to
- * the internal eMMC. Add functionality to read ADC channel 0 (the func
- * button) as early as possible in the boot process to provide some
- * protection against this. If we ever get an open TPL stage, we should
- * consider moving this function there.
- */
-void read_func_button(void)
-{
- int ret;
- u32 reg;
-
- /* Turn off SARADC to reset it. */
- writel(0, (SARADC_BASE + SARADC_CTRL));
-
- /* Enable channel 0 and power on SARADC. */
- writel(((0 & SARADC_INPUT_SRC_MSK) | SARADC_POWER_CTRL),
- (SARADC_BASE + SARADC_CTRL));
-
- /*
-* Wait for data to be ready. Use timeout of 2us from
-* rockchip_saradc driver.
-*/
- ret = readl_poll_timeout((SARADC_BASE + SARADC_STAS), reg,
-!(reg & SARADC_ADC_STATUS), 2);
- if (ret) {
- printf("ADC Timeout");
- return;
- }
-
- /* Read the data from the SARADC. */
- reg = readl((SARADC_BASE + SARADC_DATA));
-
- /* Turn the SARADC back off so it's ready to be used again. */
- writel(0, (SARADC_BASE + SARADC_CTRL));
-
- /*
-* If the value is less than 30 the button is being pressed.
-* Reset the device back into Rockchip download mode.
-*/
- if (reg <= 30) {
- printf("download key pressed, entering download mode...");
- writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
- do_reset(NULL, 0, 0, NULL);
- }
-};
-
/*
* Start LED very early so user knows device is on. Set color
* to red.
*/
void spl_board_init(void)
{
- read_func_button();
-
/* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */
writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \
(GPIO_C7 | GPIO_C6 | GPIO_C5),
Re: [PATCH v2] clk: rockchip: rk3588: Set SPLL frequency during SPL stage
On 2024/5/23 01:31, Heiko Stuebner wrote:
From: Heiko Stuebner
All parts expect the SPLL to run at 702MHz. In U-Boot it's the SPLL_HZ
declaring this rate and in the kernel it's a fixed clock definition.
While everything is expecting 702MHz, the SPLL is not running that
frequency when coming from the bootrom though, instead it's running
at 351MHz and the vendor-u-boot just sets it to the expected frequency.
The SPLL itself is located inside the secure-BUSCRU and in theory
accessible as an SCMI clock, though this requires an unknown amount
of cooperation from trusted-firmware to set at a later stage, though
during the SPL stage we can still access the relevant CRU directly.
The SPLL is for example necessary for the DSI controllers to produce
output.
As the SPLL is "just" another rk3588 pll, just set the desired rate
directly during the SPL stage.
Tested on rk3588-rock5b and rk3588-tiger by reading back the PLL rate
and also observing working DSI output with this change.
Fixes: 6737771600d4 ("rockchip: rk3588: Add support for sdmmc clocks in SPL")
Suggested-by: Andy Yan
Signed-off-by: Heiko Stuebner
Cc: Jonas Karlman
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
changes in v2:
- use correct name for SBUSCRU
- use dedicated constants for SBUSCRU registers
- add comment to make it explicit that the SPLL is in a different CRU
.../include/asm/arch-rockchip/cru_rk3588.h| 4 +++
drivers/clk/rockchip/clk_rk3588.c | 30 +--
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
index a4507e5fdd7..a0e54d39654 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -29,6 +29,7 @@ enum rk3588_pll_id {
V0PLL,
AUPLL,
PPLL,
+ SPLL,
PLL_COUNT,
};
@@ -150,6 +151,9 @@ struct pll_rate_table {
#define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE +
0x800)
#define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE +
0xa00)
+#define RK3588_SBUSCRU_SPLL_CON(x) ((x) * 0x4 + 0x220)
+#define RK3588_SBUSCRU_MODE_CON0 0x280
+
enum {
/* CRU_CLK_SEL8_CON */
ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT = 14,
diff --git a/drivers/clk/rockchip/clk_rk3588.c
b/drivers/clk/rockchip/clk_rk3588.c
index 4c611a39049..c41c9be6aa3 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -37,6 +37,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
RK3588_PLL_RATE(78600, 1, 131, 2, 0),
RK3588_PLL_RATE(74250, 4, 495, 2, 0),
RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
+ RK3588_PLL_RATE(70200, 3, 351, 2, 0),
RK3588_PLL_RATE(6, 2, 200, 2, 0),
RK3588_PLL_RATE(59400, 2, 198, 2, 0),
RK3588_PLL_RATE(2, 3, 400, 4, 0),
@@ -65,6 +66,15 @@ static struct rockchip_pll_clock rk3588_pll_clks[] = {
RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
[PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
+#ifdef CONFIG_SPL_BUILD
+ /*
+* The SPLL is part of the SBUSCRU, not the main CRU and as
+* such only directly accessible during the SPL stage.
+*/
+ [SPLL] = PLL(pll_rk3588, 0, RK3588_SBUSCRU_SPLL_CON(0),
+RK3588_SBUSCRU_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
+#endif
+
};
#ifndef CONFIG_SPL_BUILD
@@ -2044,6 +2054,7 @@ U_BOOT_DRIVER(rockchip_rk3588_cru) = {
#ifdef CONFIG_SPL_BUILD
#define SCRU_BASE 0xfd7d
+#define SBUSCRU_BASE 0xfd7d8000
static ulong rk3588_scru_clk_get_rate(struct clk *clk)
{
@@ -2118,15 +2129,28 @@ static ulong rk3588_scru_clk_set_rate(struct clk *clk,
ulong rate)
return rk3588_scru_clk_get_rate(clk);
}
+static int rk3588_scru_clk_probe(struct udevice *dev)
+{
+ int ret;
+
+ ret = rockchip_pll_set_rate(&rk3588_pll_clks[SPLL],
+ (void *)SBUSCRU_BASE, SPLL, SPLL_HZ);
+ if (ret)
+ debug("%s setting spll rate failed %d\n", __func__, ret);
+
+ return 0;
+}
+
static const struct clk_ops rk3588_scru_clk_ops = {
.get_rate = rk3588_scru_clk_get_rate,
.set_rate = rk3588_scru_clk_set_rate,
};
U_BOOT_DRIVER(rockchip_rk3588_scru) = {
- .name = "rockchip_rk3588_scru",
- .id = UCLASS_CLK,
- .ops = &rk3588_scru_clk_ops,
+ .name = "rockchip_rk3588_scru",
+ .id = UCLASS_CLK,
+ .ops= &rk3588_scru_clk_ops,
+ .probe = rk3588_scru_clk_probe,
};
static int rk3588_scmi_spl_glue_bind(struct udevice *dev)
Re: [PATCH V3] board: rockchip: Add Indiedroid Nova
On 2024/5/21 23:33, Chris Morgan wrote:
From: Chris Morgan
The Indiedroid Nova is a Rockchip RK3588S based SBC from Indiedroid.
Specifications:
Rockchip RK3588S SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
Optional eMMC
2x USB 2.0, 2x USB 3.0, 1x USB 3.0 C port with DP Alt
1x MIPI-CSI Port (4-lane or 2x 2-lane)
1x MIPI-DSI 4-lane connector
1x Micro HDMI 2.1 output, 1x DP 1.4 output
Gigabit Ethernet
Realtek RTL8821CS WiFi
4 pin debug UART connector
40 pin GPIO header
Size: 85mm x 56mm (Raspberry Pi Form Factor)
Kernel commit:
3900160e164b ("arm64: dts: rockchip: Add Indiedroid Nova board")
Signed-off-by: Chris Morgan
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes since V2:
- Corrected typo in the MAINTAINERS file.
- Removed OF_UPSTREAM since it is now defined for all RK3588 boards.
Changes since V1:
- Refactored to use the upstream Linux device tree now that that is
an option.
- Added board to doc/board/rockchip/rockchip.rst.
---
arch/arm/mach-rockchip/rk3588/Kconfig | 10
board/indiedroid/nova/Kconfig | 12 +
board/indiedroid/nova/MAINTAINERS | 6 +++
configs/nova-rk3588s_defconfig| 69 +++
doc/board/rockchip/rockchip.rst | 1 +
include/configs/nova-rk3588s.h| 15 ++
6 files changed, 113 insertions(+)
create mode 100644 board/indiedroid/nova/Kconfig
create mode 100644 board/indiedroid/nova/MAINTAINERS
create mode 100644 configs/nova-rk3588s_defconfig
create mode 100644 include/configs/nova-rk3588s.h
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig
b/arch/arm/mach-rockchip/rk3588/Kconfig
index 39049ab35a..820e979abb 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -78,6 +78,15 @@ config TARGET_NANOPCT6_RK3588
Power: 5.5*2.1mm DC Jack, 12VDC input
Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case)
+config TARGET_NOVA_RK3588
+ bool "Indiedroid Nova RK3588"
+ select BOARD_LATE_INIT
+ help
+ Indiedroid Nova is a Rockchip RK3588s based SBC by Indiedroid.
+ It comes in configurations from 4GB of RAM to 16GB of RAM,
+ includes socket for eMMC storage, an SDMMC slot, and a 40-pin
+ GPIO header for expansion.
+
config TARGET_RK3588_NEU6
bool "Edgeble Neural Compute Module 6(Neu6) SoM"
select BOARD_LATE_INIT
@@ -223,6 +232,7 @@ config TEXT_BASE
source "board/edgeble/neural-compute-module-6/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
+source "board/indiedroid/nova/Kconfig"
source "board/pine64/quartzpro64-rk3588/Kconfig"
source "board/turing/turing-rk1-rk3588/Kconfig"
source "board/radxa/rock5a-rk3588s/Kconfig"
diff --git a/board/indiedroid/nova/Kconfig b/board/indiedroid/nova/Kconfig
new file mode 100644
index 00..271d15a0ed
--- /dev/null
+++ b/board/indiedroid/nova/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NOVA_RK3588
+
+config SYS_BOARD
+ default "nova-rk3588s"
+
+config SYS_VENDOR
+ default "indiedroid"
+
+config SYS_CONFIG_NAME
+ default "nova-rk3588s"
+
+endif
diff --git a/board/indiedroid/nova/MAINTAINERS
b/board/indiedroid/nova/MAINTAINERS
new file mode 100644
index 00..db40adf9ad
--- /dev/null
+++ b/board/indiedroid/nova/MAINTAINERS
@@ -0,0 +1,6 @@
+INDIEDROID-NOVA-RK3588
+M: Chris Morgan
+S: Maintained
+F: board/indiedroid/nova
+F: include/configs/nova-rk3588s.h
+F: configs/indiedroid-nova-rk3588s_defconfig
diff --git a/configs/nova-rk3588s_defconfig b/configs/nova-rk3588s_defconfig
new file mode 100644
index 00..a2e2440359
--- /dev/null
+++ b/configs/nova-rk3588s_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-indiedroid-nova"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_NOVA_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB5
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-indiedroid-nova.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names in
Re: [PATCH V4] board: rockchip: add Powkiddy X55
On 2024/5/21 23:25, Chris Morgan wrote:
From: Chris Morgan
The Powkiddy X55 is a Rockchip RK3566 based handheld gaming device.
UART, ADC, eMMC, and SDMMC are tested to work in U-Boot and this
successfully boots mainline Linux.
Kernel commit:
e99adc97e21a ("arm64: dts: rockchip: Add Powkiddy X55")
Signed-off-by: Chris Morgan
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes since V3:
- Removed sdmmc1 from the SPL-> U-Boot path, as long as we have sdmmc0
we should be okay with recovery options.
- Removed OF_UPSTREAM since that's now set across the board for
RK3568 devices.
Changes since V2:
- Refactored to use the upstream device tree from Linux.
- Removed logic for handling the adc button and instead simply try to
boot from sdmmc0 as a valid target first.
---
arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi | 9 +++
arch/arm/mach-rockchip/rk3568/Kconfig| 6 ++
board/powkiddy/x55/Kconfig | 15 +
board/powkiddy/x55/MAINTAINERS | 7 +++
board/powkiddy/x55/Makefile | 6 ++
board/powkiddy/x55/x55.c | 39 +
configs/powkiddy-x55-rk3566_defconfig| 58
doc/board/rockchip/rockchip.rst | 1 +
include/configs/powkiddy-x55-rk3566.h| 12
9 files changed, 153 insertions(+)
create mode 100644 arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
create mode 100644 board/powkiddy/x55/Kconfig
create mode 100644 board/powkiddy/x55/MAINTAINERS
create mode 100644 board/powkiddy/x55/Makefile
create mode 100644 board/powkiddy/x55/x55.c
create mode 100644 configs/powkiddy-x55-rk3566_defconfig
create mode 100644 include/configs/powkiddy-x55-rk3566.h
diff --git a/arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
b/arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
new file mode 100644
index 00..eadd3510fb
--- /dev/null
+++ b/arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = &sdmmc0, &sdhci;
+ };
+};
diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig
b/arch/arm/mach-rockchip/rk3568/Kconfig
index af537d912a..014ebf9f0b 100644
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -22,6 +22,11 @@ config TARGET_ODROID_M1_RK3568
help
Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC.
+config TARGET_POWKIDDY_X55_RK3566
+ bool "Powkiddy X55"
+ help
+ Powkiddy X55 handheld gaming console with an RK3566 SoC.
+
config TARGET_QUARTZ64_RK3566
bool "Pine64 Quartz64"
help
@@ -48,5 +53,6 @@ source "board/rockchip/evb_rk3568/Kconfig"
source "board/anbernic/rgxx3_rk3566/Kconfig"
source "board/hardkernel/odroid_m1/Kconfig"
source "board/pine64/quartz64_rk3566/Kconfig"
+source "board/powkiddy/x55/Kconfig"
endif
diff --git a/board/powkiddy/x55/Kconfig b/board/powkiddy/x55/Kconfig
new file mode 100644
index 00..a7b3ed4d0d
--- /dev/null
+++ b/board/powkiddy/x55/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_POWKIDDY_X55_RK3566
+
+config SYS_BOARD
+ default "x55"
+
+config SYS_VENDOR
+ default "powkiddy"
+
+config SYS_CONFIG_NAME
+ default "powkiddy-x55-rk3566"
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+
+endif
diff --git a/board/powkiddy/x55/MAINTAINERS b/board/powkiddy/x55/MAINTAINERS
new file mode 100644
index 00..01ae8da19d
--- /dev/null
+++ b/board/powkiddy/x55/MAINTAINERS
@@ -0,0 +1,7 @@
+X55
+M: Chris Morgan
+S: Maintained
+F: board/powkiddy/x55
+F: include/configs/powkiddy-x55-rk3566.h
+F: configs/powkiddy-x55-rk3566_defconfig
+F: arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
diff --git a/board/powkiddy/x55/Makefile b/board/powkiddy/x55/Makefile
new file mode 100644
index 00..55c8c16aa1
--- /dev/null
+++ b/board/powkiddy/x55/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2023 Chris Morgan
+#
+
+obj-y += x55.o
diff --git a/board/powkiddy/x55/x55.c b/board/powkiddy/x55/x55.c
new file mode 100644
index 00..b2703e6382
--- /dev/null
+++ b/board/powkiddy/x55/x55.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Chris Morgan
+ */
+
+#include
+
+#define GPIO4_BASE 0xfe77
+#define GPIO_SWPORT_DR_L 0x
+#define GPIO_SWPORT_DDR_L 0x0008
+#define GPIO_B4BIT(12)
+#define GPIO_B5BIT(13)
+#define GPIO_B6BIT(14)
+
+#define GPIO_WRITEMASK(bits) ((bits) << 16)
+
+/*
+ * Start LED very early so user knows device is on. Set color
+ * to red.
+ */
+void spl_board_init(void)
+{
+ /* Set GPIO4_B4, G
Re: [PATCH v2] rockchip: rv1126: Migrate to OF_UPSTREAM
On 2024/5/10 12:43, Anand Moon wrote:
Migrate RV1126 boards that exists in Linux v6.8 to use OF_UPSTREAM.
Following targets is migrated to use OF_UPSTREAM:
- rv1126-edgeble-neu2 : Board is an industrial form factor
IO board.
- sonoff-ihost-rv1126 : Gateway device designed to provide a
Smart Home Hub.
Cc: Tim Lunn
Cc: Jagan Teki
Signed-off-by: Anand Moon
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: remove the dt-bindings for clock and power
fix the typo in commit message
Tested on neu2 board.
---
arch/arm/dts/Makefile | 3 -
arch/arm/dts/rv1126-edgeble-neu2-io.dts | 112
arch/arm/dts/rv1126-edgeble-neu2.dtsi | 345 --
arch/arm/dts/rv1126-pinctrl.dtsi | 341 --
arch/arm/dts/rv1126-sonoff-ihost.dts | 29 -
arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404 ---
arch/arm/dts/rv1126.dtsi | 623 -
arch/arm/mach-rockchip/Kconfig| 1 +
configs/neu2-io-rv1126_defconfig | 2 +-
configs/sonoff-ihost-rv1126_defconfig | 2 +-
.../dt-bindings/clock/rockchip,rv1126-cru.h | 632 --
.../dt-bindings/power/rockchip,rv1126-power.h | 35 -
12 files changed, 3 insertions(+), 2526 deletions(-)
delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2-io.dts
delete mode 100644 arch/arm/dts/rv1126-edgeble-neu2.dtsi
delete mode 100644 arch/arm/dts/rv1126-pinctrl.dtsi
delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts
delete mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi
delete mode 100644 arch/arm/dts/rv1126.dtsi
delete mode 100644 include/dt-bindings/clock/rockchip,rv1126-cru.h
delete mode 100644 include/dt-bindings/power/rockchip,rv1126-power.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 087645f354..79fc100dce 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -97,9 +97,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
-dtb-$(CONFIG_ROCKCHIP_RV1126) += \
- rv1126-edgeble-neu2-io.dtb
-
dtb-$(CONFIG_ARCH_S5P4418) += \
s5p4418-nanopi2.dtb
diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
deleted file mode 100644
index 0c2396b8f8..00
--- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/dts-v1/;
-#include "rv1126.dtsi"
-#include "rv1126-edgeble-neu2.dtsi"
-
-/ {
- model = "Edgeble Neu2 IO Board";
- compatible = "edgeble,neural-compute-module-2-io",
-"edgeble,neural-compute-module-2", "rockchip,rv1126";
-
- aliases {
- serial2 = &uart2;
- };
-
- chosen {
- stdout-path = "serial2:150n8";
- };
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1200>;
- regulator-max-microvolt = <1200>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- v3v3_sys: v3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "v3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <330>;
- regulator-max-microvolt = <330>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
-&gmac {
- assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
- <&cru CLK_GMAC_ETHERNET_OUT>;
- assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
- assigned-clock-rates = <12500>, <0>, <2500>;
- clock_in_out = "input";
- phy-handle = <&phy>;
- phy-mode = "rgmii";
- phy-supply = <&vcc_3v3>;
- pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4
&clk_out_ethernetm1_pins>;
-
Re: [PATCH 41/81] misc: Remove and add needed includes
On 2024/5/2 09:30, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Tom Rini Cc: Simon Glass Cc: Sean Anderson Cc: Eugen Hristev Cc: Mario Six Cc: Philipp Tomsich Cc: Kever Yang Cc: Michael Walle Cc: Patrick Delaunay Cc: Patrice Chotard Cc: Thierry Reding Cc: Svyatoslav Ryhel Cc: Liviu Dudau Cc: "Michał Barnaś" Cc: Bin Meng Cc: Dan Carpenter Cc: "Milan P. Stanić" Cc: Neha Malcom Francis Cc: Nishanth Menon Cc: Marek Vasut Cc: Michel Alex Cc: Stefano Babic Cc: Peng Fan Cc: Igor Opaniuk Cc: Clement Faure Cc: Mathieu Othacehe Cc: Ye Li Cc: Jim Liu Cc: Heinrich Schuchardt Cc: Ilias Apalodimas Cc: Tim Lunn Cc: "Marek Behún" Cc: Stefan Roese --- drivers/misc/altera_sysid.c | 1 - drivers/misc/atsha204a-i2c.c | 1 - drivers/misc/cbmem_console.c | 2 +- drivers/misc/cros_ec.c | 2 +- drivers/misc/cros_ec_i2c.c | 1 - drivers/misc/cros_ec_lpc.c | 2 +- drivers/misc/cros_ec_sandbox.c | 2 +- drivers/misc/cros_ec_spi.c | 2 +- drivers/misc/ds4510.c| 1 - drivers/misc/esm_pmic.c | 1 - drivers/misc/fs_loader.c | 1 - drivers/misc/fsl_devdis.c| 2 +- drivers/misc/fsl_ifc.c | 2 +- drivers/misc/fsl_iim.c | 1 - drivers/misc/fsl_portals.c | 2 +- drivers/misc/fsl_sec_mon.c | 2 +- drivers/misc/gdsys_ioep.c| 1 - drivers/misc/gdsys_rxaui_ctrl.c | 1 - drivers/misc/gdsys_soc.c | 1 - drivers/misc/gpio_led.c | 1 - drivers/misc/i2c_eeprom.c| 1 - drivers/misc/i2c_eeprom_emul.c | 1 - drivers/misc/ihs_fpga.c | 1 - drivers/misc/imx8/fuse.c | 1 - drivers/misc/imx8/scu.c | 1 - drivers/misc/imx8/scu_api.c | 1 - drivers/misc/imx_ele/ele_api.c | 1 - drivers/misc/imx_ele/ele_mu.c| 1 - drivers/misc/imx_ele/fuse.c | 1 - drivers/misc/irq-uclass.c| 1 - drivers/misc/irq_sandbox.c | 1 - drivers/misc/irq_sandbox_test.c | 1 - drivers/misc/jz4780_efuse.c | 1 - drivers/misc/k3_avs.c| 1 - drivers/misc/k3_esm.c| 1 - drivers/misc/ls2_sfp.c | 1 - drivers/misc/microchip_flexcom.c | 1 - drivers/misc/misc-uclass.c | 1 - drivers/misc/misc_sandbox.c | 1 - drivers/misc/mpc83xx_serdes.c| 1 - drivers/misc/mxc_ocotp.c | 1 - drivers/misc/mxs_ocotp.c | 1 - drivers/misc/npcm_host_intf.c| 1 - drivers/misc/npcm_otp.c | 1 - drivers/misc/nuvoton_nct6102d.c | 1 - drivers/misc/nvmem.c | 1 - drivers/misc/p2sb-uclass.c | 1 - drivers/misc/p2sb_emul.c | 1 - drivers/misc/p2sb_sandbox.c | 1 - drivers/misc/pca9551_led.c | 1 - drivers/misc/pwrseq-uclass.c | 1 - drivers/misc/qfw.c | 1 - drivers/misc/rockchip-efuse.c| 1 - drivers/misc/rockchip-otp.c | 1 - drivers/misc/sandbox_adder.c | 1 - drivers/misc/sifive-otp.c| 1 - drivers/misc/sl28cpld.c | 1 - drivers/misc/smsc_lpc47m.c | 1 - drivers/misc/smsc_sio1007.c | 1 - drivers/misc/spltest_sandbox.c | 1 - drivers/misc/status_led.c| 2 +- drivers/misc/stm32_rcc.c | 1 - drivers/misc/stm32mp_fuse.c | 1 - drivers/misc/swap_case.c | 1 - drivers/misc/syscon_sandbox.c| 1 - drivers/misc/tegra186_bpmp.c | 1 - drivers/misc/tegra_car.c | 1 - drivers/misc/test_drv.c | 1 - drivers/misc/turris_omnia_mcu.c | 1 - drivers/misc/usb251xb.c | 1 - drivers/misc/vexpress_config.c | 1 - drivers/misc/winbond_w83627.c| 1 - 72 files changed, 10 insertions(+), 72 deletions(-) diff --git a/drivers/misc/altera_sysid.c b/drivers/misc/altera_sysid.c index 878df12771c8..21e64fa3e6fe 100644 --- a/drivers/misc/altera_sysid.c +++ b/drivers/misc/altera_sysid.c @@ -4,7 +4,6 @@ * Scott McNutt */ -#include #include #include #include diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c index 707daa90bdba..3b9046da880c 100644 --- a/drivers/misc/atsha204a-i2c.c +++ b/drivers/misc/atsha204a-i2c.c @@ -10,7 +10,6 @@ * published by the Free Software Foundation. */ -#include #include #include #include diff --git a/drivers/misc/cbmem_console.c b/drivers/misc/cbmem_console.c index ba3a599c4a51..8220addd579b 100644 --- a/drivers/misc/cbmem_console.c +++ b/drivers/misc/cbmem_console.c @@ -3,8 +3,8 @@ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. */ -#include #include +#include #include void cbmemc_putc(struct stdio_dev *dev, char data) diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index 9c1e6a5e3e70..fabe4964a334 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -15,7 +15,
Re: [PATCH] rockchip: rv1108: Remove unneeded local rv1108-cru.h
On 2024/5/10 00:42, Fabio Estevam wrote: After the conversion of RV1108 to OF_UPSTREAM, include/dt-bindings/clock/rv1108-cru.h is no longer needed because there is dts/upstream/include/dt-bindings/clock/rv1108-cru.h from upstream Linux. Remove the unneeded rv1108-cru.h file. Reported-by: Jonas Karlman Signed-off-by: Fabio Estevam Reviewed-by: Kever Yang Thanks, - Kever --- include/dt-bindings/clock/rv1108-cru.h | 356 - 1 file changed, 356 deletions(-) delete mode 100644 include/dt-bindings/clock/rv1108-cru.h diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h deleted file mode 100644 index 10ed9d140f4b.. --- a/include/dt-bindings/clock/rv1108-cru.h +++ /dev/null @@ -1,356 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2017 Rockchip Electronics Co. Ltd. - * Author: Shawn Lin - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H - -/* pll id */ -#define PLL_APLL 0 -#define PLL_DPLL 1 -#define PLL_GPLL 2 -#define ARMCLK 3 - -/* sclk gates (special clocks) */ -#define SCLK_SPI0 65 -#define SCLK_NANDC 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_UART0 72 -#define SCLK_UART1 73 -#define SCLK_UART2 74 -#define SCLK_I2S0 75 -#define SCLK_I2S1 76 -#define SCLK_I2S2 77 -#define SCLK_TIMER078 -#define SCLK_TIMER179 -#define SCLK_SFC 80 -#define SCLK_SDMMC_DRV 81 -#define SCLK_SDIO_DRV 82 -#define SCLK_EMMC_DRV 83 -#define SCLK_SDMMC_SAMPLE 84 -#define SCLK_SDIO_SAMPLE 85 -#define SCLK_EMMC_SAMPLE 86 -#define SCLK_VENC_CORE 87 -#define SCLK_HEVC_CORE 88 -#define SCLK_HEVC_CABAC89 -#define SCLK_PWM0_PMU 90 -#define SCLK_I2C0_PMU 91 -#define SCLK_WIFI 92 -#define SCLK_CIFOUT93 -#define SCLK_MIPI_CSI_OUT 94 -#define SCLK_CIF0 95 -#define SCLK_CIF1 96 -#define SCLK_CIF2 97 -#define SCLK_CIF3 98 -#define SCLK_DSP 99 -#define SCLK_DSP_IOP 100 -#define SCLK_DSP_EPP 101 -#define SCLK_DSP_EDP 102 -#define SCLK_DSP_EDAP 103 -#define SCLK_CVBS_HOST 104 -#define SCLK_HDMI_SFR 105 -#define SCLK_HDMI_CEC 106 -#define SCLK_CRYPTO107 -#define SCLK_SPI 108 -#define SCLK_SARADC109 -#define SCLK_TSADC 110 -#define SCLK_MAC_PRE 111 -#define SCLK_MAC 112 -#define SCLK_MAC_RX113 -#define SCLK_MAC_REF 114 -#define SCLK_MAC_REFOUT115 -#define SCLK_DSP_PFM 116 -#define SCLK_RGA 117 -#define SCLK_I2C1 118 -#define SCLK_I2C2 119 -#define SCLK_I2C3 120 -#define SCLK_PWM 121 -#define SCLK_ISP 122 -#define SCLK_USBPHY123 -#define SCLK_I2S0_SRC 124 -#define SCLK_I2S1_SRC 125 -#define SCLK_I2S2_SRC 126 -#define SCLK_UART0_SRC 127 -#define SCLK_UART1_SRC 128 -#define SCLK_UART2_SRC 129 -#define SCLK_MAC_TX130 -#define SCLK_MACREF131 -#define SCLK_MACREF_OUT132 - -#define DCLK_VOP_SRC 185 -#define DCLK_HDMIPHY 186 -#define DCLK_VOP 187 - -/* aclk gates */ -#define ACLK_DMAC 192 -#define ACLK_PRE 193 -#define ACLK_CORE 194 -#define ACLK_ENMCORE 195 -#define ACLK_RKVENC196 -#define ACLK_RKVDEC197 -#define ACLK_VPU 198 -#define ACLK_CIF0 199 -#define ACLK_VIO0 200 -#define ACLK_VIO1 201 -#define ACLK_VOP 202 -#define ACLK_IEP 203 -#define ACLK_RGA 204 -#define ACLK_ISP 205 -#define ACLK_CIF1 206 -#define ACLK_CIF2 207 -#define ACLK_CIF3
Re: [PATCH 74/81] video: Remove and add needed includes
On 2024/5/2 09:31, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Anatolij Gustschin Cc: Tom Rini Cc: Matthias Brugger Cc: Peter Robinson Cc: Liviu Dudau Cc: Stephan Gerhold Cc: Linus Walleij Cc: Neil Armstrong Cc: Stefan Bosch Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Michal Simek Cc: Patrick Delaunay Cc: Patrice Chotard Cc: Jagan Teki Cc: Andre Przywara Cc: Thierry Reding Cc: Svyatoslav Ryhel Cc: Johan Jonker --- drivers/video/anx9804.c | 1 - drivers/video/atmel_hlcdfb.c| 1 - drivers/video/atmel_lcdfb.c | 1 - drivers/video/backlight-uclass.c| 1 - drivers/video/backlight_gpio.c | 1 - drivers/video/bcm2835.c | 1 - drivers/video/bmp.c | 1 - drivers/video/bochs.c | 1 - drivers/video/bridge/anx6345.c | 1 - drivers/video/bridge/ps862x.c | 1 - drivers/video/bridge/ptn3460.c | 1 - drivers/video/bridge/ssd2825.c | 1 - drivers/video/bridge/video-bridge-uclass.c | 1 - drivers/video/broadwell_igd.c | 2 +- drivers/video/console_normal.c | 1 - drivers/video/console_rotate.c | 1 - drivers/video/console_truetype.c| 1 - drivers/video/coreboot.c| 1 - drivers/video/display-uclass.c | 1 - drivers/video/dsi-host-uclass.c | 1 - drivers/video/dw_hdmi.c | 3 ++- drivers/video/dw_mipi_dsi.c | 1 - drivers/video/efi.c | 1 - drivers/video/endeavoru-panel.c | 1 - drivers/video/exynos/exynos_dp.c| 1 - drivers/video/exynos/exynos_dp_lowlevel.c | 1 - drivers/video/exynos/exynos_fb.c| 1 - drivers/video/exynos/exynos_mipi_dsi.c | 1 - drivers/video/exynos/exynos_mipi_dsi_common.c | 1 - drivers/video/exynos/exynos_mipi_dsi_lowlevel.c | 1 - drivers/video/himax-hx8394.c| 1 - drivers/video/hitachi_tx18d42vm_lcd.c | 1 - drivers/video/hx8238d.c | 1 - drivers/video/ihs_video_out.c | 1 - drivers/video/imx/ipu_common.c | 2 +- drivers/video/imx/ipu_disp.c| 1 - drivers/video/imx/mxc_ipuv3_fb.c| 1 - drivers/video/ivybridge_igd.c | 1 - drivers/video/lm3533_backlight.c| 1 - drivers/video/logicore_dp_tx.c | 1 - drivers/video/mali_dp.c | 1 - drivers/video/mcde_simple.c | 1 - drivers/video/meson/meson_canvas.c | 1 - drivers/video/meson/meson_dw_hdmi.c | 1 - drivers/video/meson/meson_plane.c | 1 - drivers/video/meson/meson_vclk.c| 1 - drivers/video/meson/meson_venc.c| 1 - drivers/video/meson/meson_vpu.c | 1 - drivers/video/meson/meson_vpu_init.c| 1 - drivers/video/mipi_dsi.c| 1 - drivers/video/mvebu_lcd.c | 1 - drivers/video/mxsfb.c | 1 - drivers/video/nexell/s5pxx18_dp.c | 1 - drivers/video/nexell/s5pxx18_dp_hdmi.c | 1 - drivers/video/nexell/s5pxx18_dp_lvds.c | 2 +- drivers/video/nexell/s5pxx18_dp_mipi.c | 1 - drivers/video/nexell/s5pxx18_dp_rgb.c | 2 +- drivers/video/nexell/soc/s5pxx18_soc_disptop.h | 1 + drivers/video/nexell_display.c | 1 - drivers/video/omap3_dss.c | 1 - drivers/video/orisetech_otm8009a.c | 1 - drivers/video/panel-uclass.c| 1 - drivers/video/pwm_backlight.c | 1 - drivers/video/raydium-rm68200.c | 1 - drivers/video/renesas-r61307.c | 1 - drivers/video/renesas-r69328.c | 1 - drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 1 - drivers/video/rockchip/rk3288_hdmi.c| 1 - drivers/video/rockchip/rk3288_mipi.c| 1 - drivers/video/rockchip/rk3288_vop.c | 1 - drivers/video/rockchip/rk3399_hdmi.c| 1 - drivers/video/rockchip/rk3399_mipi.c| 1 - drivers/video/rockchip/rk3399_vop.c | 1 - drivers/video/rockchip/rk_edp.c | 1 - drivers/video/rockchip/rk_hdmi.c| 1 - drivers/video/rockchip/rk_lvds.c| 1 - drivers/video/rockchip/rk_mipi.c| 1 - drivers/video/rockchip/rk_vop.c | 1 - drivers/video/sandbox_dsi_host.c
Re: [PATCH 70/81] timer: Remove and add needed includes
On 2024/5/2 09:31, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Tom Rini Cc: Rick Chen Cc: Leo Cc: Patrice Chotard Cc: Eugen Hristev Cc: Michal Simek Cc: Mario Six Cc: Ryder Lee Cc: Weijie Gao Cc: Chunfeng Yun Cc: GSS_MTK_Uboot_upstream Cc: Stephan Gerhold Cc: Linus Walleij Cc: Marek Vasut Cc: Patrick Delaunay Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Thierry Reding Cc: Svyatoslav Ryhel Cc: Sean Anderson Cc: Johan Jonker Cc: Chanho Park Cc: Torsten Duwe Cc: Kuan Lim Lee Cc: Wei Liang Lim Cc: Alex Bee --- drivers/timer/altera_timer.c | 1 - drivers/timer/andes_plmt_timer.c | 1 - drivers/timer/arc_timer.c | 1 - drivers/timer/arm_global_timer.c | 2 +- drivers/timer/arm_twd_timer.c | 1 - drivers/timer/ast_timer.c | 1 - drivers/timer/atmel_pit_timer.c| 1 - drivers/timer/atmel_tcb_timer.c| 1 - drivers/timer/cadence-ttc.c| 1 - drivers/timer/dw-apb-timer.c | 1 - drivers/timer/fttmr010_timer.c | 1 - drivers/timer/imx-gpt-timer.c | 2 +- drivers/timer/mchp-pit64b-timer.c | 1 - drivers/timer/mpc83xx_timer.c | 2 +- drivers/timer/mtk_timer.c | 1 - drivers/timer/nomadik-mtu-timer.c | 1 - drivers/timer/npcm-timer.c | 1 - drivers/timer/omap-timer.c | 1 - drivers/timer/orion-timer.c| 2 +- drivers/timer/ostm_timer.c | 1 - drivers/timer/riscv_aclint_timer.c | 2 +- drivers/timer/riscv_timer.c| 2 +- drivers/timer/rockchip_timer.c | 1 - drivers/timer/sandbox_timer.c | 1 - drivers/timer/sp804_timer.c| 1 - drivers/timer/starfive-timer.c | 1 - drivers/timer/stm32_timer.c| 2 +- drivers/timer/tegra-timer.c| 1 - drivers/timer/timer-uclass.c | 1 - drivers/timer/tsc_timer.c | 1 - drivers/timer/xilinx-timer.c | 1 - 31 files changed, 7 insertions(+), 31 deletions(-) diff --git a/drivers/timer/altera_timer.c b/drivers/timer/altera_timer.c index 040dc65f48aa..ece246c23d2f 100644 --- a/drivers/timer/altera_timer.c +++ b/drivers/timer/altera_timer.c @@ -7,7 +7,6 @@ * Scott McNutt */ -#include #include #include #include diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c index 42dd4b623176..20baaf61307a 100644 --- a/drivers/timer/andes_plmt_timer.c +++ b/drivers/timer/andes_plmt_timer.c @@ -8,7 +8,6 @@ * associated with timer tick. */ -#include #include #include #include diff --git a/drivers/timer/arc_timer.c b/drivers/timer/arc_timer.c index 497f8a04155f..413bcc32f01b 100644 --- a/drivers/timer/arc_timer.c +++ b/drivers/timer/arc_timer.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Synopsys, Inc. All rights reserved. */ -#include #include #include #include diff --git a/drivers/timer/arm_global_timer.c b/drivers/timer/arm_global_timer.c index 2e50d9fbc580..b8057929f997 100644 --- a/drivers/timer/arm_global_timer.c +++ b/drivers/timer/arm_global_timer.c @@ -6,7 +6,7 @@ * ARM Cortext A9 global timer driver */ -#include +#include #include #include #include diff --git a/drivers/timer/arm_twd_timer.c b/drivers/timer/arm_twd_timer.c index 40ccd1658749..2b2f35911738 100644 --- a/drivers/timer/arm_twd_timer.c +++ b/drivers/timer/arm_twd_timer.c @@ -27,7 +27,6 @@ * Alex Zuepke */ -#include #include #include #include diff --git a/drivers/timer/ast_timer.c b/drivers/timer/ast_timer.c index 78adc96cc596..6601cab7b165 100644 --- a/drivers/timer/ast_timer.c +++ b/drivers/timer/ast_timer.c @@ -3,7 +3,6 @@ * Copyright 2016 Google Inc. */ -#include #include #include #include diff --git a/drivers/timer/atmel_pit_timer.c b/drivers/timer/atmel_pit_timer.c index 5cf46f224ab0..0a367a5a7f4a 100644 --- a/drivers/timer/atmel_pit_timer.c +++ b/drivers/timer/atmel_pit_timer.c @@ -4,7 +4,6 @@ * Wenyou.Yang */ -#include #include #include #include diff --git a/drivers/timer/atmel_tcb_timer.c b/drivers/timer/atmel_tcb_timer.c index 8c17987c7d74..3a328b2f6c72 100644 --- a/drivers/timer/atmel_tcb_timer.c +++ b/drivers/timer/atmel_tcb_timer.c @@ -5,7 +5,6 @@ * Author: Clément Léger */ -#include #include #include #include diff --git a/drivers/timer/cadence-ttc.c b/drivers/timer/cadence-ttc.c index 2eff45060ad6..3cffb1bb88db 100644 --- a/drivers/timer/cadence-ttc.c +++ b/drivers/timer/cadence-ttc.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Xilinx, Inc. (Michal Simek) */ -#include #include #include #include diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c index 0607f751ca70..77ccb98cb8df 100644 --- a/drivers/timer/dw-apb-timer.c +++ b/drivers/timer/dw-apb-timer.c @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut
Re: [PATCH 68/81] sysreset: Remove and add needed includes
On 2024/5/2 09:31, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Tom Rini Cc: Michal Simek Cc: Mario Six Cc: Weijie Gao Cc: GSS_MTK_Uboot_upstream Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Rick Chen Cc: Leo Cc: Marek Vasut Cc: Simon Goldschmidt Cc: Tien Fong Chee Cc: Patrice Chotard Cc: Max Filippov Cc: Paul Barker Cc: Bin Meng --- drivers/sysreset/poweroff_gpio.c | 1 - drivers/sysreset/sysreset-ti-sci.c| 1 - drivers/sysreset/sysreset-uclass.c| 1 - drivers/sysreset/sysreset_ast.c | 1 - drivers/sysreset/sysreset_at91.c | 1 - drivers/sysreset/sysreset_gpio.c | 1 - drivers/sysreset/sysreset_microblaze.c| 1 - drivers/sysreset/sysreset_mpc83xx.c | 1 - drivers/sysreset/sysreset_octeon.c| 1 - drivers/sysreset/sysreset_psci.c | 1 - drivers/sysreset/sysreset_resetctl.c | 1 - drivers/sysreset/sysreset_rockchip.c | 1 - drivers/sysreset/sysreset_sandbox.c | 1 - drivers/sysreset/sysreset_sbi.c | 1 - drivers/sysreset/sysreset_socfpga.c | 1 - drivers/sysreset/sysreset_socfpga_soc64.c | 1 - drivers/sysreset/sysreset_sti.c | 1 - drivers/sysreset/sysreset_syscon.c| 1 - drivers/sysreset/sysreset_watchdog.c | 1 - drivers/sysreset/sysreset_x86.c | 1 - drivers/sysreset/sysreset_xtfpga.c| 2 +- 21 files changed, 1 insertion(+), 21 deletions(-) diff --git a/drivers/sysreset/poweroff_gpio.c b/drivers/sysreset/poweroff_gpio.c index ad04e4b1a85e..d9220024f470 100644 --- a/drivers/sysreset/poweroff_gpio.c +++ b/drivers/sysreset/poweroff_gpio.c @@ -11,7 +11,6 @@ * Copyright (C) 2012 Jamie Lentin */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset-ti-sci.c b/drivers/sysreset/sysreset-ti-sci.c index 0de132633a8d..451fc5de7357 100644 --- a/drivers/sysreset/sysreset-ti-sci.c +++ b/drivers/sysreset/sysreset-ti-sci.c @@ -6,7 +6,6 @@ *Andreas Dannenberg */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c index 6151b5fe03e4..0abb4042e0f2 100644 --- a/drivers/sysreset/sysreset-uclass.c +++ b/drivers/sysreset/sysreset-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_SYSRESET -#include #include #include #include diff --git a/drivers/sysreset/sysreset_ast.c b/drivers/sysreset/sysreset_ast.c index 92fad96871bd..ef09440bbeff 100644 --- a/drivers/sysreset/sysreset_ast.c +++ b/drivers/sysreset/sysreset_ast.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Google, Inc */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_at91.c b/drivers/sysreset/sysreset_at91.c index fc85f31ebf01..457042c7aae9 100644 --- a/drivers/sysreset/sysreset_at91.c +++ b/drivers/sysreset/sysreset_at91.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/sysreset/sysreset_gpio.c b/drivers/sysreset/sysreset_gpio.c index de42b5935424..47018844a51a 100644 --- a/drivers/sysreset/sysreset_gpio.c +++ b/drivers/sysreset/sysreset_gpio.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Xilinx, Inc. - Michal Simek */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_microblaze.c b/drivers/sysreset/sysreset_microblaze.c index 83a7f77ac41f..b81d82f046bd 100644 --- a/drivers/sysreset/sysreset_microblaze.c +++ b/drivers/sysreset/sysreset_microblaze.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Xilinx, Inc. - Michal Simek */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_mpc83xx.c b/drivers/sysreset/sysreset_mpc83xx.c index ca48328f7b58..dca49299f777 100644 --- a/drivers/sysreset/sysreset_mpc83xx.c +++ b/drivers/sysreset/sysreset_mpc83xx.c @@ -4,7 +4,6 @@ * Mario Six, Guntermann & Drunck GmbH, mario@gdsys.cc */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_octeon.c b/drivers/sysreset/sysreset_octeon.c index ebdea6ab66ed..c16223720e5a 100644 --- a/drivers/sysreset/sysreset_octeon.c +++ b/drivers/sysreset/sysreset_octeon.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Stefan Roese */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_psci.c b/drivers/sysreset/sysreset_psci.c index aa09d0b88271..89b4f2dcaec4 100644 --- a/drivers/sysreset/sysreset_psci.c +++ b/drivers/sysreset/sysreset_psci.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Masahiro Yamada */ -#include #include #include #include diff --git a/drivers/sysreset/sysreset_resetctl.c b/drivers/sysreset/sysreset_resetctl.c index 25bd5c9a7ff2..fbe3999b9605 100644 --- a/drivers/sysreset/sysreset_resetctl.c +++ b/drivers/sysr
Re: [PATCH 64/81] sound: Remove and add needed includes
On 2024/5/2 09:31, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Tom Rini Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Thierry Reding Cc: Svyatoslav Ryhel --- drivers/sound/broadwell_i2s.c | 1 - drivers/sound/broadwell_sound.c | 1 - drivers/sound/codec-uclass.c| 1 - drivers/sound/da7219.c | 1 - drivers/sound/hda_codec.c | 1 - drivers/sound/i2s-uclass.c | 1 - drivers/sound/i8254_beep.c | 1 - drivers/sound/ivybridge_sound.c | 1 - drivers/sound/max98088.c| 1 - drivers/sound/max98090.c| 1 - drivers/sound/max98095.c| 1 - drivers/sound/max98357a.c | 1 - drivers/sound/maxim_codec.c | 1 - drivers/sound/rockchip_i2s.c| 1 - drivers/sound/rockchip_sound.c | 1 - drivers/sound/rt5677.c | 1 - drivers/sound/samsung-i2s.c | 2 +- drivers/sound/samsung_sound.c | 1 - drivers/sound/sandbox.c | 1 - drivers/sound/sound-uclass.c| 1 - drivers/sound/sound.c | 2 +- drivers/sound/tegra_ahub.c | 2 +- drivers/sound/tegra_i2s.c | 1 - drivers/sound/tegra_sound.c | 1 - drivers/sound/wm8994.c | 1 - 25 files changed, 3 insertions(+), 25 deletions(-) diff --git a/drivers/sound/broadwell_i2s.c b/drivers/sound/broadwell_i2s.c index 7f754e656761..bc44b5ec7e1f 100644 --- a/drivers/sound/broadwell_i2s.c +++ b/drivers/sound/broadwell_i2s.c @@ -9,7 +9,6 @@ #define LOG_CATEGORY UCLASS_I2S -#include #include #include #include diff --git a/drivers/sound/broadwell_sound.c b/drivers/sound/broadwell_sound.c index 6e083fe1f696..473f8d8f9771 100644 --- a/drivers/sound/broadwell_sound.c +++ b/drivers/sound/broadwell_sound.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_SOUND -#include #include #include #include diff --git a/drivers/sound/codec-uclass.c b/drivers/sound/codec-uclass.c index 2cb233bd3060..1c1560619ea5 100644 --- a/drivers/sound/codec-uclass.c +++ b/drivers/sound/codec-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_AUDIO_CODEC -#include #include #include diff --git a/drivers/sound/da7219.c b/drivers/sound/da7219.c index c1edef443608..5b9b3f65263f 100644 --- a/drivers/sound/da7219.c +++ b/drivers/sound/da7219.c @@ -6,7 +6,6 @@ * Parts taken from coreboot */ -#include #include #include #include diff --git a/drivers/sound/hda_codec.c b/drivers/sound/hda_codec.c index af6148ef7240..da8bde67de65 100644 --- a/drivers/sound/hda_codec.c +++ b/drivers/sound/hda_codec.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_SOUND -#include #include #include #include diff --git a/drivers/sound/i2s-uclass.c b/drivers/sound/i2s-uclass.c index fc4f686b516d..6263c4d70719 100644 --- a/drivers/sound/i2s-uclass.c +++ b/drivers/sound/i2s-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_I2S -#include #include #include diff --git a/drivers/sound/i8254_beep.c b/drivers/sound/i8254_beep.c index 5572dc4d265d..7234ad4a07e5 100644 --- a/drivers/sound/i8254_beep.c +++ b/drivers/sound/i8254_beep.c @@ -3,7 +3,6 @@ * Copyright 2018 Google LLC */ -#include #include #include #include diff --git a/drivers/sound/ivybridge_sound.c b/drivers/sound/ivybridge_sound.c index d982219e06de..aeeba1d267ec 100644 --- a/drivers/sound/ivybridge_sound.c +++ b/drivers/sound/ivybridge_sound.c @@ -12,7 +12,6 @@ #define LOG_CATEGORY UCLASS_SOUND -#include #include #include #include diff --git a/drivers/sound/max98088.c b/drivers/sound/max98088.c index c0463b8e8a62..d9037641ca46 100644 --- a/drivers/sound/max98088.c +++ b/drivers/sound/max98088.c @@ -8,7 +8,6 @@ * following the changes made in max98095.c */ -#include #include #include #include diff --git a/drivers/sound/max98090.c b/drivers/sound/max98090.c index a798762f1ee7..18a3ffa85c8e 100644 --- a/drivers/sound/max98090.c +++ b/drivers/sound/max98090.c @@ -5,7 +5,6 @@ * Copyright 2011 Maxim Integrated Products */ -#include #include #include #include diff --git a/drivers/sound/max98095.c b/drivers/sound/max98095.c index d0f701aaf105..96e772cff21b 100644 --- a/drivers/sound/max98095.c +++ b/drivers/sound/max98095.c @@ -7,7 +7,6 @@ * Modified for U-Boot by R. Chandrasekar (rcse...@samsung.com) */ -#include #include #include #include diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c index bdf6dc236ec3..da56ffdd6bb4 100644 --- a/drivers/sound/max98357a.c +++ b/drivers/sound/max98357a.c @@ -6,7 +6,6 @@ * Parts taken from coreboot */ -#include #include #include #include diff --git a/drivers/sound/maxim_codec.c b/drivers/sound/maxim_codec.c index 6553d9590472..98f094c0e9ad 100644 --- a/drivers/sound/maxim_codec.c +++ b/drivers/sound/maxim_codec.c @@ -5,7 +5,6
Re: [PATCH 57/81] reset: Remove and add needed includes
On 2024/5/2 09:31, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Ryan Chen Cc: Chia-Wei Wang Cc: Aspeed BMC SW team Cc: Joel Stanley Cc: Tom Rini Cc: Eugeniy Paltsev Cc: Ryder Lee Cc: Weijie Gao Cc: Chunfeng Yun Cc: GSS_MTK_Uboot_upstream Cc: Neil Armstrong Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Kunihiko Hayashi Cc: Dai Okamura Cc: Michal Simek Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Thierry Reding Cc: Svyatoslav Ryhel Cc: Yang Xiwen Cc: Sumit Garg Cc: Marek Vasut Cc: Eugen Hristev Cc: John Keeping Cc: Etienne Carriere Cc: AKASHI Takahiro --- drivers/reset/reset-ast2500.c | 1 - drivers/reset/reset-ast2600.c | 1 - drivers/reset/reset-bcm6345.c | 1 - drivers/reset/reset-dra7.c | 1 - drivers/reset/reset-hisilicon.c| 1 - drivers/reset/reset-hsdk.c | 1 - drivers/reset/reset-imx7.c | 1 - drivers/reset/reset-jh7110.c | 1 - drivers/reset/reset-mediatek.c | 1 - drivers/reset/reset-meson.c| 1 - drivers/reset/reset-mtmips.c | 1 - drivers/reset/reset-raspberrypi.c | 1 - drivers/reset/reset-rockchip.c | 1 - drivers/reset/reset-scmi.c | 1 - drivers/reset/reset-sifive.c | 1 - drivers/reset/reset-socfpga.c | 1 - drivers/reset/reset-sunxi.c| 1 - drivers/reset/reset-syscon.c | 1 - drivers/reset/reset-ti-sci.c | 1 - drivers/reset/reset-uclass.c | 1 - drivers/reset/reset-uniphier.c | 1 - drivers/reset/reset-zynqmp.c | 1 - drivers/reset/rst-rk3588.c | 1 - drivers/reset/sandbox-reset-test.c | 1 - drivers/reset/sandbox-reset.c | 1 - drivers/reset/sti-reset.c | 1 - drivers/reset/stm32-reset.c| 1 - drivers/reset/tegra-car-reset.c| 1 - drivers/reset/tegra186-reset.c | 1 - 29 files changed, 29 deletions(-) diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c index d9cecf3a72e8..0ed5396b3e91 100644 --- a/drivers/reset/reset-ast2500.c +++ b/drivers/reset/reset-ast2500.c @@ -4,7 +4,6 @@ * Copyright 2020 ASPEED Technology Inc. */ -#include #include #include #include diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c index 1732a450efc0..ec7b9b6625dc 100644 --- a/drivers/reset/reset-ast2600.c +++ b/drivers/reset/reset-ast2600.c @@ -3,7 +3,6 @@ * Copyright 2020 ASPEED Technology Inc. */ -#include #include #include #include diff --git a/drivers/reset/reset-bcm6345.c b/drivers/reset/reset-bcm6345.c index 5383f59ca375..6f140574216d 100644 --- a/drivers/reset/reset-bcm6345.c +++ b/drivers/reset/reset-bcm6345.c @@ -6,7 +6,6 @@ *Copyright (C) 2012 Jonas Gorski */ -#include #include #include #include diff --git a/drivers/reset/reset-dra7.c b/drivers/reset/reset-dra7.c index 05101a94f9bc..2f0ec4c042f7 100644 --- a/drivers/reset/reset-dra7.c +++ b/drivers/reset/reset-dra7.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/reset/reset-hisilicon.c b/drivers/reset/reset-hisilicon.c index 85e02b296b02..aca54cd6701c 100644 --- a/drivers/reset/reset-hisilicon.c +++ b/drivers/reset/reset-hisilicon.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/reset/reset-hsdk.c b/drivers/reset/reset-hsdk.c index 74b1173e8878..747e73b17fcb 100644 --- a/drivers/reset/reset-hsdk.c +++ b/drivers/reset/reset-hsdk.c @@ -8,7 +8,6 @@ #include #include -#include #include #include #include diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index a3b3132f2fae..65a352b71fd7 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/reset/reset-jh7110.c b/drivers/reset/reset-jh7110.c index d6bdf6bb00c4..adf722d5871a 100644 --- a/drivers/reset/reset-jh7110.c +++ b/drivers/reset/reset-jh7110.c @@ -5,7 +5,6 @@ * */ -#include #include #include #include diff --git a/drivers/reset/reset-mediatek.c b/drivers/reset/reset-mediatek.c index 97ed221f739a..4b3afab92ea7 100644 --- a/drivers/reset/reset-mediatek.c +++ b/drivers/reset/reset-mediatek.c @@ -6,7 +6,6 @@ * Weijie Gao */ -#include #include #include #include diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index 9d0c8b354f4a..6337cdaaffa2 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -6,7 +6,6 @@ * Author: Neil Armstrong */ -#include #include #include #include diff --git a/drivers/reset/reset-mtmips.c b/drivers/reset/reset-mtmips.c index 7bb8469823c8..2db6766280f2 100644 --- a/drivers/reset/reset-mtmips.c
Re: [PATCH 54/81] ram: Remove and add needed includes
On 2024/5/2 09:31, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Ryan Chen Cc: Chia-Wei Wang Cc: Aspeed BMC SW team Cc: Joel Stanley Cc: Tom Rini Cc: Ryder Lee Cc: Weijie Gao Cc: Chunfeng Yun Cc: GSS_MTK_Uboot_upstream Cc: Mario Six Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Patrick Delaunay Cc: Patrice Chotard Cc: Ralph Siemsen Cc: Marek Vasut Cc: Leo Yu-Chi Liang Cc: Yanhong Wang Cc: Andre Przywara --- drivers/ram/aspeed/sdram_ast2500.c | 2 +- drivers/ram/aspeed/sdram_ast2600.c | 2 +- drivers/ram/bmips_ram.c | 1 - drivers/ram/cadence/ddr_ctrl.c | 1 - drivers/ram/imxrt_sdram.c | 1 - drivers/ram/k3-am654-ddrss.c| 1 - drivers/ram/k3-ddrss/k3-ddrss.c | 1 - drivers/ram/mediatek/ddr3-mt7629.c | 2 +- drivers/ram/mpc83xx_sdram.c | 1 - drivers/ram/ram-uclass.c| 1 - drivers/ram/renesas/rzn1/ddr_async.c| 1 - drivers/ram/rockchip/dmc-rk3368.c | 2 +- drivers/ram/rockchip/sdram_common.c | 2 +- drivers/ram/rockchip/sdram_pctl_px30.c | 1 - drivers/ram/rockchip/sdram_phy_px30.c | 1 - drivers/ram/rockchip/sdram_px30.c | 2 +- drivers/ram/rockchip/sdram_rk3066.c | 2 +- drivers/ram/rockchip/sdram_rk3128.c | 2 +- drivers/ram/rockchip/sdram_rk3188.c | 2 +- drivers/ram/rockchip/sdram_rk322x.c | 2 +- drivers/ram/rockchip/sdram_rk3288.c | 2 +- drivers/ram/rockchip/sdram_rk3308.c | 2 +- drivers/ram/rockchip/sdram_rk3328.c | 2 +- drivers/ram/rockchip/sdram_rk3399.c | 2 +- drivers/ram/rockchip/sdram_rk3568.c | 2 +- drivers/ram/rockchip/sdram_rk3588.c | 2 +- drivers/ram/rockchip/sdram_rv1126.c | 2 +- drivers/ram/sandbox_ram.c | 1 - drivers/ram/sifive/sifive_ddr.c | 1 - drivers/ram/starfive/ddrcsr_boot.c | 1 - drivers/ram/starfive/ddrphy_start.c | 1 - drivers/ram/starfive/ddrphy_train.c | 2 +- drivers/ram/starfive/ddrphy_utils.c | 2 +- drivers/ram/starfive/starfive_ddr.c | 1 - drivers/ram/starfive/starfive_ddr.h | 2 ++ drivers/ram/stm32_sdram.c | 1 - drivers/ram/stm32mp1/stm32mp1_ddr.c | 1 - drivers/ram/stm32mp1/stm32mp1_interactive.c | 1 - drivers/ram/stm32mp1/stm32mp1_ram.c | 1 - drivers/ram/stm32mp1/stm32mp1_tests.c | 1 - drivers/ram/sunxi/dram_sun20i_d1.c | 2 +- 41 files changed, 22 insertions(+), 40 deletions(-) diff --git a/drivers/ram/aspeed/sdram_ast2500.c b/drivers/ram/aspeed/sdram_ast2500.c index dc466a88e712..0d6ab79f96fc 100644 --- a/drivers/ram/aspeed/sdram_ast2500.c +++ b/drivers/ram/aspeed/sdram_ast2500.c @@ -5,7 +5,7 @@ * Copyright 2016 Google, Inc */ -#include +#include #include #include #include diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index d463933363ee..55e80fba3dc0 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -2,7 +2,7 @@ /* * Copyright (C) ASPEED Technology Inc. */ -#include +#include #include #include #include diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c index 98045248ecfb..760bebdbba04 100644 --- a/drivers/ram/bmips_ram.c +++ b/drivers/ram/bmips_ram.c @@ -7,7 +7,6 @@ *Copyright (C) 2009 Florian Fainelli */ -#include #include #include #include diff --git a/drivers/ram/cadence/ddr_ctrl.c b/drivers/ram/cadence/ddr_ctrl.c index 3e5959a84a37..0fa60e766a7e 100644 --- a/drivers/ram/cadence/ddr_ctrl.c +++ b/drivers/ram/cadence/ddr_ctrl.c @@ -24,7 +24,6 @@ * bandwidth allocated to each AXI slave can be set. */ -#include #include #include #include diff --git a/drivers/ram/imxrt_sdram.c b/drivers/ram/imxrt_sdram.c index 6a15242c20cc..3df106c9b79a 100644 --- a/drivers/ram/imxrt_sdram.c +++ b/drivers/ram/imxrt_sdram.c @@ -4,7 +4,6 @@ * Author(s): Giulio Benetti */ -#include #include #include #include diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c index cff8ffc89295..21ff9d761e1b 100644 --- a/drivers/ram/k3-am654-ddrss.c +++ b/drivers/ram/k3-am654-ddrss.c @@ -6,7 +6,6 @@ *Lokesh Vutla */ -#include #include #include #include diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index a5c9b82cf1da..525b6d5b79fc 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -5,7 +5,6 @@ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ -#include #include #include #include diff --git a/drivers/ram/mediatek/ddr3-mt7629
Re: [PATCH 52/81] power: Remove and add needed includes
On 2024/5/2 09:31, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Jaehoon Chung Cc: Tom Rini Cc: Neil Armstrong Cc: Ryder Lee Cc: Weijie Gao Cc: Chunfeng Yun Cc: GSS_MTK_Uboot_upstream Cc: Michal Simek Cc: Stephan Gerhold Cc: Linus Walleij Cc: Caleb Connolly Cc: Sumit Garg Cc: Patrick Delaunay Cc: Patrice Chotard Cc: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Cc: Marek Vasut Cc: Sean Anderson Cc: Bryan Brattlof Cc: Nishanth Menon Cc: Neha Malcom Francis Cc: Igor Opaniuk Cc: Roger Quadros Cc: Apurva Nandan Cc: Simon Glass Cc: Svyatoslav Ryhel Cc: Kever Yang Cc: Jonas Karlman Cc: Quentin Schulz Cc: Bhargav Raviprakash Cc: Udit Kumar Cc: Dhruva Gole Cc: Eugen Hristev Cc: Joseph Chen Cc: shengfei Xu Cc: William Wu Cc: AKASHI Takahiro Cc: Etienne Carriere --- drivers/power/acpi_pmc/acpi-pmc-uclass.c | 1 - drivers/power/acpi_pmc/pmc_emul.c| 1 - drivers/power/acpi_pmc/sandbox.c | 1 - drivers/power/axp152.c | 2 +- drivers/power/axp209.c | 2 +- drivers/power/axp221.c | 1 - drivers/power/axp305.c | 1 - drivers/power/axp313.c | 1 - drivers/power/axp809.c | 1 - drivers/power/axp818.c | 1 - drivers/power/domain/apple-pmgr.c| 1 - drivers/power/domain/bcm6328-power-domain.c | 1 - drivers/power/domain/imx8-power-domain-legacy.c | 1 - drivers/power/domain/imx8-power-domain.c | 1 - drivers/power/domain/imx8m-power-domain.c| 1 - drivers/power/domain/imx8mp-hsiomix.c| 1 - drivers/power/domain/meson-ee-pwrc.c | 1 - drivers/power/domain/meson-gx-pwrc-vpu.c | 1 - drivers/power/domain/mtk-power-domain.c | 1 - drivers/power/domain/power-domain-uclass.c | 1 - drivers/power/domain/sandbox-power-domain-test.c | 1 - drivers/power/domain/sandbox-power-domain.c | 1 - drivers/power/domain/tegra186-power-domain.c | 1 - drivers/power/domain/ti-power-domain.c | 1 - drivers/power/domain/ti-sci-power-domain.c | 1 - drivers/power/domain/zynqmp-power-domain.c | 1 - drivers/power/exynos-tmu.c | 3 ++- drivers/power/mt6323.c | 1 - drivers/power/pmic/ab8500.c | 1 - drivers/power/pmic/act8846.c | 1 - drivers/power/pmic/as3722.c | 1 - drivers/power/pmic/as3722_gpio.c | 1 - drivers/power/pmic/bd71837.c | 1 - drivers/power/pmic/da9063.c | 1 - drivers/power/pmic/fan53555.c| 1 - drivers/power/pmic/i2c_pmic_emul.c | 1 - drivers/power/pmic/lp873x.c | 1 - drivers/power/pmic/lp87565.c | 1 - drivers/power/pmic/max77686.c| 1 - drivers/power/pmic/max8997.c | 1 - drivers/power/pmic/max8998.c | 1 - drivers/power/pmic/mc34708.c | 1 - drivers/power/pmic/mp5416.c | 1 - drivers/power/pmic/palmas.c | 1 - drivers/power/pmic/pca9450.c | 1 - drivers/power/pmic/pfuze100.c| 1 - drivers/power/pmic/pmic-uclass.c | 1 - drivers/power/pmic/pmic_hi6553.c | 1 - drivers/power/pmic/pmic_ltc3676.c| 1 - drivers/power/pmic/pmic_mc34vr500.c | 1 - drivers/power/pmic/pmic_pca9450.c| 1 - drivers/power/pmic/pmic_pfuze100.c | 1 - drivers/power/pmic/pmic_pfuze3000.c | 1 - drivers/power/pmic/pmic_qcom.c | 1 - drivers/power/pmic/pmic_tps62362.c | 1 - drivers/power/pmic/pmic_tps65217.c | 1 - drivers/power/pmic/pmic_tps65218.c | 1 - drivers/power/pmic/pmic_tps65910.c | 1 - drivers/power/pmic/pmic_tps65910_dm.c| 1 - drivers/power/pmic/rk8xx.c | 1 - drivers/power/pmic/rn5t567.c | 1 - drivers/power/pmic/s2mps11.c | 1 - drivers/power/pmic/s5m8767.c | 1 - drivers/power/pmic/sandbox.c | 1 - drivers/power/pmic/stpmic1.c | 1 - drivers/power/pmic/tps65090.c| 1 - drivers/power/pmic/tps65219.c| 1 - drivers/power/pmic/tps65941.c| 1 - drivers/power/power_core.c | 1 - drivers/power/power_dialog.c | 2 +- drivers/power/power_fsl.c| 2
Re: [PATCH 51/81] pinctrl: Remove and add needed includes
On 2024/5/2 09:31, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Ryan Chen Cc: Chia-Wei Wang Cc: Aspeed BMC SW team Cc: Joel Stanley Cc: Tom Rini Cc: Matthias Brugger Cc: Peter Robinson Cc: Ryder Lee Cc: Weijie Gao Cc: Chunfeng Yun Cc: GSS_MTK_Uboot_upstream Cc: Neil Armstrong Cc: Gregory CLEMENT Cc: Lars Povlsen Cc: Horatiu Vultur Cc: Stefan Roese Cc: Stefan Bosch Cc: Mark Kettenis Cc: Sean Anderson Cc: Simon Glass Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Michal Simek Cc: Caleb Connolly Cc: Sumit Garg Cc: Philipp Tomsich Cc: Kever Yang Cc: Thierry Reding Cc: Svyatoslav Ryhel Cc: Kunihiko Hayashi Cc: Dai Okamura Cc: Minkyu Kang Cc: Sam Protsenko Cc: Peng Fan Cc: Stefano Babic Cc: Matthias Schiffer Cc: Quentin Schulz Cc: Jonas Karlman Cc: Volodymyr Babchuk Cc: Robert Marko --- drivers/pinctrl/aspeed/pinctrl_ast2500.c | 1 - drivers/pinctrl/aspeed/pinctrl_ast2600.c | 1 - drivers/pinctrl/ath79/pinctrl_ar933x.c | 1 - drivers/pinctrl/ath79/pinctrl_qca953x.c | 1 - drivers/pinctrl/broadcom/pinctrl-bcm283x.c | 1 - drivers/pinctrl/broadcom/pinctrl-bcm6838.c | 1 - drivers/pinctrl/exynos/pinctrl-exynos.c | 1 - drivers/pinctrl/exynos/pinctrl-exynos7420.c | 1 - drivers/pinctrl/exynos/pinctrl-exynos78x0.c | 1 - drivers/pinctrl/intel/pinctrl.c | 1 - drivers/pinctrl/intel/pinctrl_apl.c | 1 - drivers/pinctrl/mediatek/pinctrl-mtk-common.c| 1 - drivers/pinctrl/meson/pinctrl-meson-a1.c | 1 - drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c| 1 - drivers/pinctrl/meson/pinctrl-meson-axg.c| 1 - drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1 - drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c | 1 - drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 1 - drivers/pinctrl/meson/pinctrl-meson-gxl.c| 1 - drivers/pinctrl/meson/pinctrl-meson.c| 1 - drivers/pinctrl/mscc/mscc-common.c | 1 - drivers/pinctrl/mscc/pinctrl-jr2.c | 1 - drivers/pinctrl/mscc/pinctrl-luton.c | 1 - drivers/pinctrl/mscc/pinctrl-ocelot.c| 1 - drivers/pinctrl/mscc/pinctrl-serval.c| 1 - drivers/pinctrl/mscc/pinctrl-servalt.c | 1 - drivers/pinctrl/mtmips/pinctrl-mt7628.c | 1 - drivers/pinctrl/mtmips/pinctrl-mtmips-common.c | 1 - drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 1 - drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 1 - drivers/pinctrl/mvebu/pinctrl-mvebu.c| 1 - drivers/pinctrl/nexell/pinctrl-nexell.c | 1 - drivers/pinctrl/nexell/pinctrl-s5pxx18.c | 1 - drivers/pinctrl/nxp/pinctrl-imx.c| 1 - drivers/pinctrl/nxp/pinctrl-imx5.c | 1 - drivers/pinctrl/nxp/pinctrl-imx6.c | 1 - drivers/pinctrl/nxp/pinctrl-imx7.c | 1 - drivers/pinctrl/nxp/pinctrl-imx7ulp.c| 1 - drivers/pinctrl/nxp/pinctrl-imx8.c | 1 - drivers/pinctrl/nxp/pinctrl-imx8ulp.c| 1 - drivers/pinctrl/nxp/pinctrl-imxrt.c | 1 - drivers/pinctrl/nxp/pinctrl-mxs.c| 1 - drivers/pinctrl/nxp/pinctrl-scu.c| 1 - drivers/pinctrl/nxp/pinctrl-vf610.c | 1 - drivers/pinctrl/pinctrl-apple.c | 1 - drivers/pinctrl/pinctrl-at91-pio4.c | 1 - drivers/pinctrl/pinctrl-at91.c | 1 - drivers/pinctrl/pinctrl-generic.c| 1 - drivers/pinctrl/pinctrl-k210.c | 1 - drivers/pinctrl/pinctrl-qe-io.c | 1 - drivers/pinctrl/pinctrl-sandbox.c| 1 - drivers/pinctrl/pinctrl-single.c | 1 - drivers/pinctrl/pinctrl-sti.c| 1 - drivers/pinctrl/pinctrl-stmfx.c | 1 - drivers/pinctrl/pinctrl-uclass.c | 1 - drivers/pinctrl/pinctrl-zynqmp.c | 1 - drivers/pinctrl/pinctrl_pic32.c | 1 - drivers/pinctrl/pinctrl_stm32.c | 1 - drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 - drivers/pinctrl/qcom/pinctrl-apq8096.c | 1 - drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1 - drivers/pinctrl/qcom/pinctrl-qcom.c | 1 - drivers/pinctrl/qcom/pinctrl-qcs404.c| 1 - drivers/pinctrl/qcom/pinctrl-sdm845.c| 1 - drivers/pinctrl/rockchip/pinctrl-px30.c | 1 - drivers/pinctrl/rockchip/pinctrl-rk3036.c| 1 - drivers/pinctrl/rockchip/pinctrl-rk3066.c| 1 - drivers/pinctrl/rockchip/pinctrl-rk3128.c| 1 - drivers/pinctrl/rockchip/pinctrl-rk3188.c| 1 - drivers/pinctrl/rockchip/pinctrl-rk322x.c| 1 - drivers/pinctrl/rockchip/pinctrl
Re: [PATCH 50/81] phy: Remove and add needed includes
On 2024/5/2 09:31, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Jagan Teki Cc: Andre Przywara Cc: Tom Rini Cc: Stefan Roese Cc: Neil Armstrong Cc: Stephan Gerhold Cc: Linus Walleij Cc: Mark Kettenis Cc: Ryder Lee Cc: Weijie Gao Cc: Chunfeng Yun Cc: GSS_MTK_Uboot_upstream Cc: Nobuhiro Iwamatsu Cc: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Cc: Michal Simek Cc: Caleb Connolly Cc: Sumit Garg Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Kunihiko Hayashi Cc: Dai Okamura Cc: Sean Anderson Cc: Nishanth Menon Cc: Matthias Schiffer Cc: Stefan Bosch Cc: Eugen Hristev Cc: Igor Prusov Cc: Svyatoslav Ryhel Cc: Tim Harvey Cc: Fabio Estevam Cc: Adam Ford Cc: Jonas Karlman Cc: Johan Jonker Cc: Jon Lin Cc: Ren Jianing Cc: Frank Wang Cc: Siddharth Vadapalli Cc: Ravi Gunasekaran --- drivers/phy/allwinner/phy-sun4i-usb.c | 1 - drivers/phy/bcm6318-usbh-phy.c | 1 - drivers/phy/bcm6348-usbh-phy.c | 1 - drivers/phy/bcm6358-usbh-phy.c | 1 - drivers/phy/bcm6368-usbh-phy.c | 1 - drivers/phy/cadence/phy-cadence-sierra.c | 1 - drivers/phy/cadence/phy-cadence-torrent.c | 1 - drivers/phy/keystone-usb-phy.c | 1 - drivers/phy/marvell/comphy_a3700.c | 1 - drivers/phy/marvell/comphy_core.c | 1 - drivers/phy/marvell/comphy_cp110.c | 2 +- drivers/phy/marvell/comphy_mux.c | 1 - drivers/phy/meson-axg-mipi-dphy.c | 1 - drivers/phy/meson-axg-mipi-pcie-analog.c | 1 - drivers/phy/meson-g12a-usb2.c | 1 - drivers/phy/meson-g12a-usb3-pcie.c | 1 - drivers/phy/meson-gxbb-usb2.c | 1 - drivers/phy/meson-gxl-usb2.c | 1 - drivers/phy/mt76x8-usb-phy.c | 1 - drivers/phy/nop-phy.c | 1 - drivers/phy/omap-usb2-phy.c| 1 - drivers/phy/phy-ab8500-usb.c | 1 - drivers/phy/phy-apple-atc.c| 1 - drivers/phy/phy-bcm-sr-pcie.c | 1 - drivers/phy/phy-core-mipi-dphy.c | 2 +- drivers/phy/phy-da8xx-usb.c| 2 +- drivers/phy/phy-imx8mq-usb.c | 1 - drivers/phy/phy-mtk-tphy.c | 1 - drivers/phy/phy-npcm-usb.c | 1 - drivers/phy/phy-rcar-gen2.c| 1 - drivers/phy/phy-rcar-gen3.c| 1 - drivers/phy/phy-stm32-usbphyc.c| 1 - drivers/phy/phy-ti-am654.c | 1 - drivers/phy/phy-uclass.c | 1 - drivers/phy/phy-zynqmp.c | 1 - drivers/phy/qcom/msm8916-usbh-phy.c| 1 - drivers/phy/qcom/phy-qcom-ipq4019-usb.c| 1 - drivers/phy/qcom/phy-qcom-usb-hs-28nm.c| 1 - drivers/phy/qcom/phy-qcom-usb-ss.c | 1 - drivers/phy/renesas/r8a779f0-ether-serdes.c| 1 - drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 1 - drivers/phy/rockchip/phy-rockchip-pcie.c | 1 - drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 1 - drivers/phy/rockchip/phy-rockchip-typec.c | 1 - drivers/phy/rockchip/phy-rockchip-usbdp.c | 1 - drivers/phy/sandbox-phy.c | 1 - drivers/phy/socionext/phy-uniphier-pcie.c | 1 - drivers/phy/socionext/phy-uniphier-usb3.c | 1 - drivers/phy/sti_usb_phy.c | 1 - drivers/phy/ti-pipe3-phy.c | 1 - drivers/phy/ti/phy-j721e-wiz.c | 1 - 51 files changed, 3 insertions(+), 51 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 6624e9134f43..b9306c9a8279 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -10,7 +10,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include #include diff --git a/drivers/phy/bcm6318-usbh-phy.c b/drivers/phy/bcm6318-usbh-phy.c index a2fa446cb1c9..d715541bd4cb 100644 --- a/drivers/phy/bcm6318-usbh-phy.c +++ b/drivers/phy/bcm6318-usbh-phy.c @@ -7,7 +7,6 @@ *Copyright 2013 Florian Fainelli */ -#include #include #include #include diff --git a/drivers/phy/bcm6348-usbh-phy.c b/drivers/phy/bcm6348-usbh-phy.c index 857fb575ef19..ffb37b634a31 100644 --- a/drivers/phy/bcm6348-usbh-phy.c +++ b/drivers/phy/bcm6348-usbh-phy.c @@ -7,7 +7,6 @@ *Copyright 2013 Florian Fainelli */ -#include #include #include #include diff --git
Re: [PATCH 48/81] pci: Remove and add needed includes
On 2024/5/2 09:31, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Stefan Roese Cc: Tom Rini Cc: Nobuhiro Iwamatsu Cc: Marek Vasut Cc: Heiko Schocher Cc: Simon Glass Cc: Mark Kettenis Cc: Neil Armstrong Cc: Philipp Tomsich Cc: Kever Yang Cc: Masahisa Kojima Cc: Ryder Lee Cc: Weijie Gao Cc: Chunfeng Yun Cc: GSS_MTK_Uboot_upstream Cc: liuhao Cc: shuyiqi Cc: Minda Chen Cc: Kunihiko Hayashi Cc: Dai Okamura Cc: Michal Simek Cc: Bin Meng Cc: Heinrich Schuchardt Cc: Moritz Fischer Cc: This contributor prefers not to receive mails Cc: Sergei Antonov Cc: Nikhil M Jain Cc: Sam Edwards Cc: Jonas Karlman Cc: Johan Jonker Cc: Michael Trimarchi Cc: Jon Lin Cc: Eugen Hristev Cc: Maksim Kiselev Cc: Sumit Garg Cc: Peng Fan Cc: Ioana Ciornei Cc: Mathew McBride Cc: Leo Yu-Chi Liang Cc: Mason Huo Cc: Mayuresh Chitale --- drivers/pci/pci-aardvark.c | 1 - drivers/pci/pci-emul-uclass.c | 1 - drivers/pci/pci-rcar-gen2.c| 2 +- drivers/pci/pci-rcar-gen3.c| 1 - drivers/pci/pci-uclass.c | 1 - drivers/pci/pci_auto.c | 2 +- drivers/pci/pci_auto_common.c | 1 - drivers/pci/pci_common.c | 1 - drivers/pci/pci_compat.c | 1 - drivers/pci/pci_ftpci100.c | 1 - drivers/pci/pci_mpc85xx.c | 1 - drivers/pci/pci_mvebu.c| 1 - drivers/pci/pci_rom.c | 2 +- drivers/pci/pci_sandbox.c | 1 - drivers/pci/pci_sh7751.c | 2 +- drivers/pci/pci_tegra.c| 1 - drivers/pci/pci_x86.c | 1 - drivers/pci/pcie_apple.c | 1 - drivers/pci/pcie_brcmstb.c | 1 - drivers/pci/pcie_dw_common.c | 1 - drivers/pci/pcie_dw_meson.c| 1 - drivers/pci/pcie_dw_mvebu.c| 3 ++- drivers/pci/pcie_dw_rockchip.c | 1 - drivers/pci/pcie_dw_sifive.c | 1 - drivers/pci/pcie_dw_ti.c | 1 - drivers/pci/pcie_ecam_generic.c| 1 - drivers/pci/pcie_ecam_synquacer.c | 1 - drivers/pci/pcie_fsl.c | 2 +- drivers/pci/pcie_fsl_fixup.c | 1 - drivers/pci/pcie_imx.c | 1 - drivers/pci/pcie_intel_fpga.c | 1 - drivers/pci/pcie_iproc.c | 1 - drivers/pci/pcie_layerscape.c | 1 - drivers/pci/pcie_layerscape_ep.c | 2 +- drivers/pci/pcie_layerscape_fixup.c| 1 - drivers/pci/pcie_layerscape_fixup_common.c | 2 +- drivers/pci/pcie_layerscape_gen4.c | 2 +- drivers/pci/pcie_layerscape_gen4_fixup.c | 1 - drivers/pci/pcie_layerscape_rc.c | 1 - drivers/pci/pcie_mediatek.c| 1 - drivers/pci/pcie_phytium.c | 1 - drivers/pci/pcie_plda_common.c | 1 - drivers/pci/pcie_rockchip.c| 1 - drivers/pci/pcie_starfive_jh7110.c | 1 - drivers/pci/pcie_uniphier.c| 1 - drivers/pci/pcie_xilinx.c | 1 - 46 files changed, 10 insertions(+), 46 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index af0e55cd2f2c..f5db4bdb7605 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -25,7 +25,6 @@ * */ -#include #include #include #include diff --git a/drivers/pci/pci-emul-uclass.c b/drivers/pci/pci-emul-uclass.c index a0b8afb87a01..166ee9fcd431 100644 --- a/drivers/pci/pci-emul-uclass.c +++ b/drivers/pci/pci-emul-uclass.c @@ -4,7 +4,6 @@ * Written by Simon Glass */ -#include #include #include #include diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index b81eb3536896..12c31e74087f 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -5,7 +5,7 @@ * Copyright (C) 2018 Marek Vasut */ -#include +#include #include #include #include diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 1252ef74c581..76878246f1e0 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -15,7 +15,6 @@ * Author: Phil Edworthy */ -#include #include #include #include diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 1a48256de036..6571e653049d 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_PCI -#include #include #include #include diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 01230360bad2..90f818864457 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -8,7 +8,7 @@ * Copyright (c) 2021
Re: [PATCH 45/81] net: Remove and add needed includes
On 2024/5/2 09:31, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Joe Hershberger Cc: Ramon Fried Cc: Tom Rini Cc: Ryan Chen Cc: Chia-Wei Wang Cc: Aspeed BMC SW team Cc: Joel Stanley Cc: Alex Nemirovsky Cc: Caleb Connolly Cc: Neil Armstrong Cc: Sumit Garg Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Robert Marko Cc: Luka Kovacic Cc: Luka Perkov Cc: Gregory CLEMENT Cc: Lars Povlsen Cc: Horatiu Vultur Cc: Ryder Lee Cc: Weijie Gao Cc: Chunfeng Yun Cc: GSS_MTK_Uboot_upstream Cc: Michal Simek Cc: Radu Pirea Cc: Nobuhiro Iwamatsu Cc: Marek Vasut Cc: Peng Fan Cc: Ioana Ciornei Cc: Laurentiu Tudor Cc: Nate Drude Cc: Rasmus Villemoes Cc: "Rafał Miłecki" Cc: Nishanth Menon Cc: Frank de Brabander Cc: Leo Yu-Chi Liang Cc: Lukasz Tekieli Cc: Nicolas Frattaroli Cc: Yanhong Wang Cc: Jacky Chou Cc: Dan Carpenter Cc: Eugeniu Rosca Cc: Tejas Bhumkar Cc: "Sébastien Szymanski" Cc: Stefan Herbrechtsmeier Cc: Johan Jonker Cc: Roger Quadros Cc: Siddharth Vadapalli Cc: Michael Walle Cc: Maxime Ripard Cc: Sean Anderson Cc: Suman Anna Cc: Andreas Dannenberg --- drivers/net/ag7xxx.c | 1 - drivers/net/altera_tse.c | 1 - drivers/net/aspeed_mdio.c | 1 - drivers/net/bcm-sf2-eth-gmac.c| 1 - drivers/net/bcm-sf2-eth.c | 1 - drivers/net/bcm6348-eth.c | 1 - drivers/net/bcm6368-eth.c | 1 - drivers/net/bnxt/bnxt.c | 1 - drivers/net/calxedaxgmac.c| 1 - drivers/net/cortina_ni.c | 1 - drivers/net/dc2114x.c | 1 - drivers/net/designware.c | 1 - drivers/net/dm9000x.c | 1 - drivers/net/dwc_eth_qos.c | 1 - drivers/net/dwc_eth_qos_imx.c | 1 - drivers/net/dwc_eth_qos_qcom.c| 1 - drivers/net/dwc_eth_qos_rockchip.c| 1 - drivers/net/dwc_eth_qos_starfive.c| 1 - drivers/net/dwmac_meson8b.c | 1 - drivers/net/dwmac_s700.c | 1 - drivers/net/dwmac_socfpga.c | 1 - drivers/net/e1000.c | 1 - drivers/net/e1000_spi.c | 2 +- drivers/net/eepro100.c| 2 +- drivers/net/eth-phy-uclass.c | 1 - drivers/net/ethoc.c | 1 - drivers/net/fec_mxc.c | 1 - drivers/net/fm/b4860.c| 2 +- drivers/net/fm/dtsec.c| 1 - drivers/net/fm/eth.c | 2 +- drivers/net/fm/ls1043.c | 2 +- drivers/net/fm/ls1046.c | 2 +- drivers/net/fm/memac.c| 1 - drivers/net/fm/memac_phy.c| 1 - drivers/net/fm/p1023.c| 2 +- drivers/net/fm/p4080.c| 2 +- drivers/net/fm/p5020.c| 2 +- drivers/net/fm/p5040.c| 2 +- drivers/net/fm/t1024.c| 2 +- drivers/net/fm/t1040.c| 2 +- drivers/net/fm/t2080.c| 2 +- drivers/net/fm/t4240.c| 2 +- drivers/net/fm/tgec.c | 1 - drivers/net/fm/tgec_phy.c | 1 - drivers/net/fsl-mc/mc.c | 2 +- drivers/net/fsl-mc/mc_sys.c | 1 - drivers/net/fsl_enetc.c | 1 - drivers/net/fsl_enetc_mdio.c | 1 - drivers/net/fsl_ls_mdio.c | 1 - drivers/net/fsl_mdio.c| 1 - drivers/net/ftgmac100.c | 1 - drivers/net/ftmac100.c| 1 - drivers/net/gmac_rockchip.c | 1 - drivers/net/higmacv300.c | 1 - drivers/net/ks8851_mll.c | 1 - drivers/net/ldpaa_eth/ldpaa_eth.c | 1 - drivers/net/ldpaa_eth/ldpaa_wriop.c | 1 - drivers/net/ldpaa_eth/ls1088a.c | 2 +- drivers/net/ldpaa_eth/ls2080a.c | 2 +- drivers/net/ldpaa_eth/lx2160a.c | 2 +- drivers/net/macb.c| 1 - drivers/net/mcffec.c | 2 +- drivers/net/mcfmii.c | 1 - drivers/net/mdio-ipq4019.c| 1 - drivers/net/mpc8xx_fec.c | 1 - drivers/net/mscc_eswitch/jr2_switch.c | 1 - drivers/net/mscc_eswitch/luton_switch.c | 1 - drivers/net/mscc_eswitch/ocelot_switch.c | 1 - drivers/net/mscc_eswitch/serval_switch.c | 1 - drivers/net/mscc_eswitch/servalt_switch.c | 1 - drivers/net/mt7628-eth.c | 1 - drivers/net/mtk_eth.c | 1 - drivers/net/mv88e6xxx.c | 1 - drivers/net/mvgbe.c | 1 -
Re: [PATCH 42/81] mmc: Remove and add needed includes
On 2024/5/2 09:30, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Peng Fan Cc: Jaehoon Chung Cc: Tom Rini Cc: Ryan Chen Cc: Chia-Wei Wang Cc: Aspeed BMC SW team Cc: Joel Stanley Cc: Matthias Brugger Cc: Peter Robinson Cc: Thomas Fitzsimmons Cc: Alex Nemirovsky Cc: Masahisa Kojima Cc: Neil Armstrong Cc: Simon Glass Cc: Caleb Connolly Cc: Sumit Garg Cc: Ryder Lee Cc: Weijie Gao Cc: Chunfeng Yun Cc: GSS_MTK_Uboot_upstream Cc: Tianrui Wei Cc: Philipp Tomsich Cc: Kever Yang Cc: Nobuhiro Iwamatsu Cc: Marek Vasut Cc: Eugeniy Paltsev Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Thierry Reding Cc: Svyatoslav Ryhel Cc: Kunihiko Hayashi Cc: Dai Okamura Cc: Stefan Roese Cc: Michal Simek --- drivers/mmc/am654_sdhci.c | 1 - drivers/mmc/arm_pl180_mmci.c | 1 - drivers/mmc/aspeed_sdhci.c| 1 - drivers/mmc/atmel_sdhci.c | 1 - drivers/mmc/bcm2835_sdhci.c | 1 - drivers/mmc/bcm2835_sdhost.c | 1 - drivers/mmc/bcmstb_sdhci.c| 1 - drivers/mmc/ca_dw_mmc.c | 1 - drivers/mmc/davinci_mmc.c | 1 - drivers/mmc/dw_mmc.c | 1 - drivers/mmc/exynos_dw_mmc.c | 1 - drivers/mmc/f_sdh30.c | 1 - drivers/mmc/fsl_esdhc.c | 1 - drivers/mmc/fsl_esdhc_imx.c | 1 - drivers/mmc/fsl_esdhc_spl.c | 2 +- drivers/mmc/ftsdc010_mci.c| 1 - drivers/mmc/gen_atmel_mci.c | 2 +- drivers/mmc/hi6220_dw_mmc.c | 1 - drivers/mmc/iproc_sdhci.c | 1 - drivers/mmc/jz_mmc.c | 1 - drivers/mmc/kona_sdhci.c | 1 - drivers/mmc/meson_gx_mmc.c| 1 - drivers/mmc/mmc-pwrseq.c | 1 - drivers/mmc/mmc-uclass.c | 1 - drivers/mmc/mmc.c | 3 ++- drivers/mmc/mmc_boot.c| 1 - drivers/mmc/mmc_bootdev.c | 1 - drivers/mmc/mmc_legacy.c | 1 - drivers/mmc/mmc_spi.c | 1 - drivers/mmc/mmc_write.c | 1 - drivers/mmc/msm_sdhci.c | 1 - drivers/mmc/mtk-sd.c | 1 - drivers/mmc/mv_sdhci.c| 1 - drivers/mmc/mvebu_mmc.c | 1 - drivers/mmc/mxcmmc.c | 1 - drivers/mmc/mxsmmc.c | 1 - drivers/mmc/nexell_dw_mmc.c | 1 - drivers/mmc/npcm_sdhci.c | 1 - drivers/mmc/omap_hsmmc.c | 1 - drivers/mmc/owl_mmc.c | 1 - drivers/mmc/pci_mmc.c | 1 - drivers/mmc/piton_mmc.c | 1 - drivers/mmc/rockchip_dw_mmc.c | 1 - drivers/mmc/rockchip_sdhci.c | 1 - drivers/mmc/rpmb.c| 1 - drivers/mmc/s5p_sdhci.c | 1 - drivers/mmc/sandbox_mmc.c | 1 - drivers/mmc/sdhci-adma.c | 1 - drivers/mmc/sdhci-cadence.c | 1 - drivers/mmc/sdhci.c | 2 +- drivers/mmc/sh_mmcif.c| 1 - drivers/mmc/snps_dw_mmc.c | 1 - drivers/mmc/socfpga_dw_mmc.c | 1 - drivers/mmc/sti_sdhci.c | 1 - drivers/mmc/stm32_sdmmc2.c| 1 - drivers/mmc/sunxi_mmc.c | 1 - drivers/mmc/tangier_sdhci.c | 1 - drivers/mmc/tegra_mmc.c | 1 - drivers/mmc/tmio-common.c | 1 - drivers/mmc/uniphier-sd.c | 1 - drivers/mmc/xenon_sdhci.c | 1 - drivers/mmc/zynq_sdhci.c | 1 - 62 files changed, 5 insertions(+), 62 deletions(-) diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index ffb461c2f6c1..48fac7a11b48 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index cecc7ad783d0..f00b0ff0dc95 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -11,7 +11,6 @@ /* #define DEBUG */ -#include "common.h" #include #include #include diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c index c9626c6beb8f..87a6f66ebb37 100644 --- a/drivers/mmc/aspeed_sdhci.c +++ b/drivers/mmc/aspeed_sdhci.c @@ -4,7 +4,6 @@ * Eddie James */ -#include #include #include #include diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c index d92bad97b71e..0b265196f025 100644 --- a/drivers/mmc/atmel_sdhci.c +++ b/drivers/mmc/atmel_sdhci.c @@ -4,7 +4,6 @@ * Wenyou.Yang */ -#include #include #include #include diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c index 5e48394fd0fb..598a51d914a9 100644 --- a/drivers/mmc/bcm2835_sdhci.c +++ b/drivers/mmc/bcm2835_sdhci.c @@ -36,7 +36,6 @@ * Inspired by sdhci-pci.c, by Pierre Ossman */ -#include #include #include #include diff --git a/drivers/mmc/bcm2835_sdhost.c b/drivers/mmc/bcm2835_sdhost.c index 5c23c03d10d7..720127468d37 100644 --- a/drivers/mmc/bcm2835_sdhost.c +++ b/drivers/mmc/bcm2835_sdhost.c @@ -30,7 +30,6 @@ * sdhci.c and sdhci-pci.c by Pierre Ossman */ #include -#include #include #include #include diff --git
Re: [PATCH 33/81] gpio: Remove and add needed includes
On 2024/5/2 09:30, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Tom Rini Cc: Matthias Brugger Cc: Peter Robinson Cc: Alex Nemirovsky Cc: Ryan Chen Cc: Chia-Wei Wang Cc: Aspeed BMC SW team Cc: Joel Stanley Cc: Nobuhiro Iwamatsu Cc: Marek Vasut Cc: Kunihiko Hayashi Cc: Dai Okamura Cc: Michal Simek Cc: Eugeniy Paltsev Cc: Gregory CLEMENT Cc: Lars Povlsen Cc: Horatiu Vultur Cc: Caleb Connolly Cc: Neil Armstrong Cc: Sumit Garg Cc: Stefan Roese Cc: Stephan Gerhold Cc: Linus Walleij Cc: Stefan Bosch Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Michael Walle Cc: Patrick Delaunay Cc: Patrice Chotard Cc: Thierry Reding Cc: Svyatoslav Ryhel Cc: Sean Anderson Cc: Andre Przywara Cc: Qu Wenruo Cc: Ilias Apalodimas Cc: Heiko Schocher Cc: Peng Fan Cc: Bin Meng Cc: Piotr Wojtaszczyk Cc: Jim Liu Cc: Nishanth Menon Cc: Samuel Holland Cc: Sam Edwards --- drivers/gpio/74x164_gpio.c | 1 - drivers/gpio/altera_pio.c | 1 - drivers/gpio/at91_gpio.c| 1 - drivers/gpio/atmel_pio4.c | 1 - drivers/gpio/axp_gpio.c | 1 - drivers/gpio/bcm2835_gpio.c | 1 - drivers/gpio/bcm6345_gpio.c | 1 - drivers/gpio/cortina_gpio.c | 1 - drivers/gpio/da8xx_gpio.c | 1 - drivers/gpio/ftgpio010.c| 1 - drivers/gpio/gpio-aspeed.c | 1 - drivers/gpio/gpio-fxl6408.c | 1 - drivers/gpio/gpio-rcar.c| 1 - drivers/gpio/gpio-rza1.c| 1 - drivers/gpio/gpio-uclass.c | 1 - drivers/gpio/gpio-uniphier.c| 1 - drivers/gpio/gpio_slg7xl45106.c | 1 - drivers/gpio/hi6220_gpio.c | 1 - drivers/gpio/hsdk-creg-gpio.c | 1 - drivers/gpio/imx_rgpio2p.c | 1 - drivers/gpio/intel_broadwell_gpio.c | 1 - drivers/gpio/intel_gpio.c | 1 - drivers/gpio/intel_ich6_gpio.c | 1 - drivers/gpio/iproc_gpio.c | 1 - drivers/gpio/kw_gpio.c | 1 - drivers/gpio/lpc32xx_gpio.c | 1 - drivers/gpio/max7320_gpio.c | 1 - drivers/gpio/mcp230xx_gpio.c| 1 - drivers/gpio/mpc83xx_spisel_boot.c | 1 - drivers/gpio/mpc8xx_gpio.c | 1 - drivers/gpio/mpc8xxx_gpio.c | 1 - drivers/gpio/mscc_sgpio.c | 1 - drivers/gpio/msm_gpio.c | 1 - drivers/gpio/mt7621_gpio.c | 1 - drivers/gpio/mvebu_gpio.c | 1 - drivers/gpio/mxc_gpio.c | 1 - drivers/gpio/mxs_gpio.c | 1 - drivers/gpio/nmk_gpio.c | 1 - drivers/gpio/npcm_gpio.c| 1 - drivers/gpio/nx_gpio.c | 1 - drivers/gpio/omap_gpio.c| 1 - drivers/gpio/pca953x.c | 3 ++- drivers/gpio/pca953x_gpio.c | 1 - drivers/gpio/pcf8575_gpio.c | 1 - drivers/gpio/pic32_gpio.c | 1 - drivers/gpio/qcom_pmic_gpio.c | 1 - drivers/gpio/qe_gpio.c | 1 - drivers/gpio/rk_gpio.c | 1 - drivers/gpio/s5p_gpio.c | 1 - drivers/gpio/sandbox.c | 1 - drivers/gpio/sandbox_test.c | 1 - drivers/gpio/sh_pfc.c | 1 - drivers/gpio/sifive-gpio.c | 1 - drivers/gpio/sl28cpld-gpio.c| 1 - drivers/gpio/stm32_gpio.c | 1 - drivers/gpio/sunxi_gpio.c | 1 - drivers/gpio/tca642x.c | 2 +- drivers/gpio/tegra186_gpio.c| 1 - drivers/gpio/tegra_gpio.c | 1 - drivers/gpio/vybrid_gpio.c | 1 - drivers/gpio/xilinx_gpio.c | 1 - drivers/gpio/zynq_gpio.c| 1 - drivers/gpio/zynqmp_gpio_modepin.c | 1 - 63 files changed, 3 insertions(+), 63 deletions(-) diff --git a/drivers/gpio/74x164_gpio.c b/drivers/gpio/74x164_gpio.c index 7a7cfe86114b..331428ccdb9a 100644 --- a/drivers/gpio/74x164_gpio.c +++ b/drivers/gpio/74x164_gpio.c @@ -8,7 +8,6 @@ * */ -#include #include #include #include diff --git a/drivers/gpio/altera_pio.c b/drivers/gpio/altera_pio.c index edc5a8093b0c..7ba1595e4ae3 100644 --- a/drivers/gpio/altera_pio.c +++ b/drivers/gpio/altera_pio.c @@ -4,7 +4,6 @@ * Copyright (C) 2011 Missing Link Electronics * Joachim Foerster */ -#include #include #include #include diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index f80f4afd24ff..50a698159075 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c index be1dd752bf76..65d064b46dfb 100644 --- a/drivers/gpio/atmel_pio4.c +++ b/drivers/gpio/atmel_pio4.c @@ -5,7 +5,6 @@ * Copyright (C) 2015 Atmel Corporation * Wenyou.Yang */ -#include #include
Re: [PATCH 19/81] clk: Remove and add needed includes
On 2024/5/2 09:30, Tom Rini wrote: Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Lukasz Majewski Cc: Sean Anderson Cc: Tom Rini Cc: Ryan Chen Cc: Chia-Wei Wang Cc: Aspeed BMC SW team Cc: Joel Stanley Cc: Eugeniy Paltsev Cc: Simon Glass Cc: Michal Simek Cc: Liviu Dudau Cc: Ryder Lee Cc: Weijie Gao Cc: Chunfeng Yun Cc: GSS_MTK_Uboot_upstream Cc: Neil Armstrong Cc: Mario Six Cc: Stefan Roese Cc: Manivannan Sadhasivam Cc: Caleb Connolly Cc: Sumit Garg Cc: Philipp Tomsich Cc: Kever Yang Cc: Patrick Delaunay Cc: Patrice Chotard Cc: Jagan Teki Cc: Andre Przywara Cc: Thierry Reding Cc: Svyatoslav Ryhel Cc: Kunihiko Hayashi Cc: Dai Okamura Cc: Eugen Hristev Cc: Igor Prusov Cc: Stefan Bosch Cc: Francois Berder Cc: Johan Jonker Cc: Minkyu Kang Cc: Chanho Park Cc: Sam Protsenko Cc: Konrad Dybcio Cc: Volodymyr Babchuk Cc: Torsten Duwe Cc: Hal Feng Cc: Leo Yu-Chi Liang Cc: Xingyu Wu Cc: Hoegeun Kwon Cc: Vishal Mahaveer Cc: Nishanth Menon Cc: Bryan Brattlof Cc: Hari Nagalla Cc: Apurva Nandan Cc: Neha Malcom Francis Cc: Udit Kumar --- drivers/clk/altera/clk-agilex.c | 1 - drivers/clk/altera/clk-arria10.c | 1 - drivers/clk/altera/clk-mem-n5x.c | 1 - drivers/clk/altera/clk-n5x.c | 1 - drivers/clk/aspeed/clk_ast2500.c | 1 - drivers/clk/aspeed/clk_ast2600.c | 1 - drivers/clk/at91/clk-generic.c | 1 - drivers/clk/at91/clk-main.c | 1 - drivers/clk/at91/clk-master.c| 1 - drivers/clk/at91/clk-peripheral.c| 1 - drivers/clk/at91/clk-programmable.c | 1 - drivers/clk/at91/clk-sam9x60-pll.c | 1 - drivers/clk/at91/clk-system.c| 1 - drivers/clk/at91/clk-utmi.c | 1 - drivers/clk/at91/compat.c| 2 +- drivers/clk/at91/pmc.c | 1 - drivers/clk/at91/sam9x60.c | 1 - drivers/clk/at91/sama7g5.c | 1 - drivers/clk/at91/sckc.c | 1 - drivers/clk/clk-cdce9xx.c| 1 - drivers/clk/clk-composite.c | 1 - drivers/clk/clk-divider.c| 1 - drivers/clk/clk-fixed-factor.c | 1 - drivers/clk/clk-gate.c | 1 - drivers/clk/clk-hsdk-cgu.c | 1 - drivers/clk/clk-mux.c| 1 - drivers/clk/clk-uclass.c | 1 - drivers/clk/clk-xlnx-clock-wizard.c | 1 - drivers/clk/clk.c| 1 - drivers/clk/clk_bcm6345.c| 1 - drivers/clk/clk_boston.c | 1 - drivers/clk/clk_fixed_factor.c | 1 - drivers/clk/clk_fixed_rate.c | 1 - drivers/clk/clk_k210.c | 1 - drivers/clk/clk_pic32.c | 1 - drivers/clk/clk_sandbox.c| 1 - drivers/clk/clk_sandbox_ccf.c| 1 - drivers/clk/clk_sandbox_test.c | 1 - drivers/clk/clk_scmi.c | 1 - drivers/clk/clk_versaclock.c | 1 - drivers/clk/clk_versal.c | 1 - drivers/clk/clk_vexpress_osc.c | 1 - drivers/clk/clk_zynq.c | 1 - drivers/clk/clk_zynqmp.c | 1 - drivers/clk/exynos/clk-exynos7420.c | 1 - drivers/clk/ics8n3qv01.c | 1 - drivers/clk/imx/clk-composite-8m.c | 1 - drivers/clk/imx/clk-composite-93.c | 1 - drivers/clk/imx/clk-fracn-gppll.c| 1 - drivers/clk/imx/clk-gate-93.c| 1 - drivers/clk/imx/clk-gate2.c | 1 - drivers/clk/imx/clk-imx6q.c | 1 - drivers/clk/imx/clk-imx8.c | 1 - drivers/clk/imx/clk-imx8mm.c | 1 - drivers/clk/imx/clk-imx8mn.c | 1 - drivers/clk/imx/clk-imx8mp.c | 1 - drivers/clk/imx/clk-imx8mq.c | 1 - drivers/clk/imx/clk-imx8qm.c | 1 - drivers/clk/imx/clk-imx8qxp.c| 1 - drivers/clk/imx/clk-imx93.c | 1 - drivers/clk/imx/clk-imxrt1020.c | 1 - drivers/clk/imx/clk-imxrt1050.c | 1 - drivers/clk/imx/clk-imxrt1170.c | 1 - drivers/clk/imx/clk-pfd.c| 1 - drivers/clk/imx/clk-pll14xx.c| 1 - drivers/clk/imx/clk-pllv3.c | 1 - drivers/clk/intel/clk_intel.c| 1 - drivers/clk/mediatek/clk-mt7622.c| 1 - drivers/clk/mediatek/clk-mt7623.c| 1 - drivers/clk/mediatek/clk-mt7629.c| 1 - drivers/clk/mediatek/clk-mt8183.c| 1 - drivers/clk/mediatek/clk-mt8512.c| 1 - drivers/clk/mediatek/clk-mt8516.c| 1 - drivers/clk/mediatek/clk-mt8518.c| 1 - drivers/clk/mediatek/clk-mtk.c | 1 - drivers/clk/meson/a1.c | 1 - drivers/clk/meson/axg-ao.c | 1 - drivers/clk
Re: [PATCH 14/81] block: Remove and add needed includes
On 2024/5/2 09:30, Tom Rini wrote:
Remove from this driver directory and when needed
add missing include files directly.
Signed-off-by: Tom Rini
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Cc: Tom Rini
Cc: Tobias Waldekranz
Cc: Simon Glass
Cc: Heinrich Schuchardt
Cc: Marek Vasut
Cc: Bin Meng
Cc: Johan Jonker
Cc: Kever Yang
Cc: Dan Carpenter
Cc: Mattijs Korpershoek
---
drivers/block/blk-uclass.c | 1 -
drivers/block/blk_legacy.c | 1 -
drivers/block/blkcache.c | 1 -
drivers/block/blkmap.c | 1 -
drivers/block/efi-media-uclass.c | 1 -
drivers/block/efi_blk.c | 1 -
drivers/block/host-uclass.c | 1 -
drivers/block/host_dev.c | 1 -
drivers/block/ide.c | 1 -
drivers/block/sandbox.c | 1 -
drivers/block/sb_efi_media.c | 1 -
11 files changed, 11 deletions(-)
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index 77066da352a3..512c952f4d7a 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_BLK
-#include
#include
#include
#include
diff --git a/drivers/block/blk_legacy.c b/drivers/block/blk_legacy.c
index 5bf1d0471524..f36932183d1f 100644
--- a/drivers/block/blk_legacy.c
+++ b/drivers/block/blk_legacy.c
@@ -4,7 +4,6 @@
* Written by Simon Glass
*/
-#include
#include
#include
#include
diff --git a/drivers/block/blkcache.c b/drivers/block/blkcache.c
index 26bcbea43533..0e69160249c7 100644
--- a/drivers/block/blkcache.c
+++ b/drivers/block/blkcache.c
@@ -4,7 +4,6 @@
* Author: Eric Nelson
*
*/
-#include
#include
#include
#include
diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c
index 21201409ed4b..34eed1380dca 100644
--- a/drivers/block/blkmap.c
+++ b/drivers/block/blkmap.c
@@ -4,7 +4,6 @@
* Author: Tobias Waldekranz
*/
-#include
#include
#include
#include
diff --git a/drivers/block/efi-media-uclass.c b/drivers/block/efi-media-uclass.c
index e012f6f2f4c4..dc5e4f59b7f3 100644
--- a/drivers/block/efi-media-uclass.c
+++ b/drivers/block/efi-media-uclass.c
@@ -5,7 +5,6 @@
* Copyright 2021 Google LLC
*/
-#include
#include
UCLASS_DRIVER(efi_media) = {
diff --git a/drivers/block/efi_blk.c b/drivers/block/efi_blk.c
index 917a19f60254..9766cd6f8327 100644
--- a/drivers/block/efi_blk.c
+++ b/drivers/block/efi_blk.c
@@ -8,7 +8,6 @@
* Copyright 2021 Google LLC
*/
-#include
#include
#include
#include
diff --git a/drivers/block/host-uclass.c b/drivers/block/host-uclass.c
index b3647e3ce335..cf42bd1e07ac 100644
--- a/drivers/block/host-uclass.c
+++ b/drivers/block/host-uclass.c
@@ -9,7 +9,6 @@
#define LOG_CATEGORY UCLASS_HOST
-#include
#include
#include
#include
diff --git a/drivers/block/host_dev.c b/drivers/block/host_dev.c
index 52313435a0cb..b3ff3cd1fab9 100644
--- a/drivers/block/host_dev.c
+++ b/drivers/block/host_dev.c
@@ -9,7 +9,6 @@
#define LOG_CATEGORY UCLASS_HOST
-#include
#include
#include
#include
diff --git a/drivers/block/ide.c b/drivers/block/ide.c
index c698f9cbd558..b16623d7a3ab 100644
--- a/drivers/block/ide.c
+++ b/drivers/block/ide.c
@@ -6,7 +6,6 @@
#define LOG_CATEGORY UCLASS_IDE
-#include
#include
#include
#include
diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
index be4e02cb601a..ec34f1ad8c2e 100644
--- a/drivers/block/sandbox.c
+++ b/drivers/block/sandbox.c
@@ -3,7 +3,6 @@
* Copyright (C) 2013 Henrik Nordstrom
*/
-#include
#include
#include
#include
diff --git a/drivers/block/sb_efi_media.c b/drivers/block/sb_efi_media.c
index 52af155a6001..3255db064961 100644
--- a/drivers/block/sb_efi_media.c
+++ b/drivers/block/sb_efi_media.c
@@ -5,7 +5,6 @@
* Copyright 2021 Google LLC
*/
-#include
#include
static const struct udevice_id sandbox_efi_media_ids[] = {
Re: [PATCH v2] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module
Hi Quentin, On 2024/5/8 16:34, Quentin Schulz wrote: Hi Kever, On 5/8/24 4:42 AM, Kever Yang wrote: Hi Quentin, Could you please update this patch with OF_UPSTREAM support? No, I cannot yet :/ Tiger is only available in Linux kernel v6.9-rcX and dts/ in U-Boot is currently at v6.8. I see, then we may need to support the board without OF_UPSTREAM during the dts is available in kernel tree but not available in U-Boot dts/upstream. What are we supposed to do for this then? Would bumping dts/ to an -rc tag be ok for U-Boot? Hi Tom, What's policy of the dts/upstream suppose to update? This is the typical issue there is gap between the dts merge in mainline kernel and available in next release. Thanks, - Kever After all, those are rc and not "stable" branches. Do we need to wait for the actual kernel release before bumping dts/ (so wait for up to 2 months before supporting a board in U-Boot)? Should we have an intermediate solution where we use the "old" model (NOT OF_UPSTREAM) until we bump dts/ to the latest kernel release and the DTS is available through OF_UPSTREAM? Cheers, Quentin
Re: [PATCH] board: rockchip: add ArmSoM Sige7 Rk3588 board
Hi Jianfeng,
On 2024/5/5 01:05, Jianfeng Liu wrote:
ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) by
ArmSoM.
There are two variants depending on the DRAM size : 8G and 16G.
Specification:
Rockchip Rk3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
8/16GB memory LPDDR4x
Mali G610MC4 GPU
2x MIPI CSI 2 multiple lanes connector
64GB/128GB on board eMMC
uSD slot
1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C
1x HDMI 2.1 output
2x 2.5 Gbps Ethernet port
40-pin IO header including UART, SPI and I2C
USB PD over USB Type-C
Size: 92mm x 62mm
Kernel commit:
81c828a67c78 (arm64: dts: rockchip: Add ArmSom Sige7 board)
Note that these commits:
- e18e5e8188f2 (arm64: dts: rockchip: add USBDP phys on rk3588)
- 6fca4edb93d3 (arm64: dts: rockchip: Add rk3588 GPU node)
are not synced to u-boot, so I remove usb3 drd nodes and gpu from kernel
devicetree.
Signed-off-by: Jianfeng Liu
---
MAINTAINERS | 1 +
arch/arm/dts/Makefile| 1 +
arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi | 31 +
arch/arm/dts/rk3588-armsom-sige7.dts | 691 +++
We have enable OF_UPSTREAM which is using dts from
dts/upstream/src/arm64/rockchip/,
please update to use OF_UPSTREAM so that we will easy to keep sync the dts.
Thanks,
- Kever
arch/arm/mach-rockchip/rk3588/Kconfig| 26 +
board/armsom/sige7-rk3588/Kconfig| 12 +
board/armsom/sige7-rk3588/MAINTAINERS| 8 +
configs/sige7-rk3588_defconfig | 104 +++
doc/board/rockchip/rockchip.rst | 1 +
include/configs/sige7-rk3588.h | 15 +
10 files changed, 890 insertions(+)
create mode 100644 arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3588-armsom-sige7.dts
create mode 100644 board/armsom/sige7-rk3588/Kconfig
create mode 100644 board/armsom/sige7-rk3588/MAINTAINERS
create mode 100644 configs/sige7-rk3588_defconfig
create mode 100644 include/configs/sige7-rk3588.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 7a3b4d3712..52367bf38c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -532,6 +532,7 @@ F: arch/arm/dts/rv11*
F:arch/arm/include/asm/arch-rockchip/
F:arch/arm/mach-rockchip/
F:board/amarula/vyasa-rk3288/
+F: board/armsom/sige7-rk3588/
F:board/anbernic/rgxx3_rk3566/
F:board/chipspark/popmetal_rk3288
F:board/engicam/px30_core/
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c9f1b25ad6..040238dede 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -166,6 +166,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
+ rk3588-armsom-sige7.dtb \
rk3588s-coolpi-4b.dtb \
rk3588-coolpi-cm5-evb.dtb \
rk3588-edgeble-neu6a-io.dtb \
diff --git a/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
new file mode 100644
index 00..b9196ba5f5
--- /dev/null
+++ b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 ArmSoM Technology Co., Ltd.
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
+&usbdp_phy1 {
+ status = "okay";
+};
+
+&usbdp_phy1_u3 {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-armsom-sige7.dts
b/arch/arm/dts/rk3588-armsom-sige7.dts
new file mode 100644
index 00..c7b46536ec
--- /dev/null
+++ b/arch/arm/dts/rk3588-armsom-sige7.dts
@@ -0,0 +1,691 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include
+#include
+#include "rk3588.dtsi"
+
+/ {
+ model = "ArmSoM Sige7";
+ compatible = "armsom,sige7", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ analog-sound {
+ compatible = "audio-graph-card";
+ dais = <&i2s0_8ch_p0>;
+ label = "rk3588-es8316";
+ hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_rgb_g>;
+
+ led_green: led-0 {
+ color = ;
+
Re: [PATCH V3] board: rockchip: add Powkiddy X55
On 2024/5/3 05:40, Chris Morgan wrote:
From: Chris Morgan
The Powkiddy X55 is a Rockchip RK3566 based handheld gaming device.
UART, ADC, eMMC, and SDMMC are tested to work in U-Boot and this
successfully boots mainline Linux.
Kernel commit:
e99adc97e21a ("arm64: dts: rockchip: Add Powkiddy X55")
Signed-off-by: Chris Morgan
---
Changes since V2:
- Refactored to use the upstream device tree from Linux.
- Removed logic for handling the adc button and instead simply try to
boot from sdmmc0 as a valid target first.
---
arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi | 9 +++
arch/arm/mach-rockchip/rk3568/Kconfig| 6 ++
board/powkiddy/x55/Kconfig | 15 +
board/powkiddy/x55/MAINTAINERS | 7 +++
board/powkiddy/x55/Makefile | 6 ++
board/powkiddy/x55/x55.c | 39 +
configs/powkiddy-x55-rk3566_defconfig| 59
doc/board/rockchip/rockchip.rst | 1 +
include/configs/powkiddy-x55-rk3566.h| 12
9 files changed, 154 insertions(+)
create mode 100644 arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
create mode 100644 board/powkiddy/x55/Kconfig
create mode 100644 board/powkiddy/x55/MAINTAINERS
create mode 100644 board/powkiddy/x55/Makefile
create mode 100644 board/powkiddy/x55/x55.c
create mode 100644 configs/powkiddy-x55-rk3566_defconfig
create mode 100644 include/configs/powkiddy-x55-rk3566.h
diff --git a/arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
b/arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
new file mode 100644
index 00..c440201ec7
--- /dev/null
+++ b/arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = &sdmmc0, &sdmmc1, &sdhci;
+ };
+};
diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig
b/arch/arm/mach-rockchip/rk3568/Kconfig
index af537d912a..014ebf9f0b 100644
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -22,6 +22,11 @@ config TARGET_ODROID_M1_RK3568
help
Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC.
+config TARGET_POWKIDDY_X55_RK3566
+ bool "Powkiddy X55"
+ help
+ Powkiddy X55 handheld gaming console with an RK3566 SoC.
+
config TARGET_QUARTZ64_RK3566
bool "Pine64 Quartz64"
help
@@ -48,5 +53,6 @@ source "board/rockchip/evb_rk3568/Kconfig"
source "board/anbernic/rgxx3_rk3566/Kconfig"
source "board/hardkernel/odroid_m1/Kconfig"
source "board/pine64/quartz64_rk3566/Kconfig"
+source "board/powkiddy/x55/Kconfig"
endif
diff --git a/board/powkiddy/x55/Kconfig b/board/powkiddy/x55/Kconfig
new file mode 100644
index 00..a7b3ed4d0d
--- /dev/null
+++ b/board/powkiddy/x55/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_POWKIDDY_X55_RK3566
+
+config SYS_BOARD
+ default "x55"
+
+config SYS_VENDOR
+ default "powkiddy"
+
+config SYS_CONFIG_NAME
+ default "powkiddy-x55-rk3566"
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+
+endif
diff --git a/board/powkiddy/x55/MAINTAINERS b/board/powkiddy/x55/MAINTAINERS
new file mode 100644
index 00..01ae8da19d
--- /dev/null
+++ b/board/powkiddy/x55/MAINTAINERS
@@ -0,0 +1,7 @@
+X55
+M: Chris Morgan
+S: Maintained
+F: board/powkiddy/x55
+F: include/configs/powkiddy-x55-rk3566.h
+F: configs/powkiddy-x55-rk3566_defconfig
+F: arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
diff --git a/board/powkiddy/x55/Makefile b/board/powkiddy/x55/Makefile
new file mode 100644
index 00..55c8c16aa1
--- /dev/null
+++ b/board/powkiddy/x55/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2023 Chris Morgan
+#
+
+obj-y += x55.o
diff --git a/board/powkiddy/x55/x55.c b/board/powkiddy/x55/x55.c
new file mode 100644
index 00..b2703e6382
--- /dev/null
+++ b/board/powkiddy/x55/x55.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Chris Morgan
+ */
+
+#include
+
+#define GPIO4_BASE 0xfe77
+#define GPIO_SWPORT_DR_L 0x
+#define GPIO_SWPORT_DDR_L 0x0008
+#define GPIO_B4BIT(12)
+#define GPIO_B5BIT(13)
+#define GPIO_B6BIT(14)
+
+#define GPIO_WRITEMASK(bits) ((bits) << 16)
+
+/*
+ * Start LED very early so user knows device is on. Set color
+ * to red.
+ */
+void spl_board_init(void)
+{
+ /* Set GPIO4_B4, GPIO4_B5, and GPIO4_B6 to output. */
+ writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | \
+ (GPIO_B6 | GPIO_B5 | GPIO_B4),
+ (GPIO4_BASE + GPIO_SWPORT_DDR_L));
+ /* Set GPIO4_B5 and GPIO4_B6 to 0 and GPIO4_B4 to 1. */
+ writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | GPIO_B4,
+ (GPIO4_BASE + GPIO_SWPORT_DR_L));
+}
+
+int rk_board_late_i
Re: [PATCH V2] board: rockchip: Add Indiedroid Nova
On 2024/5/3 02:57, Chris Morgan wrote:
From: Chris Morgan
The Indiedroid Nova is a Rockchip RK3588S based SBC from Indiedroid.
Specifications:
Rockchip RK3588S SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
Optional eMMC
2x USB 2.0, 2x USB 3.0, 1x USB 3.0 C port with DP Alt
1x MIPI-CSI Port (4-lane or 2x 2-lane)
1x MIPI-DSI 4-lane connector
1x Micro HDMI 2.1 output, 1x DP 1.4 output
Gigabit Ethernet
Realtek RTL8821CS WiFi
4 pin debug UART connector
40 pin GPIO header
Size: 85mm x 56mm (Raspberry Pi Form Factor)
Kernel commit:
3900160e164b ("arm64: dts: rockchip: Add Indiedroid Nova board")
Signed-off-by: Chris Morgan
---
Changes since V1:
- Refactored to use the upstream Linux device tree now that that is
an option.
- Added board to doc/board/rockchip/rockchip.rst.
---
arch/arm/mach-rockchip/rk3588/Kconfig | 10
board/indiedroid/nova/Kconfig | 12 +
board/indiedroid/nova/MAINTAINERS | 6 +++
configs/nova-rk3588s_defconfig| 70 +++
doc/board/rockchip/rockchip.rst | 1 +
include/configs/nova-rk3588s.h| 15 ++
6 files changed, 114 insertions(+)
create mode 100644 board/indiedroid/nova/Kconfig
create mode 100644 board/indiedroid/nova/MAINTAINERS
create mode 100644 configs/nova-rk3588s_defconfig
create mode 100644 include/configs/nova-rk3588s.h
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig
b/arch/arm/mach-rockchip/rk3588/Kconfig
index 39049ab35a..820e979abb 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -78,6 +78,15 @@ config TARGET_NANOPCT6_RK3588
Power: 5.5*2.1mm DC Jack, 12VDC input
Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case)
+config TARGET_NOVA_RK3588
+ bool "Indiedroid Nova RK3588"
+ select BOARD_LATE_INIT
+ help
+ Indiedroid Nova is a Rockchip RK3588s based SBC by Indiedroid.
+ It comes in configurations from 4GB of RAM to 16GB of RAM,
+ includes socket for eMMC storage, an SDMMC slot, and a 40-pin
+ GPIO header for expansion.
+
config TARGET_RK3588_NEU6
bool "Edgeble Neural Compute Module 6(Neu6) SoM"
select BOARD_LATE_INIT
@@ -223,6 +232,7 @@ config TEXT_BASE
source "board/edgeble/neural-compute-module-6/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
+source "board/indiedroid/nova/Kconfig"
source "board/pine64/quartzpro64-rk3588/Kconfig"
source "board/turing/turing-rk1-rk3588/Kconfig"
source "board/radxa/rock5a-rk3588s/Kconfig"
diff --git a/board/indiedroid/nova/Kconfig b/board/indiedroid/nova/Kconfig
new file mode 100644
index 00..271d15a0ed
--- /dev/null
+++ b/board/indiedroid/nova/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NOVA_RK3588
+
+config SYS_BOARD
+ default "nova-rk3588s"
+
+config SYS_VENDOR
+ default "indiedroid"
+
+config SYS_CONFIG_NAME
+ default "nova-rk3588s"
+
+endif
diff --git a/board/indiedroid/nova/MAINTAINERS
b/board/indiedroid/nova/MAINTAINERS
new file mode 100644
index 00..9c56d01bf0
--- /dev/null
+++ b/board/indiedroid/nova/MAINTAINERS
@@ -0,0 +1,6 @@
+INDIEDROID-NOVA-RK3588
+M: Chris Morgan
+S: Maintained
+F: board/indiedroid/nova
+F: include/configs/nova-rk3588s.h
+F: configs/indiedroid-nova-rk3588_defconfig
diff --git a/configs/nova-rk3588s_defconfig b/configs/nova-rk3588s_defconfig
new file mode 100644
index 00..231831fb55
--- /dev/null
+++ b/configs/nova-rk3588s_defconfig
@@ -0,0 +1,70 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=2400
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-indiedroid-nova"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_NOVA_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB5
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-indiedroid-nova.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_UPSTREAM=y
The OF_UPSTREAM already enabled for ROCKCHIP_RK3588, so no need here,
please help to rebase on latest code.
Thanks,
- Kever
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks
assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_R
Re: [PATCH v2] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module
Hi Quentin,
Could you please update this patch with OF_UPSTREAM support?
Thanks,
- Kever
On 2024/4/23 18:18, Quentin Schulz wrote:
From: Quentin Schulz
The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3588.
It provides the following feature set:
* up to 16GB LPDDR4x
* on-module eMMC
* SD card (on a baseboard) via edge connector
* Gigabit Ethernet with on-module GbE PHY
* HDMI/eDP
* MIPI-DSI
* 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
* HDMI input over FPC connector
* CAN
* USB
- 1x USB 3.0 dual-role (direct connection)
- 2x USB 3.0 host + 1x USB 2.0 host
* PCIe
- 1x PCIe 2.1 Gen3, 4 lanes
- 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
* on-module ATtiny816 companion controller, implementing:
- low-power RTC functionality (ISL1208 emulation)
- fan controller (AMC6821 emulation)
* on-module Secure Element with Global Platform 2.2.1 compliant
JavaCard environment
The support is added for Tiger on Haikou devkit, similarly to RK3399
Puma and PX30 Ringneck.
The DTS and DTSI are taken from upstream Linux kernel v6.9-rc4.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
This has a light dependency on
https://lore.kernel.org/u-boot/20240415-rk35xx-dram-atags-v3-0-5bc5475b3...@theobroma-systems.com/
(the Tiger defconfig can be updated to remove the dependency if required)
To: Tom Rini
To: Klaus Goger
To: Heiko Stuebner
To: Simon Glass
To: Philipp Tomsich
To: Kever Yang
Cc: u-boot@lists.denx.de
Signed-off-by: Quentin Schulz
Changes in v2:
- removed uart controller muxing patch as not necessary until we get
open-source DRAM init,
- disabled DEBUG_UART_BOARD_INIT as it's only used for muxing the UART
controller and it's not necessary since DDR bin does this for us
already,
- added missing uart2 mux bootph in U-Boot dtsi (though not required
yet),
- switched to USB_DWC3_GENERIC from USB_XHCI_DWC3 as requested by Jonas,
- Link to v1:
https://lore.kernel.org/r/20240422-tiger-v1-0-8816b070d...@theobroma-systems.com
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi | 59 ++
arch/arm/dts/rk3588-tiger-haikou.dts | 266
arch/arm/dts/rk3588-tiger.dtsi | 690 +
arch/arm/mach-rockchip/rk3588/Kconfig | 31 +
board/theobroma-systems/tiger_rk3588/Kconfig | 16 +
board/theobroma-systems/tiger_rk3588/MAINTAINERS | 13 +
board/theobroma-systems/tiger_rk3588/Makefile | 10 +
.../theobroma-systems/tiger_rk3588/tiger_rk3588.c | 53 ++
configs/tiger-rk3588_defconfig | 114
doc/board/rockchip/rockchip.rst| 1 +
doc/board/theobroma-systems/index.rst | 1 +
doc/board/theobroma-systems/tiger_rk3588.rst | 102 +++
include/configs/tiger_rk3588.h | 15 +
14 files changed, 1372 insertions(+)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b1c9c6222e5..ef901642a0a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -180,6 +180,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-quartzpro64.dtb \
rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb \
+ rk3588-tiger-haikou.dtb \
rk3588-turing-rk1.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
diff --git a/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
new file mode 100644
index 000..bfcefe256b0
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+ };
+};
+
+&emmc_pwrseq {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_reset {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdhci {
+ /* U-Boot currently cannot handle anything below HS200 for eMMC on
RK3588 */
+ /delete-property/ mmc-ddr-1_8v;
+ /delete-property/ cap-mmc-highspeed;
+};
+
+/* Q7 USB P0 */
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
+&uart2m2_xfer {
+ bootph-all;
+};
+
+/* Q7 USB P0 */
+&usbdp_phy1 {
+ status = "okay";
+};
+
+&usbdp_phy1_u3 {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-tiger-haikou.dts
b/arch/arm/dts/rk3588-tiger-haikou.dts
new file mode 100644
index 000..d672198c6b6
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou.dts
@@
Pull request: u-boot-rockchip-20240507
Hi Tom, Please pull the updates for rockchip platform, this PR is mainly for: - migrate to use OF_UPSTREAM for rv1108, rk3308, rk3328, rk356x, rk3588; CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/20628 Thanks, - Kever The following changes since commit 52835266d3e933656a217233eaf672dd9ccd7352: Prepare v2024.07-rc2 (2024-05-06 13:54:17 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-20240507 for you to fetch changes up to bc7cb4b67a4070129bbfc5bffb2f5e9fd206991e: configs: rk3588-turing-rk1: disable SPI flash by default (2024-05-07 15:56:10 +0800) Fabio Estevam (1): rockchip: rv1108: Convert to OF_UPSTREAM Jonas Karlman (58): rockchip: rk3399-gru: Fix max SPL size on bob and kevin rockchip: rk3399-puma: Update SPL_PAD_TO Kconfig option rockchip: rk3399-puma: Use common bss and stack addresses rockchip: rk3399-ficus: Enable TPL and use common bss and stack addr rockchip: rk3399: Sort imply statements alphabetically rockchip: rk3399: Enable ARMv8 crypto and FIT checksum validation rockchip: rk3399: Enable random generator on all boards rockchip: rk3399: Imply support for GbE PHY rockchip: rk3399: Enable DT overlay support on all boards rockchip: rk3399: Remove use of xPL_MISC_DRIVERS options rockchip: rk3399: Add a default spl-boot-order prop rockchip: rk3399: Remove inherited bootph-all props rockchip: rk3399: Sort nodes in u-boot.dtsi files rockchip: rk3399: Fix bootph prop for vop nodes rockchip: rk3399-puma: Move uart0 bootph to board u-boot.dtsi rockchip: rk3399: Include uart related pinctrl nodes in TPL/SPL rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC rockchip: rk3399: Configure sdmmc regulator pinctrl in SPL clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support rockchip: rk3399: Sync SoC DT from Linux kernel v6.8 rockchip: rk3399-gru: Sync DT from Linux kernel v6.8 rockchip: rk3399-puma: Sync DT from Linux kernel v6.8 rockchip: rk3399-rock-pi-n10: Sync DT from v6.8 and update defconfig rockchip: rk3399-eaidk-610: Sync DT from v6.8 and update defconfig rockchip: rk3399-leez: Sync DT from v6.8 and update defconfig rockchip: rk3399-evb: Sync DT from v6.8 and update defconfig rockchip: rk3399-firefly: Sync DT from v6.8 and update defconfig rockchip: rk3399-orangepi: Sync DT from v6.8 and update defconfig rockchip: rk3399-roc-pc: Sync DT from v6.8 and update defconfig rockchip: rk3399-nanopi-4: Sync DT from v6.8 and update defconfig rockchip: rk3399-rock960: Sync DT from v6.8 and update defconfig rockchip: rk3399-khadas: Sync DT from v6.8 and update defconfig rockchip: rk3399-rock-pi-4: Sync DT from v6.8 and update defconfig rockchip: rk3399-rockpro64: Sync DT from v6.8 and update defconfig rockchip: rk3399-pinebook-pro: Sync DT from v6.8 and update defconfig rockchip: rk3399-pinephone-pro: Sync DT from v6.8 and update defconfig rockchip: rk3399: Drop ethernet0 alias from SoC u-boot.dtsi rockchip: rk3308: Migrate to OF_UPSTREAM rockchip: rk3308: Remove redundant device tree files rockchip: rk3328: Migrate to OF_UPSTREAM rockchip: rk3328: Remove redundant device tree files rockchip: rk3399: Migrate to OF_UPSTREAM rockchip: rk3399: Remove redundant device tree files rockchip: rk356x: Add rk3568-u-boot.dtsi rockchip: rk356x: Migrate to OF_UPSTREAM rockchip: rk356x: Remove redundant device tree files phy: rockchip: usbdp: Find phy-id from the io address phy: rockchip: usbdp: Drop rockchip_u3phy_uboot_init() phy: rockchip: usbdp: Adopt driver to work with upstream DT rockchip: rk3588-rock-5b: Drop usb-typec node from u-boot.dtsi rockchip: rk3588: Update USB3 related nodes in u-boot.dtsi rockchip: rk3588: Migrate to OF_UPSTREAM rockchip: rk3588: Remove redundant device tree files rockchip: rk3328: Add missing bootph-some-ram props clk: rockchip: rk3328: Add SCLK_USB3OTG_REF support Sam Edwards (1): configs: rk3588-turing-rk1: disable SPI flash by default arch/arm/dts/Makefile | 88 - arch/arm/dts/rk3288-vmarc-som.dtsi | 48 + arch/arm/dts/rk3308-evb.dts| 230 -- arch/arm/dts/rk3308-roc-cc.dts | 190 -- arch/arm/dts/rk3308-rock-pi-s.dts | 314 -- arch/arm/dts/rk3308.dtsi | 1888 --- arch/arm/dts/rk3328-evb.dts
Re: [PATCH 060/149] board: firefly: Remove and add needed includes
On 2024/5/1 10:41, Tom Rini wrote: Remove from this board vendor directory and when needed add missing include files directly. Signed-off-by: Tom Rini Reviewed-by: Kever Yang Thanks, - Kever --- Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Andy Yan Cc: Levin Du Cc: Suniel Mahesh --- board/firefly/firefly-rk3288/firefly-rk3288.c | 1 - board/firefly/firefly-rk3308/roc_cc_rk3308.c | 1 - board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 1 - 3 files changed, 3 deletions(-) diff --git a/board/firefly/firefly-rk3288/firefly-rk3288.c b/board/firefly/firefly-rk3288/firefly-rk3288.c index 95d8b00924d8..8e67ab4b1327 100644 --- a/board/firefly/firefly-rk3288/firefly-rk3288.c +++ b/board/firefly/firefly-rk3288/firefly-rk3288.c @@ -3,7 +3,6 @@ * (C) Copyright 2015 Google, Inc */ -#include #include #include #include diff --git a/board/firefly/firefly-rk3308/roc_cc_rk3308.c b/board/firefly/firefly-rk3308/roc_cc_rk3308.c index af00250e118d..404bdc632bbc 100644 --- a/board/firefly/firefly-rk3308/roc_cc_rk3308.c +++ b/board/firefly/firefly-rk3308/roc_cc_rk3308.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include #include #include #include diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c index 590519b32af2..a149e4fe822e 100644 --- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c +++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include #include #include #include
