[PATCH] env: sf: report malloc error to caller
In the non-redundant code for env_sf_save(), a failure to malloc() the
temporary buffer produces the following output:
Saving Environment to SPIFlash... OK
This is misleading as the flash has neither been erased nor written.
Fix it to return an error to the caller, so the output will be:
Saving Environment to SPIFlash... Failed (-12)
Note that there is another copy of env_sf_save() in the same file, for
handling redundant environment, and it already has the same logic.
Signed-off-by: Ralph Siemsen
---
env/sf.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/env/sf.c b/env/sf.c
index a425ecc11c8..8f5c03b00d3 100644
--- a/env/sf.c
+++ b/env/sf.c
@@ -210,8 +210,10 @@ static int env_sf_save(void)
saved_size = sect_size - CONFIG_ENV_SIZE;
saved_offset = CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE;
saved_buffer = malloc(saved_size);
- if (!saved_buffer)
+ if (!saved_buffer) {
+ ret = -ENOMEM;
goto done;
+ }
ret = spi_flash_read(env_flash, saved_offset,
saved_size, saved_buffer);
--
2.25.1
[PATCH v7 00/10] Renesas RZ/N1 SoC initial support
The RZ/N1 is a family of SoC devices from Renesas [1], featuring ARM Cortex-A7 and/or Cortex-M3 CPU, industrial ethernet protocols, integrated Ethernet switch, and numerous peripherals. This is a first step in upstreaming support for the RZ/N1 family. Currently it contains just enough to boot to the u-boot prompt. Additional patches will follow to support flash, SD, USB, Ethernet, etc. This work is based on a vendor-supplied u-boot 2017.01 tree [2], which supports several eval boards, none of which I have access to. Instead development has been done on a Schneider RZN1 board, which is fairly similar to the Renesas RZ/N1D-DB Demo board. [1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzn1 [2] https://github.com/renesas-rz/rzn1_u-boot/tree/rzn1-stable Changes in v7: - fix htmldocs warning - fix breakage of "dumpimage -l" - revert back to static allocation for config file data Changes in v6: - rebase to u-boot v2023.07-rc2 - add R-b tags Changes in v5: - rebase to u-boot v2023.04-1037-gb646e1f69f - many small changes in response to reviewer comments - move rzn1 into mach-rmobile (similar to existing rza1) - move board-specific DDR init to board dir Changes in v4: - rebase to u-boot v2023.04-rc3 - remove RFC prefix - cc entire series to Marek by request - clock tables synced with linux (pending patches) - documentation and comment improvements Changes in v3: - many tweaks to clock driver based on reviewer feedback - rebased to u-boot v2023.04-rc2 - reviewer suggestions added to spkgimage.c - many small cleanups, checkpatch, FIXMEs resolved Changes in v2: - rewrote the stand-alone spkg_utility to integrate into mkimage Ralph Siemsen (10): ARM: armv7: add non-SPL enable for Cortex SMPEN clk: renesas: prepare for non R-Car clock drivers clk: renesas: add R906G032 driver pinctrl: renesas: add R906G032 driver ram: cadence: add driver for Cadence EDAC ARM: dts: add devicetree for Renesas RZ/N1 SoC ARM: rmobile: Add support for Renesas RZ/N1 SoC board: schneider: add RZN1 board support tools: spkgimage: add Renesas SPKG format doc: renesas: add Renesas board docs arch/arm/cpu/armv7/Kconfig|5 + arch/arm/dts/r9a06g032-ddr.dtsi | 512 arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi | 23 + arch/arm/dts/r9a06g032-rzn1-snarc.dts | 92 ++ arch/arm/dts/r9a06g032.dtsi | 477 +++ arch/arm/mach-rmobile/Kconfig | 19 + arch/arm/mach-rmobile/Kconfig.rzn1| 20 + arch/arm/mach-rmobile/cpu_info.c | 10 +- board/schneider/rzn1-snarc/Kconfig| 18 + board/schneider/rzn1-snarc/Makefile |3 + board/schneider/rzn1-snarc/rzn1.c | 31 + board/schneider/rzn1-snarc/spkgimage.cfg | 26 + boot/image.c |1 + configs/rzn1_snarc_defconfig | 24 + doc/board/index.rst |1 + doc/board/renesas/index.rst | 10 + doc/board/renesas/renesas.rst | 45 + doc/board/renesas/rzn1.rst| 76 ++ doc/mkimage.1 | 45 + drivers/clk/renesas/Kconfig | 15 +- drivers/clk/renesas/Makefile |3 +- drivers/clk/renesas/r9a06g032-clocks.c| 1103 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/renesas/Kconfig |7 + drivers/pinctrl/renesas/Makefile |1 + drivers/pinctrl/renesas/pinctrl-rzn1.c| 379 ++ drivers/ram/Kconfig |1 + drivers/ram/Makefile |3 + drivers/ram/cadence/Kconfig | 12 + drivers/ram/cadence/Makefile |1 + drivers/ram/cadence/ddr_ctrl.c| 414 +++ drivers/ram/renesas/Makefile |3 + drivers/ram/renesas/rzn1/Makefile |3 + drivers/ram/renesas/rzn1/ddr_async.c | 376 ++ include/configs/rzn1-snarc.h | 13 + include/dt-bindings/clock/r9a06g032-sysctrl.h | 149 +++ include/dt-bindings/pinctrl/rzn1-pinctrl.h| 141 +++ include/image.h |1 + include/renesas/ddr_ctrl.h| 175 +++ include/renesas/is43tr16256a_125k_CTL.h | 419 +++ .../renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++ tools/Makefile|1 + tools/renesas_spkgimage.c | 336 + tools/renesas_spkgimage.h | 87 ++ 44 files changed, 5477 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/r9a06g032-ddr.dtsi create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc.dts create mode 100644 arch/arm/dts/r9a06g032.dtsi create mode 1
[PATCH v7 08/10] board: schneider: add RZN1 board support
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
(no changes since v6)
Changes in v6:
- move board-specific DDR init to drivers/ram/renesas/rzn1
- drop call to fdtdec_setup_mem_size_base()
- minor code cleanups
- use wait_for_bit macros instead of endless while loop
- in commit message fix Schneider Electronics -> Electric
Changes in v5:
- put all local DTS changes in r9a06g032-rzn1-snarc.dts
- move board-specific DDR init out of drivers/ram/cadence.
- tables of DDR paramters are now stored in devicetree
- support two different DDR memory types
- use BIT() macro
- obtain RZN1_DDR_BASE from DT
- uncomment error return when syscon fails
- make some functions static
Changes in v4:
- add binman support via r9a06g032-rzn1-snarc-u-boot.dtsi
Changes in v3:
- rename board LCES to rzn1-snarc
- move CONFIG_SYS_NS16550_MEM32 to Kconfig
- define CFG_SYS_INIT_RAM_{ADDR,SIZE}
- removed debug uart settings from defconfig
arch/arm/dts/r9a06g032-ddr.dtsi | 512 ++
arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi | 23 +
arch/arm/dts/r9a06g032-rzn1-snarc.dts | 92
board/schneider/rzn1-snarc/Kconfig| 18 +
board/schneider/rzn1-snarc/Makefile | 3 +
board/schneider/rzn1-snarc/rzn1.c | 31 ++
configs/rzn1_snarc_defconfig | 24 +
drivers/ram/Makefile | 1 +
drivers/ram/renesas/Makefile | 3 +
drivers/ram/renesas/rzn1/Makefile | 3 +
drivers/ram/renesas/rzn1/ddr_async.c | 376 +
include/configs/rzn1-snarc.h | 13 +
include/renesas/is43tr16256a_125k_CTL.h | 419 ++
.../renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++
14 files changed, 1917 insertions(+)
create mode 100644 arch/arm/dts/r9a06g032-ddr.dtsi
create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi
create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc.dts
create mode 100644 board/schneider/rzn1-snarc/Kconfig
create mode 100644 board/schneider/rzn1-snarc/Makefile
create mode 100644 board/schneider/rzn1-snarc/rzn1.c
create mode 100644 configs/rzn1_snarc_defconfig
create mode 100644 drivers/ram/renesas/Makefile
create mode 100644 drivers/ram/renesas/rzn1/Makefile
create mode 100644 drivers/ram/renesas/rzn1/ddr_async.c
create mode 100644 include/configs/rzn1-snarc.h
create mode 100644 include/renesas/is43tr16256a_125k_CTL.h
create mode 100644 include/renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h
diff --git a/arch/arm/dts/r9a06g032-ddr.dtsi b/arch/arm/dts/r9a06g032-ddr.dtsi
new file mode 100644
index 00..8c7d0873fe
--- /dev/null
+++ b/arch/arm/dts/r9a06g032-ddr.dtsi
@@ -0,0 +1,512 @@
+// SPDX-License-Identifier: GPL-2.0
+
+ cadence,ctl-000 = <
+ DENALI_CTL_00_DATA
+ DENALI_CTL_01_DATA
+ DENALI_CTL_02_DATA
+ DENALI_CTL_03_DATA
+ DENALI_CTL_04_DATA
+ DENALI_CTL_05_DATA
+ DENALI_CTL_06_DATA
+ DENALI_CTL_07_DATA
+ DENALI_CTL_08_DATA
+ DENALI_CTL_09_DATA
+
+ DENALI_CTL_10_DATA
+ DENALI_CTL_11_DATA
+ DENALI_CTL_12_DATA
+ DENALI_CTL_13_DATA
+ DENALI_CTL_14_DATA
+ DENALI_CTL_15_DATA
+ DENALI_CTL_16_DATA
+ DENALI_CTL_17_DATA
+ DENALI_CTL_18_DATA
+ DENALI_CTL_19_DATA
+
+ DENALI_CTL_20_DATA
+ DENALI_CTL_21_DATA
+ DENALI_CTL_22_DATA
+ DENALI_CTL_23_DATA
+ DENALI_CTL_24_DATA
+ DENALI_CTL_25_DATA
+ DENALI_CTL_26_DATA
+ DENALI_CTL_27_DATA
+ DENALI_CTL_28_DATA
+ DENALI_CTL_29_DATA
+
+ DENALI_CTL_30_DATA
+ DENALI_CTL_31_DATA
+ DENALI_CTL_32_DATA
+ DENALI_CTL_33_DATA
+ DENALI_CTL_34_DATA
+ DENALI_CTL_35_DATA
+ DENALI_CTL_36_DATA
+ DENALI_CTL_37_DATA
+ DENALI_CTL_38_DATA
+ DENALI_CTL_39_DATA
+
+ DENALI_CTL_40_DATA
+ DENALI_CTL_41_DATA
+ DENALI_CTL_42_DATA
+ DENALI_CTL_43_DATA
+ DENALI_CTL_44_DATA
+ DENALI_CTL_45_DATA
+ DENALI_CTL_46_DATA
+ DENALI_CTL_47_DATA
+ DENALI_CTL_48_DATA
+ DENALI_CTL_49_DATA
+
+ DENALI_CTL_50_DATA
+ DENALI_CTL_51_DATA
+ DENALI_CTL_52_DATA
+ DENALI_CTL_53_DATA
+ DENALI_CTL_54_DATA
+ DENALI_CTL_5
[PATCH v7 09/10] tools: spkgimage: add Renesas SPKG format
Renesas RZ/N1 devices contain BootROM code that loads a custom SPKG
image from QSPI, NAND or USB DFU. Support this format in mkimage tool.
SPKGs can optionally be signed, however creation of signed SPKG is not
currently supported.
Example of how to use it:
tools/mkimage -n board/schneider/rzn1-snarc/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
Reviewed-by: Simon Glass
Reviewed-by: Marek Vasut
---
Changes in v7:
- restore static globals for the config file structure
- restore check_image_types() to only recognise SPKG.
For details of why this is necessary refer to
https://lore.kernel.org/u-boot/20220826150123.ga1235...@maple.netwinder.org/
Changes in v5:
- use strcspn() instead of open-coded loop for \n removal
- rename source files to include vendor name
- replace static globals with dynamically allocated structure
- update print_header function signature
Changes in v4:
- added tags
- add RZ/N1 board documentation
- added binman support
Changes in v3:
- provide definition of __packed (as done in kwbimage.h)
- explain why a local copy of roundup() is needed
- document spkgimage in doc/mkimage.1
- add range checks when parsing config file values
- add line numbers for reporting errors in config file
- rename SPKG_HEADER_SIGNATURE to SPKG_HEADER_MARKER
- fix segfault when image is padded by less than 4 bytes
- minor style and typo fixes
Changes in v2:
- rewrote the stand-alone spkg_utility to integrate into mkimage
board/schneider/rzn1-snarc/spkgimage.cfg | 26 ++
boot/image.c | 1 +
doc/mkimage.1| 45 +++
include/image.h | 1 +
tools/Makefile | 1 +
tools/renesas_spkgimage.c| 336 +++
tools/renesas_spkgimage.h| 87 ++
7 files changed, 497 insertions(+)
create mode 100644 board/schneider/rzn1-snarc/spkgimage.cfg
create mode 100644 tools/renesas_spkgimage.c
create mode 100644 tools/renesas_spkgimage.h
diff --git a/board/schneider/rzn1-snarc/spkgimage.cfg
b/board/schneider/rzn1-snarc/spkgimage.cfg
new file mode 100644
index 00..b5faf96b00
--- /dev/null
+++ b/board/schneider/rzn1-snarc/spkgimage.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Schneider Electric
+#
+# SPKG image header, for booting on RZ/N1
+
+# b[35:32] SPKG version
+VERSION1
+
+# b[42:41] ECC Block size: 0=256 bytes, 1=512 bytes, 2=1024 bytes
+NAND_ECC_BLOCK_SIZE1
+
+# b[45] NAND enable (boolean)
+NAND_ECC_ENABLE1
+
+# b[50:48] ECC Scheme: 0=BCH2 1=BCH4 2=BCH8 3=BCH16 4=BCH24 5=BCH32
+NAND_ECC_SCHEME3
+
+# b[63:56] ECC bytes per block
+NAND_BYTES_PER_ECC_BLOCK 28
+
+# Provide dummy BLp header (boolean)
+ADD_DUMMY_BLP 1
+
+# Pad the image to a multiple of
+PADDING64K
diff --git a/boot/image.c b/boot/image.c
index 958dbf8534..5c4f9b807d 100644
--- a/boot/image.c
+++ b/boot/image.c
@@ -181,6 +181,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_SUNXI_EGON, "sunxi_egon", "Allwinner eGON Boot Image"
},
{ IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image"
},
{ IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat
Device Tree ", },
+ { IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" },
{ -1, "", "", },
};
diff --git a/doc/mkimage.1 b/doc/mkimage.1
index d8727ec73c..76c7859bb0 100644
--- a/doc/mkimage.1
+++ b/doc/mkimage.1
@@ -662,6 +662,51 @@ rk3568
.TE
.RE
.
+.SS spkgimage
+The primary configuration file consists of lines containing key/value pairs
+delimited by whitespace. An example follows.
+.PP
+.RS
+.EX
+# Comments and blank lines may be used
+.I key1 value1
+.I key2 value2
+.EE
+.RE
+.P
+The supported
+.I key
+types are as follows.
+.TP
+.B VERSION
+.TQ
+.B NAND_ECC_BLOCK_SIZE
+.TQ
+.B NAND_ECC_ENABLE
+.TQ
+.B NAND_ECC_SCHEME
+.TQ
+.B NAND_BYTES_PER_ECC_BLOCK
+These all take a positive integer value as their argument.
+The value will be copied directly into the respective field
+of the SPKG header structure. For details on these values,
+refer to Section 7.4 of the Renesas RZ/N1 User's Manual.
+.
+.TP
+.B ADD_DUMMY_BLP
+Takes a numeric argument, which is treated as a boolean. Any nonzero
+value will cause a fake BLp security header to be included in the SPKG
+output.
+.
+.TP
+.B PADDING
+Takes a positive integer value, with an optional
+.B K
+or
+.B M
+suffix, indicating KiB / MiB respectively.
+The output SPKG file will be padded to a multiple of this val
[PATCH v7 10/10] doc: renesas: add Renesas board docs
As a starting point, list all currently supported Renesas boards. For the RZ/N1 board, add details about booting and flashing. Signed-off-by: Ralph Siemsen Reviewed-by: Marek Vasut --- Changes in v7: - replace broken link to binman.rst Changes in v5: - added renesas dir to doc/board/index.rst - corrections to list of Renesas boards - move RZ/N1 detail into its own file - moved binman description ahead of mkimage doc/board/index.rst | 1 + doc/board/renesas/index.rst | 10 + doc/board/renesas/renesas.rst | 45 + doc/board/renesas/rzn1.rst| 76 +++ 4 files changed, 132 insertions(+) create mode 100644 doc/board/renesas/index.rst create mode 100644 doc/board/renesas/renesas.rst create mode 100644 doc/board/renesas/rzn1.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index b2da6ec553..9040e16e01 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -33,6 +33,7 @@ Board-specific doc openpiton/index purism/index qualcomm/index + renesas/index rockchip/index samsung/index siemens/index diff --git a/doc/board/renesas/index.rst b/doc/board/renesas/index.rst new file mode 100644 index 00..fb6558ec11 --- /dev/null +++ b/doc/board/renesas/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas +=== + +.. toctree:: + :maxdepth: 2 + + renesas + rzn1 diff --git a/doc/board/renesas/renesas.rst b/doc/board/renesas/renesas.rst new file mode 100644 index 00..04dee8da24 --- /dev/null +++ b/doc/board/renesas/renesas.rst @@ -0,0 +1,45 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas +=== + +About this +-- + +This document describes the information about Renesas supported boards +and their usage steps. + +Renesas boards +-- + +Renesas is a SoC solutions provider for automotive and industrial applications. + +U-Boot supports several Renesas SoC families: + +* R-Car Gen2 (32-bit) +- Blanche board +- Gose board +- Koelsch board +- Lager board +- Silk board +- Porter board +- Stout board +* R-Car Gen3 (64-bit) +- Condor board +- Draak board +- Eagle board +- Ebisu board +- Salvator-X and Salvator-XS boards +- ULCB board +* R-Car Gen4 (64-bit) +- Falcon board +- Spider board +- Whitehawk board +* RZ/A1 (32-bit) +- GR-PEACH board +* RZ/G +- Beacon-rzg2 board +- Hihope-rzg2 board +- ek874 board +* RZ/N1 (32-bit) +- Schneider rzn1-snarc board diff --git a/doc/board/renesas/rzn1.rst b/doc/board/renesas/rzn1.rst new file mode 100644 index 00..e6d636b89e --- /dev/null +++ b/doc/board/renesas/rzn1.rst @@ -0,0 +1,76 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas RZ/N1 += + +Building + + +This document describes how to build and flash U-Boot for the RZ/N1. + +U-Boot +^^ + +Clone the U-Boot repository and build it as follows: + +.. code-block:: bash + +git clone --depth 1 https://source.denx.de/u-boot/u-boot.git +cd u-boot +make rzn1_snarc_defconfig +make CROSS_COMPILE=arm-linux-gnu- + +This produces `u-boot` which is an ELF executable, suitable for use with `gdb` +and JTAG debugging tools. + +It also produceds `u-boot.bin` which is a raw binary. + +Binman +^^ + +The BootROM in the RZ/N1 SoC expects to find the boot image in SPKG format. +This format is documented in Chapter 7.4 of the RZ/N1 User Manual. + +The `binman` tool may be used to generate the SPKG format for booting. +See tools/binman/binman.rst for details on this tool and its pre-requisites. + +.. code-block:: bash + +binman -d arch/arm/dts/r9a06g032-rzn1-snarc.dtb -o + +This will produce `u-boot.bin.spkg` in the specified directory. It can +then be flashed into QSPI, NAND, or loaded via USB-DFU mode. + +SPKG image +^^ + +Alternatively, the same SPKG image can be built by calling `mkimage` as follows: + +.. code-block:: bash + +tools/mkimage -n board/schneider/rzn1-snarc/spkgimage.cfg \ +-T spkgimage -a 0x2004 -e 0x2004 \ +-d u-boot.bin u-boot.bin.spkg + +This produces `u-boot.bin.spkg` which can be flashed into QSPI, NAND, or loaded +via USB-DFU mode. + +Take note of the load and execution address, which are encoded into the SPKG +headers. For development convenience, mkimage computes the execution offset +(part of the SPKG header) by subtracting the supplied load address from the +supplied execution address. + +Also note there are other parameters, notably ECC configuration in the case of +boot from NAND, specified in the `spkgimage.cfg` configuration file. + +Flashing + + +The RZ/N1 is able to boot from QSPI, NAND, or via USB (DFU). In all cases the +on-board BootROM expects for the binary to be wrapped with a "SPKG" header. + +It is possible to recover a bricked unit by using the USB (DFU) boot mode. This +allows uploading U-Boot into the internal RAM. Th
[PATCH v7 07/10] ARM: rmobile: Add support for Renesas RZ/N1 SoC
The RZ/N1 is a family of SoC devices from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD
Add basic support for this family, modeled on the existing RZA1.
Signed-off-by: Ralph Siemsen
---
(no changes since v6)
Changes in v6:
- make the #ifdef a bit clearer
Changes in v5:
- fold mach-rzn1 into mach-rmobile
arch/arm/mach-rmobile/Kconfig | 19 +++
arch/arm/mach-rmobile/Kconfig.rzn1 | 20
arch/arm/mach-rmobile/cpu_info.c | 10 --
3 files changed, 47 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-rmobile/Kconfig.rzn1
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 1ef7d68bdf..3061ccd34c 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -48,6 +48,24 @@ config RZA1
prompt "Renesas ARM SoCs RZ/A1 (32bit)"
select CPU_V7A
+config RZN1
+ prompt "Renesas ARM SoCs RZ/N1 (32bit)"
+ select CPU_V7A
+ select ARMV7_SET_CORTEX_SMPEN if !SPL
+ select SPL_ARMV7_SET_CORTEX_SMPEN if SPL
+ select CLK
+ select CLK_RENESAS
+ select CLK_R9A06G032
+ select DM
+ select DM_ETH
+ select DM_SERIAL
+ select PINCTRL
+ select PINCONF
+ select REGMAP
+ select SYSRESET
+ select SYSRESET_SYSCON
+ imply CMD_DM
+
endchoice
config SYS_SOC
@@ -56,5 +74,6 @@ config SYS_SOC
source "arch/arm/mach-rmobile/Kconfig.32"
source "arch/arm/mach-rmobile/Kconfig.64"
source "arch/arm/mach-rmobile/Kconfig.rza1"
+source "arch/arm/mach-rmobile/Kconfig.rzn1"
endif
diff --git a/arch/arm/mach-rmobile/Kconfig.rzn1
b/arch/arm/mach-rmobile/Kconfig.rzn1
new file mode 100644
index 00..73138d69f9
--- /dev/null
+++ b/arch/arm/mach-rmobile/Kconfig.rzn1
@@ -0,0 +1,20 @@
+if RZN1
+
+choice
+ prompt "Renesas RZ/N1 Board select"
+ default TARGET_SCHNEIDER_RZN1
+
+config TARGET_SCHNEIDER_RZN1
+ bool "Schneider RZN1 board"
+ help
+ Support the Schneider RZN1D and RZN1S boards, which are based
+ on the Renesas RZ/N1 SoC.
+
+endchoice
+
+config SYS_SOC
+ default "rzn1"
+
+source "board/schneider/rzn1-snarc/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 7e7465a2c8..71a856ea87 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -30,7 +30,7 @@ void enable_caches(void)
#endif
#ifdef CONFIG_DISPLAY_CPUINFO
-#ifndef CONFIG_RZA1
+#if !defined(CONFIG_RZA1) && !defined(CONFIG_RZN1)
__weak const u8 *rzg_get_cpu_name(void)
{
return 0;
@@ -126,11 +126,17 @@ int print_cpuinfo(void)
return 0;
}
-#else
+#elif defined(CONFIG_RZA1)
int print_cpuinfo(void)
{
printf("CPU: Renesas Electronics RZ/A1\n");
return 0;
}
+#else /* CONFIG_RZN1 */
+int print_cpuinfo(void)
+{
+ printf("CPU: Renesas Electronics RZ/N1\n");
+ return 0;
+}
#endif
#endif /* CONFIG_DISPLAY_CPUINFO */
--
2.25.1
[PATCH v7 06/10] ARM: dts: add devicetree for Renesas RZ/N1 SoC
This is taken directly from Linux kernel 6.3
(commit 457391b0380335d5e9a5babdec90ac53928b23b4)
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
(no changes since v6)
Changes in v6:
- updated comment to reflact linux 6.3, and add commit hash.
(the files themselves have not changed)
Changes in v5:
- r9a06g032.dtsi now identical to linux 6.3-rc7 version
Changes in v3:
- add syscon phandle to ddrctl
- simplify UART compatible strings
arch/arm/dts/r9a06g032.dtsi | 477 ++
include/dt-bindings/clock/r9a06g032-sysctrl.h | 149 ++
2 files changed, 626 insertions(+)
create mode 100644 arch/arm/dts/r9a06g032.dtsi
create mode 100644 include/dt-bindings/clock/r9a06g032-sysctrl.h
diff --git a/arch/arm/dts/r9a06g032.dtsi b/arch/arm/dts/r9a06g032.dtsi
new file mode 100644
index 00..0fa565a1c3
--- /dev/null
+++ b/arch/arm/dts/r9a06g032.dtsi
@@ -0,0 +1,477 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include
+#include
+
+/ {
+ compatible = "renesas,r9a06g032";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <1>;
+ clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+ enable-method = "renesas,r9a06g032-smp";
+ cpu-release-addr = <0 0x4000c204>;
+ };
+ };
+
+ ext_jtag_clk: extjtagclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ext_mclk: extmclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000>;
+ };
+
+ ext_rgmii_ref: extrgmiiref {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ext_rtc_clk: extrtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ rtc0: rtc@40006000 {
+ compatible = "renesas,r9a06g032-rtc",
"renesas,rzn1-rtc";
+ reg = <0x40006000 0x1000>;
+ interrupts = ,
+,
+;
+ interrupt-names = "alarm", "timer", "pps";
+ clocks = <&sysctrl R9A06G032_HCLK_RTC>;
+ clock-names = "hclk";
+ power-domains = <&sysctrl>;
+ status = "disabled";
+ };
+
+ wdt0: watchdog@40008000 {
+ compatible = "renesas,r9a06g032-wdt",
"renesas,rzn1-wdt";
+ reg = <0x40008000 0x1000>;
+ interrupts = ;
+ clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
+ status = "disabled";
+ };
+
+ wdt1: watchdog@40009000 {
+ compatible = "renesas,r9a06g032-wdt",
"renesas,rzn1-wdt";
+ reg = <0x40009000 0x1000>;
+ interrupts = ;
+ clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
+ status = "disabled";
+ };
+
+ sysctrl: system-controller@4000c000 {
+ compatible = "renesas,r9a06g032-sysctrl";
+ reg = <0x4000c000 0x1000>;
+ status = "okay";
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+
+ clocks = <&ext_mclk>, <&ext_rtc_clk>,
+
[PATCH v7 03/10] clk: renesas: add R906G032 driver
Clock driver for the Renesas RZ/N1 SoC family. This is based on
Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in
commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"),
with the following additional patch series applied:
https://lore.kernel.org/linux-renesas-soc/20230301215520.828455-1-ralph.siem...@linaro.org/
Notable difference: this version avoids allocating a 'struct clk'
for each clock source, as this is problematic before relocation.
Instead, it uses the same approach as existing Renesas R-Car Gen2/3
clock drivers, using a temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
(no changes since v6)
Changes in v6:
- add macros for RSTEN register and its bits
Changes in v5:
- eliminate "err" in probe function
Changes in v4:
- commit message now includes hash of Linux upon which this is based
as well as the additional patches (clock table cleanups)
- sync changes from review on linux patches, including
- move RB macro higher up and document it, matching Linux driver
- use multiply/divide instead of shifts for computing reg address
- improve comments for clock gate, descriptor structures
Changes in v3:
- convert data table to explicit reg/bit numbers
- drop the unused scon, mirack, mirstat fields
- added some kernel docs to structures
- use enum for type field of struct r9a06g032_clkdesc
- cleanup macros for one assignment per line
- add a macro for top-most clock ID value ~0
- use dev_dbg() instead of debug/print
- minor reformatting, declarations before code, etc
- !foo instead of foo == 0
- IS_ERR / PTR_ERR where appropriate
- implement div_table handling
- remove some #if 0 old test code
drivers/clk/renesas/Kconfig|6 +
drivers/clk/renesas/Makefile |1 +
drivers/clk/renesas/r9a06g032-clocks.c | 1103
3 files changed, 1110 insertions(+)
create mode 100644 drivers/clk/renesas/r9a06g032-clocks.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index bdb81a1bbe..437a82cd48 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -150,3 +150,9 @@ config CLK_R8A779G0
depends on CLK_RCAR_GEN3
help
Enable this to support the clocks on Renesas R8A779G0 SoC.
+
+config CLK_R9A06G032
+ bool "Renesas R9A06G032 clock driver"
+ depends on CLK_RENESAS
+ help
+ Enable this to support the clocks on Renesas R9A06G032 SoC.
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index c95dee67f3..48373e61b9 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
+obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c
b/drivers/clk/renesas/r9a06g032-clocks.c
new file mode 100644
index 00..d2f61236fe
--- /dev/null
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -0,0 +1,1103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R9A06G032 clock driver
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet ,
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+/**
+ * struct regbit - describe one bit in a register
+ * @reg: offset of register relative to base address,
+ * expressed in units of 32-bit words (not bytes),
+ * @bit: which bit (0 to 31) in the register
+ *
+ * This structure is used to compactly encode the location
+ * of a single bit in a register. Five bits are needed to
+ * encode the bit number. With uint16_t data type, this
+ * leaves 11 bits to encode a register offset up to 2047.
+ *
+ * Since registers are aligned on 32-bit boundaries, the
+ * offset will be specified in 32-bit words rather than bytes.
+ * This allows encoding an offset up to 0x1FFC (8188) bytes.
+ *
+ * Helper macro RB() takes care of converting the register
+ * offset from bytes to 32-bit words.
+ */
+struct regbit {
+ u16 reg:11;
+ u16 bit:5;
+};
+
+#define RB(_reg, _bit) ((struct regbit) { \
+ .reg = (_reg) / 4, \
+ .bit = (_bit) \
+})
+
+/**
+ * struct r9a06g032_gate - clock-related control bits
+ * @gate: clock enable/disable
+ * @reset: clock module reset (active low)
+ * @ready: enables NoC forwarding of read/write requests to device,
+ * (eg. device is ready to handle read/write requests)
+ * @midle: request to idle the NoC interconnect
+ *
+ * Each of these fields describes a single bit in a register,
+ * which controls some aspect of clock gating. The @gate field
+ * is mandatory, this one enables/disables the clock. The
+ * other fields are optional, with zero indicating &quo
[PATCH v7 05/10] ram: cadence: add driver for Cadence EDAC
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1. Signed-off-by: Ralph Siemsen --- (no changes since v6) Changes in v6: - use wait_for_bit macros instead of endless while loop Changes in v5: - move board-specific init out of the driver. Changes in v3: - assorted small cleanups - support version 1.0 silicon (previously #if 0...) drivers/ram/Kconfig| 1 + drivers/ram/Makefile | 2 + drivers/ram/cadence/Kconfig| 12 + drivers/ram/cadence/Makefile | 1 + drivers/ram/cadence/ddr_ctrl.c | 414 + include/renesas/ddr_ctrl.h | 175 ++ 6 files changed, 605 insertions(+) create mode 100644 drivers/ram/cadence/Kconfig create mode 100644 drivers/ram/cadence/Makefile create mode 100644 drivers/ram/cadence/ddr_ctrl.c create mode 100644 include/renesas/ddr_ctrl.h diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 1acf212f87..bf99964577 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -108,6 +108,7 @@ config IMXRT_SDRAM This driver is for the sdram memory interface with the SEMC. source "drivers/ram/aspeed/Kconfig" +source "drivers/ram/cadence/Kconfig" source "drivers/ram/rockchip/Kconfig" source "drivers/ram/sifive/Kconfig" source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 2b9429cfee..b281129f89 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -24,3 +24,5 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/ endif obj-$(CONFIG_ARCH_OCTEON) += octeon/ + +obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/ diff --git a/drivers/ram/cadence/Kconfig b/drivers/ram/cadence/Kconfig new file mode 100644 index 00..2d5469cb8e --- /dev/null +++ b/drivers/ram/cadence/Kconfig @@ -0,0 +1,12 @@ +if RAM || SPL_RAM + +config CADENCE_DDR_CTRL + bool "Enable Cadence DDR controller" + depends on DM + help + Enable support for Cadence DDR controller, as found on + the Renesas RZ/N1 SoC. This controller has a large number + of registers which need to be programmed, mostly using values + obtained from Denali SOMA files via a TCL script. + +endif diff --git a/drivers/ram/cadence/Makefile b/drivers/ram/cadence/Makefile new file mode 100644 index 00..b4226cf6f2 --- /dev/null +++ b/drivers/ram/cadence/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_CADENCE_DDR_CTRL) += ddr_ctrl.o diff --git a/drivers/ram/cadence/ddr_ctrl.c b/drivers/ram/cadence/ddr_ctrl.c new file mode 100644 index 00..3e5959a84a --- /dev/null +++ b/drivers/ram/cadence/ddr_ctrl.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Cadence DDR Controller + * + * Copyright (C) 2015 Renesas Electronics Europe Ltd + */ + +/* + * The Cadence DDR Controller has a huge number of registers that principally + * cover two aspects, DDR specific timing information and AXI bus interfacing. + * Cadence's TCL script generates all of the register values for specific + * DDR devices operating at a specific frequency. The TCL script uses Denali + * SOMA files as inputs. The tool also generates the AXI bus register values as + * well, however this driver assumes that users will want to modifiy these to + * meet a specific application's needs. + * Therefore, this driver is passed two arrays containing register values for + * the DDR device specific information, and explicity sets the AXI registers. + * + * AXI bus interfacing: + * The controller has four AXI slaves connections, and each of these can be + * programmed to accept requests from specific AXI masters (using their IDs). + * The regions of DDR that can be accessed by each AXI slave can be set such + * as to isolate DDR used by one AXI master from another. Further, the maximum + * bandwidth allocated to each AXI slave can be set. + */ + +#include +#include +#include +#include +#include +#include + +/* avoid warning for real pr_debug in */ +#ifdef pr_debug +#undef pr_debug +#endif + +#ifdef DEBUG + #define pr_debug(fmt, args...) printf(fmt, ##args) + #define pr_debug2(fmt, args...) printf(fmt, ##args) +#else + #define pr_debug(fmt, args...) + #define pr_debug2(fmt, args...) +#endif + +#define DDR_NR_AXI_PORTS 4 +#define DDR_NR_ENTRIES 16 + +#define DDR_START_REG (0) /* DENALI_CTL_00 */ +#define DDR_CS0_MR1_REG(32 * 4)/* DENALI_CTL_32 */ +#define DDR_CS0_MR2_REG(32 * 4 + 2)/* DENALI_CTL_32 */ +#define DDR_CS1_MR1_REG(34 * 4 + 2)/* DENALI_CTL_34 */ +#define DDR_CS1_MR2_REG(35 * 4)/* DENALI_CTL_35 */ +#define DDR_ECC_ENABLE_REG (36 * 4 + 2)/* DENALI_CTL_36 */ +#define DDR_ECC_DISABLE_W_UC_ERR_REG (37 * 4 + 2)/* DENALI_CTL_37 */ +#
[PATCH v7 04/10] pinctrl: renesas: add R906G032 driver
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
(no changes since v5)
Changes in v5:
- add R-b tag
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/renesas/Kconfig| 7 +
drivers/pinctrl/renesas/Makefile | 1 +
drivers/pinctrl/renesas/pinctrl-rzn1.c | 379 +
include/dt-bindings/pinctrl/rzn1-pinctrl.h | 141
5 files changed, 529 insertions(+)
create mode 100644 drivers/pinctrl/renesas/pinctrl-rzn1.c
create mode 100644 include/dt-bindings/pinctrl/rzn1-pinctrl.h
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 852adee4b4..fc1f01a02c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_INTEL) += intel/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
+obj-$(CONFIG_ARCH_RZN1) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_PINCTRL_SUNXI)+= sunxi/
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 509cdd3fb2..0ea39b4a3f 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -139,3 +139,10 @@ config PINCTRL_PFC_R7S72100
Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
endif
+
+config PINCTRL_RZN1
+ bool "Renesas RZ/N1 R906G032 pin control driver"
+ depends on RZN1
+ default y if RZN1
+ help
+ Support pin multiplexing control on Renesas RZ/N1 R906G032 SoCs.
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 5cea1423ca..1a61c39d84 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o
obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
+obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
diff --git a/drivers/pinctrl/renesas/pinctrl-rzn1.c
b/drivers/pinctrl/renesas/pinctrl-rzn1.c
new file mode 100644
index 00..fdc43c8e71
--- /dev/null
+++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
+ *
+ * Phil Edworthy
+ * Based on a driver originally written by Michel Pollet at Renesas.
+ */
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+/* Field positions and masks in the pinmux registers */
+#define RZN1_L1_PIN_DRIVE_STRENGTH 10
+#define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0
+#define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1
+#define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2
+#define RZN1_L1_PIN_DRIVE_STRENGTH_12MA3
+#define RZN1_L1_PIN_PULL 8
+#define RZN1_L1_PIN_PULL_NONE 0
+#define RZN1_L1_PIN_PULL_UP1
+#define RZN1_L1_PIN_PULL_DOWN 3
+#define RZN1_L1_FUNCTION 0
+#define RZN1_L1_FUNC_MASK 0xf
+#define RZN1_L1_FUNCTION_L20xf
+
+/*
+ * The hardware manual describes two levels of multiplexing, but it's more
+ * logical to think of the hardware as three levels, with level 3 consisting of
+ * the multiplexing for Ethernet MDIO signals.
+ *
+ * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf)
specifying
+ * that level 2 functions are used instead. Level 2 has a lot more options,
+ * going from 0 to 61. Level 3 allows selection of MDIO functions which can be
+ * floating, or one of seven internal peripherals. Unfortunately, there are two
+ * level 2 functions that can select MDIO, and two MDIO channels so we have
four
+ * sets of level 3 functions.
+ *
+ * For this driver, we've compounded the numbers together, so:
+ *0 to 9 is level 1
+ * 10 to 71 is 10 + level 2 number
+ * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function.
+ * 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function.
+ * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function.
+ * 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function.
+ * Examples:
+ * Function 28 corresponds UART0
+ * Function 73 corresponds to MDIO0 to GMAC0
+ *
+ * There are 170 configurable pins (called PL_GPIO in the datasheet).
+ */
+
+/*
+ * Structure detailing the HW registers on the RZ/N1 devices.
+ * Both the Level 1 mux registers and Level 2 mux registers have the same
+ * structure. The only difference is that Level 2 has additional MDIO registers
+ * at the end.
+ */
+struct rzn1_pinctrl_regs {
+ u32 conf[170];
+ u32 pad0[86];
+ u32 status_protect; /* 0x400 */
+ /* MDIO mux registe
[PATCH v7 01/10] ARM: armv7: add non-SPL enable for Cortex SMPEN
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
This will be used by the following commit that adds RZ/N1 support.
(no changes since v5)
Changes in v5:
- add R-b tag
arch/arm/cpu/armv7/Kconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index f1e4e26b8f..e33e53636a 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -107,6 +107,11 @@ config ARMV7_LPAE
Say Y here to use the long descriptor page table format. This is
required if U-Boot runs in HYP mode.
+config ARMV7_SET_CORTEX_SMPEN
+ bool
+ help
+ Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
+
config SPL_ARMV7_SET_CORTEX_SMPEN
bool
help
--
2.25.1
[PATCH v7 02/10] clk: renesas: prepare for non R-Car clock drivers
Add new CONFIG_CLK_RCAR to control compilation of shared code for R-Car clock drivers (renesas-cpg-mssr.c). Enable this for R-Car Gen2 and 3. This is necessary so that CONFIG_CLK_RENESAS can be enabled, allowing recursion into the drivers/clk/reneasas directory, without bringing in the R-Car support code. The support code contains platform specific access (TMU_BASE) which is not needed on other Renesas devices such as RZ/N1. Signed-off-by: Ralph Siemsen Reviewed-by: Sean Anderson Reviewed-by: Marek Vasut --- (no changes since v5) Changes in v5: - add symbol CONFIG_CLK_RCAR and select it for R-Car Gen2/3. - use this to control compilation of renesas-cpg-mssr.c, rather than CONFIG_CLK_RENESAS which also controls directory recursion. - update the commit message accordingly Changes in v3: - added tags drivers/clk/renesas/Kconfig | 9 - drivers/clk/renesas/Makefile | 2 +- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 45671c6925..bdb81a1bbe 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -2,7 +2,12 @@ config CLK_RENESAS bool "Renesas clock drivers" depends on CLK && ARCH_RMOBILE help - Enable support for clock present on Renesas RCar SoCs. + Enable support for clock present on Renesas SoCs. + +config CLK_RCAR + bool "Renesas RCar clock driver support" + help + Enable common code for clocks on Renesas RCar SoCs. config CLK_RCAR_CPG_LIB bool "CPG/MSSR library functions" @@ -11,6 +16,7 @@ config CLK_RCAR_GEN2 bool "Renesas RCar Gen2 clock driver" def_bool y if RCAR_32 depends on CLK_RENESAS + select CLK_RCAR help Enable this to support the clocks on Renesas RCar Gen2 SoC. @@ -48,6 +54,7 @@ config CLK_RCAR_GEN3 bool "Renesas RCar Gen3 and Gen4 clock driver" def_bool y if RCAR_64 depends on CLK_RENESAS + select CLK_RCAR select CLK_RCAR_CPG_LIB select DM_RESET help diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index fe0391e520..c95dee67f3 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -1,4 +1,4 @@ -obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o +obj-$(CONFIG_CLK_RCAR) += renesas-cpg-mssr.o obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o -- 2.25.1
[PATCH v5 00/10] Renesas RZ/N1 SoC initial support
The RZ/N1 is a family of SoC devices from Renesas [1], featuring ARM Cortex-A7 and/or Cortex-M3 CPU, industrial ethernet protocols, integrated Ethernet switch, and numerous peripherals. This is a first step in upstreaming support for the RZ/N1 family. Currently it contains just enough to boot to the u-boot prompt. Additional patches will follow to support flash, SD, USB, Ethernet, etc. This work is based on a vendor-supplied u-boot 2017.01 tree [2], which supports several eval boards, none of which I have access to. Instead development has been done on a Schneider RZN1 board, which is fairly similar to the Renesas RZ/N1D-DB Demo board. [1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzn1 [2] https://github.com/renesas-rz/rzn1_u-boot/tree/rzn1-stable Changes in v6: - rebase to u-boot v2023.07-rc2 - add R-b tags Changes in v5: - rebase to u-boot v2023.04-1037-gb646e1f69f - many small changes in response to reviewer comments - move rzn1 into mach-rmobile (similar to existing rza1) - move board-specific DDR init to board dir Changes in v4: - rebase to u-boot v2023.04-rc3 - remove RFC prefix - cc entire series to Marek by request - clock tables synced with linux (pending patches) - documentation and comment improvements Changes in v3: - many tweaks to clock driver based on reviewer feedback - rebased to u-boot v2023.04-rc2 - reviewer suggestions added to spkgimage.c - many small cleanups, checkpatch, FIXMEs resolved Changes in v2: - rewrote the stand-alone spkg_utility to integrate into mkimage Ralph Siemsen (10): ARM: armv7: add non-SPL enable for Cortex SMPEN clk: renesas: prepare for non R-Car clock drivers clk: renesas: add R906G032 driver pinctrl: renesas: add R906G032 driver ram: cadence: add driver for Cadence EDAC ARM: dts: add devicetree for Renesas RZ/N1 SoC ARM: rmobile: Add support for Renesas RZ/N1 SoC board: schneider: add RZN1 board support tools: spkgimage: add Renesas SPKG format doc: renesas: add Renesas board docs arch/arm/cpu/armv7/Kconfig|5 + arch/arm/dts/r9a06g032-ddr.dtsi | 512 arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi | 23 + arch/arm/dts/r9a06g032-rzn1-snarc.dts | 92 ++ arch/arm/dts/r9a06g032.dtsi | 477 +++ arch/arm/mach-rmobile/Kconfig | 19 + arch/arm/mach-rmobile/Kconfig.rzn1| 20 + arch/arm/mach-rmobile/cpu_info.c | 10 +- board/schneider/rzn1-snarc/Kconfig| 18 + board/schneider/rzn1-snarc/Makefile |3 + board/schneider/rzn1-snarc/rzn1.c | 31 + board/schneider/rzn1-snarc/spkgimage.cfg | 26 + boot/image.c |1 + configs/rzn1_snarc_defconfig | 24 + doc/board/index.rst |1 + doc/board/renesas/index.rst | 10 + doc/board/renesas/renesas.rst | 45 + doc/board/renesas/rzn1.rst| 77 ++ doc/mkimage.1 | 45 + drivers/clk/renesas/Kconfig | 15 +- drivers/clk/renesas/Makefile |3 +- drivers/clk/renesas/r9a06g032-clocks.c| 1103 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/renesas/Kconfig |7 + drivers/pinctrl/renesas/Makefile |1 + drivers/pinctrl/renesas/pinctrl-rzn1.c| 379 ++ drivers/ram/Kconfig |1 + drivers/ram/Makefile |3 + drivers/ram/cadence/Kconfig | 12 + drivers/ram/cadence/Makefile |1 + drivers/ram/cadence/ddr_ctrl.c| 414 +++ drivers/ram/renesas/Makefile |3 + drivers/ram/renesas/rzn1/Makefile |3 + drivers/ram/renesas/rzn1/ddr_async.c | 376 ++ include/configs/rzn1-snarc.h | 13 + include/dt-bindings/clock/r9a06g032-sysctrl.h | 149 +++ include/dt-bindings/pinctrl/rzn1-pinctrl.h| 141 +++ include/image.h |1 + include/renesas/ddr_ctrl.h| 175 +++ include/renesas/is43tr16256a_125k_CTL.h | 419 +++ .../renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++ tools/Makefile|1 + tools/renesas_spkgimage.c | 338 + tools/renesas_spkgimage.h | 87 ++ 44 files changed, 5480 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/r9a06g032-ddr.dtsi create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc.dts create mode 100644 arch/arm/dts/r9a06g032.dtsi create mode 100644 arch/arm/mach-rmobile/Kconfig.rzn1 create mode 100644 board/schneider/rzn1-snarc/Kconfig create mode 100644 board/schneider/rzn1
[PATCH v5 08/10] board: schneider: add RZN1 board support
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
Changes in v6:
- move board-specific DDR init to drivers/ram/renesas/rzn1
- drop call to fdtdec_setup_mem_size_base()
- minor code cleanups
- use wait_for_bit macros instead of endless while loop
- in commit message fix Schneider Electronics -> Electric
Changes in v5:
- put all local DTS changes in r9a06g032-rzn1-snarc.dts
- move board-specific DDR init out of drivers/ram/cadence.
- tables of DDR paramters are now stored in devicetree
- support two different DDR memory types
- use BIT() macro
- obtain RZN1_DDR_BASE from DT
- uncomment error return when syscon fails
- make some functions static
Changes in v4:
- add binman support via r9a06g032-rzn1-snarc-u-boot.dtsi
Changes in v3:
- rename board LCES to rzn1-snarc
- move CONFIG_SYS_NS16550_MEM32 to Kconfig
- define CFG_SYS_INIT_RAM_{ADDR,SIZE}
- removed debug uart settings from defconfig
arch/arm/dts/r9a06g032-ddr.dtsi | 512 ++
arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi | 23 +
arch/arm/dts/r9a06g032-rzn1-snarc.dts | 92
board/schneider/rzn1-snarc/Kconfig| 18 +
board/schneider/rzn1-snarc/Makefile | 3 +
board/schneider/rzn1-snarc/rzn1.c | 31 ++
configs/rzn1_snarc_defconfig | 24 +
drivers/ram/Makefile | 1 +
drivers/ram/renesas/Makefile | 3 +
drivers/ram/renesas/rzn1/Makefile | 3 +
drivers/ram/renesas/rzn1/ddr_async.c | 376 +
include/configs/rzn1-snarc.h | 13 +
include/renesas/is43tr16256a_125k_CTL.h | 419 ++
.../renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++
14 files changed, 1917 insertions(+)
create mode 100644 arch/arm/dts/r9a06g032-ddr.dtsi
create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi
create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc.dts
create mode 100644 board/schneider/rzn1-snarc/Kconfig
create mode 100644 board/schneider/rzn1-snarc/Makefile
create mode 100644 board/schneider/rzn1-snarc/rzn1.c
create mode 100644 configs/rzn1_snarc_defconfig
create mode 100644 drivers/ram/renesas/Makefile
create mode 100644 drivers/ram/renesas/rzn1/Makefile
create mode 100644 drivers/ram/renesas/rzn1/ddr_async.c
create mode 100644 include/configs/rzn1-snarc.h
create mode 100644 include/renesas/is43tr16256a_125k_CTL.h
create mode 100644 include/renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h
diff --git a/arch/arm/dts/r9a06g032-ddr.dtsi b/arch/arm/dts/r9a06g032-ddr.dtsi
new file mode 100644
index 00..8c7d0873fe
--- /dev/null
+++ b/arch/arm/dts/r9a06g032-ddr.dtsi
@@ -0,0 +1,512 @@
+// SPDX-License-Identifier: GPL-2.0
+
+ cadence,ctl-000 = <
+ DENALI_CTL_00_DATA
+ DENALI_CTL_01_DATA
+ DENALI_CTL_02_DATA
+ DENALI_CTL_03_DATA
+ DENALI_CTL_04_DATA
+ DENALI_CTL_05_DATA
+ DENALI_CTL_06_DATA
+ DENALI_CTL_07_DATA
+ DENALI_CTL_08_DATA
+ DENALI_CTL_09_DATA
+
+ DENALI_CTL_10_DATA
+ DENALI_CTL_11_DATA
+ DENALI_CTL_12_DATA
+ DENALI_CTL_13_DATA
+ DENALI_CTL_14_DATA
+ DENALI_CTL_15_DATA
+ DENALI_CTL_16_DATA
+ DENALI_CTL_17_DATA
+ DENALI_CTL_18_DATA
+ DENALI_CTL_19_DATA
+
+ DENALI_CTL_20_DATA
+ DENALI_CTL_21_DATA
+ DENALI_CTL_22_DATA
+ DENALI_CTL_23_DATA
+ DENALI_CTL_24_DATA
+ DENALI_CTL_25_DATA
+ DENALI_CTL_26_DATA
+ DENALI_CTL_27_DATA
+ DENALI_CTL_28_DATA
+ DENALI_CTL_29_DATA
+
+ DENALI_CTL_30_DATA
+ DENALI_CTL_31_DATA
+ DENALI_CTL_32_DATA
+ DENALI_CTL_33_DATA
+ DENALI_CTL_34_DATA
+ DENALI_CTL_35_DATA
+ DENALI_CTL_36_DATA
+ DENALI_CTL_37_DATA
+ DENALI_CTL_38_DATA
+ DENALI_CTL_39_DATA
+
+ DENALI_CTL_40_DATA
+ DENALI_CTL_41_DATA
+ DENALI_CTL_42_DATA
+ DENALI_CTL_43_DATA
+ DENALI_CTL_44_DATA
+ DENALI_CTL_45_DATA
+ DENALI_CTL_46_DATA
+ DENALI_CTL_47_DATA
+ DENALI_CTL_48_DATA
+ DENALI_CTL_49_DATA
+
+ DENALI_CTL_50_DATA
+ DENALI_CTL_51_DATA
+ DENALI_CTL_52_DATA
+ DENALI_CTL_53_DATA
+ DENALI_CTL_54_DATA
+ DENALI_CTL_55_DATA
+ DENALI_CTL_5
[PATCH v5 10/10] doc: renesas: add Renesas board docs
As a starting point, list all currently supported Renesas boards. For the RZ/N1 board, add details about booting and flashing. Signed-off-by: Ralph Siemsen Reviewed-by: Marek Vasut --- (no changes since v5) Changes in v5: - added renesas dir to doc/board/index.rst - corrections to list of Renesas boards - move RZ/N1 detail into its own file - moved binman description ahead of mkimage doc/board/index.rst | 1 + doc/board/renesas/index.rst | 10 + doc/board/renesas/renesas.rst | 45 doc/board/renesas/rzn1.rst| 77 +++ 4 files changed, 133 insertions(+) create mode 100644 doc/board/renesas/index.rst create mode 100644 doc/board/renesas/renesas.rst create mode 100644 doc/board/renesas/rzn1.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index b2da6ec553..9040e16e01 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -33,6 +33,7 @@ Board-specific doc openpiton/index purism/index qualcomm/index + renesas/index rockchip/index samsung/index siemens/index diff --git a/doc/board/renesas/index.rst b/doc/board/renesas/index.rst new file mode 100644 index 00..fb6558ec11 --- /dev/null +++ b/doc/board/renesas/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas +=== + +.. toctree:: + :maxdepth: 2 + + renesas + rzn1 diff --git a/doc/board/renesas/renesas.rst b/doc/board/renesas/renesas.rst new file mode 100644 index 00..04dee8da24 --- /dev/null +++ b/doc/board/renesas/renesas.rst @@ -0,0 +1,45 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas +=== + +About this +-- + +This document describes the information about Renesas supported boards +and their usage steps. + +Renesas boards +-- + +Renesas is a SoC solutions provider for automotive and industrial applications. + +U-Boot supports several Renesas SoC families: + +* R-Car Gen2 (32-bit) +- Blanche board +- Gose board +- Koelsch board +- Lager board +- Silk board +- Porter board +- Stout board +* R-Car Gen3 (64-bit) +- Condor board +- Draak board +- Eagle board +- Ebisu board +- Salvator-X and Salvator-XS boards +- ULCB board +* R-Car Gen4 (64-bit) +- Falcon board +- Spider board +- Whitehawk board +* RZ/A1 (32-bit) +- GR-PEACH board +* RZ/G +- Beacon-rzg2 board +- Hihope-rzg2 board +- ek874 board +* RZ/N1 (32-bit) +- Schneider rzn1-snarc board diff --git a/doc/board/renesas/rzn1.rst b/doc/board/renesas/rzn1.rst new file mode 100644 index 00..2750629e81 --- /dev/null +++ b/doc/board/renesas/rzn1.rst @@ -0,0 +1,77 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas RZ/N1 += + +Building + + +This document describes how to build and flash U-Boot for the RZ/N1. + +U-Boot +^^ + +Clone the U-Boot repository and build it as follows: + +.. code-block:: bash + +git clone --depth 1 https://source.denx.de/u-boot/u-boot.git +cd u-boot +make rzn1_snarc_defconfig +make CROSS_COMPILE=arm-linux-gnu- + +This produces `u-boot` which is an ELF executable, suitable for use with `gdb` +and JTAG debugging tools. + +It also produceds `u-boot.bin` which is a raw binary. + +Binman +^^ + +The BootROM in the RZ/N1 SoC expects to find the boot image in SPKG format. +This format is documented in Chapter 7.4 of the RZ/N1 User Manual. + +The `binman` tool may be used to generate the SPKG format for booting. +This tool and its pre-requisites must be installed as per +:doc:`../../../tools/binman/binman.rst`` + +.. code-block:: bash + +binman -d arch/arm/dts/r9a06g032-rzn1-snarc.dtb -o + +This will produce `u-boot.bin.spkg` in the specified directory. It can +then be flashed into QSPI, NAND, or loaded via USB-DFU mode. + +SPKG image +^^ + +Alternatively, the same SPKG image can be built by calling `mkimage` as follows: + +.. code-block:: bash + +tools/mkimage -n board/schneider/rzn1-snarc/spkgimage.cfg \ +-T spkgimage -a 0x2004 -e 0x2004 \ +-d u-boot.bin u-boot.bin.spkg + +This produces `u-boot.bin.spkg` which can be flashed into QSPI, NAND, or loaded +via USB-DFU mode. + +Take note of the load and execution address, which are encoded into the SPKG +headers. For development convenience, mkimage computes the execution offset +(part of the SPKG header) by subtracting the supplied load address from the +supplied execution address. + +Also note there are other parameters, notably ECC configuration in the case of +boot from NAND, specified in the `spkgimage.cfg` configuration file. + +Flashing + + +The RZ/N1 is able to boot from QSPI, NAND, or via USB (DFU). In all cases the +on-board BootROM expects for the binary to be wrapped with a "SPKG" header. + +It is possible to recover a bricked unit by using the USB (DFU) boot mode. This +allows uploading U-Boot into the internal RAM. Thereaf
[PATCH v5 09/10] tools: spkgimage: add Renesas SPKG format
Renesas RZ/N1 devices contain BootROM code that loads a custom SPKG
image from QSPI, NAND or USB DFU. Support this format in mkimage tool.
SPKGs can optionally be signed, however creation of signed SPKG is not
currently supported.
Example of how to use it:
tools/mkimage -n board/schneider/rzn1-snarc/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
Reviewed-by: Simon Glass
Reviewed-by: Marek Vasut
---
(no changes since v5)
Changes in v5:
- use strcspn() instead of open-coded loop for \n removal
- rename source files to include vendor name
- replace static globals with dynamically allocated structure
- update print_header function signature
Changes in v4:
- added tags
- add RZ/N1 board documentation
- added binman support
Changes in v3:
- provide definition of __packed (as done in kwbimage.h)
- explain why a local copy of roundup() is needed
- document spkgimage in doc/mkimage.1
- add range checks when parsing config file values
- add line numbers for reporting errors in config file
- rename SPKG_HEADER_SIGNATURE to SPKG_HEADER_MARKER
- fix segfault when image is padded by less than 4 bytes
- minor style and typo fixes
Changes in v2:
- rewrote the stand-alone spkg_utility to integrate into mkimage
board/schneider/rzn1-snarc/spkgimage.cfg | 26 ++
boot/image.c | 1 +
doc/mkimage.1| 45 +++
include/image.h | 1 +
tools/Makefile | 1 +
tools/renesas_spkgimage.c| 338 +++
tools/renesas_spkgimage.h| 87 ++
7 files changed, 499 insertions(+)
create mode 100644 board/schneider/rzn1-snarc/spkgimage.cfg
create mode 100644 tools/renesas_spkgimage.c
create mode 100644 tools/renesas_spkgimage.h
diff --git a/board/schneider/rzn1-snarc/spkgimage.cfg
b/board/schneider/rzn1-snarc/spkgimage.cfg
new file mode 100644
index 00..b5faf96b00
--- /dev/null
+++ b/board/schneider/rzn1-snarc/spkgimage.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Schneider Electric
+#
+# SPKG image header, for booting on RZ/N1
+
+# b[35:32] SPKG version
+VERSION1
+
+# b[42:41] ECC Block size: 0=256 bytes, 1=512 bytes, 2=1024 bytes
+NAND_ECC_BLOCK_SIZE1
+
+# b[45] NAND enable (boolean)
+NAND_ECC_ENABLE1
+
+# b[50:48] ECC Scheme: 0=BCH2 1=BCH4 2=BCH8 3=BCH16 4=BCH24 5=BCH32
+NAND_ECC_SCHEME3
+
+# b[63:56] ECC bytes per block
+NAND_BYTES_PER_ECC_BLOCK 28
+
+# Provide dummy BLp header (boolean)
+ADD_DUMMY_BLP 1
+
+# Pad the image to a multiple of
+PADDING64K
diff --git a/boot/image.c b/boot/image.c
index 958dbf8534..5c4f9b807d 100644
--- a/boot/image.c
+++ b/boot/image.c
@@ -181,6 +181,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_SUNXI_EGON, "sunxi_egon", "Allwinner eGON Boot Image"
},
{ IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image"
},
{ IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat
Device Tree ", },
+ { IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" },
{ -1, "", "", },
};
diff --git a/doc/mkimage.1 b/doc/mkimage.1
index d8727ec73c..76c7859bb0 100644
--- a/doc/mkimage.1
+++ b/doc/mkimage.1
@@ -662,6 +662,51 @@ rk3568
.TE
.RE
.
+.SS spkgimage
+The primary configuration file consists of lines containing key/value pairs
+delimited by whitespace. An example follows.
+.PP
+.RS
+.EX
+# Comments and blank lines may be used
+.I key1 value1
+.I key2 value2
+.EE
+.RE
+.P
+The supported
+.I key
+types are as follows.
+.TP
+.B VERSION
+.TQ
+.B NAND_ECC_BLOCK_SIZE
+.TQ
+.B NAND_ECC_ENABLE
+.TQ
+.B NAND_ECC_SCHEME
+.TQ
+.B NAND_BYTES_PER_ECC_BLOCK
+These all take a positive integer value as their argument.
+The value will be copied directly into the respective field
+of the SPKG header structure. For details on these values,
+refer to Section 7.4 of the Renesas RZ/N1 User's Manual.
+.
+.TP
+.B ADD_DUMMY_BLP
+Takes a numeric argument, which is treated as a boolean. Any nonzero
+value will cause a fake BLp security header to be included in the SPKG
+output.
+.
+.TP
+.B PADDING
+Takes a positive integer value, with an optional
+.B K
+or
+.B M
+suffix, indicating KiB / MiB respectively.
+The output SPKG file will be padded to a multiple of this value.
+.
.SS sunxi_egon
The primary configuration is the name to use for the device tree.
.
diff --git a/include/image.h b/include/image.h
index 456197d6fd..01a6787d21 100644
--- a/include/image.h
+++ b/include/image.h
@@
[PATCH v5 03/10] clk: renesas: add R906G032 driver
Clock driver for the Renesas RZ/N1 SoC family. This is based on
Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in
commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"),
with the following additional patch series applied:
https://lore.kernel.org/linux-renesas-soc/20230301215520.828455-1-ralph.siem...@linaro.org/
Notable difference: this version avoids allocating a 'struct clk'
for each clock source, as this is problematic before relocation.
Instead, it uses the same approach as existing Renesas R-Car Gen2/3
clock drivers, using a temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
Changes in v6:
- add macros for RSTEN register and its bits
Changes in v5:
- eliminate "err" in probe function
Changes in v4:
- commit message now includes hash of Linux upon which this is based
as well as the additional patches (clock table cleanups)
- sync changes from review on linux patches, including
- move RB macro higher up and document it, matching Linux driver
- use multiply/divide instead of shifts for computing reg address
- improve comments for clock gate, descriptor structures
Changes in v3:
- convert data table to explicit reg/bit numbers
- drop the unused scon, mirack, mirstat fields
- added some kernel docs to structures
- use enum for type field of struct r9a06g032_clkdesc
- cleanup macros for one assignment per line
- add a macro for top-most clock ID value ~0
- use dev_dbg() instead of debug/print
- minor reformatting, declarations before code, etc
- !foo instead of foo == 0
- IS_ERR / PTR_ERR where appropriate
- implement div_table handling
- remove some #if 0 old test code
drivers/clk/renesas/Kconfig|6 +
drivers/clk/renesas/Makefile |1 +
drivers/clk/renesas/r9a06g032-clocks.c | 1103
3 files changed, 1110 insertions(+)
create mode 100644 drivers/clk/renesas/r9a06g032-clocks.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index bdb81a1bbe..437a82cd48 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -150,3 +150,9 @@ config CLK_R8A779G0
depends on CLK_RCAR_GEN3
help
Enable this to support the clocks on Renesas R8A779G0 SoC.
+
+config CLK_R9A06G032
+ bool "Renesas R9A06G032 clock driver"
+ depends on CLK_RENESAS
+ help
+ Enable this to support the clocks on Renesas R9A06G032 SoC.
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index c95dee67f3..48373e61b9 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
+obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c
b/drivers/clk/renesas/r9a06g032-clocks.c
new file mode 100644
index 00..d2f61236fe
--- /dev/null
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -0,0 +1,1103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R9A06G032 clock driver
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet ,
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+/**
+ * struct regbit - describe one bit in a register
+ * @reg: offset of register relative to base address,
+ * expressed in units of 32-bit words (not bytes),
+ * @bit: which bit (0 to 31) in the register
+ *
+ * This structure is used to compactly encode the location
+ * of a single bit in a register. Five bits are needed to
+ * encode the bit number. With uint16_t data type, this
+ * leaves 11 bits to encode a register offset up to 2047.
+ *
+ * Since registers are aligned on 32-bit boundaries, the
+ * offset will be specified in 32-bit words rather than bytes.
+ * This allows encoding an offset up to 0x1FFC (8188) bytes.
+ *
+ * Helper macro RB() takes care of converting the register
+ * offset from bytes to 32-bit words.
+ */
+struct regbit {
+ u16 reg:11;
+ u16 bit:5;
+};
+
+#define RB(_reg, _bit) ((struct regbit) { \
+ .reg = (_reg) / 4, \
+ .bit = (_bit) \
+})
+
+/**
+ * struct r9a06g032_gate - clock-related control bits
+ * @gate: clock enable/disable
+ * @reset: clock module reset (active low)
+ * @ready: enables NoC forwarding of read/write requests to device,
+ * (eg. device is ready to handle read/write requests)
+ * @midle: request to idle the NoC interconnect
+ *
+ * Each of these fields describes a single bit in a register,
+ * which controls some aspect of clock gating. The @gate field
+ * is mandatory, this one enables/disables the clock. The
+ * other fields are optional, with zero indicating "not used".
+ *
+ *
[PATCH v5 07/10] ARM: rmobile: Add support for Renesas RZ/N1 SoC
The RZ/N1 is a family of SoC devices from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD
Add basic support for this family, modeled on the existing RZA1.
Signed-off-by: Ralph Siemsen
---
Changes in v6:
- make the #ifdef a bit clearer
Changes in v5:
- fold mach-rzn1 into mach-rmobile
arch/arm/mach-rmobile/Kconfig | 19 +++
arch/arm/mach-rmobile/Kconfig.rzn1 | 20
arch/arm/mach-rmobile/cpu_info.c | 10 --
3 files changed, 47 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-rmobile/Kconfig.rzn1
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 1ef7d68bdf..3061ccd34c 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -48,6 +48,24 @@ config RZA1
prompt "Renesas ARM SoCs RZ/A1 (32bit)"
select CPU_V7A
+config RZN1
+ prompt "Renesas ARM SoCs RZ/N1 (32bit)"
+ select CPU_V7A
+ select ARMV7_SET_CORTEX_SMPEN if !SPL
+ select SPL_ARMV7_SET_CORTEX_SMPEN if SPL
+ select CLK
+ select CLK_RENESAS
+ select CLK_R9A06G032
+ select DM
+ select DM_ETH
+ select DM_SERIAL
+ select PINCTRL
+ select PINCONF
+ select REGMAP
+ select SYSRESET
+ select SYSRESET_SYSCON
+ imply CMD_DM
+
endchoice
config SYS_SOC
@@ -56,5 +74,6 @@ config SYS_SOC
source "arch/arm/mach-rmobile/Kconfig.32"
source "arch/arm/mach-rmobile/Kconfig.64"
source "arch/arm/mach-rmobile/Kconfig.rza1"
+source "arch/arm/mach-rmobile/Kconfig.rzn1"
endif
diff --git a/arch/arm/mach-rmobile/Kconfig.rzn1
b/arch/arm/mach-rmobile/Kconfig.rzn1
new file mode 100644
index 00..73138d69f9
--- /dev/null
+++ b/arch/arm/mach-rmobile/Kconfig.rzn1
@@ -0,0 +1,20 @@
+if RZN1
+
+choice
+ prompt "Renesas RZ/N1 Board select"
+ default TARGET_SCHNEIDER_RZN1
+
+config TARGET_SCHNEIDER_RZN1
+ bool "Schneider RZN1 board"
+ help
+ Support the Schneider RZN1D and RZN1S boards, which are based
+ on the Renesas RZ/N1 SoC.
+
+endchoice
+
+config SYS_SOC
+ default "rzn1"
+
+source "board/schneider/rzn1-snarc/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 7e7465a2c8..71a856ea87 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -30,7 +30,7 @@ void enable_caches(void)
#endif
#ifdef CONFIG_DISPLAY_CPUINFO
-#ifndef CONFIG_RZA1
+#if !defined(CONFIG_RZA1) && !defined(CONFIG_RZN1)
__weak const u8 *rzg_get_cpu_name(void)
{
return 0;
@@ -126,11 +126,17 @@ int print_cpuinfo(void)
return 0;
}
-#else
+#elif defined(CONFIG_RZA1)
int print_cpuinfo(void)
{
printf("CPU: Renesas Electronics RZ/A1\n");
return 0;
}
+#else /* CONFIG_RZN1 */
+int print_cpuinfo(void)
+{
+ printf("CPU: Renesas Electronics RZ/N1\n");
+ return 0;
+}
#endif
#endif /* CONFIG_DISPLAY_CPUINFO */
--
2.25.1
[PATCH v5 05/10] ram: cadence: add driver for Cadence EDAC
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1. Signed-off-by: Ralph Siemsen --- Changes in v6: - use wait_for_bit macros instead of endless while loop Changes in v5: - move board-specific init out of the driver. Changes in v3: - assorted small cleanups - support version 1.0 silicon (previously #if 0...) drivers/ram/Kconfig| 1 + drivers/ram/Makefile | 2 + drivers/ram/cadence/Kconfig| 12 + drivers/ram/cadence/Makefile | 1 + drivers/ram/cadence/ddr_ctrl.c | 414 + include/renesas/ddr_ctrl.h | 175 ++ 6 files changed, 605 insertions(+) create mode 100644 drivers/ram/cadence/Kconfig create mode 100644 drivers/ram/cadence/Makefile create mode 100644 drivers/ram/cadence/ddr_ctrl.c create mode 100644 include/renesas/ddr_ctrl.h diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 1acf212f87..bf99964577 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -108,6 +108,7 @@ config IMXRT_SDRAM This driver is for the sdram memory interface with the SEMC. source "drivers/ram/aspeed/Kconfig" +source "drivers/ram/cadence/Kconfig" source "drivers/ram/rockchip/Kconfig" source "drivers/ram/sifive/Kconfig" source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 2b9429cfee..b281129f89 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -24,3 +24,5 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/ endif obj-$(CONFIG_ARCH_OCTEON) += octeon/ + +obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/ diff --git a/drivers/ram/cadence/Kconfig b/drivers/ram/cadence/Kconfig new file mode 100644 index 00..2d5469cb8e --- /dev/null +++ b/drivers/ram/cadence/Kconfig @@ -0,0 +1,12 @@ +if RAM || SPL_RAM + +config CADENCE_DDR_CTRL + bool "Enable Cadence DDR controller" + depends on DM + help + Enable support for Cadence DDR controller, as found on + the Renesas RZ/N1 SoC. This controller has a large number + of registers which need to be programmed, mostly using values + obtained from Denali SOMA files via a TCL script. + +endif diff --git a/drivers/ram/cadence/Makefile b/drivers/ram/cadence/Makefile new file mode 100644 index 00..b4226cf6f2 --- /dev/null +++ b/drivers/ram/cadence/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_CADENCE_DDR_CTRL) += ddr_ctrl.o diff --git a/drivers/ram/cadence/ddr_ctrl.c b/drivers/ram/cadence/ddr_ctrl.c new file mode 100644 index 00..3e5959a84a --- /dev/null +++ b/drivers/ram/cadence/ddr_ctrl.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Cadence DDR Controller + * + * Copyright (C) 2015 Renesas Electronics Europe Ltd + */ + +/* + * The Cadence DDR Controller has a huge number of registers that principally + * cover two aspects, DDR specific timing information and AXI bus interfacing. + * Cadence's TCL script generates all of the register values for specific + * DDR devices operating at a specific frequency. The TCL script uses Denali + * SOMA files as inputs. The tool also generates the AXI bus register values as + * well, however this driver assumes that users will want to modifiy these to + * meet a specific application's needs. + * Therefore, this driver is passed two arrays containing register values for + * the DDR device specific information, and explicity sets the AXI registers. + * + * AXI bus interfacing: + * The controller has four AXI slaves connections, and each of these can be + * programmed to accept requests from specific AXI masters (using their IDs). + * The regions of DDR that can be accessed by each AXI slave can be set such + * as to isolate DDR used by one AXI master from another. Further, the maximum + * bandwidth allocated to each AXI slave can be set. + */ + +#include +#include +#include +#include +#include +#include + +/* avoid warning for real pr_debug in */ +#ifdef pr_debug +#undef pr_debug +#endif + +#ifdef DEBUG + #define pr_debug(fmt, args...) printf(fmt, ##args) + #define pr_debug2(fmt, args...) printf(fmt, ##args) +#else + #define pr_debug(fmt, args...) + #define pr_debug2(fmt, args...) +#endif + +#define DDR_NR_AXI_PORTS 4 +#define DDR_NR_ENTRIES 16 + +#define DDR_START_REG (0) /* DENALI_CTL_00 */ +#define DDR_CS0_MR1_REG(32 * 4)/* DENALI_CTL_32 */ +#define DDR_CS0_MR2_REG(32 * 4 + 2)/* DENALI_CTL_32 */ +#define DDR_CS1_MR1_REG(34 * 4 + 2)/* DENALI_CTL_34 */ +#define DDR_CS1_MR2_REG(35 * 4)/* DENALI_CTL_35 */ +#define DDR_ECC_ENABLE_REG (36 * 4 + 2)/* DENALI_CTL_36 */ +#define DDR_ECC_DISABLE_W_UC_ERR_REG (37 * 4 + 2)/* DENALI_CTL_37 */ +#define DDR_HALF_DATAPATH_REG
[PATCH v5 06/10] ARM: dts: add devicetree for Renesas RZ/N1 SoC
This is taken directly from Linux kernel 6.3
(commit 457391b0380335d5e9a5babdec90ac53928b23b4)
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
Changes in v6:
- updated comment to reflact linux 6.3, and add commit hash.
(the files themselves have not changed)
Changes in v5:
- r9a06g032.dtsi now identical to linux 6.3-rc7 version
Changes in v3:
- add syscon phandle to ddrctl
- simplify UART compatible strings
arch/arm/dts/r9a06g032.dtsi | 477 ++
include/dt-bindings/clock/r9a06g032-sysctrl.h | 149 ++
2 files changed, 626 insertions(+)
create mode 100644 arch/arm/dts/r9a06g032.dtsi
create mode 100644 include/dt-bindings/clock/r9a06g032-sysctrl.h
diff --git a/arch/arm/dts/r9a06g032.dtsi b/arch/arm/dts/r9a06g032.dtsi
new file mode 100644
index 00..0fa565a1c3
--- /dev/null
+++ b/arch/arm/dts/r9a06g032.dtsi
@@ -0,0 +1,477 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include
+#include
+
+/ {
+ compatible = "renesas,r9a06g032";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <1>;
+ clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+ enable-method = "renesas,r9a06g032-smp";
+ cpu-release-addr = <0 0x4000c204>;
+ };
+ };
+
+ ext_jtag_clk: extjtagclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ext_mclk: extmclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000>;
+ };
+
+ ext_rgmii_ref: extrgmiiref {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ext_rtc_clk: extrtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ rtc0: rtc@40006000 {
+ compatible = "renesas,r9a06g032-rtc",
"renesas,rzn1-rtc";
+ reg = <0x40006000 0x1000>;
+ interrupts = ,
+,
+;
+ interrupt-names = "alarm", "timer", "pps";
+ clocks = <&sysctrl R9A06G032_HCLK_RTC>;
+ clock-names = "hclk";
+ power-domains = <&sysctrl>;
+ status = "disabled";
+ };
+
+ wdt0: watchdog@40008000 {
+ compatible = "renesas,r9a06g032-wdt",
"renesas,rzn1-wdt";
+ reg = <0x40008000 0x1000>;
+ interrupts = ;
+ clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
+ status = "disabled";
+ };
+
+ wdt1: watchdog@40009000 {
+ compatible = "renesas,r9a06g032-wdt",
"renesas,rzn1-wdt";
+ reg = <0x40009000 0x1000>;
+ interrupts = ;
+ clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
+ status = "disabled";
+ };
+
+ sysctrl: system-controller@4000c000 {
+ compatible = "renesas,r9a06g032-sysctrl";
+ reg = <0x4000c000 0x1000>;
+ status = "okay";
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+
+ clocks = <&ext_mclk>, <&ext_rtc_clk>,
+ <&ext_jtag_clk>,
[PATCH v5 04/10] pinctrl: renesas: add R906G032 driver
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
(no changes since v5)
Changes in v5:
- add R-b tag
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/renesas/Kconfig| 7 +
drivers/pinctrl/renesas/Makefile | 1 +
drivers/pinctrl/renesas/pinctrl-rzn1.c | 379 +
include/dt-bindings/pinctrl/rzn1-pinctrl.h | 141
5 files changed, 529 insertions(+)
create mode 100644 drivers/pinctrl/renesas/pinctrl-rzn1.c
create mode 100644 include/dt-bindings/pinctrl/rzn1-pinctrl.h
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 852adee4b4..fc1f01a02c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_INTEL) += intel/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
+obj-$(CONFIG_ARCH_RZN1) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_PINCTRL_SUNXI)+= sunxi/
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 509cdd3fb2..0ea39b4a3f 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -139,3 +139,10 @@ config PINCTRL_PFC_R7S72100
Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
endif
+
+config PINCTRL_RZN1
+ bool "Renesas RZ/N1 R906G032 pin control driver"
+ depends on RZN1
+ default y if RZN1
+ help
+ Support pin multiplexing control on Renesas RZ/N1 R906G032 SoCs.
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 5cea1423ca..1a61c39d84 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o
obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
+obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
diff --git a/drivers/pinctrl/renesas/pinctrl-rzn1.c
b/drivers/pinctrl/renesas/pinctrl-rzn1.c
new file mode 100644
index 00..fdc43c8e71
--- /dev/null
+++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
+ *
+ * Phil Edworthy
+ * Based on a driver originally written by Michel Pollet at Renesas.
+ */
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+/* Field positions and masks in the pinmux registers */
+#define RZN1_L1_PIN_DRIVE_STRENGTH 10
+#define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0
+#define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1
+#define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2
+#define RZN1_L1_PIN_DRIVE_STRENGTH_12MA3
+#define RZN1_L1_PIN_PULL 8
+#define RZN1_L1_PIN_PULL_NONE 0
+#define RZN1_L1_PIN_PULL_UP1
+#define RZN1_L1_PIN_PULL_DOWN 3
+#define RZN1_L1_FUNCTION 0
+#define RZN1_L1_FUNC_MASK 0xf
+#define RZN1_L1_FUNCTION_L20xf
+
+/*
+ * The hardware manual describes two levels of multiplexing, but it's more
+ * logical to think of the hardware as three levels, with level 3 consisting of
+ * the multiplexing for Ethernet MDIO signals.
+ *
+ * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf)
specifying
+ * that level 2 functions are used instead. Level 2 has a lot more options,
+ * going from 0 to 61. Level 3 allows selection of MDIO functions which can be
+ * floating, or one of seven internal peripherals. Unfortunately, there are two
+ * level 2 functions that can select MDIO, and two MDIO channels so we have
four
+ * sets of level 3 functions.
+ *
+ * For this driver, we've compounded the numbers together, so:
+ *0 to 9 is level 1
+ * 10 to 71 is 10 + level 2 number
+ * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function.
+ * 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function.
+ * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function.
+ * 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function.
+ * Examples:
+ * Function 28 corresponds UART0
+ * Function 73 corresponds to MDIO0 to GMAC0
+ *
+ * There are 170 configurable pins (called PL_GPIO in the datasheet).
+ */
+
+/*
+ * Structure detailing the HW registers on the RZ/N1 devices.
+ * Both the Level 1 mux registers and Level 2 mux registers have the same
+ * structure. The only difference is that Level 2 has additional MDIO registers
+ * at the end.
+ */
+struct rzn1_pinctrl_regs {
+ u32 conf[170];
+ u32 pad0[86];
+ u32 status_protect; /* 0x400 */
+ /* MDIO mux registe
[PATCH v5 02/10] clk: renesas: prepare for non R-Car clock drivers
Add new CONFIG_CLK_RCAR to control compilation of shared code for R-Car clock drivers (renesas-cpg-mssr.c). Enable this for R-Car Gen2 and 3. This is necessary so that CONFIG_CLK_RENESAS can be enabled, allowing recursion into the drivers/clk/reneasas directory, without bringing in the R-Car support code. The support code contains platform specific access (TMU_BASE) which is not needed on other Renesas devices such as RZ/N1. Signed-off-by: Ralph Siemsen Reviewed-by: Sean Anderson Reviewed-by: Marek Vasut --- (no changes since v5) Changes in v5: - add symbol CONFIG_CLK_RCAR and select it for R-Car Gen2/3. - use this to control compilation of renesas-cpg-mssr.c, rather than CONFIG_CLK_RENESAS which also controls directory recursion. - update the commit message accordingly Changes in v3: - added tags drivers/clk/renesas/Kconfig | 9 - drivers/clk/renesas/Makefile | 2 +- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 45671c6925..bdb81a1bbe 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -2,7 +2,12 @@ config CLK_RENESAS bool "Renesas clock drivers" depends on CLK && ARCH_RMOBILE help - Enable support for clock present on Renesas RCar SoCs. + Enable support for clock present on Renesas SoCs. + +config CLK_RCAR + bool "Renesas RCar clock driver support" + help + Enable common code for clocks on Renesas RCar SoCs. config CLK_RCAR_CPG_LIB bool "CPG/MSSR library functions" @@ -11,6 +16,7 @@ config CLK_RCAR_GEN2 bool "Renesas RCar Gen2 clock driver" def_bool y if RCAR_32 depends on CLK_RENESAS + select CLK_RCAR help Enable this to support the clocks on Renesas RCar Gen2 SoC. @@ -48,6 +54,7 @@ config CLK_RCAR_GEN3 bool "Renesas RCar Gen3 and Gen4 clock driver" def_bool y if RCAR_64 depends on CLK_RENESAS + select CLK_RCAR select CLK_RCAR_CPG_LIB select DM_RESET help diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index fe0391e520..c95dee67f3 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -1,4 +1,4 @@ -obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o +obj-$(CONFIG_CLK_RCAR) += renesas-cpg-mssr.o obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o -- 2.25.1
[PATCH v5 01/10] ARM: armv7: add non-SPL enable for Cortex SMPEN
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
This will be used by the following commit that adds RZ/N1 support.
(no changes since v5)
Changes in v5:
- add R-b tag
arch/arm/cpu/armv7/Kconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index f1e4e26b8f..e33e53636a 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -107,6 +107,11 @@ config ARMV7_LPAE
Say Y here to use the long descriptor page table format. This is
required if U-Boot runs in HYP mode.
+config ARMV7_SET_CORTEX_SMPEN
+ bool
+ help
+ Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
+
config SPL_ARMV7_SET_CORTEX_SMPEN
bool
help
--
2.25.1
Re: [PATCH v5 09/10] tools: spkgimage: add Renesas SPKG format
On Tue, May 09, 2023 at 11:42:30AM -0400, Ralph Siemsen wrote: On Tue, May 09, 2023 at 04:52:45PM +0200, Marek Vasut wrote: Do we have some sort of global (?) state structure which exists during the whole work cycle of the tool ? If so, add a link list into there. There is struct image_tool_params which is passed to the callbacks and holds most of the state. And in fact it is a global, but declared static in mkimage.c, without any accessor function. If we really want to worry about the lifecycle of these dynamic allocations, then we'd probably need to add some kind of "cleanup" method to the API, and call it right before exiting from main(). I can do an example implementation, but there are 9 other image formats already in the tree, which also do dynamic allocation. I don't want to start touching each one of those, or I'll never get this RZ/N1 in... I'll keep the current logic (which leaks) and send a separate RFC patch to discuss a strategy for fixing this in all the tools/*image.c drivers. Ralph
Re: [PATCH v5 08/10] board: schneider: add RZN1 board support
On Tue, May 09, 2023 at 09:21:02AM -0400, Ralph Siemsen wrote: On Tue, May 09, 2023 at 04:26:57AM +0200, Marek Vasut wrote: On 5/8/23 20:23, Ralph Siemsen wrote: I moved it to board-specific directory as an interim step. Hopefully we can do some consolidation of the multiple CDNS DDR controller implementations, and then figure out the right way to split things up. For now this seemed like the less-bad option. How about putting it into drivers/soc/ ? Possibly, although it would complicate things for me right now. I have some (as yet unfinished) patches to handle the RZ/N1 variants using drivers/soc. As discussed on IRC, it is now moved into drivers/ram/renesas/rzn1 Ralph
Re: [PATCH v5 09/10] tools: spkgimage: add Renesas SPKG format
On Tue, May 09, 2023 at 04:52:45PM +0200, Marek Vasut wrote: Do we have some sort of global (?) state structure which exists during the whole work cycle of the tool ? If so, add a link list into there. There is struct image_tool_params which is passed to the callbacks and holds most of the state. And in fact it is a global, but declared static in mkimage.c, without any accessor function. If we really want to worry about the lifecycle of these dynamic allocations, then we'd probably need to add some kind of "cleanup" method to the API, and call it right before exiting from main(). I can do an example implementation, but there are 9 other image formats already in the tree, which also do dynamic allocation. I don't want to start touching each one of those, or I'll never get this RZ/N1 in... Ralph
Re: [PATCH v5 08/10] board: schneider: add RZN1 board support
On Tue, May 09, 2023 at 04:26:57AM +0200, Marek Vasut wrote: On 5/8/23 20:23, Ralph Siemsen wrote: I moved it to board-specific directory as an interim step. Hopefully we can do some consolidation of the multiple CDNS DDR controller implementations, and then figure out the right way to split things up. For now this seemed like the less-bad option. How about putting it into drivers/soc/ ? Possibly, although it would complicate things for me right now. I have some (as yet unfinished) patches to handle the RZ/N1 variants using drivers/soc. Ralph
Re: [PATCH v5 09/10] tools: spkgimage: add Renesas SPKG format
On Tue, May 09, 2023 at 04:25:06AM +0200, Marek Vasut wrote: The usual fail path handling like: " if (there is an error) goto exit; ... exit: free(data); return ret; " does not work here ? Yes, this would handle de-allocation in the failing case. However in the normal case (no error), there is no corresponding call to free(). And there is no good place to put such a call, given the API of the callbacks. It would be possible call free() from print_header, however this is brittle since it relies on mkimage core calling print_header as the last step (and only once). Ralph
Re: [PATCH v5 08/10] board: schneider: add RZN1 board support
On Sun, May 07, 2023 at 06:06:40PM +0200, Marek Vasut wrote:
On 4/24/23 03:15, Ralph Siemsen wrote:
Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
The DT comes from Linux kernel, right ? Please include commit ID from
which the DT is imported in the commit message, I suspect that would
be Linux 6.3 commit ID.
Yes, the DT is copied verbatim from Linux. I have updated the commit
message to mention 6.3 and include the hash. (There have been no changes
diff --git a/board/schneider/rzn1-snarc/ddr_async.c
b/board/schneider/rzn1-snarc/ddr_async.c
new file mode 100644
index 00..4b4c280e45
--- /dev/null
+++ b/board/schneider/rzn1-snarc/ddr_async.c
Please correct me if I'm wrong, but shouldn't this be in drivers/ram/ ?
I had it there originally, but moved it in v5 of the patch series. There
is a lot of board-specific (or at least architecture-specific) logic in
this file. For example the sequence of steps to setup the clocks and
interconnect, prior to bringing the DDR controller out of reset. This
depends on choices made by the RZ/N1 designers, rather than the CDNS IP
that drivers/ram/cadence is aiming to cover.
Likewise for some board-specific PHY settings, and choices such as
operating in async mode.
I moved it to board-specific directory as an interim step. Hopefully we
can do some consolidation of the multiple CDNS DDR controller
implementations, and then figure out the right way to split things up.
For now this seemed like the less-bad option.
+
+ /* Step 15 Wait for 200us or more, or wait for DFIINITCOMPLETE to be
"1" */
+ while (!(phy_readl(DLLCTRL) & DLLCTRL_ASDLLOCK))
+ ;
Please avoid endless loops, use readl_poll_timeout() or
wait_for_bit*() where possible.
Will do.
+int board_init(void)
+{
+ /*
+* Initial values for gd->ram_base and gd->ram_size
+* are obtained from the "/memory" node in devicetree.
+* The size will be updated in later when probing DDR.
+*/
+ fdtdec_setup_mem_size_base();
Are you absolutely sure this call ^ is needed at all ?
I was sure at the time when I wrote it, however I just tried removing it
now and it seems to work fine.
You can just do this here:
err = uclass...();
if (err)
debug(...);
return err;
Done.
+#ifndef __RZN1_H
Better use __RZN1_SNARC_H , so that when other boards get added, there
won't be trouble.
Good catch, done.
Ralph
Re: [PATCH v5 09/10] tools: spkgimage: add Renesas SPKG format
On Sun, May 07, 2023 at 06:08:33PM +0200, Marek Vasut wrote:
[...]
+static int spkgimage_parse_config_file(char *filename)
+{
+ FILE *fcfg;
+ char line[256];
+ size_t line_num = 0;
+
+ fcfg = fopen(filename, "r");
+ if (!fcfg)
+ return -EINVAL;
+
+ conf = calloc(1, sizeof(struct config_file));
+ if (!conf)
+ return -ENOMEM;
+
+ while (fgets(line, sizeof(line), fcfg)) {
+ line_num += 1;
+
+ /* Skip blank lines and comments */
+ if (line[0] == '\n' || line[0] == '#')
+ continue;
+
+ /* Strip any trailing newline */
+ line[strcspn(line, "\n")] = 0;
+
+ /* Parse the line */
+ if (spkgimage_parse_config_line(line, line_num))
+ return -EINVAL;
Wouldn't this return -EINVAL; leak memory allocated by the calloc() above?
You are correct. But note that in the normal (non-error) code path, the
structure remains allocated as well, and there is no good place to
free() it, given the available callbacks in struct image_type_params.
So I am relying on the OS to free all memory upon program exit, both in
the error and non-error case. I would think this is reasonable for a
small one-shot utility program, keeps things simple.
If this is not acceptable, I can rework it, but there are quite a few
other spots which would also need to free resources before bailing out.
[...]
With that fixed:
Reviewed-by: Marek Vasut
I'll wait to hear back from you before applying this tag.
Regards,
Ralph
[PATCH v5 00/10] Renesas RZ/N1 SoC initial support
The RZ/N1 is a family of SoC devices from Renesas [1], featuring ARM Cortex-A7 and/or Cortex-M3 CPU, industrial ethernet protocols, integrated Ethernet switch, and numerous peripherals. This is a first step in upstreaming support for the RZ/N1 family. Currently it contains just enough to boot to the u-boot prompt. Additional patches will follow to support flash, SD, USB, Ethernet, etc. This work is based on a vendor-supplied u-boot 2017.01 tree [2], which supports several eval boards, none of which I have access to. Instead development has been done on a Schneider RZN1 board, which is fairly similar to the Renesas RZ/N1D-DB Demo board. [1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzn1 [2] https://github.com/renesas-rz/rzn1_u-boot/tree/rzn1-stable Changes in v5: - rebase to u-boot v2023.04-1037-gb646e1f69f - many small changes in response to reviewer comments - move rzn1 into mach-rmobile (similar to existing rza1) - move board-specific DDR init to board dir Changes in v4: - rebase to u-boot v2023.04-rc3 - remove RFC prefix - cc entire series to Marek by request - clock tables synced with linux (pending patches) - documentation and comment improvements Changes in v3: - many tweaks to clock driver based on reviewer feedback - rebased to u-boot v2023.04-rc2 - reviewer suggestions added to spkgimage.c - many small cleanups, checkpatch, FIXMEs resolved Changes in v2: - rewrote the stand-alone spkg_utility to integrate into mkimage Ralph Siemsen (10): ARM: armv7: add non-SPL enable for Cortex SMPEN clk: renesas: prepare for non R-Car clock drivers clk: renesas: add R906G032 driver pinctrl: renesas: add R906G032 driver ram: cadence: add driver for Cadence EDAC ARM: dts: add devicetree for Renesas RZ/N1 SoC ARM: rmobile: Add support for Renesas RZ/N1 SoC board: schneider: add RZN1 board support tools: spkgimage: add Renesas SPKG format doc: renesas: add Renesas board docs arch/arm/cpu/armv7/Kconfig|5 + arch/arm/dts/r9a06g032-ddr.dtsi | 512 arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi | 23 + arch/arm/dts/r9a06g032-rzn1-snarc.dts | 92 ++ arch/arm/dts/r9a06g032.dtsi | 477 +++ arch/arm/mach-rmobile/Kconfig | 19 + arch/arm/mach-rmobile/Kconfig.rzn1| 20 + arch/arm/mach-rmobile/cpu_info.c |8 + board/schneider/rzn1-snarc/Kconfig| 18 + board/schneider/rzn1-snarc/Makefile |3 + board/schneider/rzn1-snarc/ddr_async.c| 377 ++ board/schneider/rzn1-snarc/rzn1.c | 40 + board/schneider/rzn1-snarc/spkgimage.cfg | 26 + boot/image.c |1 + configs/rzn1_snarc_defconfig | 24 + doc/board/index.rst |1 + doc/board/renesas/index.rst | 10 + doc/board/renesas/renesas.rst | 45 + doc/board/renesas/rzn1.rst| 77 ++ doc/mkimage.1 | 45 + drivers/clk/renesas/Kconfig | 15 +- drivers/clk/renesas/Makefile |3 +- drivers/clk/renesas/r9a06g032-clocks.c| 1091 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/renesas/Kconfig |7 + drivers/pinctrl/renesas/Makefile |1 + drivers/pinctrl/renesas/pinctrl-rzn1.c| 379 ++ drivers/ram/Kconfig |1 + drivers/ram/Makefile |2 + drivers/ram/cadence/Kconfig | 12 + drivers/ram/cadence/Makefile |1 + drivers/ram/cadence/ddr_ctrl.c| 414 +++ include/configs/rzn1-snarc.h | 13 + include/dt-bindings/clock/r9a06g032-sysctrl.h | 149 +++ include/dt-bindings/pinctrl/rzn1-pinctrl.h| 141 +++ include/image.h |1 + include/renesas/ddr_ctrl.h| 175 +++ include/renesas/is43tr16256a_125k_CTL.h | 419 +++ .../renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++ tools/Makefile|1 + tools/renesas_spkgimage.c | 338 + tools/renesas_spkgimage.h | 87 ++ 42 files changed, 5471 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/r9a06g032-ddr.dtsi create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc.dts create mode 100644 arch/arm/dts/r9a06g032.dtsi create mode 100644 arch/arm/mach-rmobile/Kconfig.rzn1 create mode 100644 board/schneider/rzn1-snarc/Kconfig create mode 100644 board/schneider/rzn1-snarc/Makefile create mode 100644 board/schneider/rzn1-snarc/ddr_async.c create mode 100644 board/schneider/rzn1-snarc/rzn1.c create mode 100644 board/schneider/rzn1-snarc
[PATCH v5 08/10] board: schneider: add RZN1 board support
Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
Changes in v5:
- put all local DTS changes in r9a06g032-rzn1-snarc.dts
- move board-specific DDR init out of drivers/ram/cadence.
- tables of DDR paramters are now stored in devicetree
- support two different DDR memory types
- use BIT() macro
- obtain RZN1_DDR_BASE from DT
- uncomment error return when syscon fails
- make some functions static
Changes in v4:
- add binman support via r9a06g032-rzn1-snarc-u-boot.dtsi
Changes in v3:
- rename board LCES to rzn1-snarc
- move CONFIG_SYS_NS16550_MEM32 to Kconfig
- define CFG_SYS_INIT_RAM_{ADDR,SIZE}
- removed debug uart settings from defconfig
arch/arm/dts/r9a06g032-ddr.dtsi | 512 ++
arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi | 23 +
arch/arm/dts/r9a06g032-rzn1-snarc.dts | 92
board/schneider/rzn1-snarc/Kconfig| 18 +
board/schneider/rzn1-snarc/Makefile | 3 +
board/schneider/rzn1-snarc/ddr_async.c| 377 +
board/schneider/rzn1-snarc/rzn1.c | 40 ++
configs/rzn1_snarc_defconfig | 24 +
include/configs/rzn1-snarc.h | 13 +
include/renesas/is43tr16256a_125k_CTL.h | 419 ++
.../renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++
11 files changed, 1920 insertions(+)
create mode 100644 arch/arm/dts/r9a06g032-ddr.dtsi
create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi
create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc.dts
create mode 100644 board/schneider/rzn1-snarc/Kconfig
create mode 100644 board/schneider/rzn1-snarc/Makefile
create mode 100644 board/schneider/rzn1-snarc/ddr_async.c
create mode 100644 board/schneider/rzn1-snarc/rzn1.c
create mode 100644 configs/rzn1_snarc_defconfig
create mode 100644 include/configs/rzn1-snarc.h
create mode 100644 include/renesas/is43tr16256a_125k_CTL.h
create mode 100644 include/renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h
diff --git a/arch/arm/dts/r9a06g032-ddr.dtsi b/arch/arm/dts/r9a06g032-ddr.dtsi
new file mode 100644
index 00..8c7d0873fe
--- /dev/null
+++ b/arch/arm/dts/r9a06g032-ddr.dtsi
@@ -0,0 +1,512 @@
+// SPDX-License-Identifier: GPL-2.0
+
+ cadence,ctl-000 = <
+ DENALI_CTL_00_DATA
+ DENALI_CTL_01_DATA
+ DENALI_CTL_02_DATA
+ DENALI_CTL_03_DATA
+ DENALI_CTL_04_DATA
+ DENALI_CTL_05_DATA
+ DENALI_CTL_06_DATA
+ DENALI_CTL_07_DATA
+ DENALI_CTL_08_DATA
+ DENALI_CTL_09_DATA
+
+ DENALI_CTL_10_DATA
+ DENALI_CTL_11_DATA
+ DENALI_CTL_12_DATA
+ DENALI_CTL_13_DATA
+ DENALI_CTL_14_DATA
+ DENALI_CTL_15_DATA
+ DENALI_CTL_16_DATA
+ DENALI_CTL_17_DATA
+ DENALI_CTL_18_DATA
+ DENALI_CTL_19_DATA
+
+ DENALI_CTL_20_DATA
+ DENALI_CTL_21_DATA
+ DENALI_CTL_22_DATA
+ DENALI_CTL_23_DATA
+ DENALI_CTL_24_DATA
+ DENALI_CTL_25_DATA
+ DENALI_CTL_26_DATA
+ DENALI_CTL_27_DATA
+ DENALI_CTL_28_DATA
+ DENALI_CTL_29_DATA
+
+ DENALI_CTL_30_DATA
+ DENALI_CTL_31_DATA
+ DENALI_CTL_32_DATA
+ DENALI_CTL_33_DATA
+ DENALI_CTL_34_DATA
+ DENALI_CTL_35_DATA
+ DENALI_CTL_36_DATA
+ DENALI_CTL_37_DATA
+ DENALI_CTL_38_DATA
+ DENALI_CTL_39_DATA
+
+ DENALI_CTL_40_DATA
+ DENALI_CTL_41_DATA
+ DENALI_CTL_42_DATA
+ DENALI_CTL_43_DATA
+ DENALI_CTL_44_DATA
+ DENALI_CTL_45_DATA
+ DENALI_CTL_46_DATA
+ DENALI_CTL_47_DATA
+ DENALI_CTL_48_DATA
+ DENALI_CTL_49_DATA
+
+ DENALI_CTL_50_DATA
+ DENALI_CTL_51_DATA
+ DENALI_CTL_52_DATA
+ DENALI_CTL_53_DATA
+ DENALI_CTL_54_DATA
+ DENALI_CTL_55_DATA
+ DENALI_CTL_56_DATA
+ DENALI_CTL_57_DATA
+ DENALI_CTL_58_DATA
+ DENALI_CTL_59_DATA
+
+ DENALI_CTL_60_DATA
+ DENALI_CTL_61_DATA
+ DENALI_CTL_62_DATA
+ DENALI_CTL_63_DATA
+ DENALI_CTL_64_DATA
+ DENALI_CTL_65_DATA
+ DENALI_CTL_66_DATA
+ DENALI_CTL_67_DATA
+ DENALI_CTL_68_DATA
+ DENALI_CTL_69_DATA
+
+ DENALI_CTL_70_DATA
+ DENALI_CTL_71_D
[PATCH v5 09/10] tools: spkgimage: add Renesas SPKG format
Renesas RZ/N1 devices contain BootROM code that loads a custom SPKG
image from QSPI, NAND or USB DFU. Support this format in mkimage tool.
SPKGs can optionally be signed, however creation of signed SPKG is not
currently supported.
Example of how to use it:
tools/mkimage -n board/schneider/rzn1-snarc/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
Reviewed-by: Simon Glass
squash! tools: spkgimage: add Renesas SPKG format
---
Changes in v5:
- use strcspn() instead of open-coded loop for \n removal
- rename source files to include vendor name
- replace static globals with dynamically allocated structure
- update print_header function signature
Changes in v4:
- added tags
- add RZ/N1 board documentation
- added binman support
Changes in v3:
- provide definition of __packed (as done in kwbimage.h)
- explain why a local copy of roundup() is needed
- document spkgimage in doc/mkimage.1
- add range checks when parsing config file values
- add line numbers for reporting errors in config file
- rename SPKG_HEADER_SIGNATURE to SPKG_HEADER_MARKER
- fix segfault when image is padded by less than 4 bytes
- minor style and typo fixes
Changes in v2:
- rewrote the stand-alone spkg_utility to integrate into mkimage
board/schneider/rzn1-snarc/spkgimage.cfg | 26 ++
boot/image.c | 1 +
doc/mkimage.1| 45 +++
include/image.h | 1 +
tools/Makefile | 1 +
tools/renesas_spkgimage.c| 338 +++
tools/renesas_spkgimage.h| 87 ++
7 files changed, 499 insertions(+)
create mode 100644 board/schneider/rzn1-snarc/spkgimage.cfg
create mode 100644 tools/renesas_spkgimage.c
create mode 100644 tools/renesas_spkgimage.h
diff --git a/board/schneider/rzn1-snarc/spkgimage.cfg
b/board/schneider/rzn1-snarc/spkgimage.cfg
new file mode 100644
index 00..b5faf96b00
--- /dev/null
+++ b/board/schneider/rzn1-snarc/spkgimage.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Schneider Electric
+#
+# SPKG image header, for booting on RZ/N1
+
+# b[35:32] SPKG version
+VERSION1
+
+# b[42:41] ECC Block size: 0=256 bytes, 1=512 bytes, 2=1024 bytes
+NAND_ECC_BLOCK_SIZE1
+
+# b[45] NAND enable (boolean)
+NAND_ECC_ENABLE1
+
+# b[50:48] ECC Scheme: 0=BCH2 1=BCH4 2=BCH8 3=BCH16 4=BCH24 5=BCH32
+NAND_ECC_SCHEME3
+
+# b[63:56] ECC bytes per block
+NAND_BYTES_PER_ECC_BLOCK 28
+
+# Provide dummy BLp header (boolean)
+ADD_DUMMY_BLP 1
+
+# Pad the image to a multiple of
+PADDING64K
diff --git a/boot/image.c b/boot/image.c
index 958dbf8534..5c4f9b807d 100644
--- a/boot/image.c
+++ b/boot/image.c
@@ -181,6 +181,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_SUNXI_EGON, "sunxi_egon", "Allwinner eGON Boot Image"
},
{ IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image"
},
{ IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat
Device Tree ", },
+ { IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" },
{ -1, "", "", },
};
diff --git a/doc/mkimage.1 b/doc/mkimage.1
index d8727ec73c..76c7859bb0 100644
--- a/doc/mkimage.1
+++ b/doc/mkimage.1
@@ -662,6 +662,51 @@ rk3568
.TE
.RE
.
+.SS spkgimage
+The primary configuration file consists of lines containing key/value pairs
+delimited by whitespace. An example follows.
+.PP
+.RS
+.EX
+# Comments and blank lines may be used
+.I key1 value1
+.I key2 value2
+.EE
+.RE
+.P
+The supported
+.I key
+types are as follows.
+.TP
+.B VERSION
+.TQ
+.B NAND_ECC_BLOCK_SIZE
+.TQ
+.B NAND_ECC_ENABLE
+.TQ
+.B NAND_ECC_SCHEME
+.TQ
+.B NAND_BYTES_PER_ECC_BLOCK
+These all take a positive integer value as their argument.
+The value will be copied directly into the respective field
+of the SPKG header structure. For details on these values,
+refer to Section 7.4 of the Renesas RZ/N1 User's Manual.
+.
+.TP
+.B ADD_DUMMY_BLP
+Takes a numeric argument, which is treated as a boolean. Any nonzero
+value will cause a fake BLp security header to be included in the SPKG
+output.
+.
+.TP
+.B PADDING
+Takes a positive integer value, with an optional
+.B K
+or
+.B M
+suffix, indicating KiB / MiB respectively.
+The output SPKG file will be padded to a multiple of this value.
+.
.SS sunxi_egon
The primary configuration is the name to use for the device tree.
.
diff --git a/include/image.h b/include/image.h
index 456197d6fd..01a6787d21 100644
--- a/include/image.h
+++ b/include/image.h
@@
[PATCH v5 10/10] doc: renesas: add Renesas board docs
As a starting point, list all currently supported Renesas boards. For the RZ/N1 board, add details about booting and flashing. Signed-off-by: Ralph Siemsen --- Changes in v5: - added renesas dir to doc/board/index.rst - corrections to list of Renesas boards - move RZ/N1 detail into its own file - moved binman description ahead of mkimage doc/board/index.rst | 1 + doc/board/renesas/index.rst | 10 + doc/board/renesas/renesas.rst | 45 doc/board/renesas/rzn1.rst| 77 +++ 4 files changed, 133 insertions(+) create mode 100644 doc/board/renesas/index.rst create mode 100644 doc/board/renesas/renesas.rst create mode 100644 doc/board/renesas/rzn1.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index b2da6ec553..9040e16e01 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -33,6 +33,7 @@ Board-specific doc openpiton/index purism/index qualcomm/index + renesas/index rockchip/index samsung/index siemens/index diff --git a/doc/board/renesas/index.rst b/doc/board/renesas/index.rst new file mode 100644 index 00..fb6558ec11 --- /dev/null +++ b/doc/board/renesas/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas +=== + +.. toctree:: + :maxdepth: 2 + + renesas + rzn1 diff --git a/doc/board/renesas/renesas.rst b/doc/board/renesas/renesas.rst new file mode 100644 index 00..33a21c64ac --- /dev/null +++ b/doc/board/renesas/renesas.rst @@ -0,0 +1,45 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas +=== + +About this +-- + +This document describes the information about Renesas supported boards +and their usage steps. + +Renesas boards +-- + +Renesas is a SoC solutions provider for automotive and industrial applications. + +U-Boot supports several Renesas SoC families: + +* R-Car Gen2 (32-bit) +- Blanche board +- Gose board +- Koelsch board +- Lager board +- Silk board +- Porter board +- Stout board +* R-Car Gen3 (64-bit) +- Condor board +- Draak board +- Eagle board +- Ebisu board +- Salvator-X and Salvator-XS boards +- ULCB board +* R-Car Gen4 +- Falcon board +- Spider board +- Whitehawk board +* RZ/A1 (32-bit) +- GR-PEACH board +* RZ/G +- Beacon-rzg2 board +- Hihope-rzg2 board +- ek874 board +* RZ/N1 (32-bit) +- Schneider rzn1-snarc board diff --git a/doc/board/renesas/rzn1.rst b/doc/board/renesas/rzn1.rst new file mode 100644 index 00..2750629e81 --- /dev/null +++ b/doc/board/renesas/rzn1.rst @@ -0,0 +1,77 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas RZ/N1 += + +Building + + +This document describes how to build and flash U-Boot for the RZ/N1. + +U-Boot +^^ + +Clone the U-Boot repository and build it as follows: + +.. code-block:: bash + +git clone --depth 1 https://source.denx.de/u-boot/u-boot.git +cd u-boot +make rzn1_snarc_defconfig +make CROSS_COMPILE=arm-linux-gnu- + +This produces `u-boot` which is an ELF executable, suitable for use with `gdb` +and JTAG debugging tools. + +It also produceds `u-boot.bin` which is a raw binary. + +Binman +^^ + +The BootROM in the RZ/N1 SoC expects to find the boot image in SPKG format. +This format is documented in Chapter 7.4 of the RZ/N1 User Manual. + +The `binman` tool may be used to generate the SPKG format for booting. +This tool and its pre-requisites must be installed as per +:doc:`../../../tools/binman/binman.rst`` + +.. code-block:: bash + +binman -d arch/arm/dts/r9a06g032-rzn1-snarc.dtb -o + +This will produce `u-boot.bin.spkg` in the specified directory. It can +then be flashed into QSPI, NAND, or loaded via USB-DFU mode. + +SPKG image +^^ + +Alternatively, the same SPKG image can be built by calling `mkimage` as follows: + +.. code-block:: bash + +tools/mkimage -n board/schneider/rzn1-snarc/spkgimage.cfg \ +-T spkgimage -a 0x2004 -e 0x2004 \ +-d u-boot.bin u-boot.bin.spkg + +This produces `u-boot.bin.spkg` which can be flashed into QSPI, NAND, or loaded +via USB-DFU mode. + +Take note of the load and execution address, which are encoded into the SPKG +headers. For development convenience, mkimage computes the execution offset +(part of the SPKG header) by subtracting the supplied load address from the +supplied execution address. + +Also note there are other parameters, notably ECC configuration in the case of +boot from NAND, specified in the `spkgimage.cfg` configuration file. + +Flashing + + +The RZ/N1 is able to boot from QSPI, NAND, or via USB (DFU). In all cases the +on-board BootROM expects for the binary to be wrapped with a "SPKG" header. + +It is possible to recover a bricked unit by using the USB (DFU) boot mode. This +allows uploading U-Boot into the internal RAM. Thereafter U-Boot can be used to +program the QSPI and/or NAND, mak
[PATCH v5 06/10] ARM: dts: add devicetree for Renesas RZ/N1 SoC
This is taken directly from Linux kernel 6.3-rc7.
Signed-off-by: Ralph Siemsen
---
Changes in v5:
- r9a06g032.dtsi now identical to linux 6.3-rc7 version
Changes in v3:
- add syscon phandle to ddrctl
- simplify UART compatible strings
arch/arm/dts/r9a06g032.dtsi | 477 ++
include/dt-bindings/clock/r9a06g032-sysctrl.h | 149 ++
2 files changed, 626 insertions(+)
create mode 100644 arch/arm/dts/r9a06g032.dtsi
create mode 100644 include/dt-bindings/clock/r9a06g032-sysctrl.h
diff --git a/arch/arm/dts/r9a06g032.dtsi b/arch/arm/dts/r9a06g032.dtsi
new file mode 100644
index 00..0fa565a1c3
--- /dev/null
+++ b/arch/arm/dts/r9a06g032.dtsi
@@ -0,0 +1,477 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include
+#include
+
+/ {
+ compatible = "renesas,r9a06g032";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <1>;
+ clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+ enable-method = "renesas,r9a06g032-smp";
+ cpu-release-addr = <0 0x4000c204>;
+ };
+ };
+
+ ext_jtag_clk: extjtagclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ext_mclk: extmclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000>;
+ };
+
+ ext_rgmii_ref: extrgmiiref {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ext_rtc_clk: extrtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ rtc0: rtc@40006000 {
+ compatible = "renesas,r9a06g032-rtc",
"renesas,rzn1-rtc";
+ reg = <0x40006000 0x1000>;
+ interrupts = ,
+,
+;
+ interrupt-names = "alarm", "timer", "pps";
+ clocks = <&sysctrl R9A06G032_HCLK_RTC>;
+ clock-names = "hclk";
+ power-domains = <&sysctrl>;
+ status = "disabled";
+ };
+
+ wdt0: watchdog@40008000 {
+ compatible = "renesas,r9a06g032-wdt",
"renesas,rzn1-wdt";
+ reg = <0x40008000 0x1000>;
+ interrupts = ;
+ clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
+ status = "disabled";
+ };
+
+ wdt1: watchdog@40009000 {
+ compatible = "renesas,r9a06g032-wdt",
"renesas,rzn1-wdt";
+ reg = <0x40009000 0x1000>;
+ interrupts = ;
+ clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
+ status = "disabled";
+ };
+
+ sysctrl: system-controller@4000c000 {
+ compatible = "renesas,r9a06g032-sysctrl";
+ reg = <0x4000c000 0x1000>;
+ status = "okay";
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+
+ clocks = <&ext_mclk>, <&ext_rtc_clk>,
+ <&ext_jtag_clk>, <&ext_rgmii_ref>;
+ clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+ #address-cell
[PATCH v5 03/10] clk: renesas: add R906G032 driver
Clock driver for the Renesas RZ/N1 SoC family. This is based on
Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in
commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"),
with the following additional patch series applied:
https://lore.kernel.org/linux-renesas-soc/20230301215520.828455-1-ralph.siem...@linaro.org/
Notable difference: this version avoids allocating a 'struct clk'
for each clock source, as this is problematic before relocation.
Instead, it uses the same approach as existing Renesas R-Car Gen2/3
clock drivers, using a temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen
---
Changes in v5:
- eliminate "err" in probe function
Changes in v4:
- commit message now includes hash of Linux upon which this is based
as well as the additional patches (clock table cleanups)
- sync changes from review on linux patches, including
- move RB macro higher up and document it, matching Linux driver
- use multiply/divide instead of shifts for computing reg address
- improve comments for clock gate, descriptor structures
Changes in v3:
- convert data table to explicit reg/bit numbers
- drop the unused scon, mirack, mirstat fields
- added some kernel docs to structures
- use enum for type field of struct r9a06g032_clkdesc
- cleanup macros for one assignment per line
- add a macro for top-most clock ID value ~0
- use dev_dbg() instead of debug/print
- minor reformatting, declarations before code, etc
- !foo instead of foo == 0
- IS_ERR / PTR_ERR where appropriate
- implement div_table handling
- remove some #if 0 old test code
drivers/clk/renesas/Kconfig|6 +
drivers/clk/renesas/Makefile |1 +
drivers/clk/renesas/r9a06g032-clocks.c | 1091
3 files changed, 1098 insertions(+)
create mode 100644 drivers/clk/renesas/r9a06g032-clocks.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index bdb81a1bbe..437a82cd48 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -150,3 +150,9 @@ config CLK_R8A779G0
depends on CLK_RCAR_GEN3
help
Enable this to support the clocks on Renesas R8A779G0 SoC.
+
+config CLK_R9A06G032
+ bool "Renesas R9A06G032 clock driver"
+ depends on CLK_RENESAS
+ help
+ Enable this to support the clocks on Renesas R9A06G032 SoC.
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index c95dee67f3..48373e61b9 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
+obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c
b/drivers/clk/renesas/r9a06g032-clocks.c
new file mode 100644
index 00..62f4427068
--- /dev/null
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -0,0 +1,1091 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R9A06G032 clock driver
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet ,
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+/**
+ * struct regbit - describe one bit in a register
+ * @reg: offset of register relative to base address,
+ * expressed in units of 32-bit words (not bytes),
+ * @bit: which bit (0 to 31) in the register
+ *
+ * This structure is used to compactly encode the location
+ * of a single bit in a register. Five bits are needed to
+ * encode the bit number. With uint16_t data type, this
+ * leaves 11 bits to encode a register offset up to 2047.
+ *
+ * Since registers are aligned on 32-bit boundaries, the
+ * offset will be specified in 32-bit words rather than bytes.
+ * This allows encoding an offset up to 0x1FFC (8188) bytes.
+ *
+ * Helper macro RB() takes care of converting the register
+ * offset from bytes to 32-bit words.
+ */
+struct regbit {
+ u16 reg:11;
+ u16 bit:5;
+};
+
+#define RB(_reg, _bit) ((struct regbit) { \
+ .reg = (_reg) / 4, \
+ .bit = (_bit) \
+})
+
+/**
+ * struct r9a06g032_gate - clock-related control bits
+ * @gate: clock enable/disable
+ * @reset: clock module reset (active low)
+ * @ready: enables NoC forwarding of read/write requests to device,
+ * (eg. device is ready to handle read/write requests)
+ * @midle: request to idle the NoC interconnect
+ *
+ * Each of these fields describes a single bit in a register,
+ * which controls some aspect of clock gating. The @gate field
+ * is mandatory, this one enables/disables the clock. The
+ * other fields are optional, with zero indicating "not used".
+ *
+ * In most cases there is a @reset bit which needs to be
+ * de-asserted to bring the mod
[PATCH v5 07/10] ARM: rmobile: Add support for Renesas RZ/N1 SoC
The RZ/N1 is a family of SoC devices from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD
Add basic support for this family, modeled on the existing RZA1.
Signed-off-by: Ralph Siemsen
---
Changes in v5:
- fold mach-rzn1 into mach-rmobile
arch/arm/mach-rmobile/Kconfig | 19 +++
arch/arm/mach-rmobile/Kconfig.rzn1 | 20
arch/arm/mach-rmobile/cpu_info.c | 8
3 files changed, 47 insertions(+)
create mode 100644 arch/arm/mach-rmobile/Kconfig.rzn1
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 1ef7d68bdf..3061ccd34c 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -48,6 +48,24 @@ config RZA1
prompt "Renesas ARM SoCs RZ/A1 (32bit)"
select CPU_V7A
+config RZN1
+ prompt "Renesas ARM SoCs RZ/N1 (32bit)"
+ select CPU_V7A
+ select ARMV7_SET_CORTEX_SMPEN if !SPL
+ select SPL_ARMV7_SET_CORTEX_SMPEN if SPL
+ select CLK
+ select CLK_RENESAS
+ select CLK_R9A06G032
+ select DM
+ select DM_ETH
+ select DM_SERIAL
+ select PINCTRL
+ select PINCONF
+ select REGMAP
+ select SYSRESET
+ select SYSRESET_SYSCON
+ imply CMD_DM
+
endchoice
config SYS_SOC
@@ -56,5 +74,6 @@ config SYS_SOC
source "arch/arm/mach-rmobile/Kconfig.32"
source "arch/arm/mach-rmobile/Kconfig.64"
source "arch/arm/mach-rmobile/Kconfig.rza1"
+source "arch/arm/mach-rmobile/Kconfig.rzn1"
endif
diff --git a/arch/arm/mach-rmobile/Kconfig.rzn1
b/arch/arm/mach-rmobile/Kconfig.rzn1
new file mode 100644
index 00..73138d69f9
--- /dev/null
+++ b/arch/arm/mach-rmobile/Kconfig.rzn1
@@ -0,0 +1,20 @@
+if RZN1
+
+choice
+ prompt "Renesas RZ/N1 Board select"
+ default TARGET_SCHNEIDER_RZN1
+
+config TARGET_SCHNEIDER_RZN1
+ bool "Schneider RZN1 board"
+ help
+ Support the Schneider RZN1D and RZN1S boards, which are based
+ on the Renesas RZ/N1 SoC.
+
+endchoice
+
+config SYS_SOC
+ default "rzn1"
+
+source "board/schneider/rzn1-snarc/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 7e7465a2c8..15be32af31 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -31,6 +31,7 @@ void enable_caches(void)
#ifdef CONFIG_DISPLAY_CPUINFO
#ifndef CONFIG_RZA1
+#ifndef CONFIG_RZN1
__weak const u8 *rzg_get_cpu_name(void)
{
return 0;
@@ -128,6 +129,13 @@ int print_cpuinfo(void)
}
#else
int print_cpuinfo(void)
+{
+ printf("CPU: Renesas Electronics RZ/N1\n");
+ return 0;
+}
+#endif
+#else
+int print_cpuinfo(void)
{
printf("CPU: Renesas Electronics RZ/A1\n");
return 0;
--
2.25.1
[PATCH v5 04/10] pinctrl: renesas: add R906G032 driver
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
Changes in v5:
- add R-b tag
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/renesas/Kconfig| 7 +
drivers/pinctrl/renesas/Makefile | 1 +
drivers/pinctrl/renesas/pinctrl-rzn1.c | 379 +
include/dt-bindings/pinctrl/rzn1-pinctrl.h | 141
5 files changed, 529 insertions(+)
create mode 100644 drivers/pinctrl/renesas/pinctrl-rzn1.c
create mode 100644 include/dt-bindings/pinctrl/rzn1-pinctrl.h
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 852adee4b4..fc1f01a02c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_INTEL) += intel/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
+obj-$(CONFIG_ARCH_RZN1) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_PINCTRL_SUNXI)+= sunxi/
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 509cdd3fb2..0ea39b4a3f 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -139,3 +139,10 @@ config PINCTRL_PFC_R7S72100
Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
endif
+
+config PINCTRL_RZN1
+ bool "Renesas RZ/N1 R906G032 pin control driver"
+ depends on RZN1
+ default y if RZN1
+ help
+ Support pin multiplexing control on Renesas RZ/N1 R906G032 SoCs.
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 5cea1423ca..1a61c39d84 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o
obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
+obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
diff --git a/drivers/pinctrl/renesas/pinctrl-rzn1.c
b/drivers/pinctrl/renesas/pinctrl-rzn1.c
new file mode 100644
index 00..fdc43c8e71
--- /dev/null
+++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
+ *
+ * Phil Edworthy
+ * Based on a driver originally written by Michel Pollet at Renesas.
+ */
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+/* Field positions and masks in the pinmux registers */
+#define RZN1_L1_PIN_DRIVE_STRENGTH 10
+#define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0
+#define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1
+#define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2
+#define RZN1_L1_PIN_DRIVE_STRENGTH_12MA3
+#define RZN1_L1_PIN_PULL 8
+#define RZN1_L1_PIN_PULL_NONE 0
+#define RZN1_L1_PIN_PULL_UP1
+#define RZN1_L1_PIN_PULL_DOWN 3
+#define RZN1_L1_FUNCTION 0
+#define RZN1_L1_FUNC_MASK 0xf
+#define RZN1_L1_FUNCTION_L20xf
+
+/*
+ * The hardware manual describes two levels of multiplexing, but it's more
+ * logical to think of the hardware as three levels, with level 3 consisting of
+ * the multiplexing for Ethernet MDIO signals.
+ *
+ * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf)
specifying
+ * that level 2 functions are used instead. Level 2 has a lot more options,
+ * going from 0 to 61. Level 3 allows selection of MDIO functions which can be
+ * floating, or one of seven internal peripherals. Unfortunately, there are two
+ * level 2 functions that can select MDIO, and two MDIO channels so we have
four
+ * sets of level 3 functions.
+ *
+ * For this driver, we've compounded the numbers together, so:
+ *0 to 9 is level 1
+ * 10 to 71 is 10 + level 2 number
+ * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function.
+ * 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function.
+ * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function.
+ * 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function.
+ * Examples:
+ * Function 28 corresponds UART0
+ * Function 73 corresponds to MDIO0 to GMAC0
+ *
+ * There are 170 configurable pins (called PL_GPIO in the datasheet).
+ */
+
+/*
+ * Structure detailing the HW registers on the RZ/N1 devices.
+ * Both the Level 1 mux registers and Level 2 mux registers have the same
+ * structure. The only difference is that Level 2 has additional MDIO registers
+ * at the end.
+ */
+struct rzn1_pinctrl_regs {
+ u32 conf[170];
+ u32 pad0[86];
+ u32 status_protect; /* 0x400 */
+ /* MDIO mux registers, level2 onl
[PATCH v5 05/10] ram: cadence: add driver for Cadence EDAC
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1. Signed-off-by: Ralph Siemsen --- Changes in v5: - move board-specific init out of the driver. Changes in v3: - assorted small cleanups - support version 1.0 silicon (previously #if 0...) drivers/ram/Kconfig| 1 + drivers/ram/Makefile | 2 + drivers/ram/cadence/Kconfig| 12 + drivers/ram/cadence/Makefile | 1 + drivers/ram/cadence/ddr_ctrl.c | 414 + include/renesas/ddr_ctrl.h | 175 ++ 6 files changed, 605 insertions(+) create mode 100644 drivers/ram/cadence/Kconfig create mode 100644 drivers/ram/cadence/Makefile create mode 100644 drivers/ram/cadence/ddr_ctrl.c create mode 100644 include/renesas/ddr_ctrl.h diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 1acf212f87..bf99964577 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -108,6 +108,7 @@ config IMXRT_SDRAM This driver is for the sdram memory interface with the SEMC. source "drivers/ram/aspeed/Kconfig" +source "drivers/ram/cadence/Kconfig" source "drivers/ram/rockchip/Kconfig" source "drivers/ram/sifive/Kconfig" source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 2b9429cfee..b281129f89 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -24,3 +24,5 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/ endif obj-$(CONFIG_ARCH_OCTEON) += octeon/ + +obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/ diff --git a/drivers/ram/cadence/Kconfig b/drivers/ram/cadence/Kconfig new file mode 100644 index 00..2d5469cb8e --- /dev/null +++ b/drivers/ram/cadence/Kconfig @@ -0,0 +1,12 @@ +if RAM || SPL_RAM + +config CADENCE_DDR_CTRL + bool "Enable Cadence DDR controller" + depends on DM + help + Enable support for Cadence DDR controller, as found on + the Renesas RZ/N1 SoC. This controller has a large number + of registers which need to be programmed, mostly using values + obtained from Denali SOMA files via a TCL script. + +endif diff --git a/drivers/ram/cadence/Makefile b/drivers/ram/cadence/Makefile new file mode 100644 index 00..b4226cf6f2 --- /dev/null +++ b/drivers/ram/cadence/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_CADENCE_DDR_CTRL) += ddr_ctrl.o diff --git a/drivers/ram/cadence/ddr_ctrl.c b/drivers/ram/cadence/ddr_ctrl.c new file mode 100644 index 00..35544fbb95 --- /dev/null +++ b/drivers/ram/cadence/ddr_ctrl.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Cadence DDR Controller + * + * Copyright (C) 2015 Renesas Electronics Europe Ltd + */ + +/* + * The Cadence DDR Controller has a huge number of registers that principally + * cover two aspects, DDR specific timing information and AXI bus interfacing. + * Cadence's TCL script generates all of the register values for specific + * DDR devices operating at a specific frequency. The TCL script uses Denali + * SOMA files as inputs. The tool also generates the AXI bus register values as + * well, however this driver assumes that users will want to modifiy these to + * meet a specific application's needs. + * Therefore, this driver is passed two arrays containing register values for + * the DDR device specific information, and explicity sets the AXI registers. + * + * AXI bus interfacing: + * The controller has four AXI slaves connections, and each of these can be + * programmed to accept requests from specific AXI masters (using their IDs). + * The regions of DDR that can be accessed by each AXI slave can be set such + * as to isolate DDR used by one AXI master from another. Further, the maximum + * bandwidth allocated to each AXI slave can be set. + */ + +#include +#include +#include +#include +#include + +/* avoid warning for real pr_debug in */ +#ifdef pr_debug +#undef pr_debug +#endif + +#ifdef DEBUG + #define pr_debug(fmt, args...) printf(fmt, ##args) + #define pr_debug2(fmt, args...) printf(fmt, ##args) +#else + #define pr_debug(fmt, args...) + #define pr_debug2(fmt, args...) +#endif + +#define DDR_NR_AXI_PORTS 4 +#define DDR_NR_ENTRIES 16 + +#define DDR_START_REG (0) /* DENALI_CTL_00 */ +#define DDR_CS0_MR1_REG(32 * 4)/* DENALI_CTL_32 */ +#define DDR_CS0_MR2_REG(32 * 4 + 2)/* DENALI_CTL_32 */ +#define DDR_CS1_MR1_REG(34 * 4 + 2)/* DENALI_CTL_34 */ +#define DDR_CS1_MR2_REG(35 * 4)/* DENALI_CTL_35 */ +#define DDR_ECC_ENABLE_REG (36 * 4 + 2)/* DENALI_CTL_36 */ +#define DDR_ECC_DISABLE_W_UC_ERR_REG (37 * 4 + 2)/* DENALI_CTL_37 */ +#define DDR_HALF_DATAPATH_REG (54 * 4)/* DENALI_CTL_54 */ +#define DDR_INTERRUPT_STATUS
[PATCH v5 01/10] ARM: armv7: add non-SPL enable for Cortex SMPEN
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
This will be used by the following commit that adds RZ/N1 support.
Changes in v5:
- add R-b tag
arch/arm/cpu/armv7/Kconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index f1e4e26b8f..e33e53636a 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -107,6 +107,11 @@ config ARMV7_LPAE
Say Y here to use the long descriptor page table format. This is
required if U-Boot runs in HYP mode.
+config ARMV7_SET_CORTEX_SMPEN
+ bool
+ help
+ Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
+
config SPL_ARMV7_SET_CORTEX_SMPEN
bool
help
--
2.25.1
[PATCH v5 02/10] clk: renesas: prepare for non R-Car clock drivers
Add new CONFIG_CLK_RCAR to control compilation of shared code for R-Car clock drivers (renesas-cpg-mssr.c). Enable this for R-Car Gen2 and 3. This is necessary so that CONFIG_CLK_RENESAS can be enabled, allowing recursion into the drivers/clk/reneasas directory, without bringing in the R-Car support code. The support code contains platform specific access (TMU_BASE) which is not needed on other Renesas devices such as RZ/N1. Signed-off-by: Ralph Siemsen Reviewed-by: Sean Anderson --- Changes in v5: - add symbol CONFIG_CLK_RCAR and select it for R-Car Gen2/3. - use this to control compilation of renesas-cpg-mssr.c, rather than CONFIG_CLK_RENESAS which also controls directory recursion. - update the commit message accordingly Changes in v3: - added tags drivers/clk/renesas/Kconfig | 9 - drivers/clk/renesas/Makefile | 2 +- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 45671c6925..bdb81a1bbe 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -2,7 +2,12 @@ config CLK_RENESAS bool "Renesas clock drivers" depends on CLK && ARCH_RMOBILE help - Enable support for clock present on Renesas RCar SoCs. + Enable support for clock present on Renesas SoCs. + +config CLK_RCAR + bool "Renesas RCar clock driver support" + help + Enable common code for clocks on Renesas RCar SoCs. config CLK_RCAR_CPG_LIB bool "CPG/MSSR library functions" @@ -11,6 +16,7 @@ config CLK_RCAR_GEN2 bool "Renesas RCar Gen2 clock driver" def_bool y if RCAR_32 depends on CLK_RENESAS + select CLK_RCAR help Enable this to support the clocks on Renesas RCar Gen2 SoC. @@ -48,6 +54,7 @@ config CLK_RCAR_GEN3 bool "Renesas RCar Gen3 and Gen4 clock driver" def_bool y if RCAR_64 depends on CLK_RENESAS + select CLK_RCAR select CLK_RCAR_CPG_LIB select DM_RESET help diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index fe0391e520..c95dee67f3 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -1,4 +1,4 @@ -obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o +obj-$(CONFIG_CLK_RCAR) += renesas-cpg-mssr.o obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o -- 2.25.1
Re: [PATCH] rmobile: avoid deprecated srec_cat flags
On Tue, Apr 18, 2023 at 3:36 PM Marek Vasut wrote: > I'm afraid this needs some backward compatibility sreccat version check > . Similar to GCC compiler flags presence check. To avoid breaking legacy > users. I'll revisit this after the rz/n1 work, which is more important. Also I noticed that srec_cat is being called even when it is not installed, which of course causes the build to fail. This is curious since the makefile checks for srec_cat prior to using it. Ralph
[PATCH] rmobile: avoid deprecated srec_cat flags
The -l-e-constant flag has been deprecated since 2012. [1] Use the recommended replacement instead. [1] https://sourceforge.net/p/srecord/code/ci/1.59.D009/ Signed-off-by: Ralph Siemsen --- arch/arm/mach-rmobile/Makefile | 48 +- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 5b86221bc2..84ee70fb6e 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -52,34 +52,34 @@ quiet_cmd_srec_cat = SRECCAT $@ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ -offset -0x13fd0 \ -Output_Block_Size 16 \ - -generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \ - -generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \ - -generate 0xe63005d4 0xe63005d8 -l-e-constant 0xe6304000 4 \ - -generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \ - -generate 0xe6301154 0xe6301158 -l-e-constant 0xe6304000 4 \ - -generate 0xe6301264 0xe6301268 -l-e-constant $2 4 \ - -generate 0xe6304000 0xe6304004 -l-e-constant 0xd2bcc000 4 \ - -generate 0xe6304004 0xe6304008 -l-e-constant 0xb26c0400 4 \ - -generate 0xe6304008 0xe630400c -l-e-constant 0xb2720001 4 \ - -generate 0xe630400c 0xe6304010 -l-e-constant 0xb27c0421 4 \ - -generate 0xe6304010 0xe6304014 -l-e-constant 0xb2710402 4 \ - -generate 0xe6304014 0xe6304018 -l-e-constant 0xaa0203e0 4 \ - -generate 0xe6304018 0xe630401c -l-e-constant 0xd28e0003 4 \ - -generate 0xe630401c 0xe6304020 -l-e-constant 0xa8c11424 4 \ - -generate 0xe6304020 0xe6304024 -l-e-constant 0xa8811444 4 \ - -generate 0xe6304024 0xe6304028 -l-e-constant 0xf1004063 4 \ - -generate 0xe6304028 0xe630402c -l-e-constant 0x54aa 4 \ - -generate 0xe630402c 0xe6304030 -l-e-constant 0xd61f 4 + -generate 0xe6300400 0xe6300404 -constant-l-e 0x0 4 \ + -generate 0xe630048c 0xe6300490 -constant-l-e 0x0 4 \ + -generate 0xe63005d4 0xe63005d8 -constant-l-e 0xe6304000 4 \ + -generate 0xe63006e4 0xe63006e8 -constant-l-e $2 4 \ + -generate 0xe6301154 0xe6301158 -constant-l-e 0xe6304000 4 \ + -generate 0xe6301264 0xe6301268 -constant-l-e $2 4 \ + -generate 0xe6304000 0xe6304004 -constant-l-e 0xd2bcc000 4 \ + -generate 0xe6304004 0xe6304008 -constant-l-e 0xb26c0400 4 \ + -generate 0xe6304008 0xe630400c -constant-l-e 0xb2720001 4 \ + -generate 0xe630400c 0xe6304010 -constant-l-e 0xb27c0421 4 \ + -generate 0xe6304010 0xe6304014 -constant-l-e 0xb2710402 4 \ + -generate 0xe6304014 0xe6304018 -constant-l-e 0xaa0203e0 4 \ + -generate 0xe6304018 0xe630401c -constant-l-e 0xd28e0003 4 \ + -generate 0xe630401c 0xe6304020 -constant-l-e 0xa8c11424 4 \ + -generate 0xe6304020 0xe6304024 -constant-l-e 0xa8811444 4 \ + -generate 0xe6304024 0xe6304028 -constant-l-e 0xf1004063 4 \ + -generate 0xe6304028 0xe630402c -constant-l-e 0x54aa 4 \ + -generate 0xe630402c 0xe6304030 -constant-l-e 0xd61f 4 else quiet_cmd_srec_cat = SRECCAT $@ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ -Output_Block_Size 16 \ - -generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \ - -generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \ - -generate 0xe63005d4 0xe63005d8 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \ - -generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \ - -generate 0xe6301154 0xe6301158 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \ - -generate 0xe6301264 0xe6301268 -l-e-constant $2 4 + -generate 0xe6300400 0xe6300404 -constant-l-e 0x0 4 \ + -generate 0xe630048c 0xe6300490 -constant-l-e 0x0 4 \ + -generate 0xe63005d4 0xe63005d8 -constant-l-e $(CONFIG_SPL_TEXT_BASE) 4 \ + -generate 0xe63006e4 0xe63006e8 -constant-l-e $2 4 \ + -generate 0xe6301154 0xe6301158 -constant-l-e $(CONFIG_SPL_TEXT_BASE) 4 \ + -generate 0xe6301264 0xe6301268 -constant-l-e $2 4 endif spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin -- 2.25.1
Re: [PATCH v4 01/10] ARM: armv7: add non-SPL enable for Cortex SMPEN
On Mon, Apr 17, 2023 at 4:21 PM Marek Vasut wrote:
>
> On 4/17/23 20:26, Ralph Siemsen wrote:
> > On Mon, Apr 17, 2023 at 07:04:15PM +0200, Marek Vasut wrote:
> >> You could send this patch as a separate one.
> >
> > In fact I did that almost a year ago:
> > https://lore.kernel.org/u-boot/20220421175202.2614945-1-ralph.siem...@linaro.org/T/#u
>
> Hmmm, Tom (+Cc) pointed out the patch does not do anything, but that is
> not correct, is it ? If I look at 2564fce7eea3 ("sunxi: move Cortex
> SMPEN setting into start.S") , this extra Kconfig symbol just makes that
> functionality available outside of SPL (i.e. in normal U-Boot), while
> before this change the functionality was only available in SPL. Right ?
Correct, my patch makes the symbol available outside of SPL.
I think Tom's objection was to adding the symbol without any users.
This is rectified by patch 07 ("ARM: rzn1: basic support"),
Ralph
Re: [PATCH v4 10/10] doc: renesas: add Renesas board docs
On Mon, Apr 17, 2023 at 10:34:08PM +0200, Marek Vasut wrote: On 4/17/23 22:29, Ralph Siemsen wrote: Indeed it does, see below. I did however want to document how to call mkimage manually, since it took me a while to work out the right arguments (especially using -n for the config file). Then maybe just swap the binman and mkimage chapters and be done with it ? You mean put binman info first? Sure, I can do that ;-) Ralph
Re: [PATCH v4 02/10] clk: renesas: prepare for non-RCAR clock drivers
On Mon, Apr 17, 2023 at 10:33:18PM +0200, Marek Vasut wrote: On 4/17/23 20:22, Ralph Siemsen wrote: Perhaps we could change Kconfig to select CPG also for gen2. I can make this patch, but how to test that this does not introduce any new problems? Might there be an autobuilder for R-Car somewhere? You could introduce CONFIG_CLK_RCAR Kconfig symbol and use that for renesas-cpg-mssr.o . Would that work ? I can certainly make the patch, and hopefully also do at least a compile-test. Though I will need to figure out which defconfigs I need to test... Ralph
Re: [PATCH v4 07/10] ARM: rzn1: basic support for Renesas RZ/N1 SoC
On Mon, Apr 17, 2023 at 10:30:26PM +0200, Marek Vasut wrote: I mean, if you drop 'CLK' and 'CLK_RENESAS' from this list, do they still get selected because 'CLK_R8A06G032' is in this list ? If yes, then drop them from this list, else keep them. If I drop the first two, I get some kconfig warnings: WARNING: unmet direct dependencies detected for CLK_R9A06G032 Depends on [n]: CLK_RENESAS [=n] Selected by [y]: - ARCH_RZN1 [=y] && And there is no output on the UART. I don't have a strong preference, if moving to mach-rmobile makes sense, let me know and I can give it a go. I think it does make sense to keep all the renesas stuff in mach-rmobile . We can rename that to mach-renesas in some subsequent patch. Okay, I will try moving it. Does this also then mean I should abandon ARCH_RZN1 in favour of ARCH_RMOBILE? This could be more challenging... Why not enable icache with icache_enable() too ? The I-cache is enabled quite early in arch/arm/cpu/armv7/start.S Add a comment please. Done! Ralph
Re: [PATCH v4 05/10] ram: cadence: add driver for Cadence EDAC
On Mon, Apr 17, 2023 at 07:32:30PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
[...]
+#define FUNCCTRL 0x00
+#define FUNCCTRL_MASKSDLOFS (0x18 << 16)
+#define FUNCCTRL_DVDDQ_1_5V (1 << 8)
+#define FUNCCTRL_RESET_N (1 << 0)
+#define DLLCTRL0x04
+#define DLLCTRL_ASDLLOCK (1 << 26)
+#define DLLCTRL_MFSL_500MHz (2 << 1)
+#define DLLCTRL_MDLLSTBY (1 << 0)
Use BIT() macro where applicable.
Will do.
+ /* DDR PHY setup */
+ phy_writel(DLLCTRL_MFSL_500MHz | DLLCTRL_MDLLSTBY, DLLCTRL);
+ phy_writel(0x0182, ZQCALCTRL);
+ if (ddr_type == RZN1_DDR3_DUAL_BANK)
+ phy_writel(0xAB330031, ZQODTCTRL);
+ else if (ddr_type == RZN1_DDR3_SINGLE_BANK)
+ phy_writel(0xAB320051, ZQODTCTRL);
+ else /* DDR2 */
+ phy_writel(0xAB330071, ZQODTCTRL);
+ phy_writel(0xB545B544, RDCTRL);
+ phy_writel(0x00B0, RDTMG);
+ phy_writel(0x020A0806, OUTCTRL);
+ if (ddr_type == RZN1_DDR3_DUAL_BANK)
+ phy_writel(0x80005556, WLCTRL1);
+ else
+ phy_writel(0x80005C5D, WLCTRL1);
+ phy_writel(0x0101, FIFOINIT);
+ phy_writel(0x4545, DQCALOFS1);
Is there any macro which defines those magic bits in magic numbers ?
If so, please use them.
This init sequence came from the u-boot 2017 repo published by Renesas.
There do not appear to be any macros to help with all these magic
numbers.
+ /* DDR Controller is always in ASYNC mode */
+ cdns_ddr_ctrl_init((void *)RZN1_DDR_BASE, 1,
+ ddr_00_87_async, ddr_350_374_async,
+ ddr_start_addr, CFG_SYS_SDRAM_SIZE,
+ priv->enable_ecc, priv->enable_8bit);
+
+ rzn1_ddr3_single_bank((void *)RZN1_DDR_BASE);
Can you obtain the DRAM base from DT ?
I'll check if it is possible.
+ priv->syscon = syscon_regmap_lookup_by_phandle(dev, "syscon");
+ if (IS_ERR(priv->syscon)) {
+ dev_err(dev, "No syscon node found\n");
+ //return PTR_ERR(priv->syscon);
This shouldn't be commented out, right ?
Does indeed look like an oversight. I'll fix it up, thanks for spotting!
Ralph
Re: [PATCH v4 10/10] doc: renesas: add Renesas board docs
On Mon, Apr 17, 2023 at 07:28:05PM +0200, Marek Vasut wrote: On 3/8/23 21:26, Ralph Siemsen wrote: RZ/N1 +- Schneider rzn1-snarc board + +Building + + +NOTE: the following information is for the rzn1 board only. Maybe this should be in a separate document , some rzn1 specific .rst file ? Originally I did just document the RZ/N1 stuff, since I really have no experience or knowledge of the other ones. But it felt wrong to create "doc/board/renesas" containing only RZ/N1 information. So I tried to at least collect the names of the other Renesas boards from U-Boot sources. I'll make the fixes you suggested, and will move the RZ/N1 details into their own file. +tools/mkimage -n board/schneider/rzn1-snarc/spkgimage.cfg \ +-T spkgimage -a 0x2004 -e 0x2004 \ +-d u-boot.bin u-boot.bin.spkg Shouldn't binman do this for you ? That should be the primary option. Indeed it does, see below. I did however want to document how to call mkimage manually, since it took me a while to work out the right arguments (especially using -n for the config file). +Binman +^^ + +Alternatively `binman` may be used to generate the SPKG format for booting. +This tool and its pre-requisites must be installed as per +:doc:`../../../tools/binman/binman.rst`` + +.. code-block:: bash + +binman -d arch/arm/dts/r9a06g032-rzn1-snarc.dtb -o + +This will produce `u-boot.bin.spkg` in the specified directory. Ralph
Re: [PATCH v4 09/10] tools: spkgimage: add Renesas SPKG format
On Mon, Apr 17, 2023 at 07:23:46PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
+ spkgimage.o \
Maybe just call the file renesas_spkgimage.o so its clear which
SoC/vendor this file is associtated with.
Okay, will do.
+static struct spkg_file out_buf;
+
+static uint32_t padding;
Is this padding here and the padding in struct config_file below
different padding ? Can we get rid of these static global variables ?
I will give it a try.
+static int check_range(const char *name, int val, int min, int max)
+{
+ if (val < min) {
+ fprintf(stderr, "Warning: param '%s' adjusted to min %d\n",
+ name, min);
+ val = min;
+ }
+
+ if (val > max) {
+ fprintf(stderr, "Warning: param '%s' adjusted to max %d\n",
+ name, max);
+ val = max;
+ }
There is a macro clamp() which implements range limiting .
Thanks for pointing that out. However I think there is value in the
diagnostic print when the value is clamped. Ideally it should help the
user to fix their invoking script/binman/etc.
Of course, I could call clamp() and check if the value differs, but that
seems just as complex as the check_range().
+ while (fgets(line, sizeof(line), fcfg)) {
+ line_num += 1;
+
+ /* Skip blank lines and comments */
+ if (line[0] == '\n' || line[0] == '#')
+ continue;
+
+ /* Strip the trailing newline */
+ len = strlen(line);
+ if (line[len - 1] == '\n')
+ line[--len] = 0;
Use len - 1 here too to avoid confusion ?
Old habit. I always try to update the length in sync with modifying the
string. If done as a separate line/statement, it is more likely to be
lost during subsequent modifications.
In this case I do not need "len" at all, so I could just do:
line[strcspn(line, "\n")] = 0;
Ralph
Re: [PATCH v4 08/10] board: schneider: add RZN1 board support
On Mon, Apr 17, 2023 at 07:18:46PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
diff --git a/board/schneider/rzn1-snarc/ddr_timing.c
b/board/schneider/rzn1-snarc/ddr_timing.c
new file mode 100644
index 00..8bc3fe7be4
--- /dev/null
+++ b/board/schneider/rzn1-snarc/ddr_timing.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include
+
+#include "jedec_ddr3_2g_x16_1333h_500_cl8.h"
+
+u32 ddr_00_87_async[] = {
Should this be 'static u32...' ?
It should, but there is bit of kludge going on here. This table is used
when starting the DDR controller, in drivers/ram/cadence/ddr_async.c
There are several other boards in u-boot already which appear to use the
same (or a similar) DDR controller from Cadence. Some of these also use
a similar kludge as I have done. Others instead put the DDR parameters
into the device tree.
While using the devicetree is cleaner, it does increase the size of the
DTB by quite a bit, which creates some additional challenges. Even more
so when you need to support multiple DDR chips, each with their own
configuration parameters.
So I opted for the low-tech approach, at least in this initial version.
+#define DENALI_CTL_00_DATA 0x0600
You might want to run checkpatch --f --fix --fix-inplace on this to
fix formatting , esp. use one space after #define and tab after the
macro name. Note that diff -wdb will let you diff updates to this file
while ignoring space changes.
+#define DENALI_CTL_01_DATA 0x
+#define DENALI_CTL_02_DATA 0x
+#define DENALI_CTL_03_DATA 0x
+#define DENALI_CTL_04_DATA 0x
I had also considered eliminating the header file entirely, and just
putting the values directly into the array in the .c file. It is not
like the names of the #defines are particularly illuminating.
However, this runs into friction each time a new DDR appears, along with
the new set of parameters (autogenerated by some vendor tool). In fact
I've had to add some new DDR devices quite recently (but that didn't
make it into the current patches).
I'm happy to reformat this to match upstream preference. But I would
also be happy to discuss how we can better handle this type of "large
binary blob" of configuration data, to make it simpler for everyone.
+++ b/board/schneider/rzn1-snarc/rzn1.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct udevice *dev;
+ int err;
+
+ /* This will end up calling cadence_ddr_probe() */
+ err = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (err) {
+ debug("DRAM init failed: %d\n", err);
+ return err;
+ }
+
+ if (fdtdec_setup_mem_size_base() != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
I wonder how much of this should really be in arch/... since this is
common to all machines with RZN1 . Maybe move it there instead ?
I can certainly do that. When I first put this together, I looked at
many other dram_init() functions, both in arch/... and board/...
Ralph
Re: [PATCH v4 07/10] ARM: rzn1: basic support for Renesas RZ/N1 SoC
On Mon, Apr 17, 2023 at 07:15:07PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
[...]
+++ b/arch/arm/Kconfig
@@ -1031,6 +1031,21 @@ config ARCH_RMOBILE
imply SYS_THUMB_BUILD
imply ARCH_MISC_INIT if DISPLAY_CPUINFO
+config ARCH_RZN1
+ bool "Reneasa RZ/N1 SoC"
+ select CLK
+ select CLK_RENESAS
+ select CLK_R9A06G032
Does 'select CLK_R9A06G032' automatically activate the dependencies
like 'CLK_RENESAS' too ?
Do you mean things like CLK_RCAR_CPG_LIB for example?
The new clock driver has no dependencies (except perhaps ARCH_RZN1).
Since this clock driver is essential to boot, I figured it was best to
select it in Kconfig, rather than require each board defconfig to
specify the same options.
If there is a better/preferred approach, I will implement it.
+ select DM
+ select DM_ETH
+ select DM_SERIAL
+ select PINCTRL
+ select PINCONF
+ select REGMAP
+ select SYSRESET
+ select SYSRESET_SYSCON
+ imply CMD_DM
+
config ARCH_SNAPDRAGON
bool "Qualcomm Snapdragon SoCs"
select ARM64
@@ -2207,6 +,8 @@ source "arch/arm/mach-owl/Kconfig"
source "arch/arm/mach-rmobile/Kconfig"
+source "arch/arm/mach-rzn1/Kconfig"
Should this be in mach-rmobile (which, maybe, should be renamed to
mach-renesas) ?
I vaguely recall that I discussed this with someone (possibly you),
likely on IRC. And I think the conclusion was there was a significant
enough difference (possibly Cortex-A7 versus A9?).
I don't have a strong preference, if moving to mach-rmobile makes sense,
let me know and I can give it a go.
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+void enable_caches(void)
+{
Why not enable icache with icache_enable() too ?
The I-cache is enabled quite early in arch/arm/cpu/armv7/start.S
Ralph
Re: [PATCH v4 06/10] dts: basic devicetree for Renesas RZ/N1 SoC
On Mon, Apr 17, 2023 at 07:12:31PM +0200, Marek Vasut wrote: On 3/8/23 21:26, Ralph Siemsen wrote: This is taken from Linux kernel 5.17, and contains just bare minimum functionality: CPU, UART and system timer. Why Linux 5.17 and not e.g. 6.2 or 6.1 LTS ? It was the current version at the time when this work was started. I fully intend to update it, especially now that much of the RZ/N1 support has landed in mainline. Can you extract all the changes to arch/arm/dts/r9a06g032-u-boot.dtsi and include that u-boot dtsi in your board DT, so the arch/arm/dts/r9a06g032.dtsi can be synchronized with Linux with ease due to no changes in it ? I'll see if I can make that work. Ralph
Re: [PATCH v4 03/10] clk: renesas: add R906G032 driver
On Mon, Apr 17, 2023 at 07:07:57PM +0200, Marek Vasut wrote:
R-Car , not RCAR .
Ack, will fix in next version (including in some commit msg)
+static int r9a06g032_clk_probe(struct udevice *dev)
+{
+ struct r9a06g032_priv *priv = dev_get_priv(dev);
+ int err;
+
+ priv->regmap = syscon_regmap_lookup_by_phandle(dev, "regmap");
+ if (IS_ERR(priv->regmap)) {
+ dev_dbg(dev, "unable to find regmap\n");
+ return PTR_ERR(priv->regmap);
+ }
+
+ /* Enable S/W reset */
+ regmap_write(priv->regmap, 0x120, 0x41);
+
+ /* Get master clock */
+ err = clk_get_by_name(dev, "mclk", &priv->mclk);
+ if (err)
+ return err;
+
+ return 0;
You can use 'return clk_get_by_name(...)' here directly instead of the
Will do.
Ralph
Re: [PATCH v4 01/10] ARM: armv7: add non-SPL enable for Cortex SMPEN
On Mon, Apr 17, 2023 at 07:04:15PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
You could send this patch as a separate one.
In fact I did that almost a year ago:
https://lore.kernel.org/u-boot/20220421175202.2614945-1-ralph.siem...@linaro.org/T/#u
Ralph
Re: [PATCH v4 02/10] clk: renesas: prepare for non-RCAR clock drivers
Hi Marek, On Mon, Apr 17, 2023 at 07:02:34PM +0200, Marek Vasut wrote: On 3/8/23 21:26, Ralph Siemsen wrote: diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 8f82a7aa3e..a0d8c10bdb 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -1,6 +1,5 @@ -obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o -obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o +obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o renesas-cpg-mssr.o Why not move the renesas-cpg-mssr.o into obj-$(CONFIG_CLK_RCAR_CPG_LIB) line instead ? I think this would break the build for gen2 devices, because they make calls to CPG functions (eg. renesas_clk_endisable from clk-rcar-gen2.c), however Kconfig only selects CPG lib for gen3. Perhaps we could change Kconfig to select CPG also for gen2. I can make this patch, but how to test that this does not introduce any new problems? Might there be an autobuilder for R-Car somewhere? I suspect RZN1 is not using the CPG lib anyway ? You are correct, RZN1 does not use the CPG lib. Regards Ralph
[PATCH v4 00/10] Renesas RZ/N1 SoC initial support
The RZ/N1 is a family of SoC devices from Renesas [1], featuring ARM Cortex-A7 and/or Cortex-M3 CPU, industrial ethernet protocols, integrated Ethernet switch, and numerous peripherals. This is a first step in upstreaming support for the RZ/N1 family. Currently it contains just enough to boot to the u-boot prompt. Additional patches will follow to support flash, SD, USB, Ethernet, etc. This work is based on a vendor-supplied u-boot 2017.01 tree [2], which supports several eval boards, none of which I have access to. Instead development has been done on a Schneider RZN1 board, which is fairly similar to the Renesas RZ/N1D-DB Demo board. [1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzn1 [2] https://github.com/renesas-rz/rzn1_u-boot/tree/rzn1-stable Changes in v4: - rebase to u-boot v2023.04-rc3 - remove RFC prefix - cc entire series to Marek by request - clock tables synced with linux (pending patches) - documentation and comment improvements Changes in v3: - many tweaks to clock driver based on reviewer feedback - rebased to u-boot v2023.04-rc2 - reviewer suggestions added to spkgimage.c - many small cleanups, checkpatch, FIXMEs resolved Changes in v2: - rewrote the stand-alone spkg_utility to integrate into mkimage Ralph Siemsen (10): ARM: armv7: add non-SPL enable for Cortex SMPEN clk: renesas: prepare for non-RCAR clock drivers clk: renesas: add R906G032 driver pinctrl: renesas: add R906G032 driver ram: cadence: add driver for Cadence EDAC dts: basic devicetree for Renesas RZ/N1 SoC ARM: rzn1: basic support for Renesas RZ/N1 SoC board: schneider: add RZN1 board support tools: spkgimage: add Renesas SPKG format doc: renesas: add Renesas board docs arch/arm/Kconfig | 17 + arch/arm/Makefile |1 + arch/arm/cpu/armv7/Kconfig|5 + arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi | 23 + arch/arm/dts/r9a06g032-rzn1-snarc.dts | 51 + arch/arm/dts/r9a06g032.dtsi | 226 arch/arm/mach-rzn1/Kconfig| 32 + arch/arm/mach-rzn1/Makefile |3 + arch/arm/mach-rzn1/cpu_info.c | 19 + board/schneider/rzn1-snarc/Kconfig| 18 + board/schneider/rzn1-snarc/Makefile |3 + board/schneider/rzn1-snarc/ddr_timing.c | 140 +++ .../jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++ board/schneider/rzn1-snarc/rzn1.c | 39 + board/schneider/rzn1-snarc/spkgimage.cfg | 26 + boot/image.c |1 + configs/rzn1_snarc_defconfig | 21 + doc/board/renesas/index.rst |9 + doc/board/renesas/renesas.rst | 115 ++ doc/mkimage.1 | 45 + drivers/clk/renesas/Kconfig |8 +- drivers/clk/renesas/Makefile |6 +- drivers/clk/renesas/r9a06g032-clocks.c| 1096 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/renesas/Kconfig |7 + drivers/pinctrl/renesas/Makefile |1 + drivers/pinctrl/renesas/pinctrl-rzn1.c| 379 ++ drivers/ram/Kconfig |1 + drivers/ram/Makefile |2 + drivers/ram/cadence/Kconfig | 12 + drivers/ram/cadence/Makefile |1 + drivers/ram/cadence/ddr_async.c | 311 + drivers/ram/cadence/ddr_ctrl.c| 414 +++ drivers/ram/cadence/ddr_ctrl.h| 175 +++ include/configs/rzn1-snarc.h | 17 + include/dt-bindings/clock/r9a06g032-sysctrl.h | 148 +++ include/dt-bindings/pinctrl/rzn1-pinctrl.h| 141 +++ include/image.h |1 + tools/Makefile|1 + tools/spkgimage.c | 330 + tools/spkgimage.h | 87 ++ 41 files changed, 4328 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc.dts create mode 100644 arch/arm/dts/r9a06g032.dtsi create mode 100644 arch/arm/mach-rzn1/Kconfig create mode 100644 arch/arm/mach-rzn1/Makefile create mode 100644 arch/arm/mach-rzn1/cpu_info.c create mode 100644 board/schneider/rzn1-snarc/Kconfig create mode 100644 board/schneider/rzn1-snarc/Makefile create mode 100644 board/schneider/rzn1-snarc/ddr_timing.c create mode 100644 board/schneider/rzn1-snarc/jedec_ddr3_2g_x16_1333h_500_cl8.h create mode 100644 board/schneider/rzn1-snarc/rzn1.c create mode 100644 board/schneider/rzn1-snarc/spkgimage.cfg create mode 100644 configs/rzn1_snarc_defconfig create mode 100644 doc/board/renesas/index.rst create mode 100644 doc/board/renesas/renesas.rst create mode
[PATCH v4 08/10] board: schneider: add RZN1 board support
Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
Changes in v4:
- add binman support via r9a06g032-rzn1-snarc-u-boot.dtsi
Changes in v3:
- rename board LCES to rzn1-snarc
- move CONFIG_SYS_NS16550_MEM32 to Kconfig
- define CFG_SYS_INIT_RAM_{ADDR,SIZE}
- removed debug uart settings from defconfig
arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi | 23 +
arch/arm/dts/r9a06g032-rzn1-snarc.dts | 51 +++
arch/arm/mach-rzn1/Kconfig| 14 +
board/schneider/rzn1-snarc/Kconfig| 18 +
board/schneider/rzn1-snarc/Makefile | 3 +
board/schneider/rzn1-snarc/ddr_timing.c | 140 ++
.../jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++
board/schneider/rzn1-snarc/rzn1.c | 39 ++
configs/rzn1_snarc_defconfig | 21 +
include/configs/rzn1-snarc.h | 17 +
10 files changed, 725 insertions(+)
create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi
create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc.dts
create mode 100644 board/schneider/rzn1-snarc/Kconfig
create mode 100644 board/schneider/rzn1-snarc/Makefile
create mode 100644 board/schneider/rzn1-snarc/ddr_timing.c
create mode 100644 board/schneider/rzn1-snarc/jedec_ddr3_2g_x16_1333h_500_cl8.h
create mode 100644 board/schneider/rzn1-snarc/rzn1.c
create mode 100644 configs/rzn1_snarc_defconfig
create mode 100644 include/configs/rzn1-snarc.h
diff --git a/arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi
b/arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi
new file mode 100644
index 00..794e711103
--- /dev/null
+++ b/arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Configuration file for binman
+ *
+ * After building u-boot, can generate the SPKG output by running:
+ * tools/binman/binman build -d arch/arm/dts/r9a06g032-rzn1-snarc.dtb -O
+ */
+
+#include
+
+/ {
+ binman: binman {
+ };
+};
+
+&binman {
+ mkimage {
+ filename = "u-boot.bin.spkg";
+ args = "-n board/schneider/rzn1-snarc/spkgimage.cfg -T
spkgimage -a 0x2004 -e 0x2004";
+ u-boot {
+ };
+ };
+};
diff --git a/arch/arm/dts/r9a06g032-rzn1-snarc.dts
b/arch/arm/dts/r9a06g032-rzn1-snarc.dts
new file mode 100644
index 00..abb269cc21
--- /dev/null
+++ b/arch/arm/dts/r9a06g032-rzn1-snarc.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for Schneider RZ/N1 Board
+ *
+ * Based on r9a06g032-rzn1d400-db.dts
+ */
+
+/dts-v1/;
+
+#include "r9a06g032.dtsi"
+#include
+
+/ {
+ model = "Schneider RZ/N1 Board";
+ compatible = "schneider,rzn1", "renesas,r9a06g032";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x8000 0x1000>;
+ };
+};
+
+&ddrctrl {
+ status = "okay";
+};
+
+&pinctrl {
+ status = "okay";
+
+ pins_uart0: pins_uart0 {
+ pinmux = <
+ RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
+ RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
+ >;
+ bias-disable;
+ };
+};
+
+&uart0 {
+ pinctrl-0 = <&pins_uart0>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm/mach-rzn1/Kconfig b/arch/arm/mach-rzn1/Kconfig
index 707895874d..4b13afbb32 100644
--- a/arch/arm/mach-rzn1/Kconfig
+++ b/arch/arm/mach-rzn1/Kconfig
@@ -15,4 +15,18 @@ endchoice
config SYS_SOC
default "rzn1"
+choice
+ prompt "Board select"
+ default TARGET_SCHNEIDER_RZN1
+
+config TARGET_SCHNEIDER_RZN1
+ bool "Schneider RZN1 board"
+ help
+ Support the Schneider RZN1D and RZN1S boards, which are based
+ on the Renesas RZ/N1 SoC.
+
+endchoice
+
+source "board/schneider/rzn1-snarc/Kconfig"
+
endif
diff --git a/board/schneider/rzn1-snarc/Kconfig
b/board/schneider/rzn1-snarc/Kconfig
new file mode 100644
index 00..bb6d394077
--- /dev/null
+++ b/board/schneider/rzn1-snarc/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SCHNEIDER_RZN1
+
+config TEXT_BASE
+ default 0x2004 if ARCH_RZN1
+
+config SYS_MONITOR_LEN
+ default 524288 if ARCH_RZN1
+
+config SYS_BOARD
+ default "rzn1-snarc"
+
+config SYS_VENDOR
+ default "schneider"
+
+config SYS_CONFIG_NAME
+ default "
[PATCH v4 10/10] doc: renesas: add Renesas board docs
Collect the list of currerently supported Renesas boards. For the RZ/N1 board, add details about booting and flashing. Signed-off-by: Ralph Siemsen --- (no changes since v1) doc/board/renesas/index.rst | 9 +++ doc/board/renesas/renesas.rst | 115 ++ 2 files changed, 124 insertions(+) create mode 100644 doc/board/renesas/index.rst create mode 100644 doc/board/renesas/renesas.rst diff --git a/doc/board/renesas/index.rst b/doc/board/renesas/index.rst new file mode 100644 index 00..3244c9d45e --- /dev/null +++ b/doc/board/renesas/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas +=== + +.. toctree:: + :maxdepth: 2 + + renesas diff --git a/doc/board/renesas/renesas.rst b/doc/board/renesas/renesas.rst new file mode 100644 index 00..5ae84004cf --- /dev/null +++ b/doc/board/renesas/renesas.rst @@ -0,0 +1,115 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas +=== + +About this +-- + +This document describes the information about Renesas supported boards +and their usage steps. + +Renesas boards +-- + +Renesas is a SoC solutions provider for industrial applications. + +U-boot supports several Renesas SoC families: + +* rcar gen1/gen2 (32-bit) +- Blanche board +- Gose board +- Koelsch board +- Lager board +- Silk board +- Porter board +- Stout board +* rcar gen3 (64-bit) +- Condor board +- Draak board +- Eagle board +- Ebisu board +- Falcon board +- Salvator-x board +- Ulcb board +- Beacon-rzg2 board +- Hihope-rzg2 board +- ek874 board +* rza1 (32-bit) +- GR-PEACH board +* rzn1 (32-bit) +- Schneider rzn1-snarc board + +Building + + +NOTE: the following information is for the rzn1 board only. + +U-Boot +^^ + +Clone the u-boot repository and build it as follows: + +.. code-block:: bash + +git clone --depth 1 https://source.denx.de/u-boot/u-boot.git +cd u-boot +make rzn1_snarc_defconfig +make CROSS_COMPILE=arm-linux-gnu- + +This produces `u-boot` which is an ELF executable, suitable for use with `gdb` +and JTAG debugging tools. + +It also produceds `u-boot.bin` which is a raw binary. + +SPKG image +^^ + +The BootROM in the RZ/N1 SoC expects to find the boot image in SPKG format. +This format is documented in Chapter 7.4 of the RZ/N1 User Manual. + +The raw u-boot binary can be wrapped into SPKG format as follows: + +.. code-block:: bash + +tools/mkimage -n board/schneider/rzn1-snarc/spkgimage.cfg \ +-T spkgimage -a 0x2004 -e 0x2004 \ +-d u-boot.bin u-boot.bin.spkg + +This produces `u-boot.bin.spkg` which can be flashed into QSPI, NAND, or loaded +via USB-DFU mode. + +Take note of the load and execution address, which are encoded into the SPKG +headers. For development convenience, mkimage computes the execution offset +(part of the SPKG header) by subtracting the supplied load address from the +supplied execution address. + +Also note there are other parameters, notably ECC configuration in the case of +boot from NAND, specified in the `spkgimage.cfg` configuration file. + +Binman +^^ + +Alternatively `binman` may be used to generate the SPKG format for booting. +This tool and its pre-requisites must be installed as per +:doc:`../../../tools/binman/binman.rst`` + +.. code-block:: bash + +binman -d arch/arm/dts/r9a06g032-rzn1-snarc.dtb -o + +This will produce `u-boot.bin.spkg` in the specified directory. + +Flashing + + +The RZ/N1 is able to boot from QSPI, NAND, or via USB (DFU). In all cases the +on-board BootROM expects for the binary to be wrapped with a "SPKG" header. +This format is detailed in the RZ/N1 User Manual, and can be produced using +the u-boot `mkimage` utility. + +It is possible to recover a bricked unit by using the USB (DFU) boot mode. This +allows uploading u-boot into the internal RAM. Thereafter u-boot can be used to +program the QSPI and/or NAND, making use of u-boot dfu mode. + +Otherwise the only other option for recovery is via JTAG. -- 2.25.1
[PATCH v4 07/10] ARM: rzn1: basic support for Renesas RZ/N1 SoC
The RZ/N1 is a family of SoC devics from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD
Add basic support in the form of ARCH_RZN1 symbol.
Signed-off-by: Ralph Siemsen
---
(no changes since v1)
arch/arm/Kconfig | 17 +
arch/arm/Makefile | 1 +
arch/arm/mach-rzn1/Kconfig| 18 ++
arch/arm/mach-rzn1/Makefile | 3 +++
arch/arm/mach-rzn1/cpu_info.c | 19 +++
5 files changed, 58 insertions(+)
create mode 100644 arch/arm/mach-rzn1/Kconfig
create mode 100644 arch/arm/mach-rzn1/Makefile
create mode 100644 arch/arm/mach-rzn1/cpu_info.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bd7fffcce0..8e2a30f852 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1031,6 +1031,21 @@ config ARCH_RMOBILE
imply SYS_THUMB_BUILD
imply ARCH_MISC_INIT if DISPLAY_CPUINFO
+config ARCH_RZN1
+ bool "Reneasa RZ/N1 SoC"
+ select CLK
+ select CLK_RENESAS
+ select CLK_R9A06G032
+ select DM
+ select DM_ETH
+ select DM_SERIAL
+ select PINCTRL
+ select PINCONF
+ select REGMAP
+ select SYSRESET
+ select SYSRESET_SYSCON
+ imply CMD_DM
+
config ARCH_SNAPDRAGON
bool "Qualcomm Snapdragon SoCs"
select ARM64
@@ -2207,6 +,8 @@ source "arch/arm/mach-owl/Kconfig"
source "arch/arm/mach-rmobile/Kconfig"
+source "arch/arm/mach-rzn1/Kconfig"
+
source "arch/arm/mach-meson/Kconfig"
source "arch/arm/mach-mediatek/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ac602aed9c..1ec95a87e1 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -76,6 +76,7 @@ machine-$(CONFIG_ARCH_ORION5X)+= orion5x
machine-$(CONFIG_ARCH_OWL) += owl
machine-$(CONFIG_ARCH_RMOBILE) += rmobile
machine-$(CONFIG_ARCH_ROCKCHIP)+= rockchip
+machine-$(CONFIG_ARCH_RZN1)+= rzn1
machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
diff --git a/arch/arm/mach-rzn1/Kconfig b/arch/arm/mach-rzn1/Kconfig
new file mode 100644
index 00..707895874d
--- /dev/null
+++ b/arch/arm/mach-rzn1/Kconfig
@@ -0,0 +1,18 @@
+if ARCH_RZN1
+
+choice
+ prompt "Target Renesas RZ/N1 SoC select"
+ default RZN1
+
+config RZN1
+ bool "Renesas ARM SoCs RZ/N1 (32bit)"
+ select CPU_V7A
+ select ARMV7_SET_CORTEX_SMPEN if !SPL
+ select SPL_ARMV7_SET_CORTEX_SMPEN if SPL
+
+endchoice
+
+config SYS_SOC
+ default "rzn1"
+
+endif
diff --git a/arch/arm/mach-rzn1/Makefile b/arch/arm/mach-rzn1/Makefile
new file mode 100644
index 00..b20f845c0f
--- /dev/null
+++ b/arch/arm/mach-rzn1/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y = cpu_info.o
diff --git a/arch/arm/mach-rzn1/cpu_info.c b/arch/arm/mach-rzn1/cpu_info.c
new file mode 100644
index 00..37c2492b51
--- /dev/null
+++ b/arch/arm/mach-rzn1/cpu_info.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include
+#include
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+ dcache_enable();
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ printf("CPU: Renesas Electronics RZ/N1\n");
+ return 0;
+}
+#endif
--
2.25.1
[PATCH v4 09/10] tools: spkgimage: add Renesas SPKG format
Renesas RZ/N1 devices contain BootROM code that loads a custom SPKG
image from QSPI, NAND or USB DFU. Support this format in mkimage tool.
SPKGs can optionally be signed, however creation of signed SPKG is not
currently supported.
Example of how to use it:
tools/mkimage -n board/schneider/rzn1-snarc/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
Reviewed-by: Simon Glass
---
Changes in v4:
- added tags
- add RZ/N1 board documentation
- added binman support
Changes in v3:
- provide definition of __packed (as done in kwbimage.h)
- explain why a local copy of roundup() is needed
- document spkgimage in doc/mkimage.1
- add range checks when parsing config file values
- add line numbers for reporting errors in config file
- rename SPKG_HEADER_SIGNATURE to SPKG_HEADER_MARKER
- fix segfault when image is padded by less than 4 bytes
- minor style and typo fixes
Changes in v2:
- rewrote the stand-alone spkg_utility to integrate into mkimage
board/schneider/rzn1-snarc/spkgimage.cfg | 26 ++
boot/image.c | 1 +
doc/mkimage.1| 45
include/image.h | 1 +
tools/Makefile | 1 +
tools/spkgimage.c| 330 +++
tools/spkgimage.h| 87 ++
7 files changed, 491 insertions(+)
create mode 100644 board/schneider/rzn1-snarc/spkgimage.cfg
create mode 100644 tools/spkgimage.c
create mode 100644 tools/spkgimage.h
diff --git a/board/schneider/rzn1-snarc/spkgimage.cfg
b/board/schneider/rzn1-snarc/spkgimage.cfg
new file mode 100644
index 00..b5faf96b00
--- /dev/null
+++ b/board/schneider/rzn1-snarc/spkgimage.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Schneider Electric
+#
+# SPKG image header, for booting on RZ/N1
+
+# b[35:32] SPKG version
+VERSION1
+
+# b[42:41] ECC Block size: 0=256 bytes, 1=512 bytes, 2=1024 bytes
+NAND_ECC_BLOCK_SIZE1
+
+# b[45] NAND enable (boolean)
+NAND_ECC_ENABLE1
+
+# b[50:48] ECC Scheme: 0=BCH2 1=BCH4 2=BCH8 3=BCH16 4=BCH24 5=BCH32
+NAND_ECC_SCHEME3
+
+# b[63:56] ECC bytes per block
+NAND_BYTES_PER_ECC_BLOCK 28
+
+# Provide dummy BLp header (boolean)
+ADD_DUMMY_BLP 1
+
+# Pad the image to a multiple of
+PADDING64K
diff --git a/boot/image.c b/boot/image.c
index 958dbf8534..5c4f9b807d 100644
--- a/boot/image.c
+++ b/boot/image.c
@@ -181,6 +181,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_SUNXI_EGON, "sunxi_egon", "Allwinner eGON Boot Image"
},
{ IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image"
},
{ IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat
Device Tree ", },
+ { IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" },
{ -1, "", "", },
};
diff --git a/doc/mkimage.1 b/doc/mkimage.1
index d8727ec73c..76c7859bb0 100644
--- a/doc/mkimage.1
+++ b/doc/mkimage.1
@@ -662,6 +662,51 @@ rk3568
.TE
.RE
.
+.SS spkgimage
+The primary configuration file consists of lines containing key/value pairs
+delimited by whitespace. An example follows.
+.PP
+.RS
+.EX
+# Comments and blank lines may be used
+.I key1 value1
+.I key2 value2
+.EE
+.RE
+.P
+The supported
+.I key
+types are as follows.
+.TP
+.B VERSION
+.TQ
+.B NAND_ECC_BLOCK_SIZE
+.TQ
+.B NAND_ECC_ENABLE
+.TQ
+.B NAND_ECC_SCHEME
+.TQ
+.B NAND_BYTES_PER_ECC_BLOCK
+These all take a positive integer value as their argument.
+The value will be copied directly into the respective field
+of the SPKG header structure. For details on these values,
+refer to Section 7.4 of the Renesas RZ/N1 User's Manual.
+.
+.TP
+.B ADD_DUMMY_BLP
+Takes a numeric argument, which is treated as a boolean. Any nonzero
+value will cause a fake BLp security header to be included in the SPKG
+output.
+.
+.TP
+.B PADDING
+Takes a positive integer value, with an optional
+.B K
+or
+.B M
+suffix, indicating KiB / MiB respectively.
+The output SPKG file will be padded to a multiple of this value.
+.
.SS sunxi_egon
The primary configuration is the name to use for the device tree.
.
diff --git a/include/image.h b/include/image.h
index 7717a4c13d..acfbb6a53a 100644
--- a/include/image.h
+++ b/include/image.h
@@ -230,6 +230,7 @@ enum image_type_t {
IH_TYPE_SUNXI_EGON, /* Allwinner eGON Boot Image */
IH_TYPE_SUNXI_TOC0, /* Allwinner TOC0 Boot Image */
IH_TYPE_FDT_LEGACY, /* Binary Flat Device Tree Blob in a
Legacy Image */
+ IH_TYPE_RENE
[PATCH v4 03/10] clk: renesas: add R906G032 driver
Clock driver for the Renesas RZ/N1 SoC family. This is based on
Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in
commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"),
with the following additional patch series applied:
https://lore.kernel.org/linux-renesas-soc/20230301215520.828455-1-ralph.siem...@linaro.org/
Notable difference: this version avoids allocating a 'struct clk'
for each clock source, as this is problematic before relocation.
Instead, it uses the same approach as existing Renesas RCAR2/3
clock drivers, using a temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen
---
Changes in v4:
- commit message now includes hash of Linux upon which this is based
as well as the additional patches (clock table cleanups)
- sync changes from review on linux patches, including
- move RB macro higher up and document it, matching Linux driver
- use multiply/divide instead of shifts for computing reg address
- improve comments for clock gate, descriptor structures
Changes in v3:
- convert data table to explicit reg/bit numbers
- drop the unused scon, mirack, mirstat fields
- added some kernel docs to structures
- use enum for type field of struct r9a06g032_clkdesc
- cleanup macros for one assignment per line
- add a macro for top-most clock ID value ~0
- use dev_dbg() instead of debug/print
- minor reformatting, declarations before code, etc
- !foo instead of foo == 0
- IS_ERR / PTR_ERR where appropriate
- implement div_table handling
- remove some #if 0 old test code
drivers/clk/renesas/Kconfig|6 +
drivers/clk/renesas/Makefile |1 +
drivers/clk/renesas/r9a06g032-clocks.c | 1096
3 files changed, 1103 insertions(+)
create mode 100644 drivers/clk/renesas/r9a06g032-clocks.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 6788415eed..bbc618f464 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -130,3 +130,9 @@ config CLK_R8A779A0
depends on CLK_RCAR_GEN3
help
Enable this to support the clocks on Renesas R8A779A0 SoC.
+
+config CLK_R9A06G032
+ bool "Renesas R9A06G032 clock driver"
+ depends on CLK_RENESAS
+ help
+ Enable this to support the clocks on Renesas R9A06G032 SoC.
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index a0d8c10bdb..7f0ef28367 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
+obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c
b/drivers/clk/renesas/r9a06g032-clocks.c
new file mode 100644
index 00..a2adefc9bb
--- /dev/null
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -0,0 +1,1096 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R9A06G032 clock driver
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet ,
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+/**
+ * struct regbit - describe one bit in a register
+ * @reg: offset of register relative to base address,
+ * expressed in units of 32-bit words (not bytes),
+ * @bit: which bit (0 to 31) in the register
+ *
+ * This structure is used to compactly encode the location
+ * of a single bit in a register. Five bits are needed to
+ * encode the bit number. With uint16_t data type, this
+ * leaves 11 bits to encode a register offset up to 2047.
+ *
+ * Since registers are aligned on 32-bit boundaries, the
+ * offset will be specified in 32-bit words rather than bytes.
+ * This allows encoding an offset up to 0x1FFC (8188) bytes.
+ *
+ * Helper macro RB() takes care of converting the register
+ * offset from bytes to 32-bit words.
+ */
+struct regbit {
+ u16 reg:11;
+ u16 bit:5;
+};
+
+#define RB(_reg, _bit) ((struct regbit) { \
+ .reg = (_reg) / 4, \
+ .bit = (_bit) \
+})
+
+/**
+ * struct r9a06g032_gate - clock-related control bits
+ * @gate: clock enable/disable
+ * @reset: clock module reset (active low)
+ * @ready: enables NoC forwarding of read/write requests to device,
+ * (eg. device is ready to handle read/write requests)
+ * @midle: request to idle the NoC interconnect
+ *
+ * Each of these fields describes a single bit in a register,
+ * which controls some aspect of clock gating. The @gate field
+ * is mandatory, this one enables/disables the clock. The
+ * other fields are optional, with zero indicating "not used".
+ *
+ * In most cases there is a @reset bit which needs to be
+ * de-asserted to bring the module out of reset.
+ *
+ * Modules may also need to signal when the
[PATCH v4 05/10] ram: cadence: add driver for Cadence EDAC
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen
---
(no changes since v3)
Changes in v3:
- assorted small cleanups
- support version 1.0 silicon (previously #if 0...)
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile| 2 +
drivers/ram/cadence/Kconfig | 12 +
drivers/ram/cadence/Makefile| 1 +
drivers/ram/cadence/ddr_async.c | 311
drivers/ram/cadence/ddr_ctrl.c | 414
drivers/ram/cadence/ddr_ctrl.h | 175 ++
7 files changed, 916 insertions(+)
create mode 100644 drivers/ram/cadence/Kconfig
create mode 100644 drivers/ram/cadence/Makefile
create mode 100644 drivers/ram/cadence/ddr_async.c
create mode 100644 drivers/ram/cadence/ddr_ctrl.c
create mode 100644 drivers/ram/cadence/ddr_ctrl.h
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index e085119963..2b6d8f1c7b 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -108,6 +108,7 @@ config IMXRT_SDRAM
This driver is for the sdram memory interface with the SEMC.
source "drivers/ram/aspeed/Kconfig"
+source "drivers/ram/cadence/Kconfig"
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 83948e2c43..e2d5e730d1 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -22,3 +22,5 @@ obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
obj-$(CONFIG_RAM_SIFIVE) += sifive/
obj-$(CONFIG_ARCH_OCTEON) += octeon/
+
+obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/
diff --git a/drivers/ram/cadence/Kconfig b/drivers/ram/cadence/Kconfig
new file mode 100644
index 00..2d5469cb8e
--- /dev/null
+++ b/drivers/ram/cadence/Kconfig
@@ -0,0 +1,12 @@
+if RAM || SPL_RAM
+
+config CADENCE_DDR_CTRL
+ bool "Enable Cadence DDR controller"
+ depends on DM
+ help
+ Enable support for Cadence DDR controller, as found on
+ the Renesas RZ/N1 SoC. This controller has a large number
+ of registers which need to be programmed, mostly using values
+ obtained from Denali SOMA files via a TCL script.
+
+endif
diff --git a/drivers/ram/cadence/Makefile b/drivers/ram/cadence/Makefile
new file mode 100644
index 00..16c7fe8488
--- /dev/null
+++ b/drivers/ram/cadence/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CADENCE_DDR_CTRL) += ddr_async.o ddr_ctrl.o
diff --git a/drivers/ram/cadence/ddr_async.c b/drivers/ram/cadence/ddr_async.c
new file mode 100644
index 00..444eeb8ac7
--- /dev/null
+++ b/drivers/ram/cadence/ddr_async.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * RZ/N1 DDR Controller initialisation
+ *
+ * The DDR Controller register values for a specific DDR device, mode and
+ * frequency are generated using a Cadence tool.
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe Ltd
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "ddr_ctrl.h"
+
+void clk_rzn1_reset_state(struct clk *clk, int on);
+
+extern u32 ddr_00_87_async[];
+extern u32 ddr_350_374_async[];
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct cadence_ddr_info {
+ struct udevice *dev;
+ void __iomem *ddrc;
+ void __iomem *phy;
+ struct clk clk_ddrc;
+ struct clk hclk_ddrc;
+ struct regmap *syscon;
+ bool enable_ecc;
+ bool enable_8bit;
+};
+
+static inline u32 cadence_readl(void __iomem *addr, unsigned int offset)
+{
+ return readl(addr + offset);
+}
+
+static inline void cadence_writel(void __iomem *addr, unsigned int offset,
+ u32 data)
+{
+ debug("%s: addr = 0x%p, value = 0x%08x\n", __func__, addr + offset,
data);
+ writel(data, addr + offset);
+}
+
+#define ddrc_readl(off)cadence_readl(priv->ddrc, off)
+#define ddrc_writel(val, off) cadence_writel(priv->ddrc, off, val)
+
+#define phy_readl(off) cadence_readl(priv->phy, off)
+#define phy_writel(val, off) cadence_writel(priv->phy, off, val)
+
+#define RZN1_DDR3_SINGLE_BANK 3
+#define RZN1_DDR3_DUAL_BANK 32
+
+#define FUNCCTRL 0x00
+#define FUNCCTRL_MASKSDLOFS (0x18 << 16)
+#define FUNCCTRL_DVDDQ_1_5V (1 << 8)
+#define FUNCCTRL_RESET_N (1 << 0)
+#define DLLCTRL0x04
+#define DLLCTRL_ASDLLOCK (1 << 26)
+#define DLLCTRL_MFSL_500MHz (2 << 1)
+#define DLLCTRL_MDLLSTBY (1 << 0)
+#define ZQCALCTRL 0x08
+#define ZQCALCTRL_ZQCALEND(1 << 30)
+#define ZQCALCTRL_ZQCALRSTB (1 << 0)
+#define ZQODTCTRL 0x0c
+#define RDCTRL 0x10
+#define RDTMG 0x14
+#define FIFOINIT 0x18
+#define FIFOINIT_RDPTINITEXE (1 << 8)
+#define FIFOINIT_WRPTINITEXE (1 << 0)
+#define OUTCTRL
[PATCH v4 06/10] dts: basic devicetree for Renesas RZ/N1 SoC
This is taken from Linux kernel 5.17, and contains just bare minimum
functionality: CPU, UART and system timer.
Additional functionality (from newer kernel versions) will be added
later. Note that the Linux side is under active development.
Signed-off-by: Ralph Siemsen
---
The following changes were made, compared with Linux 5.17:
1) Add node for system controller registers.
Declare it as syscon to provide a regmap interface.
2) In the clock controller node (renesas,r9a06g032-sysctrl),
replace regs with regmap.
3) Add syscon-reset node, making use of the syscon regmap.
4) Add syscon phandle to ddrctrl. Used for checking h/w version.
5) Simplify the compatible string for all the UARTS, as per
doc/device-tree-bindings/serial/snps-dw-apb-uart.txt
I could not find a way to avoid 1) and 2). Putting "syscon" in the
compatible string for the clock controller leads to a catch-22,
where the driver fails to initialize, and then boot hangs.
(no changes since v3)
Changes in v3:
- add syscon phandle to ddrctl
- simplify UART compatible strings
arch/arm/dts/r9a06g032.dtsi | 226 ++
include/dt-bindings/clock/r9a06g032-sysctrl.h | 148
2 files changed, 374 insertions(+)
create mode 100644 arch/arm/dts/r9a06g032.dtsi
create mode 100644 include/dt-bindings/clock/r9a06g032-sysctrl.h
diff --git a/arch/arm/dts/r9a06g032.dtsi b/arch/arm/dts/r9a06g032.dtsi
new file mode 100644
index 00..e0ddffb074
--- /dev/null
+++ b/arch/arm/dts/r9a06g032.dtsi
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include
+#include
+
+/ {
+ compatible = "renesas,r9a06g032";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <1>;
+ clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+ enable-method = "renesas,r9a06g032-smp";
+ cpu-release-addr = <0 0x4000c204>;
+ };
+ };
+
+ ext_jtag_clk: extjtagclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ext_mclk: extmclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000>;
+ };
+
+ ext_rgmii_ref: extrgmiiref {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ext_rtc_clk: extrtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ plat_regs: system-controller@4000c000 {
+ compatible = "syscon";
+ reg = <0x4000c000 0x1000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ sysctrl: clock {
+ compatible = "renesas,r9a06g032-sysctrl";
+ #clock-cells = <1>;
+ regmap = <&plat_regs>;
+ u-boot,dm-pre-reloc;
+
+ clocks = <&ext_mclk>, <&ext_rtc_clk>,
+ <&ext_jtag_clk>, <&ext_rgmii_ref>;
+ clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+ };
+
+ ddrctrl: memory-controller@4000d000 {
+ compatible = "cadence,ddr-ctrl";
+ reg = <0x4000d000 0x1000>, <0x4000e000 0x100>;
+ reg-names = "ddrc", "phy";
+ interrupts = ;
+ clocks = <&sysctrl R9A06G032_CLK_DDRC>, <&sysctrl
R9A06G032_HCLK_DDRC>;
+ clock-names = "clk_ddrc&q
[PATCH v4 04/10] pinctrl: renesas: add R906G032 driver
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen
---
(no changes since v1)
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/renesas/Kconfig| 7 +
drivers/pinctrl/renesas/Makefile | 1 +
drivers/pinctrl/renesas/pinctrl-rzn1.c | 379 +
include/dt-bindings/pinctrl/rzn1-pinctrl.h | 141
5 files changed, 529 insertions(+)
create mode 100644 drivers/pinctrl/renesas/pinctrl-rzn1.c
create mode 100644 include/dt-bindings/pinctrl/rzn1-pinctrl.h
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 3b167d099f..450267732c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_INTEL) += intel/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
+obj-$(CONFIG_ARCH_RZN1) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_PINCTRL_SUNXI)+= sunxi/
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 8f994d8d76..b707d7549b 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -127,3 +127,10 @@ config PINCTRL_PFC_R7S72100
Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
endif
+
+config PINCTRL_RZN1
+ bool "Renesas RZ/N1 R906G032 pin control driver"
+ depends on ARCH_RZN1
+ default y if ARCH_RZN1
+ help
+ Support pin multiplexing control on Renesas RZ/N1 R906G032 SoCs.
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 1198c86855..39b2f65f2e 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
+obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
diff --git a/drivers/pinctrl/renesas/pinctrl-rzn1.c
b/drivers/pinctrl/renesas/pinctrl-rzn1.c
new file mode 100644
index 00..fdc43c8e71
--- /dev/null
+++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
+ *
+ * Phil Edworthy
+ * Based on a driver originally written by Michel Pollet at Renesas.
+ */
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+/* Field positions and masks in the pinmux registers */
+#define RZN1_L1_PIN_DRIVE_STRENGTH 10
+#define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0
+#define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1
+#define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2
+#define RZN1_L1_PIN_DRIVE_STRENGTH_12MA3
+#define RZN1_L1_PIN_PULL 8
+#define RZN1_L1_PIN_PULL_NONE 0
+#define RZN1_L1_PIN_PULL_UP1
+#define RZN1_L1_PIN_PULL_DOWN 3
+#define RZN1_L1_FUNCTION 0
+#define RZN1_L1_FUNC_MASK 0xf
+#define RZN1_L1_FUNCTION_L20xf
+
+/*
+ * The hardware manual describes two levels of multiplexing, but it's more
+ * logical to think of the hardware as three levels, with level 3 consisting of
+ * the multiplexing for Ethernet MDIO signals.
+ *
+ * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf)
specifying
+ * that level 2 functions are used instead. Level 2 has a lot more options,
+ * going from 0 to 61. Level 3 allows selection of MDIO functions which can be
+ * floating, or one of seven internal peripherals. Unfortunately, there are two
+ * level 2 functions that can select MDIO, and two MDIO channels so we have
four
+ * sets of level 3 functions.
+ *
+ * For this driver, we've compounded the numbers together, so:
+ *0 to 9 is level 1
+ * 10 to 71 is 10 + level 2 number
+ * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function.
+ * 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function.
+ * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function.
+ * 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function.
+ * Examples:
+ * Function 28 corresponds UART0
+ * Function 73 corresponds to MDIO0 to GMAC0
+ *
+ * There are 170 configurable pins (called PL_GPIO in the datasheet).
+ */
+
+/*
+ * Structure detailing the HW registers on the RZ/N1 devices.
+ * Both the Level 1 mux registers and Level 2 mux registers have the same
+ * structure. The only difference is that Level 2 has additional MDIO registers
+ * at the end.
+ */
+struct rzn1_pinctrl_regs {
+ u32 conf[170];
+ u32 pad0[86];
+ u32 status_protect; /* 0x400 */
+ /* MDIO mux registers, level2 only */
+ u32 l2_md
[PATCH v4 02/10] clk: renesas: prepare for non-RCAR clock drivers
Allow CONFIG_CLK_RENESAS to be set without bringing in RCAR-GEN2/3 code. CONFIG_RENESAS is used in drivers/clk/Makefile to control recursion into the drivers/clk/renesas subdirectory. It also controls compilation of renesas-cpg-mssr.c support code for the RCAR-GEN2 and RCAR-GEN3 devices. The support code contains platform specific hardware access (TMU_BASE), and it is not needed for other Renesas devices such as RZ/N1. Therefore, alter Makefile to build renesas-cpg-mssr.c only for RCAR-GEN2/3. Signed-off-by: Ralph Siemsen Reviewed-by: Sean Anderson --- (no changes since v3) Changes in v3: - added tags drivers/clk/renesas/Kconfig | 2 +- drivers/clk/renesas/Makefile | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 1686410d6d..6788415eed 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -1,6 +1,6 @@ config CLK_RENESAS bool "Renesas clock drivers" - depends on CLK && ARCH_RMOBILE + depends on CLK && (ARCH_RMOBILE || ARCH_RZN1) help Enable support for clock present on Renesas RCar SoCs. diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 8f82a7aa3e..a0d8c10bdb 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -1,6 +1,5 @@ -obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o -obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o +obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o renesas-cpg-mssr.o obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o @@ -10,7 +9,7 @@ obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o obj-$(CONFIG_CLK_R8A7793) += r8a7791-cpg-mssr.o obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o -obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o +obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o renesas-cpg-mssr.o obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o obj-$(CONFIG_CLK_R8A77960) += r8a7796-cpg-mssr.o obj-$(CONFIG_CLK_R8A77961) += r8a7796-cpg-mssr.o -- 2.25.1
[PATCH v4 01/10] ARM: armv7: add non-SPL enable for Cortex SMPEN
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off-by: Ralph Siemsen
---
This will be used by the following commit that adds ARCH_RZN1.
(no changes since v1)
arch/arm/cpu/armv7/Kconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index f1e4e26b8f..e33e53636a 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -107,6 +107,11 @@ config ARMV7_LPAE
Say Y here to use the long descriptor page table format. This is
required if U-Boot runs in HYP mode.
+config ARMV7_SET_CORTEX_SMPEN
+ bool
+ help
+ Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
+
config SPL_ARMV7_SET_CORTEX_SMPEN
bool
help
--
2.25.1
Re: [RFC PATCH v3 5/9] ram: cadence: add driver for Cadence EDAC
On Fri, Feb 24, 2023 at 10:19:53AM -0500, Ralph Siemsen wrote: Hi Bryan, On Thu, Feb 23, 2023 at 2:54 PM Bryan Brattlof wrote: Hi Ralph! Love seeing more boards here, though I know of a few chips that use some type of cadence controller. I'm just curious if it would it make sense to name this with some type of Renesas specific branding? Indeed the this IP from Cadence likely is used in quite a few places. However it is usually quite difficult to figure out exactly which version of the IP is present, what bugs/workarounds are needed, etc. I am fine with renaming this in a more renesas-specific manner (suggestions welcomed!). On the other hand, it would good to try and encourage having one driver for this, rather than a bunch of similar-but-not-quite-equivalent ones scattered about. Perhaps a non-specific name might help? Can anyone offer guidance on the naming of the DDR controller? Other than this issue, I have v4 of this patch series ready to post. Thanks! Ralph
Re: [RFC PATCH v3 3/9] clk: renesas: add R906G032 driver
Hi Marek, On Fri, Feb 24, 2023 at 12:05 PM Marek Vasut wrote: > > Could you at least submit the clean up to Linux and then sync the result > to U-Boot, and indicate the Linux clock table came from commit > with extra patch on top ? Yes will do. I am refreshing my linux-side patch as we speak. Ralph
Re: [RFC PATCH v3 5/9] ram: cadence: add driver for Cadence EDAC
Hi Bryan, On Thu, Feb 23, 2023 at 2:54 PM Bryan Brattlof wrote: > > Hi Ralph! > Love seeing more boards here, though I know of a few chips that use some > type of cadence controller. I'm just curious if it would it make sense > to name this with some type of Renesas specific branding? Indeed the this IP from Cadence likely is used in quite a few places. However it is usually quite difficult to figure out exactly which version of the IP is present, what bugs/workarounds are needed, etc. I am fine with renaming this in a more renesas-specific manner (suggestions welcomed!). On the other hand, it would good to try and encourage having one driver for this, rather than a bunch of similar-but-not-quite-equivalent ones scattered about. Perhaps a non-specific name might help? Ralph
Re: [RFC PATCH v3 3/9] clk: renesas: add R906G032 driver
On Thu, Feb 23, 2023 at 9:09 AM Miquel Raynal wrote: > > Hi Marek, > > marek.va...@mailbox.org wrote on Thu, 23 Feb 2023 14:56:41 +0100: > > > > Either way is fine by me, I just want to be sure the u-boot clock tables > > are in sync with Linux as much as possible, and can be easily resynced in > > the future, that's all. > > Of course. The fix is mainline already, so on that regard we should be > fine. Right, so mainline has all the fixes, the only thing missing there is the "cleanup" of the clock tables, which I have done in the u-boot version under review. Assuming this is satisfactory, I will aim to get the same cleanup done on the clock tables in the kernel side, so they are in sync with u-boot. Ralp
Re: [RFC PATCH v3 9/9] tools: spkgimage: add Renesas SPKG format
Hi Simon, Thanks for your review! On Wed, Feb 22, 2023 at 2:17 PM Simon Glass wrote: > > Can you please add some details to doc/ for this SoC and how it boots, > the use of mkimage, etc.? Sure, I will cobble something together. Any particular good examples to look at for inspiration? > Also as a follow-on, can you add a binman entry type for this so that > building a functioning image is automatic? I'm talking a look at this as well. In this case though, it would just automate the call to mkimage, as there are no other binaries. > Finally, please add comments to struct spkg_hdr members below Yes, although they will be pretty much verbatim from the user manual, which documents the format. The docs are available publicly, but you need to click through a few links to reach them. Regards, Ralph
[PATCH] tools: binman: minor formatting fix in docs
This should fix a rendering oddity when viewing the docs online at https://u-boot.readthedocs.io/en/latest/develop/package/binman.html Signed-off-by: Ralph Siemsen --- tools/binman/binman.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst index 03a99a19bc..0921e31878 100644 --- a/tools/binman/binman.rst +++ b/tools/binman/binman.rst @@ -393,9 +393,9 @@ system-library directory, replace the last line with: Running binman -- -Type:: +Type: -.. code-block: bash +.. code-block:: bash make NO_PYTHON=1 PREFIX=/ install binman build -b -- 2.25.1
Re: [RFC PATCH v3 3/9] clk: renesas: add R906G032 driver
On Wed, Feb 22, 2023 at 07:45:45PM +0100, Marek Vasut wrote: On 2/22/23 19:32, Ralph Siemsen wrote: On Wed, Feb 22, 2023 at 06:47:44PM +0100, Marek Vasut wrote: Are those fixes in mainline Linux ? Yes, they are in mainline: 2dee50ab9e72 clk: renesas: r9a06g032: Fix UART clkgrp bitsel merged into 6.0, and also backported to earlier LTS branches 2a6da4a11f47 clk: renesas: r9a06g032: Fix the RTC hclock description merged into 5.19, seems to be missing from LTS branches Use Linux 6.2.y as a base then. Okay, done. And please submit the missing patches for LTS branch inclusion too if possible, I guess they were missing Fixes: tag ? Seems it was part of a series which added support for the RTC device: https://lore.kernel.org/all/20220421090016.79517-3-miquel.ray...@bootlin.com/ Since it is new feature, I guess one could argue that the clock table fix is not needed in older LTS kernels, since no driver uses that clock. But most likely it was just overlooked. I'll check with Miquel. Regards, Ralph
Re: [RFC PATCH v3 3/9] clk: renesas: add R906G032 driver
On Wed, Feb 22, 2023 at 06:47:44PM +0100, Marek Vasut wrote:
On 2/22/23 18:21, Ralph Siemsen wrote:
On Wed, Feb 22, 2023 at 06:07:45PM +0100, Marek Vasut wrote:
On 2/22/23 17:57, Ralph Siemsen wrote:
On Wed, Feb 22, 2023 at 05:06:14PM +0100, Marek Vasut wrote:
On 2/22/23 16:44, Ralph Siemsen wrote:
Clock driver for the Renesas RZ/N1 SoC family. This is based
on the Linux kernel drivers/clk/renesas/r9a06g032-clocks.c.
For starters, can you please include the exact kernel version
, ideally commit ID, from which this way pulled, so that
future updates can pull in the diffs from that commit easily ?
Very reasonable request, but a bit difficult to give a concise
answer. Originally I took the driver as found in the 5.15
kernel. The driver actually had not changed since 5.13 commit
6bd913f54f2f ("clk: renesas: r9a06g032: Switch to
.determine_rate()"). So that's the starting point.
I incorporated subsequent changes to the clock tables and
related cleanups. Those were only merged into Linux much later:
2dee50ab9e72 clk: renesas: r9a06g032: Fix UART clkgrp bitsel
f46efcc4746f clk: renesas: r9a06g032: Drop some unused fields
2a6da4a11f47 clk: renesas: r9a06g032: Fix the RTC hclock description
Linux driver also had a few other commits, but these are not
applicable to the u-boot version due to structural changes:
6bd913f54f2f clk: renesas: r9a06g032: Switch to .determine_rate()
f2fb4fe62390 clk: renesas: Zero init clk_init_data
2182066d95c3 clk: renesas: r9a06g032: Probe possible children
885525c1e7e2 clk: renesas: r9a06g032: Export function to set dmamux
02693e11611e clk: renesas: r9a06g032: Repair grave increment error
So I would say it is "up to date" with the lastest Linux commit,
even though it is based on an earlier version. Is there a good
way to include the above in the commit message, succinctly?
Is this still in sync with Linux 6.1.y ? That's the latest LTS .
Yes. Although the commits have different hashes than what I reported
above, the 6.1.y LTS branch has the same changes.
Then please include the Linux 6.1.y commit ID , or Torvalds' tree if
that contains new fixes . Let's not use some old/downstream stuff .
I've amended the commit message as follows:
Clock driver for the Renesas RZ/N1 SoC family. This is based
on the Linux kernel drivers/clk/renesas/r9a06g032-clocks.c as found in
commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment
error")
included in Torvalds kernel v6.2. Identical code is in LTS 6.1.y.
Note that the u-boot version of the driver has changed considerably
from the Linux version. In terms of pulling future diffs over, I
would be concerned mostly about keeping the clock tables in sync.
There have been a few mistakes found and fixed in those already.
Are those fixes in mainline Linux ?
Yes, they are in mainline:
2dee50ab9e72 clk: renesas: r9a06g032: Fix UART clkgrp bitsel
merged into 6.0, and also backported to earlier LTS branches
2a6da4a11f47 clk: renesas: r9a06g032: Fix the RTC hclock description
merged into 5.19, seems to be missing from LTS branches
Regards,
Ralph
Re: [RFC PATCH v1 3/9] clk: renesas: add R906G032 driver
Hi Sean, I finally got around to posting v3 of this patch series. I wanted to touch on a few issues you had mentioned in previous review. On Fri, Aug 26, 2022 at 11:47 AM Ralph Siemsen wrote: > > On Tue, Aug 23, 2022 at 12:14:31AM -0400, Sean Anderson wrote: > >>Regarding the unused fields (scon, mirack, mistat): I am not really > >>sure what their purpose is. Maybe there is some value in having them. > >>I'll try to find out more information about them. If we do decide to > >>drop them, I would like to keep it synchronised with the Linux driver. > > > >OK, well if you don't use them then perhaps you can just leave them in > >the macro but remove them from the struct. That way you can add support > >for them later if you need to, but they don't take up space in the mean > >time. A comment summarizing your explanation above would be helpful. So I ended up doing as you suggested: keeping the values in the tables, in case they are needed in the future, but omitting them from the structure to save space. > >>>DIV_ROUND_CLOSEST? > >> > >>I'm hesitant to change the logic on this, as it could subtly alter the > >>values. > > > >Well if you have 2MHz divided by 3, the resulting rate is closer to > >67 kHz than 66 Hz. This could result in the chosen clock rate being higher than what was requested. And in turn that could result in violating the spec of a hardware device. So I have kept the original logic here. Regards Ralph
Re: [RFC PATCH v3 3/9] clk: renesas: add R906G032 driver
On Wed, Feb 22, 2023 at 06:07:45PM +0100, Marek Vasut wrote:
On 2/22/23 17:57, Ralph Siemsen wrote:
On Wed, Feb 22, 2023 at 05:06:14PM +0100, Marek Vasut wrote:
On 2/22/23 16:44, Ralph Siemsen wrote:
Clock driver for the Renesas RZ/N1 SoC family. This is based
on the Linux kernel drivers/clk/renesas/r9a06g032-clocks.c.
For starters, can you please include the exact kernel version ,
ideally commit ID, from which this way pulled, so that future
updates can pull in the diffs from that commit easily ?
Very reasonable request, but a bit difficult to give a concise
answer. Originally I took the driver as found in the 5.15 kernel.
The driver actually had not changed since 5.13 commit 6bd913f54f2f
("clk: renesas: r9a06g032: Switch to .determine_rate()"). So that's
the starting point.
I incorporated subsequent changes to the clock tables and related
cleanups. Those were only merged into Linux much later:
2dee50ab9e72 clk: renesas: r9a06g032: Fix UART clkgrp bitsel
f46efcc4746f clk: renesas: r9a06g032: Drop some unused fields
2a6da4a11f47 clk: renesas: r9a06g032: Fix the RTC hclock description
Linux driver also had a few other commits, but these are not
applicable to the u-boot version due to structural changes:
6bd913f54f2f clk: renesas: r9a06g032: Switch to .determine_rate()
f2fb4fe62390 clk: renesas: Zero init clk_init_data
2182066d95c3 clk: renesas: r9a06g032: Probe possible children
885525c1e7e2 clk: renesas: r9a06g032: Export function to set dmamux
02693e11611e clk: renesas: r9a06g032: Repair grave increment error
So I would say it is "up to date" with the lastest Linux commit,
even though it is based on an earlier version. Is there a good way
to include the above in the commit message, succinctly?
Is this still in sync with Linux 6.1.y ? That's the latest LTS .
Yes. Although the commits have different hashes than what I reported
above, the 6.1.y LTS branch has the same changes.
Note that the u-boot version of the driver has changed considerably from
the Linux version. In terms of pulling future diffs over, I would be
concerned mostly about keeping the clock tables in sync. There have been
a few mistakes found and fixed in those already.
Ralph
Re: [RFC PATCH v3 3/9] clk: renesas: add R906G032 driver
On Wed, Feb 22, 2023 at 05:06:14PM +0100, Marek Vasut wrote:
On 2/22/23 16:44, Ralph Siemsen wrote:
Clock driver for the Renesas RZ/N1 SoC family. This is based
on the Linux kernel drivers/clk/renesas/r9a06g032-clocks.c.
For starters, can you please include the exact kernel version ,
ideally commit ID, from which this way pulled, so that future updates
can pull in the diffs from that commit easily ?
Very reasonable request, but a bit difficult to give a concise answer.
Originally I took the driver as found in the 5.15 kernel. The driver
actually had not changed since 5.13 commit 6bd913f54f2f ("clk: renesas:
r9a06g032: Switch to .determine_rate()"). So that's the starting point.
I incorporated subsequent changes to the clock tables and related
cleanups. Those were only merged into Linux much later:
2dee50ab9e72 clk: renesas: r9a06g032: Fix UART clkgrp bitsel
f46efcc4746f clk: renesas: r9a06g032: Drop some unused fields
2a6da4a11f47 clk: renesas: r9a06g032: Fix the RTC hclock description
Linux driver also had a few other commits, but these are not applicable
to the u-boot version due to structural changes:
6bd913f54f2f clk: renesas: r9a06g032: Switch to .determine_rate()
f2fb4fe62390 clk: renesas: Zero init clk_init_data
2182066d95c3 clk: renesas: r9a06g032: Probe possible children
885525c1e7e2 clk: renesas: r9a06g032: Export function to set dmamux
02693e11611e clk: renesas: r9a06g032: Repair grave increment error
So I would say it is "up to date" with the lastest Linux commit, even
though it is based on an earlier version. Is there a good way to include
the above in the commit message, succinctly?
Also, can you please CC me on the entire series ?
I've added you to series-cc for future versions. Note that some of the
mails are currently stuck in moderation queue (too many recipients). I
let patman pick the default recipients.
Ralph
[RFC PATCH v3 0/9] Renesas RZ/N1 SoC initial support
The RZ/N1 is a family of SoC devices from Renesas [1], featuring ARM Cortex-A7 and/or Cortex-M3 CPU, industrial ethernet protocols, integrated Ethernet switch, and numerous peripherals. This is a first step in upstreaming support for the RZ/N1 family. Currently it contains just enough to boot to the u-boot prompt. Additional patches will follow to support flash, SD, USB, Ethernet, etc. This work is based on a vendor-supplied u-boot 2017.01 tree [2], which supports several eval boards, none of which I have access to. Instead development has been done on a Schneider RZN1 board, which is fairly similar to the Renesas RZ/N1D-DB Demo board. [1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzn1 [2] https://github.com/renesas-rz/rzn1_u-boot/tree/rzn1-stable Changes in v3: - many tweaks to clock driver based on reviewer feedback - rebased to u-boot v2023.04-rc2 - reviewer suggestions added to spkgimage.c - many small cleanups, checkpatch, FIXMEs resolved Changes in v2: - rewrote the stand-alone spkg_utility to integrate into mkimage Ralph Siemsen (9): ARM: armv7: add non-SPL enable for Cortex SMPEN clk: renesas: prepare for non-RCAR clock drivers clk: renesas: add R906G032 driver pinctrl: renesas: add R906G032 driver ram: cadence: add driver for Cadence EDAC dts: basic devicetree for Renesas RZ/N1 SoC ARM: rzn1: basic support for Renesas RZ/N1 SoC board: schneider: add RZN1 board support tools: spkgimage: add Renesas SPKG format arch/arm/Kconfig | 17 + arch/arm/Makefile |1 + arch/arm/cpu/armv7/Kconfig|5 + arch/arm/dts/r9a06g032-rzn1-snarc.dts | 51 + arch/arm/dts/r9a06g032.dtsi | 226 arch/arm/mach-rzn1/Kconfig| 32 + arch/arm/mach-rzn1/Makefile |3 + arch/arm/mach-rzn1/cpu_info.c | 19 + board/schneider/rzn1-snarc/Kconfig| 18 + board/schneider/rzn1-snarc/Makefile |3 + board/schneider/rzn1-snarc/ddr_timing.c | 140 +++ .../jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++ board/schneider/rzn1-snarc/rzn1.c | 39 + board/schneider/rzn1-snarc/spkgimage.cfg | 26 + boot/image.c |1 + configs/rzn1_snarc_defconfig | 21 + doc/mkimage.1 | 45 + drivers/clk/renesas/Kconfig |8 +- drivers/clk/renesas/Makefile |6 +- drivers/clk/renesas/r9a06g032-clocks.c| 1077 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/renesas/Kconfig |7 + drivers/pinctrl/renesas/Makefile |1 + drivers/pinctrl/renesas/pinctrl-rzn1.c| 379 ++ drivers/ram/Kconfig |1 + drivers/ram/Makefile |2 + drivers/ram/cadence/Kconfig | 12 + drivers/ram/cadence/Makefile |1 + drivers/ram/cadence/ddr_async.c | 311 + drivers/ram/cadence/ddr_ctrl.c| 414 +++ drivers/ram/cadence/ddr_ctrl.h| 175 +++ include/configs/rzn1-snarc.h | 17 + include/dt-bindings/clock/r9a06g032-sysctrl.h | 148 +++ include/dt-bindings/pinctrl/rzn1-pinctrl.h| 141 +++ include/image.h |1 + tools/Makefile|1 + tools/spkgimage.c | 330 + tools/spkgimage.h | 45 + 38 files changed, 4120 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc.dts create mode 100644 arch/arm/dts/r9a06g032.dtsi create mode 100644 arch/arm/mach-rzn1/Kconfig create mode 100644 arch/arm/mach-rzn1/Makefile create mode 100644 arch/arm/mach-rzn1/cpu_info.c create mode 100644 board/schneider/rzn1-snarc/Kconfig create mode 100644 board/schneider/rzn1-snarc/Makefile create mode 100644 board/schneider/rzn1-snarc/ddr_timing.c create mode 100644 board/schneider/rzn1-snarc/jedec_ddr3_2g_x16_1333h_500_cl8.h create mode 100644 board/schneider/rzn1-snarc/rzn1.c create mode 100644 board/schneider/rzn1-snarc/spkgimage.cfg create mode 100644 configs/rzn1_snarc_defconfig create mode 100644 drivers/clk/renesas/r9a06g032-clocks.c create mode 100644 drivers/pinctrl/renesas/pinctrl-rzn1.c create mode 100644 drivers/ram/cadence/Kconfig create mode 100644 drivers/ram/cadence/Makefile create mode 100644 drivers/ram/cadence/ddr_async.c create mode 100644 drivers/ram/cadence/ddr_ctrl.c create mode 100644 drivers/ram/cadence/ddr_ctrl.h create mode 100644 include/configs/rzn1-snarc.h create mode 100644 include/dt-bindings/clock/r9a06g032-sysctrl.h create mode 100644 include/dt-bindings/pinctrl/rzn1-pinctrl.h create mode 100644 tools/spkgimage.c
[RFC PATCH v3 9/9] tools: spkgimage: add Renesas SPKG format
Renesas RZ/N1 devices contain BootROM code that loads a custom SPKG
image from QSPI, NAND or USB DFU. Support this format in mkimage tool.
SPKGs can optionally be signed, however creation of signed SPKG is not
currently supported.
Example of how to use it:
tools/mkimage -n board/schneider/rzn1-snarc/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
---
Changes in v3:
- provide definition of __packed (as done in kwbimage.h)
- explain why a local copy of roundup() is needed
- document spkgimage in doc/mkimage.1
- add range checks when parsing config file values
- add line numbers for reporting errors in config file
- rename SPKG_HEADER_SIGNATURE to SPKG_HEADER_MARKER
- fix segfault when image is padded by less than 4 bytes
- minor style and typo fixes
Changes in v2:
- rewrote the stand-alone spkg_utility to integrate into mkimage
board/schneider/rzn1-snarc/spkgimage.cfg | 26 ++
boot/image.c | 1 +
doc/mkimage.1| 45
include/image.h | 1 +
tools/Makefile | 1 +
tools/spkgimage.c| 330 +++
tools/spkgimage.h| 45
7 files changed, 449 insertions(+)
create mode 100644 board/schneider/rzn1-snarc/spkgimage.cfg
create mode 100644 tools/spkgimage.c
create mode 100644 tools/spkgimage.h
diff --git a/board/schneider/rzn1-snarc/spkgimage.cfg
b/board/schneider/rzn1-snarc/spkgimage.cfg
new file mode 100644
index 00..b5faf96b00
--- /dev/null
+++ b/board/schneider/rzn1-snarc/spkgimage.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Schneider Electric
+#
+# SPKG image header, for booting on RZ/N1
+
+# b[35:32] SPKG version
+VERSION1
+
+# b[42:41] ECC Block size: 0=256 bytes, 1=512 bytes, 2=1024 bytes
+NAND_ECC_BLOCK_SIZE1
+
+# b[45] NAND enable (boolean)
+NAND_ECC_ENABLE1
+
+# b[50:48] ECC Scheme: 0=BCH2 1=BCH4 2=BCH8 3=BCH16 4=BCH24 5=BCH32
+NAND_ECC_SCHEME3
+
+# b[63:56] ECC bytes per block
+NAND_BYTES_PER_ECC_BLOCK 28
+
+# Provide dummy BLp header (boolean)
+ADD_DUMMY_BLP 1
+
+# Pad the image to a multiple of
+PADDING64K
diff --git a/boot/image.c b/boot/image.c
index 958dbf8534..5c4f9b807d 100644
--- a/boot/image.c
+++ b/boot/image.c
@@ -181,6 +181,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_SUNXI_EGON, "sunxi_egon", "Allwinner eGON Boot Image"
},
{ IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image"
},
{ IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat
Device Tree ", },
+ { IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" },
{ -1, "", "", },
};
diff --git a/doc/mkimage.1 b/doc/mkimage.1
index d8727ec73c..76c7859bb0 100644
--- a/doc/mkimage.1
+++ b/doc/mkimage.1
@@ -662,6 +662,51 @@ rk3568
.TE
.RE
.
+.SS spkgimage
+The primary configuration file consists of lines containing key/value pairs
+delimited by whitespace. An example follows.
+.PP
+.RS
+.EX
+# Comments and blank lines may be used
+.I key1 value1
+.I key2 value2
+.EE
+.RE
+.P
+The supported
+.I key
+types are as follows.
+.TP
+.B VERSION
+.TQ
+.B NAND_ECC_BLOCK_SIZE
+.TQ
+.B NAND_ECC_ENABLE
+.TQ
+.B NAND_ECC_SCHEME
+.TQ
+.B NAND_BYTES_PER_ECC_BLOCK
+These all take a positive integer value as their argument.
+The value will be copied directly into the respective field
+of the SPKG header structure. For details on these values,
+refer to Section 7.4 of the Renesas RZ/N1 User's Manual.
+.
+.TP
+.B ADD_DUMMY_BLP
+Takes a numeric argument, which is treated as a boolean. Any nonzero
+value will cause a fake BLp security header to be included in the SPKG
+output.
+.
+.TP
+.B PADDING
+Takes a positive integer value, with an optional
+.B K
+or
+.B M
+suffix, indicating KiB / MiB respectively.
+The output SPKG file will be padded to a multiple of this value.
+.
.SS sunxi_egon
The primary configuration is the name to use for the device tree.
.
diff --git a/include/image.h b/include/image.h
index 7717a4c13d..acfbb6a53a 100644
--- a/include/image.h
+++ b/include/image.h
@@ -230,6 +230,7 @@ enum image_type_t {
IH_TYPE_SUNXI_EGON, /* Allwinner eGON Boot Image */
IH_TYPE_SUNXI_TOC0, /* Allwinner TOC0 Boot Image */
IH_TYPE_FDT_LEGACY, /* Binary Flat Device Tree Blob in a
Legacy Image */
+ IH_TYPE_RENESAS_SPKG, /* Renesas SPKG image */
IH_TYPE_COUNT, /* Number of image types */
[RFC PATCH v3 8/9] board: schneider: add RZN1 board support
Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
Changes in v3:
- rename board LCES to rzn1-snarc
- move CONFIG_SYS_NS16550_MEM32 to Kconfig
- define CFG_SYS_INIT_RAM_{ADDR,SIZE}
- removed debug uart settings from defconfig
arch/arm/dts/r9a06g032-rzn1-snarc.dts | 51 +++
arch/arm/mach-rzn1/Kconfig| 14 +
board/schneider/rzn1-snarc/Kconfig| 18 +
board/schneider/rzn1-snarc/Makefile | 3 +
board/schneider/rzn1-snarc/ddr_timing.c | 140 ++
.../jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++
board/schneider/rzn1-snarc/rzn1.c | 39 ++
configs/rzn1_snarc_defconfig | 21 +
include/configs/rzn1-snarc.h | 17 +
9 files changed, 702 insertions(+)
create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc.dts
create mode 100644 board/schneider/rzn1-snarc/Kconfig
create mode 100644 board/schneider/rzn1-snarc/Makefile
create mode 100644 board/schneider/rzn1-snarc/ddr_timing.c
create mode 100644 board/schneider/rzn1-snarc/jedec_ddr3_2g_x16_1333h_500_cl8.h
create mode 100644 board/schneider/rzn1-snarc/rzn1.c
create mode 100644 configs/rzn1_snarc_defconfig
create mode 100644 include/configs/rzn1-snarc.h
diff --git a/arch/arm/dts/r9a06g032-rzn1-snarc.dts
b/arch/arm/dts/r9a06g032-rzn1-snarc.dts
new file mode 100644
index 00..abb269cc21
--- /dev/null
+++ b/arch/arm/dts/r9a06g032-rzn1-snarc.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for Schneider RZ/N1 Board
+ *
+ * Based on r9a06g032-rzn1d400-db.dts
+ */
+
+/dts-v1/;
+
+#include "r9a06g032.dtsi"
+#include
+
+/ {
+ model = "Schneider RZ/N1 Board";
+ compatible = "schneider,rzn1", "renesas,r9a06g032";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x8000 0x1000>;
+ };
+};
+
+&ddrctrl {
+ status = "okay";
+};
+
+&pinctrl {
+ status = "okay";
+
+ pins_uart0: pins_uart0 {
+ pinmux = <
+ RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
+ RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
+ >;
+ bias-disable;
+ };
+};
+
+&uart0 {
+ pinctrl-0 = <&pins_uart0>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm/mach-rzn1/Kconfig b/arch/arm/mach-rzn1/Kconfig
index 707895874d..4b13afbb32 100644
--- a/arch/arm/mach-rzn1/Kconfig
+++ b/arch/arm/mach-rzn1/Kconfig
@@ -15,4 +15,18 @@ endchoice
config SYS_SOC
default "rzn1"
+choice
+ prompt "Board select"
+ default TARGET_SCHNEIDER_RZN1
+
+config TARGET_SCHNEIDER_RZN1
+ bool "Schneider RZN1 board"
+ help
+ Support the Schneider RZN1D and RZN1S boards, which are based
+ on the Renesas RZ/N1 SoC.
+
+endchoice
+
+source "board/schneider/rzn1-snarc/Kconfig"
+
endif
diff --git a/board/schneider/rzn1-snarc/Kconfig
b/board/schneider/rzn1-snarc/Kconfig
new file mode 100644
index 00..bb6d394077
--- /dev/null
+++ b/board/schneider/rzn1-snarc/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SCHNEIDER_RZN1
+
+config TEXT_BASE
+ default 0x2004 if ARCH_RZN1
+
+config SYS_MONITOR_LEN
+ default 524288 if ARCH_RZN1
+
+config SYS_BOARD
+ default "rzn1-snarc"
+
+config SYS_VENDOR
+ default "schneider"
+
+config SYS_CONFIG_NAME
+ default "rzn1-snarc"
+
+endif
diff --git a/board/schneider/rzn1-snarc/Makefile
b/board/schneider/rzn1-snarc/Makefile
new file mode 100644
index 00..95c151898b
--- /dev/null
+++ b/board/schneider/rzn1-snarc/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := rzn1.o ddr_timing.o
diff --git a/board/schneider/rzn1-snarc/ddr_timing.c
b/board/schneider/rzn1-snarc/ddr_timing.c
new file mode 100644
index 00..8bc3fe7be4
--- /dev/null
+++ b/board/schneider/rzn1-snarc/ddr_timing.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include
+
+#include "jedec_ddr3_2g_x16_1333h_500_cl8.h"
+
+u32 ddr_00_87_async[] = {
+ DENALI_CTL_00_DATA,
+ DENALI_CTL_01_DATA,
+ DENALI_CTL_02_DATA,
+ DENALI_CTL_03_DATA,
+ DENALI_CTL_04_DATA,
+ DENALI_CTL_05_DATA,
+ DENALI_CTL_06_DATA,
+ DENALI_CTL_07_DATA,
+ DENALI_CTL_08_DATA,
+ DENALI_CTL_09_DATA,
+
+ DENALI_CTL_10_DATA,
+
[RFC PATCH v3 3/9] clk: renesas: add R906G032 driver
Clock driver for the Renesas RZ/N1 SoC family. This is based
on the Linux kernel drivers/clk/renesas/r9a06g032-clocks.c.
Notable difference: this version avoids allocating a 'struct clk'
for each clock source, as this is problematic before relocation.
Instead, it uses the same approach as existing Renesas RCAR2/3
clock drivers, using a temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen
---
Changes in v3:
- convert data table to explicit reg/bit numbers
- drop the unused scon, mirack, mirstat fields
- added some kernel docs to structures
- use enum for type field of struct r9a06g032_clkdesc
- cleanup macros for one assignment per line
- add a macro for top-most clock ID value ~0
- use dev_dbg() instead of debug/print
- minor reformatting, declarations before code, etc
- !foo instead of foo == 0
- IS_ERR / PTR_ERR where appropriate
- implement div_table handling
- remove some #if 0 old test code
drivers/clk/renesas/Kconfig|6 +
drivers/clk/renesas/Makefile |1 +
drivers/clk/renesas/r9a06g032-clocks.c | 1077
3 files changed, 1084 insertions(+)
create mode 100644 drivers/clk/renesas/r9a06g032-clocks.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 6788415eed..bbc618f464 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -130,3 +130,9 @@ config CLK_R8A779A0
depends on CLK_RCAR_GEN3
help
Enable this to support the clocks on Renesas R8A779A0 SoC.
+
+config CLK_R9A06G032
+ bool "Renesas R9A06G032 clock driver"
+ depends on CLK_RENESAS
+ help
+ Enable this to support the clocks on Renesas R9A06G032 SoC.
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index a0d8c10bdb..7f0ef28367 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
+obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c
b/drivers/clk/renesas/r9a06g032-clocks.c
new file mode 100644
index 00..5ea076ae8f
--- /dev/null
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -0,0 +1,1077 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R9A06G032 clock driver
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet ,
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+/**
+ * struct regbit - describe one bit in a register
+ * @reg: offset of register relative to base address,
+ * expressed in units of 32-bit words (not bytes),
+ * @bit: which bit (0 to 31) in the register
+ *
+ * This structure is used to compactly encode the location
+ * of a single bit in a register. Five bits are needed to
+ * encode the bit number. With uint16_t data type, this
+ * leaves 11 bits to encode a register offset up to 2047.
+ *
+ * Since registers are aligned on 32-bit boundaries, the
+ * offset will be specified in 32-bit words rather than bytes.
+ * This allows encoding an offset up to 0x1FFC (8188) bytes.
+ */
+struct regbit {
+ u16 reg:11;
+ u16 bit:5;
+};
+
+/**
+ * struct r9a06g032_gate - clock gate control bits
+ * @gate: bit which enables/disables the clock
+ * @reset: bit which controls module reset (active low)
+ * @ready: bit which indicates device is ready for access
+ * @midle: bit which requests to idle the NoC interconnect
+ *
+ * Each of these fields describes a single bit in a register,
+ * which controls some aspect of clock gating. The @gate field
+ * is mandatory, this one enables/disables the clock. The
+ * other fields are optional, with zero indicating "not used".
+ *
+ * In most cases there is a @reset bit which needs to be
+ * de-asserted to bring the module out of reset.
+ *
+ * Modules may also need to signal when the are @ready to
+ * handle requests (read/writes) from the NoC interconnect.
+ *
+ * Similarly, the @midle bit is used to idle the master.
+ */
+struct r9a06g032_gate {
+ struct regbit gate, reset, ready, midle;
+ /* Unused fields omitted to save space */
+ /* struct regbit scon, mirack, mistat */;
+};
+
+enum gate_type {
+ K_GATE = 0, /* gate which enable/disable */
+ K_FFC, /* fixed factor clock */
+ K_DIV, /* divisor */
+ K_BITSEL, /* special for UARTs */
+ K_DUALGATE /* special for UARTs */
+};
+
+/**
+ * struct r9a06g032_clkdesc - describe a single clock
+ * @name:string describing this clock
+ * @managed: not used in u-boot
+ * @type: see enum gate_type
+ * @index: the ID of this clock element
+ * @source: the ID+1 of the parent clock element.
+ * Root clock uses I
[RFC PATCH v3 7/9] ARM: rzn1: basic support for Renesas RZ/N1 SoC
The RZ/N1 is a family of SoC devics from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD
Add basic support in the form of ARCH_RZN1 symbol.
Signed-off-by: Ralph Siemsen
---
(no changes since v1)
arch/arm/Kconfig | 17 +
arch/arm/Makefile | 1 +
arch/arm/mach-rzn1/Kconfig| 18 ++
arch/arm/mach-rzn1/Makefile | 3 +++
arch/arm/mach-rzn1/cpu_info.c | 19 +++
5 files changed, 58 insertions(+)
create mode 100644 arch/arm/mach-rzn1/Kconfig
create mode 100644 arch/arm/mach-rzn1/Makefile
create mode 100644 arch/arm/mach-rzn1/cpu_info.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bd7fffcce0..8e2a30f852 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1031,6 +1031,21 @@ config ARCH_RMOBILE
imply SYS_THUMB_BUILD
imply ARCH_MISC_INIT if DISPLAY_CPUINFO
+config ARCH_RZN1
+ bool "Reneasa RZ/N1 SoC"
+ select CLK
+ select CLK_RENESAS
+ select CLK_R9A06G032
+ select DM
+ select DM_ETH
+ select DM_SERIAL
+ select PINCTRL
+ select PINCONF
+ select REGMAP
+ select SYSRESET
+ select SYSRESET_SYSCON
+ imply CMD_DM
+
config ARCH_SNAPDRAGON
bool "Qualcomm Snapdragon SoCs"
select ARM64
@@ -2207,6 +,8 @@ source "arch/arm/mach-owl/Kconfig"
source "arch/arm/mach-rmobile/Kconfig"
+source "arch/arm/mach-rzn1/Kconfig"
+
source "arch/arm/mach-meson/Kconfig"
source "arch/arm/mach-mediatek/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ac602aed9c..1ec95a87e1 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -76,6 +76,7 @@ machine-$(CONFIG_ARCH_ORION5X)+= orion5x
machine-$(CONFIG_ARCH_OWL) += owl
machine-$(CONFIG_ARCH_RMOBILE) += rmobile
machine-$(CONFIG_ARCH_ROCKCHIP)+= rockchip
+machine-$(CONFIG_ARCH_RZN1)+= rzn1
machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
diff --git a/arch/arm/mach-rzn1/Kconfig b/arch/arm/mach-rzn1/Kconfig
new file mode 100644
index 00..707895874d
--- /dev/null
+++ b/arch/arm/mach-rzn1/Kconfig
@@ -0,0 +1,18 @@
+if ARCH_RZN1
+
+choice
+ prompt "Target Renesas RZ/N1 SoC select"
+ default RZN1
+
+config RZN1
+ bool "Renesas ARM SoCs RZ/N1 (32bit)"
+ select CPU_V7A
+ select ARMV7_SET_CORTEX_SMPEN if !SPL
+ select SPL_ARMV7_SET_CORTEX_SMPEN if SPL
+
+endchoice
+
+config SYS_SOC
+ default "rzn1"
+
+endif
diff --git a/arch/arm/mach-rzn1/Makefile b/arch/arm/mach-rzn1/Makefile
new file mode 100644
index 00..b20f845c0f
--- /dev/null
+++ b/arch/arm/mach-rzn1/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y = cpu_info.o
diff --git a/arch/arm/mach-rzn1/cpu_info.c b/arch/arm/mach-rzn1/cpu_info.c
new file mode 100644
index 00..37c2492b51
--- /dev/null
+++ b/arch/arm/mach-rzn1/cpu_info.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include
+#include
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+ dcache_enable();
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ printf("CPU: Renesas Electronics RZ/N1\n");
+ return 0;
+}
+#endif
--
2.25.1
[RFC PATCH v3 5/9] ram: cadence: add driver for Cadence EDAC
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen
---
Changes in v3:
- assorted small cleanups
- support version 1.0 silicon (previously #if 0...)
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile| 2 +
drivers/ram/cadence/Kconfig | 12 +
drivers/ram/cadence/Makefile| 1 +
drivers/ram/cadence/ddr_async.c | 311
drivers/ram/cadence/ddr_ctrl.c | 414
drivers/ram/cadence/ddr_ctrl.h | 175 ++
7 files changed, 916 insertions(+)
create mode 100644 drivers/ram/cadence/Kconfig
create mode 100644 drivers/ram/cadence/Makefile
create mode 100644 drivers/ram/cadence/ddr_async.c
create mode 100644 drivers/ram/cadence/ddr_ctrl.c
create mode 100644 drivers/ram/cadence/ddr_ctrl.h
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index e085119963..2b6d8f1c7b 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -108,6 +108,7 @@ config IMXRT_SDRAM
This driver is for the sdram memory interface with the SEMC.
source "drivers/ram/aspeed/Kconfig"
+source "drivers/ram/cadence/Kconfig"
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 83948e2c43..e2d5e730d1 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -22,3 +22,5 @@ obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
obj-$(CONFIG_RAM_SIFIVE) += sifive/
obj-$(CONFIG_ARCH_OCTEON) += octeon/
+
+obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/
diff --git a/drivers/ram/cadence/Kconfig b/drivers/ram/cadence/Kconfig
new file mode 100644
index 00..2d5469cb8e
--- /dev/null
+++ b/drivers/ram/cadence/Kconfig
@@ -0,0 +1,12 @@
+if RAM || SPL_RAM
+
+config CADENCE_DDR_CTRL
+ bool "Enable Cadence DDR controller"
+ depends on DM
+ help
+ Enable support for Cadence DDR controller, as found on
+ the Renesas RZ/N1 SoC. This controller has a large number
+ of registers which need to be programmed, mostly using values
+ obtained from Denali SOMA files via a TCL script.
+
+endif
diff --git a/drivers/ram/cadence/Makefile b/drivers/ram/cadence/Makefile
new file mode 100644
index 00..16c7fe8488
--- /dev/null
+++ b/drivers/ram/cadence/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CADENCE_DDR_CTRL) += ddr_async.o ddr_ctrl.o
diff --git a/drivers/ram/cadence/ddr_async.c b/drivers/ram/cadence/ddr_async.c
new file mode 100644
index 00..444eeb8ac7
--- /dev/null
+++ b/drivers/ram/cadence/ddr_async.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * RZ/N1 DDR Controller initialisation
+ *
+ * The DDR Controller register values for a specific DDR device, mode and
+ * frequency are generated using a Cadence tool.
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe Ltd
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "ddr_ctrl.h"
+
+void clk_rzn1_reset_state(struct clk *clk, int on);
+
+extern u32 ddr_00_87_async[];
+extern u32 ddr_350_374_async[];
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct cadence_ddr_info {
+ struct udevice *dev;
+ void __iomem *ddrc;
+ void __iomem *phy;
+ struct clk clk_ddrc;
+ struct clk hclk_ddrc;
+ struct regmap *syscon;
+ bool enable_ecc;
+ bool enable_8bit;
+};
+
+static inline u32 cadence_readl(void __iomem *addr, unsigned int offset)
+{
+ return readl(addr + offset);
+}
+
+static inline void cadence_writel(void __iomem *addr, unsigned int offset,
+ u32 data)
+{
+ debug("%s: addr = 0x%p, value = 0x%08x\n", __func__, addr + offset,
data);
+ writel(data, addr + offset);
+}
+
+#define ddrc_readl(off)cadence_readl(priv->ddrc, off)
+#define ddrc_writel(val, off) cadence_writel(priv->ddrc, off, val)
+
+#define phy_readl(off) cadence_readl(priv->phy, off)
+#define phy_writel(val, off) cadence_writel(priv->phy, off, val)
+
+#define RZN1_DDR3_SINGLE_BANK 3
+#define RZN1_DDR3_DUAL_BANK 32
+
+#define FUNCCTRL 0x00
+#define FUNCCTRL_MASKSDLOFS (0x18 << 16)
+#define FUNCCTRL_DVDDQ_1_5V (1 << 8)
+#define FUNCCTRL_RESET_N (1 << 0)
+#define DLLCTRL0x04
+#define DLLCTRL_ASDLLOCK (1 << 26)
+#define DLLCTRL_MFSL_500MHz (2 << 1)
+#define DLLCTRL_MDLLSTBY (1 << 0)
+#define ZQCALCTRL 0x08
+#define ZQCALCTRL_ZQCALEND(1 << 30)
+#define ZQCALCTRL_ZQCALRSTB (1 << 0)
+#define ZQODTCTRL 0x0c
+#define RDCTRL 0x10
+#define RDTMG 0x14
+#define FIFOINIT 0x18
+#define FIFOINIT_RDPTINITEXE (1 << 8)
+#define FIFOINIT_WRPTINITEXE (1 << 0)
+#define OUTCTRL0x1c
+#define OUTCTR
[RFC PATCH v3 4/9] pinctrl: renesas: add R906G032 driver
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen
---
(no changes since v1)
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/renesas/Kconfig| 7 +
drivers/pinctrl/renesas/Makefile | 1 +
drivers/pinctrl/renesas/pinctrl-rzn1.c | 379 +
include/dt-bindings/pinctrl/rzn1-pinctrl.h | 141
5 files changed, 529 insertions(+)
create mode 100644 drivers/pinctrl/renesas/pinctrl-rzn1.c
create mode 100644 include/dt-bindings/pinctrl/rzn1-pinctrl.h
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 3b167d099f..450267732c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_INTEL) += intel/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
+obj-$(CONFIG_ARCH_RZN1) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_PINCTRL_SUNXI)+= sunxi/
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 8f994d8d76..b707d7549b 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -127,3 +127,10 @@ config PINCTRL_PFC_R7S72100
Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
endif
+
+config PINCTRL_RZN1
+ bool "Renesas RZ/N1 R906G032 pin control driver"
+ depends on ARCH_RZN1
+ default y if ARCH_RZN1
+ help
+ Support pin multiplexing control on Renesas RZ/N1 R906G032 SoCs.
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 1198c86855..39b2f65f2e 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
+obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
diff --git a/drivers/pinctrl/renesas/pinctrl-rzn1.c
b/drivers/pinctrl/renesas/pinctrl-rzn1.c
new file mode 100644
index 00..fdc43c8e71
--- /dev/null
+++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
+ *
+ * Phil Edworthy
+ * Based on a driver originally written by Michel Pollet at Renesas.
+ */
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+/* Field positions and masks in the pinmux registers */
+#define RZN1_L1_PIN_DRIVE_STRENGTH 10
+#define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0
+#define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1
+#define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2
+#define RZN1_L1_PIN_DRIVE_STRENGTH_12MA3
+#define RZN1_L1_PIN_PULL 8
+#define RZN1_L1_PIN_PULL_NONE 0
+#define RZN1_L1_PIN_PULL_UP1
+#define RZN1_L1_PIN_PULL_DOWN 3
+#define RZN1_L1_FUNCTION 0
+#define RZN1_L1_FUNC_MASK 0xf
+#define RZN1_L1_FUNCTION_L20xf
+
+/*
+ * The hardware manual describes two levels of multiplexing, but it's more
+ * logical to think of the hardware as three levels, with level 3 consisting of
+ * the multiplexing for Ethernet MDIO signals.
+ *
+ * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf)
specifying
+ * that level 2 functions are used instead. Level 2 has a lot more options,
+ * going from 0 to 61. Level 3 allows selection of MDIO functions which can be
+ * floating, or one of seven internal peripherals. Unfortunately, there are two
+ * level 2 functions that can select MDIO, and two MDIO channels so we have
four
+ * sets of level 3 functions.
+ *
+ * For this driver, we've compounded the numbers together, so:
+ *0 to 9 is level 1
+ * 10 to 71 is 10 + level 2 number
+ * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function.
+ * 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function.
+ * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function.
+ * 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function.
+ * Examples:
+ * Function 28 corresponds UART0
+ * Function 73 corresponds to MDIO0 to GMAC0
+ *
+ * There are 170 configurable pins (called PL_GPIO in the datasheet).
+ */
+
+/*
+ * Structure detailing the HW registers on the RZ/N1 devices.
+ * Both the Level 1 mux registers and Level 2 mux registers have the same
+ * structure. The only difference is that Level 2 has additional MDIO registers
+ * at the end.
+ */
+struct rzn1_pinctrl_regs {
+ u32 conf[170];
+ u32 pad0[86];
+ u32 status_protect; /* 0x400 */
+ /* MDIO mux registers, level2 only */
+ u32 l2_md
[RFC PATCH v3 6/9] dts: basic devicetree for Renesas RZ/N1 SoC
This is taken from Linux kernel 5.17, and contains just bare minimum
functionality: CPU, UART and system timer.
Additional functionality (from newer kernel versions) will be added
later. Note that the Linux side is under active development.
Signed-off-by: Ralph Siemsen
---
The following changes were made, compared with Linux 5.17:
1) Add node for system controller registers.
Declare it as syscon to provide a regmap interface.
2) In the clock controller node (renesas,r9a06g032-sysctrl),
replace regs with regmap.
3) Add syscon-reset node, making use of the syscon regmap.
4) Add syscon phandle to ddrctrl. Used for checking h/w version.
5) Simplify the compatible string for all the UARTS, as per
doc/device-tree-bindings/serial/snps-dw-apb-uart.txt
I could not find a way to avoid 1) and 2). Putting "syscon" in the
compatible string for the clock controller leads to a catch-22,
where the driver fails to initialize, and then boot hangs.
Changes in v3:
- add syscon phandle to ddrctl
- simplify UART compatible strings
arch/arm/dts/r9a06g032.dtsi | 226 ++
include/dt-bindings/clock/r9a06g032-sysctrl.h | 148
2 files changed, 374 insertions(+)
create mode 100644 arch/arm/dts/r9a06g032.dtsi
create mode 100644 include/dt-bindings/clock/r9a06g032-sysctrl.h
diff --git a/arch/arm/dts/r9a06g032.dtsi b/arch/arm/dts/r9a06g032.dtsi
new file mode 100644
index 00..e0ddffb074
--- /dev/null
+++ b/arch/arm/dts/r9a06g032.dtsi
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include
+#include
+
+/ {
+ compatible = "renesas,r9a06g032";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <1>;
+ clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+ enable-method = "renesas,r9a06g032-smp";
+ cpu-release-addr = <0 0x4000c204>;
+ };
+ };
+
+ ext_jtag_clk: extjtagclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ext_mclk: extmclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000>;
+ };
+
+ ext_rgmii_ref: extrgmiiref {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ext_rtc_clk: extrtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ plat_regs: system-controller@4000c000 {
+ compatible = "syscon";
+ reg = <0x4000c000 0x1000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ sysctrl: clock {
+ compatible = "renesas,r9a06g032-sysctrl";
+ #clock-cells = <1>;
+ regmap = <&plat_regs>;
+ u-boot,dm-pre-reloc;
+
+ clocks = <&ext_mclk>, <&ext_rtc_clk>,
+ <&ext_jtag_clk>, <&ext_rgmii_ref>;
+ clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+ };
+
+ ddrctrl: memory-controller@4000d000 {
+ compatible = "cadence,ddr-ctrl";
+ reg = <0x4000d000 0x1000>, <0x4000e000 0x100>;
+ reg-names = "ddrc", "phy";
+ interrupts = ;
+ clocks = <&sysctrl R9A06G032_CLK_DDRC>, <&sysctrl
R9A06G032_HCLK_DDRC>;
+ clock-names = "clk_ddrc", "hclk_ddrc";
+
[RFC PATCH v3 2/9] clk: renesas: prepare for non-RCAR clock drivers
Allow CONFIG_CLK_RENESAS to be set without bringing in RCAR-GEN2/3 code. CONFIG_RENESAS is used in drivers/clk/Makefile to control recursion into the drivers/clk/renesas subdirectory. It also controls compilation of renesas-cpg-mssr.c support code for the RCAR-GEN2 and RCAR-GEN3 devices. The support code contains platform specific hardware access (TMU_BASE), and it is not needed for other Renesas devices such as RZ/N1. Therefore, alter Makefile to build renesas-cpg-mssr.c only for RCAR-GEN2/3. Signed-off-by: Ralph Siemsen Reviewed-by: Sean Anderson --- Changes in v3: - added tags drivers/clk/renesas/Kconfig | 2 +- drivers/clk/renesas/Makefile | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 1686410d6d..6788415eed 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -1,6 +1,6 @@ config CLK_RENESAS bool "Renesas clock drivers" - depends on CLK && ARCH_RMOBILE + depends on CLK && (ARCH_RMOBILE || ARCH_RZN1) help Enable support for clock present on Renesas RCar SoCs. diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 8f82a7aa3e..a0d8c10bdb 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -1,6 +1,5 @@ -obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o -obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o +obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o renesas-cpg-mssr.o obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o @@ -10,7 +9,7 @@ obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o obj-$(CONFIG_CLK_R8A7793) += r8a7791-cpg-mssr.o obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o -obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o +obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o renesas-cpg-mssr.o obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o obj-$(CONFIG_CLK_R8A77960) += r8a7796-cpg-mssr.o obj-$(CONFIG_CLK_R8A77961) += r8a7796-cpg-mssr.o -- 2.25.1
[RFC PATCH v3 1/9] ARM: armv7: add non-SPL enable for Cortex SMPEN
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off-by: Ralph Siemsen
---
This will be used by the following commit that adds ARCH_RZN1.
(no changes since v1)
arch/arm/cpu/armv7/Kconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index f1e4e26b8f..e33e53636a 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -107,6 +107,11 @@ config ARMV7_LPAE
Say Y here to use the long descriptor page table format. This is
required if U-Boot runs in HYP mode.
+config ARMV7_SET_CORTEX_SMPEN
+ bool
+ help
+ Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
+
config SPL_ARMV7_SET_CORTEX_SMPEN
bool
help
--
2.25.1
Re: [RFC PATCH v1 3/9] clk: renesas: add R906G032 driver
On Tue, Aug 23, 2022 at 12:14:31AM -0400, Sean Anderson wrote: Regarding the unused fields (scon, mirack, mistat): I am not really sure what their purpose is. Maybe there is some value in having them. I'll try to find out more information about them. If we do decide to drop them, I would like to keep it synchronised with the Linux driver. OK, well if you don't use them then perhaps you can just leave them in the macro but remove them from the struct. That way you can add support for them later if you need to, but they don't take up space in the mean time. A comment summarizing your explanation above would be helpful. I did figure out (mostly) what they are for, so I can see some value in keeping at least some of them. But as you said, they are currently unused, so dropping them from the structure make sense. I have prepared patches for this firstly on the kernel side, and then I will make the same change in this u-boot driver. Stay tuned :-) I think it happened before I started working on RZ/N1, but there seemed to be quite a few iterations on how to represent the clock tree. At one point there were macros to assign/construct the bitfield values. And then a different way, and eventually the direct hex values you now see in the clock tables. At the risk of re-opening old wounds (luckily not mine) I decided to just leave this part exactly as-is in the Linux driver. Can you link to that discussion? The earliest discussion of that series I could find was [1], and there's no mention of the encoding. This encoding scheme seems to be used only for this SoC, and not for any of the other renesas drivers. I suspect that this just wasn't reviewed in detail the first time around... [1] https://lore.kernel.org/all/1527154169-32380-6-git-send-email-michel.pol...@bp.renesas.com/ That link [1] is the current driver, which uses the packed encoding (with a register offset and bit number stored as a packed uint16_t). This is based (loosely) on an earlier version of the driver, which you can find in the Schneider kernel repo [2] on the 4.19 and older branch. This version stores clock information is in the device tree [3] and uses _BIT() macro in the clock tables [4] [2] https://github.com/renesas-rz/rzn1_linux/tree/rzn1-stable-v4.19/drivers/clk/rzn1 [3] https://github.com/renesas-rz/rzn1_linux/blob/rzn1-stable-v4.19/arch/arm/boot/dts/rzn1-clocks.dtsi [4] https://github.com/renesas-rz/rzn1_linux/blob/rzn1-stable-v4.19/drivers/clk/rzn1/rzn1-clkctrl-tables.h Evidently this was not deemed suitable, and thus morphed into the version that did get merged [1]. At least that is my guess, I don't know for sure what transpired. I have modified the clock table so that the register offset and bitnum are explicit values, rather than packed together. I will run this up the kernel side and see if they agree. Am still trying to test it though... In fact quite a few of them are in the dt-bindings already, see include/dt-bindings/clock/r9a06g032-sysctrl.h I'm not really sure why some of these are defined in the .C file while others are in the dt-bindings header. Like much of the other bits, this was something I just carried over as-is from the Linux driver. I think these are "internal" clocks (that is, clocks which don't really exist like intermediate dividers) whereas the others are public-facing clocks. It's up to you, but maybe have a comment noting where the other ids come from. I guess that is plausible explanation.. I will add a comment... + else + parent->id = desc->source - 1; + + parent->dev = clk->dev; I think you need to clk_request here. Normally clk_request is called by a driver wishing to use a particular clock. That is not the case here. This is in a helper function used to compute the current rate of a given clock. It only looks at the local table (struct r9a06g032_clkdsc). You call clk_get_rate on it. Any time you "create" a new clock, you must call clk_request. So the situation here is similar to that on the mediatek patches from Weijie Gao [5], where you made a similar comment. These are not real clocks, they have no ops->request, and the only field used is clk->id. This is done primarily to avoid a bunch of malloc of struct clk, particularly in the early u-boot (before relocation). [5] https://lore.kernel.org/all/31b0e1313267c8d342e0e3d1c9f15eaa8e666114.ca...@mediatek.com/ It is for a different clock type. However I will see if I do something to avoid the duplication. I mean in r9a06g032_clk_get_parent_rate. You can also just do if (!parent_rate) ... I've fixed this (and several similar instances elsewhere). DIV_ROUND_CLOSEST? I'm hesitant to change the logic on this, as it could subtly alter the values. Well if you have 2MHz divided by 3, the resulting rate is closer to 67 kHz than 66 Hz. While I can't argue with the math, the linux driver upon which this is based uses DIV_ROUND_UP everywhere. Maybe tha
Re: [RFC PATCH v2 9/9] tools: spkgimage: add Renesas SPKG format
On Mon, Aug 22, 2022 at 11:42:54PM -0400, Sean Anderson wrote:
+static int spkgimage_check_image_types(uint8_t type)
+{
+ return type == IH_TYPE_RENESAS_SPKG ? 0 : 1;
This function is not necessary if you only support one type.
Without this function, mkimage kept telling me that my format
(spkgimage) was not supported, and none of my callbacks got invoked.
It only complained when trying to generate a header. When listing the
supported formats, spkgimage showed up correctly.
I'll take another look on Monday, maybe I missed something obvious.
I have re-checked this:
- without the function, mkimage complains that spkgimage is unknown
- with a function that unconditionally returns 0, it works fine
If it really is meant to work without the function, then a bug must
have crept in elsewhere...
Huh. I did a quick grep so maybe I missed something. IMO this *should*
work without a function, because we have tons of drivers which just
have an equality check. In any case, you can just do
return type == IH_TYPE_RENESAS_SPKG ? 0 : -EINVAL;
It works fine when I use the following for the function:
static int spkgimage_check_image_types(uint8_t type)
{
return 0;
}
However if no function is provided, i.e. U_BOOT_IMAGE_TYPE has
NULL for check_image_type field, then mkimage fails with the error:
tools/mkimage: unsupported type Renesas SPKG Image
Looking at this a bit more, it seems to be due to:
struct image_type_params *imagetool_get_type(int type)
{
...snip...
for (curr = start; curr != end; curr++) {
if ((*curr)->check_image_type) {
if (!(*curr)->check_image_type(type))
return *curr;
}
}
return NULL;
}
So the only way to get non-NULL from imagetool_get_type is for
there to be a callback function, and it must return zero. And
this in turn causes mkimage to bail out quite early in main():
/* set tparams as per input type_id */
tparams = imagetool_get_type(params.type);
if (tparams == NULL && !params.lflag) {
fprintf (stderr, "%s: unsupported type %s\n",
params.cmdname, genimg_get_type_name(params.type));
exit (EXIT_FAILURE);
}
Unless I am missing something, it seems I must provide a function.
-Ralph
PS I will post an updated series (v3) eventually. I'm working on making
changes to the clock driver on the kernel side, to keep it in sync with
the changes you requested in the u-boot side.
Re: [PATCH] arm: ARMv4 assembly compatibility
On Tue, Aug 16, 2022 at 12:17 PM Andre Przywara wrote: > > So what is the story here? This commit seems to suggest U-Boot doesn't support > even ARMv5 without "T", has this changed? There are probably other code > places which would need adjustment to run on ARMv4? Note that gcc 6.0 and later considers armv4 (non-Thumb) support to be deprecated. [1] [2] [1] https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html [2] https://lkml.iu.edu/hypermail/linux/kernel/1712.2/05158.html On Wed, 10 Aug 2022 12:04:46 +0300 Sergei Antonov wrote: > > A working preprocessor-based solution to this problem is found in > arch/arm/lib/relocate.S. Move it to the "ret" macro in > arch/arm/include/asm/assembler.h and change all "bx lr" code > to "ret lr" in functions that may run on ARMv4. Linux source code > deals with this problem in the same manner. Just wanted to point out another option: the linker has a --fix-v4bx flat, which performs the same conversion of "bx lr" to "mov pc lr". Although it is kind of an unusual place for such a transformation, it has the advantage that one does not need to fixup the source code of every piece of code you might like to compile. I used this some years ago [3], and it seems it still works in 2020 [4] [3] http://lists.infradead.org/pipermail/netwinder/2017-August/000267.html [4] https://lists.gnu.org/archive/html/bug-binutils/2020-02/msg00174.html Ralph
Re: [RFC PATCH v2 9/9] tools: spkgimage: add Renesas SPKG format
Hi Sean,
I've implemented most of the suggestions. I will post an updated
series, since it seems that sending v2 of just one patch has confused
patchwork.
However so as not to entirely remove confusion, the updated series
will be v3, since I already used v2 for the one patch. :-P
On Sat, Aug 13, 2022 at 9:45 PM Ralph Siemsen wrote:
> >
> > I wonder if you could just fill in the header directly. This is
> > for a userspace tool, and this struct will be created at most
> > once. It's OK to use 10 bytes :)
>
> I could fill the header directly, but I figured it would be cleaner to
> keep the config file parsing separate from header generation.
Does it seem reasonable to keep these structures separated?
> > > +static int spkgimage_verify_header(unsigned char *ptr, int size,
> > > +struct image_tool_params *param)
> > > +{
> > > + struct spkg_file *file = (struct spkg_file *)ptr;
> > > + struct spkg_hdr *header = (struct spkg_hdr *)ptr;
> > > + char signature[4] = SPKG_HEADER_SIGNATURE;
> >
> > If this naming does not come from documentation, I would suggest
> > something like SPKG_HEADER_MAGIC, since this is not a signature,
> > or even a CRC.
>
> The name does in fact come from the RZ/N1 documentation. However I
> agree that SPKG_HEADER_MAGIC would better reflect what these bytes
> actually are.
Upon checking the documentation, it turns out they use the term
"marker" rather than "signature" for these bytes. So I have switched
the code to match.
> > > +static int spkgimage_check_image_types(uint8_t type)
> > > +{
> > > + return type == IH_TYPE_RENESAS_SPKG ? 0 : 1;
> >
> > This function is not necessary if you only support one type.
>
> Without this function, mkimage kept telling me that my format
> (spkgimage) was not supported, and none of my callbacks got invoked.
> It only complained when trying to generate a header. When listing the
> supported formats, spkgimage showed up correctly.
>
> I'll take another look on Monday, maybe I missed something obvious.
I have re-checked this:
- without the function, mkimage complains that spkgimage is unknown
- with a function that unconditionally returns 0, it works fine
If it really is meant to work without the function, then a bug must
have crept in elsewhere...
Regards,
-Ralph
Re: [PATCH v2 2/2] patman: Add documentation to doc/
Hello Heinrich, FYI, I had some trouble trying to apply your changes (patch seems to be mangled?). Only one small question for you, see below. On Wed, Aug 10, 2022 at 2:42 AM Heinrich Schuchardt wrote: > > diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst > index 52151f6f16..f2e6d7636f 100644 > --- a/tools/patman/patman.rst > +++ b/tools/patman/patman.rst > @@ -1,19 +1,31 @@ > .. SPDX-License-Identifier: GPL-2.0+ > .. Copyright (c) 2011 The Chromium OS Authors > +.. Simon Glass > +.. v1, v2, 19-Oct-11 > +.. revised v3 24-Nov-11 > +.. revised v4 04-Jul-2020, with Patchwork integration > > Patman patch manager > > > This tool is a Python script which: > + > - Creates patch directly from your branch > + > - Cleans them up by removing unwanted tags > + > - Inserts a cover letter with change lists > + > - Runs the patches through checkpatch.pl and its own checks > + > - Optionally emails them out to selected people > > It also has some Patchwork features: > + > - shows review tags from Patchwork so you can update your local patches > + > - pulls these down into a new branch on request > + > - lists comments received on a series > > It is intended to automate patch creation and make it a less > @@ -41,12 +53,15 @@ This tool requires a certain way of working: > > - Maintain a number of branches, one for each patch series you are > working on > + > - Add tags into the commits within each branch to indicate where the > series should be sent, cover letter, version, etc. Most of these are > normally in the top commit so it is easy to change them with 'git > commit --amend' > + > - Each branch tracks the upstream branch, so that this script can > automatically determine the number of commits in it (optional) > + > - Check out a branch, and run this script to create and send out your > patches. Weeks later, change the patches and repeat, knowing that you > will get a consistent result each time. Is it necessary to have a blank line between each of the "bullet" points? It seems to work fine as long as there is one blank line separating the paragraph from the first bullet item. Otherwise, it looks good to me. Ralph
Re: [RFC PATCH v1 3/9] clk: renesas: add R906G032 driver
On Sat, Aug 13, 2022 at 01:30:19AM -0400, Sean Anderson wrote:
+
+ u16 gate, reset, ready, midle,
+ scon, mirack, mistat;
What are the scon/mirack/mistat fields for? You define them for a lot
of clocks, but I don't see them used in the driver.
These came from the Linux driver of the same name. I can only speculate
that in turn, the Linux driver definitions were auto-generated from
vendor provided XML or similar documentation.
I figured that it would be best to match the Linux kernel clock driver.
That way fixes can easily be shared. In fact while doing this work, I
found an error in the clock table [1] and I also made some
simplifications [2].
Regarding the unused fields (scon, mirack, mistat): I am not really sure
what their purpose is. Maybe there is some value in having them. I'll
try to find out more information about them. If we do decide to drop
them, I would like to keep it synchronised with the Linux driver.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2dee50ab9e72a3cae75b65e5934c8dd3e9bf01bc
[2]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f46efcc4746f5c1a539df9db625c04321f75e494
+};
+
+/* This is used to describe a clock for instantiation */
+struct r9a06g032_clkdesc {
+ const char *name;
+ uint32_t managed: 1;
+ uint32_t type: 3;
I wonder if we could define the enum here?
This is still part of the code which I've intentionally kept identical
to the Linux driver. I do agree that moving the enum seems reasonable,
I'll put together a patch for this (and test it) and see if I can get it
accepted on the kernel side.
+ uint32_t index: 8;
+ uint32_t source : 8; /* source index + 1 (0 == none) */
+ /* these are used to populate the bitsel struct */
+ union {
+ struct r9a06g032_gate gate;
+ /* for dividers */
+ struct {
+ unsigned int div_min : 10, div_max : 10, reg: 10;
+ u16 div_table[4];
+ };
+ /* For fixed-factor ones */
+ struct {
+ u16 div, mul;
+ };
+ /* for dual gate */
+ struct {
+ uint16_t group : 1;
+ u16 sel, g1, r1, g2, r2;
+ } dual;
+ };
+};
+
+#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \
+ { .gate = _clk, .reset = _rst, \
If these fields have bitfield inside them, then those bitfields should
be assigned/constructed separately. That is, if .reset is actually a combined
offset/bit, then you need to expose those in the macro. Since you have a lot of
these, you might want to do something like
#define BIT_OFFSET GENMASK(15, 5)
#define BIT_SHIFT GENMASK(4, 0)
#define PACK_BIT(offset, shift) (FIELD_PREP(BIT_OFFSET, offset) |
FIELD_PREP(BIT_SHIFT, shift))
I think it happened before I started working on RZ/N1, but there seemed
to be quite a few iterations on how to represent the clock tree. At one
point there were macros to assign/construct the bitfield values. And
then a different way, and eventually the direct hex values you now see
in the clock tables.
At the risk of re-opening old wounds (luckily not mine) I decided to
just leave this part exactly as-is in the Linux driver.
+
+/* Internal clock IDs */
+#define R9A06G032_CLKOUT 0
+#define R9A06G032_CLKOUT_D10 2
+#define R9A06G032_CLKOUT_D16 3
+#define R9A06G032_CLKOUT_D160 4
[...]
+#define R9A06G032_UART_GROUP_012 154
+#define R9A06G032_UART_GROUP_34567 155
Can you put these in your dt-bindings header? I think that would make it
much clearer why there are gaps, and would avoid someone accidentally
duplicating a clock id (although I suppose your array initializer below
might complain?)
In fact quite a few of them are in the dt-bindings already, see
include/dt-bindings/clock/r9a06g032-sysctrl.h
I'm not really sure why some of these are defined in the .C file while
others are in the dt-bindings header. Like much of the other bits, this
was something I just carried over as-is from the Linux driver.
+ parent->id = ~0; /* Top-level clock */
Can you use a define for this (instead of referring to ~0 everywhere)
Yes, that sounds reasonable. My list of fixes (for both Linux driver and
the u-boot one) is going to get rather long ;-)
+ else
+ parent->id = desc->source - 1;
+
+ parent->dev = clk->dev;
I think you need to clk_request here.
Normally clk_request is called by a driver wishing to use a particular
clock. That is not the case here. This is in a helper function used to
compute the current rate of a given clock. It only looks at the local
table (struct r9a06g032_clkdsc).
+/* register/bit pairs are encoded as an uint16_t */
+static void
+clk_rd
Re: [RFC PATCH v2 9/9] tools: spkgimage: add Renesas SPKG format
On Sat, Aug 13, 2022 at 10:47 AM Sean Anderson wrote:
> >
> > board/schneider/lces/spkgimage.cfg | 26 +++
> > boot/image.c | 1 +
> > include/image.h| 1 +
> > tools/Makefile | 1 +
> > tools/spkgimage.c | 303 +
> > tools/spkgimage.h | 39
>
> Please document your format in doc/mkimage.1
Okay, will be added in the next version.
> > +/* Note: the ordering of the bitfields does not matter */
> > +static struct config_file {
> > + unsigned int version:1;
> > + unsigned int ecc_block_size:2;
> > + unsigned int ecc_enable:1;
> > + unsigned int ecc_scheme:3;
> > + unsigned int ecc_bytes:8;
> > + unsigned int blp_len;
> > + unsigned int padding;
> > +} conf;
>
> I wonder if you could just fill in the header directly. This is
> for a userspace tool, and this struct will be created at most
> once. It's OK to use 10 bytes :)
I could fill the header directly, but I figured it would be cleaner to
keep the config file parsing separate from header generation.
As for the use of bitfields, this was not really about saving space,
but rather a cheap way to ensure the values from the config file do
not exceed their allocated bit-width in the header. The previous
stand-alone code has a somewhat similar construct, from which I
pinched the idea.
>
> > +static int spkgimage_parse_config_line(char *line)
> > +{
> > + char *saveptr;
> > + char *delim = "\t ";
> > + char *name = strtok_r(line, delim, &saveptr);
> > + char *val_str = strtok_r(NULL, delim, &saveptr);
> > + int value = atoi(val_str);
> > +
> > + if (!strcmp("VERSION", name)) {
> > + conf.version = value;
> > + } else if (!strcmp("NAND_ECC_ENABLE", name)) {
> > + conf.ecc_enable = value;
>
> Can you add some checks for the valid range of values? E.g.
> NAND_ECC_SCHEME should be 0 <= value <= 5
Yes, will add some range checks where they make sense. Probably with a
helper function.
> > + } else if (!strcmp("NAND_ECC_BLOCK_SIZE", name)) {
> > + conf.ecc_block_size = value;
> > + } else if (!strcmp("NAND_ECC_SCHEME", name)) {
> > + conf.ecc_scheme = value;
> > + } else if (!strcmp("NAND_BYTES_PER_ECC_BLOCK", name)) {
> > + conf.ecc_bytes = value;
> > + } else if (!strcmp("ADD_DUMMY_BLP", name)) {
> > + conf.blp_len = value ? SPKG_BLP_SIZE : 0;
> > + } else if (!strcmp("PADDING", name)) {
> > + if (strrchr(val_str, 'K'))
> > + conf.padding = value * 1024;
> > + else if (strrchr(val_str, 'M'))
> > + conf.padding = value * 1024 * 1024;
> > + else
> > + conf.padding = value;
> > + } else {
> > + fprintf(stderr, "Error: unknown keyword '%s' in config\n",
> > + name);
>
> perhaps print the line number?
Good idea, will do.
> > + /* Avoid divide-by-zero later on */
> > + if (conf.padding == 0)
>
> if (!conf.padding)
Will do.
> > +static int spkgimage_verify_header(unsigned char *ptr, int size,
> > +struct image_tool_params *param)
> > +{
> > + struct spkg_file *file = (struct spkg_file *)ptr;
> > + struct spkg_hdr *header = (struct spkg_hdr *)ptr;
> > + char signature[4] = SPKG_HEADER_SIGNATURE;
>
> If this naming does not come from documentation, I would suggest
> something like SPKG_HEADER_MAGIC, since this is not a signature,
> or even a CRC.
The name does in fact come from the RZ/N1 documentation. However I
agree that SPKG_HEADER_MAGIC would better reflect what these bytes
actually are.
> > + /*
> > + * mkimage copy_file() pads the input file with zeros.
> > + * Replace those zeros with flash friendly one bits.
> > + * The original version skipped the fist 4 bytes,
>
> nit: first
Well spotted, thanks.
> > +static int spkgimage_check_image_types(uint8_t type)
> > +{
> > + return type == IH_TYPE_RENESAS_SPKG ? 0 : 1;
>
> This function is not necessary if you only support one type.
Without this function, mkimage kept telling me that my format
(spkgimage) was not supported, and none of my callbacks got invoked.
It only complained when trying to generate a header. When listing the
supported formats, spkgimage showed up correctly.
I'll take another look on Monday, maybe I missed something obvious.
> > +#define SPKG_HEADER_SIGNATURE{'R', 'Z', 'N', '1'}
> > +#define SPKG_HEADER_SIZE 24
> > +#define SPKG_HEADER_COUNT8
>
> What are the other 7 headers for? Should you print them out above?
There are 8 identical copies of the 24-byte header. This is meant to
help with NAND booting, where the header is read before ECC settings
are known. The BootROM validates the header CRC and will try up to 8
headers before giving up.
Since they are identical, I only printed va
[RFC PATCH v2 9/9] tools: spkgimage: add Renesas SPKG format
Renesas RZ/N1 devices contain BootROM code that loads a custom SPKG
image from QSPI, NAND or USB DFU. Support this format in mkimage tool.
SPKGs can optionally be signed, however creation of signed SPKG is not
currently supported.
Example of how to use it:
tools/mkimage -n board/schneider/lces/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
---
Changes in v2:
- rewrote the stand-alone spkg_utility to integrate into mkimage
board/schneider/lces/spkgimage.cfg | 26 +++
boot/image.c | 1 +
include/image.h| 1 +
tools/Makefile | 1 +
tools/spkgimage.c | 303 +
tools/spkgimage.h | 39
6 files changed, 371 insertions(+)
create mode 100644 board/schneider/lces/spkgimage.cfg
create mode 100644 tools/spkgimage.c
create mode 100644 tools/spkgimage.h
diff --git a/board/schneider/lces/spkgimage.cfg
b/board/schneider/lces/spkgimage.cfg
new file mode 100644
index 00..b5faf96b00
--- /dev/null
+++ b/board/schneider/lces/spkgimage.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Schneider Electric
+#
+# SPKG image header, for booting on RZ/N1
+
+# b[35:32] SPKG version
+VERSION1
+
+# b[42:41] ECC Block size: 0=256 bytes, 1=512 bytes, 2=1024 bytes
+NAND_ECC_BLOCK_SIZE1
+
+# b[45] NAND enable (boolean)
+NAND_ECC_ENABLE1
+
+# b[50:48] ECC Scheme: 0=BCH2 1=BCH4 2=BCH8 3=BCH16 4=BCH24 5=BCH32
+NAND_ECC_SCHEME3
+
+# b[63:56] ECC bytes per block
+NAND_BYTES_PER_ECC_BLOCK 28
+
+# Provide dummy BLp header (boolean)
+ADD_DUMMY_BLP 1
+
+# Pad the image to a multiple of
+PADDING64K
diff --git a/boot/image.c b/boot/image.c
index 5dcb55ba46..7d50d708ab 100644
--- a/boot/image.c
+++ b/boot/image.c
@@ -179,6 +179,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_COPRO, "copro", "Coprocessor Image"},
{ IH_TYPE_SUNXI_EGON, "sunxi_egon", "Allwinner eGON Boot Image"
},
{ IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image"
},
+ { IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" },
{ -1, "", "", },
};
diff --git a/include/image.h b/include/image.h
index e4c6a50b88..98eaa384f4 100644
--- a/include/image.h
+++ b/include/image.h
@@ -229,6 +229,7 @@ enum {
IH_TYPE_COPRO, /* Coprocessor Image for remoteproc*/
IH_TYPE_SUNXI_EGON, /* Allwinner eGON Boot Image */
IH_TYPE_SUNXI_TOC0, /* Allwinner TOC0 Boot Image */
+ IH_TYPE_RENESAS_SPKG, /* Renesas SPKG image */
IH_TYPE_COUNT, /* Number of image types */
};
diff --git a/tools/Makefile b/tools/Makefile
index 005e7362a3..7e24f3ecb9 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -131,6 +131,7 @@ dumpimage-mkimage-objs := aisimage.o \
stm32image.o \
$(ROCKCHIP_OBS) \
socfpgaimage.o \
+ spkgimage.o \
sunxi_egon.o \
lib/crc16-ccitt.o \
lib/hash-checksum.o \
diff --git a/tools/spkgimage.c b/tools/spkgimage.c
new file mode 100644
index 00..2e8c17d94a
--- /dev/null
+++ b/tools/spkgimage.c
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Generate Renesas RZ/N1 BootROM header (SPKG)
+ * (C) Copyright 2022 Schneider Electric
+ *
+ * Based on spkg_utility.c
+ * (C) Copyright 2016 Renesas Electronics Europe Ltd
+ */
+
+#include "imagetool.h"
+#include
+#include
+#include
+#include
+#include
+#include "spkgimage.h"
+
+static struct spkg_file out_buf;
+
+static uint32_t padding;
+
+/* Note: the ordering of the bitfields does not matter */
+static struct config_file {
+ unsigned int version:1;
+ unsigned int ecc_block_size:2;
+ unsigned int ecc_enable:1;
+ unsigned int ecc_scheme:3;
+ unsigned int ecc_bytes:8;
+ unsigned int blp_len;
+ unsigned int padding;
+} conf;
+
+static int spkgimage_parse_config_line(char *line)
+{
+ char *saveptr;
+ char *delim = "\t ";
+ char *name = strtok_r(line, delim, &saveptr);
+ char *val_str = strtok_r(NULL, delim, &saveptr);
+ int value = atoi(val_str);
+
+ if (!strcmp("VERSION", name)) {
+ conf.version = value;
+ } else if (!strcmp("NAND_ECC_ENABLE", name)) {
+ conf.ecc_enable = val
Re: [RFC PATCH v1 9/9] tools: Add tool to create Renesas SPKG images
On Tue, Aug 9, 2022 at 1:15 PM Sean Anderson wrote: > > The traditional way to handle this is to specify a config file with -n. > See e.g. mtk_image Thanks Pali and Sean. I have converted this tool to work as part of mkimage, with a config file for the extra parameters. Patch v2 to follow. Ralph
Re: [RFC PATCH v1 9/9] tools: Add tool to create Renesas SPKG images
On Tue, Aug 9, 2022 at 12:07 PM Pali Rohár wrote: > > This documentation is not probably up-to-date. List of all kwbimage > config options can be visible in kwbimage_generate_config() function. I will check the code as well. > > 1) mkimage already has far too many options > > I know. But for nand there can be just --nand suboption1,suboption2,... > format. For other non-nand vendor specific option it would be an issue. > Maybe something like --vendor option or --image-options ... could be > used? In my case this would work, as there are only 3 parameters for NAND. However in general, it could get pretty messy, I see at least ten different NAND parameters described in the NAND DT binding. > > 2) covering all possible vendor-specific values/encodings of NAND > > parameters would be quite a task > > Yea, it is problematic. But... is not everything related to NAND just > common to what can be specified in device tree properties for nand node? > And de-facto already known and well-defined? I did have the thought of using device tree. It does have the advantage that it is a known format with defined parameters. > Because I cannot imagine what else for what there is not already device > tree binding, could be required for vendor bootrom. (But maybe I just do > not see it...) In quite a few cases, the DT parameters are incomplete, or just hints (see "nand-ecc-maximize"), that trigger various run-time decisions about the actual parameters. Duplicating this logic in mkimage seems difficult, bordering on impossible if it depends on run-time identification of the flash chip, for example. > Just one suggestion: It is a good idea to also implement "verify_header" > mkimage callback. Build process then use it to verify that generated > image is really correct. I'll check it out, thanks! Ralph
Re: [RFC PATCH v1 9/9] tools: Add tool to create Renesas SPKG images
Hi Pali, On Tuesday 09 August 2022 15:03:48 Pali Rohár wrote: > > Hello! You can use for example config file, like it has kwbimage.c which > is integrated into mkimage and has support for NAND ECC settings. Thank you, I was unaware of this config file approach. From a quick look at doc/README.kwbimage it seems quite reasonable for device-specific parameters. On Tue, Aug 9, 2022 at 9:07 AM Pali Rohár wrote: > > Or another option could be to extend mkimage tool to accept new argument > for specifying NAND settings. As we can see more image formats have > support for it, so some abstraction in mkimage makes sense here. In principle I agree. But practically speaking I see two problems: 1) mkimage already has far too many options 2) covering all possible vendor-specific values/encodings of NAND parameters would be quite a task So I am inclined to keep it simple for now, and try using a config file. Ralph
[RFC PATCH v1 8/9] board: schneider: add LCES board support
Add support for Schneider Electronics LCES1 / LCES2 boards, which are
based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
TODO: remove the debug UART settings from lces_defconfig.
arch/arm/dts/r9a06g032-rzn1d400-lces.dts | 50 +++
arch/arm/mach-rzn1/Kconfig| 14 +
board/schneider/lces/Kconfig | 12 +
board/schneider/lces/Makefile | 3 +
board/schneider/lces/ddr_timing.c | 140 ++
.../lces/jedec_ddr3_2g_x16_1333h_500_cl8.h| 399 ++
board/schneider/lces/lces.c | 41 ++
configs/lces_defconfig| 26 ++
include/configs/lces.h| 22 +
9 files changed, 707 insertions(+)
create mode 100644 arch/arm/dts/r9a06g032-rzn1d400-lces.dts
create mode 100644 board/schneider/lces/Kconfig
create mode 100644 board/schneider/lces/Makefile
create mode 100644 board/schneider/lces/ddr_timing.c
create mode 100644 board/schneider/lces/jedec_ddr3_2g_x16_1333h_500_cl8.h
create mode 100644 board/schneider/lces/lces.c
create mode 100644 configs/lces_defconfig
create mode 100644 include/configs/lces.h
diff --git a/arch/arm/dts/r9a06g032-rzn1d400-lces.dts
b/arch/arm/dts/r9a06g032-rzn1d400-lces.dts
new file mode 100644
index 00..7ba4dedc10
--- /dev/null
+++ b/arch/arm/dts/r9a06g032-rzn1d400-lces.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for Schneider LCES Board
+ *
+ * Based on r9a06g032-rzn1d400-db.dts
+ */
+
+/dts-v1/;
+
+#include "r9a06g032.dtsi"
+#include
+
+/ {
+ model = "Schneider LCES Board";
+ compatible = "schneider,rzn1d400-lces", "renesas,r9a06g032";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ /* TODO: (RFS) only RZN1D has DDR */
+ memory {
+ device_type = "memory";
+ reg = <0x8000 0x1000>;
+ };
+};
+
+&ddrctrl {
+ status = "okay";
+};
+&pinctrl {
+ status = "okay";
+
+ pins_uart0: pins_uart0 {
+ pinmux = <
+ RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /*
UART0_TXD */
+ RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /*
UART0_RXD */
+ >;
+ bias-disable;
+ };
+};
+&uart0 {
+ pinctrl-0 = <&pins_uart0>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm/mach-rzn1/Kconfig b/arch/arm/mach-rzn1/Kconfig
index 707895874d..9bbafeb6db 100644
--- a/arch/arm/mach-rzn1/Kconfig
+++ b/arch/arm/mach-rzn1/Kconfig
@@ -15,4 +15,18 @@ endchoice
config SYS_SOC
default "rzn1"
+choice
+ prompt "Board select"
+ default TARGET_SCHNEIDER_LCES
+
+config TARGET_SCHNEIDER_LCES
+ bool "Schneider LCES board"
+ help
+ Support the Schneider LCES1 and LCES2 boards, which are based
+ on the Renesas RZ/N1 SoC.
+
+endchoice
+
+source "board/schneider/lces/Kconfig"
+
endif
diff --git a/board/schneider/lces/Kconfig b/board/schneider/lces/Kconfig
new file mode 100644
index 00..6a1448bbd7
--- /dev/null
+++ b/board/schneider/lces/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SCHNEIDER_LCES
+
+config SYS_BOARD
+ default "lces"
+
+config SYS_VENDOR
+ default "schneider"
+
+config SYS_CONFIG_NAME
+ default "lces"
+
+endif
diff --git a/board/schneider/lces/Makefile b/board/schneider/lces/Makefile
new file mode 100644
index 00..b8f6a8f53f
--- /dev/null
+++ b/board/schneider/lces/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := lces.o ddr_timing.o
diff --git a/board/schneider/lces/ddr_timing.c
b/board/schneider/lces/ddr_timing.c
new file mode 100644
index 00..8bc3fe7be4
--- /dev/null
+++ b/board/schneider/lces/ddr_timing.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include
+
+#include "jedec_ddr3_2g_x16_1333h_500_cl8.h"
+
+u32 ddr_00_87_async[] = {
+ DENALI_CTL_00_DATA,
+ DENALI_CTL_01_DATA,
+ DENALI_CTL_02_DATA,
+ DENALI_CTL_03_DATA,
+ DENALI_CTL_04_DATA,
+ DENALI_CTL_05_DATA,
+ DENALI_CTL_06_DATA,
+ DENALI_CTL_07_DATA,
+ DENALI_CTL_08_DATA,
+ DENALI_CTL_09_DATA,
+
+ DENALI_CTL_10_DATA,
+ DENALI_CTL_11_DATA,
+ DENALI_CTL_12_DATA,
+ DENALI_CTL_13_DATA,
+ DENALI_CTL_14_DATA,
+ DENALI_CTL_15_DATA,
+ DENALI_CTL_16_DATA,
+ DENALI_CTL_17_DATA,
+ DENALI_CTL_18_DATA,
+ DENALI_CTL_19_DATA,
+
+ DENALI_CTL_20_DATA,
+
