[PATCH v5 11/11] board: starfive: Dynamic configuration of DT for 1.2A and 1.3B
The main difference between StarFive VisionFive 2 1.2A and 1.3B is gmac.
You can read the PCB version of the current board by
get_pcb_revision_from_eeprom(), and then dynamically configure the
difference of gmac in spl_perform_fixups() according to different PCB
versions, so that one DT and one defconfig can support both 1.2A and
1.3B versions, which is more user-friendly.
Signed-off-by: Yanhong Wang
---
board/starfive/visionfive2/spl.c | 157 +++
1 file changed, 157 insertions(+)
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index db0b4cb433..7acd3995aa 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -5,16 +5,173 @@
*/
#include
+#include
#include
#include
#include
+#include
+#include
+#include
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
#define JH7110_CLK_CPU_ROOT_SHIFT 24
#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
+struct starfive_vf2_pro {
+ const char *path;
+ const char *name;
+ const char *value;
+};
+
+static const struct starfive_vf2_pro starfive_vera[] = {
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0", "rx-internal-delay-ps",
+ "1900"},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0", "tx-internal-delay-ps",
+ "1350"}
+};
+
+static const struct starfive_vf2_pro starfive_verb[] = {
+ {"/soc/ethernet@1603", "starfive,tx-use-rgmii-clk", NULL},
+ {"/soc/ethernet@1604", "starfive,tx-use-rgmii-clk", NULL},
+
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-1000-inverted", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "rx-internal-delay-ps", "1900"},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "tx-internal-delay-ps", "1500"},
+
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ { "/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "rx-internal-delay-ps", "0"},
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "tx-internal-delay-ps", "0"},
+};
+
+void spl_fdt_fixup_version_a(void *fdt)
+{
+ u32 phandle;
+ u8 i;
+ int offset;
+ int ret;
+
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+ "StarFive VisionFive 2 v1.2A");
+
+ offset = fdt_path_offset(fdt, "/soc/clock-controller@1302");
+ phandle = fdt_get_phandle(fdt, offset);
+ offset = fdt_path_offset(fdt, "/soc/ethernet@1604");
+
+ fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks",
JH7110_SYSCLK_GMAC1_TX);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks",
JH7110_SYSCLK_GMAC1_RX);
+
+ fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_SYSCLK_GMAC1_RMII_RTX);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_SYSCLK_GMAC1_RMII_RTX);
+
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@1604"),
+ "phy-mode", "rmii");
+
+ for (i = 0; i < ARRAY_SIZE(starfive_vera); i++) {
+ offset = fdt_path_offset(fdt, starfive_vera[i].path);
+
+ if (starfive_vera[i].value)
+ ret = fdt_setprop_u32(fdt, offset,
starfive_vera[i].name,
+ dectoul(starfive_vera[i].value,
NULL));
+ else
+ ret = fdt_setprop_empty(fdt, offset,
starfive_vera[i].name);
+
+ if (ret) {
+ pr_err("%s set prop %s fail.\n", __func__,
starfive_vera[i].name);
+
[PATCH v5 10/11] ram: starfive: Read memory size information from EEPROM
StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of
DDR capacity includes 2G/4G/8G, a DT can not support multiple
capacities, so the capacity size information is recorded to EEPROM, when
DDR initialization required capacity size information is read from
EEPROM.
If there is no information in EEPROM, it is initialized with the default
size defined in DT.
Signed-off-by: Yanhong Wang
---
arch/riscv/cpu/jh7110/spl.c | 32 -
drivers/ram/starfive/starfive_ddr.c | 2 --
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 104f0fe949..72adcefa0e 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -3,19 +3,49 @@
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Author: Yanhong Wang
*/
-
+#include
+#include
#include
#include
#include
+#include
#include
+#include
#define CSR_U74_FEATURE_DISABLE0x7c1
#define L2_LIM_MEM_END 0x81FUL
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool check_ddr_size(phys_size_t size)
+{
+ switch (size) {
+ case SZ_2:
+ case SZ_4:
+ case SZ_8:
+ case SZ_16:
+ return true;
+ default:
+ return false;
+ }
+}
+
int spl_soc_init(void)
{
int ret;
struct udevice *dev;
+ phys_size_t size;
+
+ ret = fdtdec_setup_mem_size_base();
+ if (ret)
+ return ret;
+
+ /* Read the definition of the DDR size from eeprom, and if not,
+* use the definition in DT
+*/
+ size = (get_ddr_size_from_eeprom() >> 16) & 0xFF;
+ if (check_ddr_size(size))
+ gd->ram_size = size << 30;
/* DDR init */
ret = uclass_get_device(UCLASS_RAM, 0, );
diff --git a/drivers/ram/starfive/starfive_ddr.c
b/drivers/ram/starfive/starfive_ddr.c
index 553f2ce6f4..a0a3d6b33d 100644
--- a/drivers/ram/starfive/starfive_ddr.c
+++ b/drivers/ram/starfive/starfive_ddr.c
@@ -72,8 +72,6 @@ static int starfive_ddr_probe(struct udevice *dev)
u64 rate;
int ret;
- /* Read memory base and size from DT */
- fdtdec_setup_mem_size_base();
priv->info.base = gd->ram_base;
priv->info.size = gd->ram_size;
--
2.17.1
[PATCH v5 08/11] riscv: dts: starfive: Add support eeprom device tree node
Add support "atmel,24c04" eeprom for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
.../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 14 ++
arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 6 ++
2 files changed, 20 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 2afcec30b8..13f69da31e 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -67,6 +67,20 @@
};
};
+_pins {
+ bootph-pre-ram;
+ i2c-pins {
+ bootph-pre-ram;
+ };
+};
+
+ {
+ bootph-pre-ram;
+ eeprom@50 {
+ bootph-pre-ram;
+ };
+};
+
{
itb {
fit {
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index 3c1148ae2d..710b082766 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -120,6 +120,12 @@
pinctrl-names = "default";
pinctrl-0 = <_pins>;
status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
};
{
--
2.17.1
[PATCH v5 09/11] configs: starfive: Enable ID EEPROM configuration
Enabled ID_EEPROM and I2C configuration for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
.../visionfive2/starfive_visionfive2.c| 13 +
configs/starfive_visionfive2_defconfig| 19 ++-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c
b/board/starfive/visionfive2/starfive_visionfive2.c
index 613fe793c4..07dcca26b3 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -6,7 +6,9 @@
#include
#include
+#include
#include
+#include
#include
#define JH7110_L2_PREFETCHER_BASE_ADDR 0x203
@@ -38,3 +40,14 @@ int board_init(void)
return 0;
}
+
+void *board_fdt_blob_setup(int *err)
+{
+ *err = 0;
+ if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
+ if (gd->arch.firmware_fdt_addr)
+ return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
+ }
+
+ return (ulong *)&_end;
+}
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
index c57708199d..570a1f53a1 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="StarFive #"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x818
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -23,6 +24,7 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
+# CONFIG_OF_BOARD_FIXUP is not set
CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_BOOT=y
@@ -34,6 +36,8 @@ CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr
${fdtcontroladdr};"
CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_ID_EEPROM=y
+CONFIG_SYS_EEPROM_BUS_NUM=5
CONFIG_SPL_MAX_SIZE=0x4
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_BSS_START_ADDR=0x804
@@ -45,21 +49,34 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8000
CONFIG_SYS_SPL_MALLOC_SIZE=0x40
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
+CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_SIZE=512
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_TFTPPUT=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_JH7110=y
-# CONFIG_I2C is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0X50
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
--
2.17.1
[PATCH v5 07/11] eeprom: starfive: Enable ID EEPROM configuration
Enabled ID_EEPROM configuration for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
arch/riscv/include/asm/arch-jh7110/eeprom.h | 13 +
board/starfive/visionfive2/Makefile | 1 +
.../visionfive2/visionfive2-i2c-eeprom.c | 561 ++
3 files changed, 575 insertions(+)
create mode 100644 arch/riscv/include/asm/arch-jh7110/eeprom.h
create mode 100644 board/starfive/visionfive2/visionfive2-i2c-eeprom.c
diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h
b/arch/riscv/include/asm/arch-jh7110/eeprom.h
new file mode 100644
index 00..f354d5c60c
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#ifndef _ASM_RISCV_EEPROM_H
+#define _ASM_RISCV_EEPROM_H
+
+u8 get_pcb_revision_from_eeprom(void);
+u32 get_ddr_size_from_eeprom(void);
+
+#endif /* _ASM_RISCV_EEPROM_H */
diff --git a/board/starfive/visionfive2/Makefile
b/board/starfive/visionfive2/Makefile
index 66c854df39..c7ba4f7ed6 100644
--- a/board/starfive/visionfive2/Makefile
+++ b/board/starfive/visionfive2/Makefile
@@ -5,3 +5,4 @@
obj-y := starfive_visionfive2.o
obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_ID_EEPROM) += visionfive2-i2c-eeprom.o
diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
new file mode 100644
index 00..befe7888c4
--- /dev/null
+++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
@@ -0,0 +1,561 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define FORMAT_VERSION 0x2
+#define PCB_VERSION0xB1
+#define BOM_VERSION'A'
+/*
+ * BYTES_PER_EEPROM_PAGE: the 24FC04H datasheet says that data can
+ * only be written in page mode, which means 16 bytes at a time:
+ * 16-Byte Page Write Buffer
+ */
+#define BYTES_PER_EEPROM_PAGE 16
+
+/*
+ * EEPROM_WRITE_DELAY_MS: the 24FC04H datasheet says it takes up to
+ * 5ms to complete a given write:
+ * Write Cycle Time (byte or page) ro Page Write Time 5 ms, Maximum
+ */
+#define EEPROM_WRITE_DELAY_MS 5000
+/*
+ * StarFive OUI. Registration Date is 20xx-xx-xx
+ */
+#define STARFIVE_OUI_PREFIX"6C:CF:39:"
+#define STARFIVE_DEFAULT_MAC0 "6C:CF:39:6C:DE:AD"
+#define STARFIVE_DEFAULT_MAC1 "6C:CF:39:6C:DE:AE"
+
+/* Magic number at the first four bytes of EEPROM HATs */
+#define STARFIVE_EEPROM_HATS_SIG "SFVF" /* StarFive VisionFive */
+
+#define STARFIVE_EEPROM_HATS_SIZE_MAX 256 /* Header + Atom1&4(v1) */
+#define STARFIVE_EEPROM_WP_OFFSET 0 /* Read only field */
+#define STARFIVE_EEPROM_ATOM1_PSTR "VF7110A1-2228-D008E000-0001\0"
+#define STARFIVE_EEPROM_ATOM1_PSTR_SIZE32
+#define STARFIVE_EEPROM_ATOM1_SN_OFFSET23
+#define STARFIVE_EEPROM_ATOM1_VSTR "StarFive Technology Co., Ltd.\0\0\0"
+#define STARFIVE_EEPROM_ATOM1_VSTR_SIZE32
+
+#define MAGIC_NUMBER_BYTES 4
+#define MAC_ADDR_BYTES 6
+#define MAC_ADDR_STRLEN17
+
+/*
+ * Atom Types
+ * 0x = invalid
+ * 0x0001 = vendor info
+ * 0x0002 = GPIO map
+ * 0x0003 = Linux device tree blob
+ * 0x0004 = manufacturer custom data
+ * 0x0005-0xfffe = reserved for future use
+ * 0x = invalid
+ */
+
+#define HATS_ATOM_INVALID 0x
+#define HATS_ATOM_VENDOR 0x0001
+#define HATS_ATOM_GPIO 0x0002
+#define HATS_ATOM_DTB 0x0003
+#define HATS_ATOM_CUSTOM 0x0004
+#define HATS_ATOM_INVALID_END 0x
+
+struct eeprom_header {
+ char signature[MAGIC_NUMBER_BYTES]; /* ASCII table signature */
+ u8 version; /* EEPROM data format version */
+ /* (0x00 reserved, 0x01 = first version) */
+ u8 reversed;/* 0x00, Reserved field */
+ u16 numatoms; /* total atoms in EEPROM */
+ u32 eeplen; /* total length in bytes of all eeprom data */
+ /* (including this header) */
+};
+
+struct eeprom_atom_header {
+ u16 type;
+ u16 count;
+ u32 dlen;
+};
+
+struct eeprom_atom1_data {
+ u8 uuid[16];
+ u16 pid;
+ u16 pver;
+ u8 vslen;
+ u8 pslen;
+ uchar vstr[STARFIVE_EEPROM_ATOM1_VSTR_SIZE];
+ uchar pstr[STARFIVE_EEPROM_ATOM1_PSTR_SIZE]; /* product SN */
+};
+
+struct starfive_eeprom_atom1 {
+ struct eeprom_atom_header header;
+ struct eeprom_atom1_data data;
+ u16 crc;
+};
+
+struct eeprom_atom4_data {
+ u16 version;
+ u8 pcb_revision;/* PCB version */
+ u8 bom_revision;/* BOM version */
+ u8 mac0_addr[MAC_ADDR_B
[PATCH v5 05/11] doc: board: starfive: Reword the make defconfig information
The defconfig file name for StarFive VisionFive2 has been changed, and
the documentation description has also changed.
Signed-off-by: Yanhong Wang
---
doc/board/starfive/visionfive2.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/doc/board/starfive/visionfive2.rst
b/doc/board/starfive/visionfive2.rst
index 4d43ac9729..951e0d80fb 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -62,7 +62,7 @@ Now build the U-Boot SPL and U-Boot proper
.. code-block:: console
cd
- make starfive_visionfive2_13b_defconfig
+ make starfive_visionfive2_defconfig
make
OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
@@ -118,7 +118,7 @@ Program the SD card
sudo cp u-boot.itb /mnt/
sudo cp Image.gz /mnt/
sudo cp initramfs.cpio.gz /mnt/
- sudo cp jh7110-starfive-visionfive-2-v1.3b.dtb /mnt/
+ sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
sudo umount /mnt
Booting
@@ -264,7 +264,7 @@ Sample boot log from StarFive VisionFive2 board
StarFive #fatload mmc 1:3 ${kernel_addr_r} Image.gz
6429424 bytes read in 394 ms (15.6 MiB/s)
- StarFive #fatload mmc 1:3 ${fdt_addr_r}
jh7110-starfive-visionfive-2-v1.3b.dtb
+ StarFive #fatload mmc 1:3 ${fdt_addr_r} jh7110-starfive-visionfive-2.dtb
11285 bytes read in 5 ms (2.2 MiB/s)
StarFive #fatload mmc 1:3 ${ramdisk_addr_r} initramfs.cpio.gz
152848495 bytes read in 9271 ms (15.7 MiB/s)
--
2.17.1
[PATCH v5 06/11] configs: starfive: Enable ethernet configuration for StarFive VisionFive2
Enable DWC_ETH_QOS and PHY_MOTORCOMM configuration to support ethernet function for StarFive VisionFive 2 board,including versions 1.2A and 1.3B. Signed-off-by: Yanhong Wang --- configs/starfive_visionfive2_defconfig | 9 + 1 file changed, 9 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 566d2c3d0e..c57708199d 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -54,6 +54,8 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_MEMINFO=y CONFIG_CMD_TFTPPUT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_JH7110=y @@ -66,6 +68,13 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_STARFIVE=y +CONFIG_RGMII=y +CONFIG_RMII=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y -- 2.17.1
[PATCH v5 02/11] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.
Signed-off-by: Yanhong Wang
Reviewed-by: Ramon Fried
---
drivers/net/Kconfig| 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c | 249 +
5 files changed, 264 insertions(+)
create mode 100644 drivers/net/dwc_eth_qos_starfive.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 09039a283e..5540f0ea18 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -249,6 +249,13 @@ config DWC_ETH_QOS_QCOM
The Synopsys Designware Ethernet QOS IP block with specific
configuration used in Qcom QCS404 SoC.
+config DWC_ETH_QOS_STARFIVE
+ bool "Synopsys DWC Ethernet QOS device support for STARFIVE"
+ depends on DWC_ETH_QOS
+ help
+ The Synopsys Designware Ethernet QOS IP block with specific
+ configuration used in STARFIVE JH7110 soc.
+
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 46a40e2ed9..d4af253b6f 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
+obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9bbba6eed0..1e92bd9ca9 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1725,6 +1725,12 @@ static const struct udevice_id eqos_ids[] = {
.data = (ulong)_qcom_config
},
#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
+ {
+ .compatible = "starfive,jh7110-dwmac",
+ .data = (ulong)_jh7110_config
+ },
+#endif
{ }
};
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index fddbe9336c..a6b719af80 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -289,3 +289,4 @@ int eqos_null_ops(struct udevice *dev);
extern struct eqos_config eqos_imx_config;
extern struct eqos_config eqos_qcom_config;
+extern struct eqos_config eqos_jh7110_config;
diff --git a/drivers/net/dwc_eth_qos_starfive.c
b/drivers/net/dwc_eth_qos_starfive.c
new file mode 100644
index 00..5be8ac0f1a
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_starfive.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dwc_eth_qos.h"
+
+#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
+#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
+#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
+
+struct starfive_platform_data {
+ struct regmap *regmap;
+ struct reset_ctl_bulk resets;
+ struct clk_bulk clks;
+ phy_interface_t interface;
+ u32 offset;
+ u32 shift;
+ bool tx_use_rgmii_clk;
+};
+
+static int eqos_interface_init_jh7110(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data = pdata->priv_pdata;
+ struct ofnode_phandle_args args;
+ unsigned int mode;
+ int ret;
+
+ switch (data->interface) {
+ case PHY_INTERFACE_MODE_RMII:
+ mode = STARFIVE_DWMAC_PHY_INFT_RMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
+2, 0, );
+ if (ret)
+ return ret;
+
+ if (args.args_count != 2)
+ return -EINVAL;
+
+ data->offset = args.args[0];
+ data->shift = args.args[1];
+ data->regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
+ if (IS_ERR(data->regmap)) {
+ ret = PTR_ERR(data->regmap);
+ pr_err("Failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ return regmap_update_bits(data->regmap, data->offset,
+ STARFIVE_DWMAC_PHY_INFT_FIELD << data->shift,
+ mode << data->shift);
+}
+
+static int eqos_set_tx_clk_speed_jh7110(struct
[PATCH v5 04/11] riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B
The difference between 1.2A and 1.3B is dynamically configured according
to the PCB version, and there is no difference on the board device tree,
so the same DT file can be used.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/Makefile | 3 +-
... jh7110-starfive-visionfive-2-u-boot.dtsi} | 25 ++-
.../jh7110-starfive-visionfive-2-v1.2a.dts| 12
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 ---
...b.dts => jh7110-starfive-visionfive-2.dts} | 3 +-
configs/starfive_visionfive2_defconfig| 4 +-
6 files changed, 28 insertions(+), 88 deletions(-)
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi =>
jh7110-starfive-visionfive-2-u-boot.dtsi} (66%)
delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
delete mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts =>
jh7110-starfive-visionfive-2.dts} (65%)
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 79a58694f5..7940fe466d 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,8 +7,7 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.3b.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.2a.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
similarity index 66%
rename from arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
rename to arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 3c322c5c97..2afcec30b8 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
*/
#include "binman.dtsi"
@@ -67,3 +67,26 @@
};
};
+ {
+ itb {
+ fit {
+ images {
+ fdt-1 {
+ description = "NAME";
+ load = <0x4040>;
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ conf-1 {
+ fdt = "fdt-1";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
deleted file mode 100644
index b9d26d7af7..00
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-/dts-v1/;
-#include "jh7110-starfive-visionfive-2.dtsi"
-
-/ {
- model = "StarFive VisionFive 2 v1.2A";
- compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
-};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
deleted file mode 100644
index 3c322c5c97..00
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-#include "binman.dtsi"
-#include "jh7110-u-boot.dtsi"
-/ {
- chosen {
- bootph-pre-ram;
- };
-
- firmware {
- spi0 =
- bootph-pre-ram;
- };
-
- config {
- bootph-pre-ram;
- u-boot,spl-payload-offset = <0x10>;
- };
-
- memory@4000 {
- bootph-pre-ram;
- };
-};
-
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-
- nor-flash@0 {
- bootph-pre-ram;
- };
-};
-
- {
- bootph-pre-ram;
-};
-
-_pins {
- bootph-pre
[PATCH v5 03/11] riscv: dts: jh7110: Add ethernet device tree nodes
Add ethernet device tree node to support StarFive ethernet driver for
the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
---
.../dts/jh7110-starfive-visionfive-2.dtsi | 34 +
arch/riscv/dts/jh7110.dtsi| 69 +++
2 files changed, 103 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..3c1148ae2d 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -17,6 +17,8 @@
i2c2 =
i2c5 =
i2c6 =
+ ethernet0 =
+ ethernet1 =
};
chosen {
@@ -317,3 +319,35 @@
assigned-clock-parents = <>;
assigned-clock-rates = <0>;
};
+
+ {
+ phy-handle = <>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+ {
+ phy-handle = <>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+ };
+};
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..58e332e9d7 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -235,6 +235,13 @@
#clock-cells = <0>;
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,lpi_en;
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <4>;
+ snps,blen = <256 128 64 32 0 0 0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -539,6 +546,68 @@
status = "disabled";
};
+ gmac0: ethernet@1603 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x1603 0x0 0x1>;
+ clocks = < JH7110_AONCLK_GMAC0_AXI>,
+< JH7110_AONCLK_GMAC0_AHB>,
+< JH7110_SYSCLK_GMAC0_PTP>,
+< JH7110_AONCLK_GMAC0_TX_INV>,
+< JH7110_SYSCLK_GMAC0_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = < JH7110_AONRST_GMAC0_AXI>,
+< JH7110_AONRST_GMAC0_AHB>;
+ reset-names = "stmmaceth", "ahb";
+ interrupts = <7>, <6>, <5>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <8>;
+ rx-fifo-depth = <2048>;
+ tx-fifo-depth = <2048>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <_axi_setup>;
+ snps,tso;
+ snps,en-tx-lpi-clockgating;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ starfive,syscon = <_syscon 0xc 0x12>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@1604 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x1604 0x0 0x1>;
+ clocks = < JH7110_SYSCLK_GMAC1_AXI>,
+< JH7110_SYSCLK_GMAC1_AHB>,
+< JH7110_SYSCLK_GMAC1_PTP>,
+< JH7110_SYSCLK_GMAC1_TX_INV>,
+< JH7110_SYSCLK_GMAC1_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = < JH7110_SYSRST_GMAC1_AXI>,
+
[PATCH v5 01/11] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have verified the driver on StarFive VisionFive2 board. Signed-off-by: Yanhong Wang Reviewed-by: Ramon Fried --- drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile| 1 + drivers/net/phy/motorcomm.c | 437 3 files changed, 444 insertions(+) create mode 100644 drivers/net/phy/motorcomm.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 24158776f5..0c3c39a550 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -220,6 +220,12 @@ config PHY_MICREL_KSZ8XXX endif # PHY_MICREL +config PHY_MOTORCOMM + tristate "Motorcomm PHYs" + help + Enables support for Motorcomm network PHYs. + Currently supports the YT8531 Gigabit Ethernet PHYs. + config PHY_MSCC bool "Microsemi Corp Ethernet PHYs support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 85d17f109c..2487f366e1 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o +obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c new file mode 100644 index 00..e822fd76f2 --- /dev/null +++ b/drivers/net/phy/motorcomm.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Motorcomm 8531 PHY driver. + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include + +#define PHY_ID_YT8531 0x4f51e91b +#define PHY_ID_MASKGENMASK(31, 0) + +/* Extended Register's Address Offset Register */ +#define YTPHY_PAGE_SELECT 0x1E + +/* Extended Register's Data Register */ +#define YTPHY_PAGE_DATA0x1F + +#define YTPHY_SYNCE_CFG_REG0xA012 + +#define YTPHY_DTS_OUTPUT_CLK_DIS 0 +#define YTPHY_DTS_OUTPUT_CLK_25M 2500 +#define YTPHY_DTS_OUTPUT_CLK_125M 12500 + +#define YT8531_SCR_SYNCE_ENABLEBIT(6) +/* 1b0 output 25m clock *default* + * 1b1 output 125m clock + */ +#define YT8531_SCR_CLK_FRE_SEL_125MBIT(4) +#define YT8531_SCR_CLK_SRC_MASKGENMASK(3, 1) +#define YT8531_SCR_CLK_SRC_PLL_125M0 +#define YT8531_SCR_CLK_SRC_UTP_RX 1 +#define YT8531_SCR_CLK_SRC_SDS_RX 2 +#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 +#define YT8531_SCR_CLK_SRC_REF_25M 4 +#define YT8531_SCR_CLK_SRC_SSC_25M 5 + +/* 1b0 use original tx_clk_rgmii *default* + * 1b1 use inverted tx_clk_rgmii. + */ +#define YT8531_RC1R_TX_CLK_SEL_INVERTEDBIT(14) +#define YT8531_RC1R_RX_DELAY_MASK GENMASK(13, 10) +#define YT8531_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) +#define YT8531_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) +#define YT8531_RC1R_RGMII_0_000_NS 0 +#define YT8531_RC1R_RGMII_0_150_NS 1 +#define YT8531_RC1R_RGMII_0_300_NS 2 +#define YT8531_RC1R_RGMII_0_450_NS 3 +#define YT8531_RC1R_RGMII_0_600_NS 4 +#define YT8531_RC1R_RGMII_0_750_NS 5 +#define YT8531_RC1R_RGMII_0_900_NS 6 +#define YT8531_RC1R_RGMII_1_050_NS 7 +#define YT8531_RC1R_RGMII_1_200_NS 8 +#define YT8531_RC1R_RGMII_1_350_NS 9 +#define YT8531_RC1R_RGMII_1_500_NS 10 +#define YT8531_RC1R_RGMII_1_650_NS 11 +#define YT8531_RC1R_RGMII_1_800_NS 12 +#define YT8531_RC1R_RGMII_1_950_NS 13 +#define YT8531_RC1R_RGMII_2_100_NS 14 +#define YT8531_RC1R_RGMII_2_250_NS 15 + +/* Phy gmii clock gating Register */ +#define YT8531_CLOCK_GATING_REG0xC +#define YT8531_CGR_RX_CLK_EN BIT(12) + +/* Specific Status Register */ +#define YTPHY_SPECIFIC_STATUS_REG 0x11 +#define YTPHY_DUPLEX_MASK BIT(13) +#define YTPHY_DUPLEX_SHIFT 13 +#define YTPHY_SPEED_MODE_MASK GENMASK(15, 14) +#define YTPHY_SPEED_MODE_SHIFT 14 + +#define YT8531_EXTREG_SLEEP_CONTROL1_REG 0x27 +#define YT8531_ESC1R_SLEEP_SW BIT(15) +#define YT8531_ESC1R_PLLON_SLP BIT(14) + +#define YT8531_RGMII_CONFIG1_REG 0xA003 + +#define YT8531_CHIP_CONFIG_REG 0xA001 +#define YT8531_CCR_SW_RST BIT(15) +/* 1b0 disable 1.9ns rxc clock delay *default* + * 1b1 enable 1.9ns rxc clock delay + */ +#define Y
[PATCH v5 00/11] Add ethernet driver for StarFive JH7110 SoC
This series of patches base on the latest branch/master,and
adds ethernet support for the StarFive JH7110 RISC-V SoC.
The series includes EEPROM, PHY and MAC drivers. The PHY model is
YT8531 (from Motorcomm Inc), and the MAC version is dwmac-5.20
(from Synopsys DesignWare).
The implementation of the phy driver is ported from linux, but it
has been adjusted for the u-boot framework.
EEPROM stores board-related information, such as DDR capacity,
PCB version, MAC address, etc.
The main difference between StarFive VisionFive 2 1.2A and 1.3B is
gmac, but the difference in gmac is not defined in DT, but reads the
PCB version from EEPROM, and then dynamically configures the difference
of gmac according to different PCB versions, which is compatible
with 1.2A and 1.3B versions, which is more user-friendly.
The PHY and MAC driver has been tested on the StarFive VisionFive 2 1.2A
and 1.3B boards and works normally.
For more information and support,you can visit RVspace wiki[1].
[1] https://wiki.rvspace.org/
v5:
- Reorder a series of patches to make each patch is independent.
- Move CONFIG_DEFAULT_FDT_FILE and CONFIG_DEFAULT_DEVICE_TREE changes to patch
4.
- Move the definition of 'board_fdt_blob_setup' to patch 9.
v4:
- Reworded the definition of the 'pbuf' variable in visionfive2-i2c-eeprom.c
from a const pointer to const union.
- Added the section (".data") attribute to the 'pbuf' and 'has_been_read'
global
variables in visionfive2-i2-eeprom.c.
v3:
- Added EEPROM support.
- Combine the board device tree of 1.2A and 1.3B into one.
- Removed the delay configuration of gmac phy clock from DT.
- Dynamically configure gmac differences of 1.2A and 1.3B to DT according to
the PCB version.
- DDR capacity information is read from EEPROM first, if not, it is defined by
default in DT.
v2:
- Reworded the phy driver. Added platform private data struct to save the
configuration data read from dts.
- Reworded the MAC driver. Added platform private data struct to save the
configuration data read from dts.
Previous versions:
v1 -
https://patchwork.ozlabs.org/project/uboot/cover/20230317010536.17860-1-yanhong.w...@starfivetech.com/
v2 -
https://patchwork.ozlabs.org/project/uboot/cover/20230329102720.25439-1-yanhong.w...@starfivetech.com/
v3 -
https://patchwork.ozlabs.org/project/uboot/cover/20230428022515.29393-1-yanhong.w...@starfivetech.com/
v4 -
https://patchwork.ozlabs.org/project/uboot/cover/20230525093637.31364-1-yanhong.w...@starfivetech.com/
Yanhong Wang (11):
net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
net: dwc_eth_qos: Add StarFive ethernet driver glue layer
riscv: dts: jh7110: Add ethernet device tree nodes
riscv: dts: jh7110: Combine the board device tree files of 1.2A and
1.3B
doc: board: starfive: Reword the make defconfig information
configs: starfive: Enable ethernet configuration for StarFive
VisionFive2
eeprom: starfive: Enable ID EEPROM configuration
riscv: dts: starfive: Add support eeprom device tree node
configs: starfive: Enable ID EEPROM configuration
ram: starfive: Read memory size information from EEPROM
board: starfive: Dynamic configuration of DT for 1.2A and 1.3B
arch/riscv/cpu/jh7110/spl.c | 32 +-
arch/riscv/dts/Makefile | 3 +-
... jh7110-starfive-visionfive-2-u-boot.dtsi} | 39 +-
.../jh7110-starfive-visionfive-2-v1.2a.dts| 12 -
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 ---
...b.dts => jh7110-starfive-visionfive-2.dts} | 3 +-
.../dts/jh7110-starfive-visionfive-2.dtsi | 40 ++
arch/riscv/dts/jh7110.dtsi| 69 +++
arch/riscv/include/asm/arch-jh7110/eeprom.h | 13 +
board/starfive/visionfive2/Makefile | 1 +
board/starfive/visionfive2/spl.c | 157 +
.../visionfive2/starfive_visionfive2.c| 13 +
.../visionfive2/visionfive2-i2c-eeprom.c | 561 ++
configs/starfive_visionfive2_defconfig| 32 +-
doc/board/starfive/visionfive2.rst| 6 +-
drivers/net/Kconfig | 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c| 249
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/motorcomm.c | 437 ++
drivers/ram/starfive/starfive_ddr.c | 2 -
24 files changed, 1665 insertions(+), 95 deletions(-)
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi =>
jh7110-starfive-visionfive-2-u-boot.dtsi} (58%)
delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
delete mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3
Re: [PATCH v4 11/11] configs: starfive: Enable ID EEPROM configuration
On 2023/6/5 3:23, Jan Kiszka wrote:
> On 25.05.23 11:36, Yanhong Wang wrote:
>> Enabled ID_EEPROM and I2C configuration for StarFive VisionFive2 board.
>>
>> Signed-off-by: Yanhong Wang
>> ---
>> configs/starfive_visionfive2_defconfig | 19 ++-
>> 1 file changed, 18 insertions(+), 1 deletion(-)
>>
>> diff --git a/configs/starfive_visionfive2_defconfig
>> b/configs/starfive_visionfive2_defconfig
>> index c57708199d..570a1f53a1 100644
>> --- a/configs/starfive_visionfive2_defconfig
>> +++ b/configs/starfive_visionfive2_defconfig
>> @@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="StarFive #"
>> CONFIG_OF_LIBFDT_OVERLAY=y
>> CONFIG_DM_RESET=y
>> CONFIG_SPL_MMC=y
>> +CONFIG_SPL_DRIVERS_MISC=y
>> CONFIG_SPL_STACK=0x818
>> CONFIG_SPL=y
>> CONFIG_SPL_SPI_FLASH_SUPPORT=y
>> @@ -23,6 +24,7 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
>> CONFIG_ARCH_RV64I=y
>> CONFIG_CMODEL_MEDANY=y
>> CONFIG_RISCV_SMODE=y
>> +# CONFIG_OF_BOARD_FIXUP is not set
>> CONFIG_FIT=y
>> CONFIG_DISTRO_DEFAULTS=y
>> CONFIG_QSPI_BOOT=y
>> @@ -34,6 +36,8 @@ CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr
>> ${fdtcontroladdr};"
>> CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
>> CONFIG_DISPLAY_CPUINFO=y
>> CONFIG_DISPLAY_BOARDINFO=y
>> +CONFIG_ID_EEPROM=y
>> +CONFIG_SYS_EEPROM_BUS_NUM=5
>> CONFIG_SPL_MAX_SIZE=0x4
>> CONFIG_SPL_PAD_TO=0x0
>> CONFIG_SPL_BSS_START_ADDR=0x804
>> @@ -45,21 +49,34 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8000
>> CONFIG_SYS_SPL_MALLOC_SIZE=0x40
>> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
>> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
>> +CONFIG_SPL_I2C=y
>> CONFIG_SPL_DM_SPI_FLASH=y
>> CONFIG_SPL_DM_RESET=y
>> CONFIG_SPL_SPI_LOAD=y
>> CONFIG_SYS_CBSIZE=256
>> CONFIG_SYS_PBSIZE=276
>> CONFIG_SYS_BOOTM_LEN=0x400
>> +CONFIG_CMD_EEPROM=y
>> +CONFIG_SYS_EEPROM_SIZE=512
>> +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
>> +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
>> CONFIG_CMD_MEMINFO=y
>> +CONFIG_CMD_I2C=y
>> CONFIG_CMD_TFTPPUT=y
>> +CONFIG_OF_BOARD=y
>> CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>> +CONFIG_SPL_DM_SEQ_ALIAS=y
>> CONFIG_REGMAP=y
>> CONFIG_SYSCON=y
>> CONFIG_SPL_CLK_COMPOSITE_CCF=y
>> CONFIG_CLK_COMPOSITE_CCF=y
>> CONFIG_SPL_CLK_JH7110=y
>> -# CONFIG_I2C is not set
>> +CONFIG_DM_I2C=y
>> +CONFIG_SYS_I2C_DW=y
>> +CONFIG_MISC=y
>> +CONFIG_I2C_EEPROM=y
>> +CONFIG_SPL_I2C_EEPROM=y
>> +CONFIG_SYS_I2C_EEPROM_ADDR=0X50
>> CONFIG_MMC_HS400_SUPPORT=y
>> CONFIG_SPL_MMC_HS400_SUPPORT=y
>> CONFIG_MMC_DW=y
>
> This comes too late: Already patch 4 needs at least CONFIG_ID_EEPROM=y,
> if not more.
>
Moving patch 4 to the series end, is that okay?
> Make sure you don't leave non-bisectable commit series behind. Whenever
> something breaks (like 55171aedda88), people will use bisection to find
> the causing commit, and then they will appreciate not having to deal
> with such hick-ups.
>
> Jan
>
Re: [PATCH v4 10/11] configs: starfive: Enable ethernet configuration for StarFive VisionFive2
On 2023/6/5 2:53, Jan Kiszka wrote:
> On 25.05.23 11:36, Yanhong Wang wrote:
>> Enable DWC_ETH_QOS and PHY_MOTORCOMM configuration to support ethernet
>> function for StarFive VisionFive 2 board,including versions 1.2A and
>> 1.3B.
>>
>> Signed-off-by: Yanhong Wang
>> ---
>> configs/starfive_visionfive2_defconfig | 13 +++--
>> 1 file changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/configs/starfive_visionfive2_defconfig
>> b/configs/starfive_visionfive2_defconfig
>> index ffbc4b9476..c57708199d 100644
>> --- a/configs/starfive_visionfive2_defconfig
>> +++ b/configs/starfive_visionfive2_defconfig
>> @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>> CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000
>> CONFIG_SF_DEFAULT_SPEED=1
>> CONFIG_SPL_DM_SPI=y
>> -CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b"
>> +CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2"
>> CONFIG_SPL_TEXT_BASE=0x800
>> CONFIG_SYS_PROMPT="StarFive #"
>> CONFIG_OF_LIBFDT_OVERLAY=y
>> @@ -31,7 +31,7 @@ CONFIG_USE_BOOTARGS=y
>> CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
>> CONFIG_USE_PREBOOT=y
>> CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr
>> ${fdtcontroladdr};"
>> -CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
>> +CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
>
> These two hunks belong into patch 7.
>
Ok, I'll move the two chunks to patch 7.
> Jan
>
>> CONFIG_DISPLAY_CPUINFO=y
>> CONFIG_DISPLAY_BOARDINFO=y
>> CONFIG_SPL_MAX_SIZE=0x4
>> @@ -54,6 +54,8 @@ CONFIG_SYS_BOOTM_LEN=0x400
>> CONFIG_CMD_MEMINFO=y
>> CONFIG_CMD_TFTPPUT=y
>> CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>> +CONFIG_REGMAP=y
>> +CONFIG_SYSCON=y
>> CONFIG_SPL_CLK_COMPOSITE_CCF=y
>> CONFIG_CLK_COMPOSITE_CCF=y
>> CONFIG_SPL_CLK_JH7110=y
>> @@ -66,6 +68,13 @@ CONFIG_SPI_FLASH_EON=y
>> CONFIG_SPI_FLASH_GIGADEVICE=y
>> CONFIG_SPI_FLASH_ISSI=y
>> CONFIG_SPI_FLASH_MACRONIX=y
>> +CONFIG_PHY_MOTORCOMM=y
>> +CONFIG_DM_MDIO=y
>> +CONFIG_DM_ETH_PHY=y
>> +CONFIG_DWC_ETH_QOS=y
>> +CONFIG_DWC_ETH_QOS_STARFIVE=y
>> +CONFIG_RGMII=y
>> +CONFIG_RMII=y
>> CONFIG_PINCTRL=y
>> CONFIG_PINCONF=y
>> CONFIG_SPL_PINCTRL=y
>
Re: [PATCH v4 00/11] Add ethernet driver for StarFive JH7110 SoC
On 2023/6/2 1:44, Torsten Duwe wrote: > On Thu, 25 May 2023 17:36:26 +0800 > Yanhong Wang wrote: > [...] >> >> base-commit: 62df7a39442902a71259568c13a4d496d5a514f4 > > Have you tested this? > I also got the following error, which was caused by the recent submission [commit ID: 55171aedda88d12666e2a1bbc661dea1bec65337]. The modifications in this submission '! (gd->flags & GD_FLG_RELOC)' [in drivers/core/root.c] causes this issue, I have emailed the author of this submission for more information. I commented this modification when I was testing. The patch link: https://patchwork.ozlabs.org/project/uboot/patch/20230504225101.2366414-2-...@chromium.org/ > I get > > | U-Boot SPL 2023.07-rc2-00170-g62df7a3944 (Jun 01 2023 - 18:58:50 +0200) > | DDR version: dc2e84f0. > | Trying to boot from MMC2 > | > | > | U-Boot 2023.07-rc2-00170-g62df7a3944 (Jun 01 2023 - 18:58:50 +0200) > | > | CPU: rv64imafdc_zba_zbb > | Model: StarFive VisionFive 2 v1.3B > | DRAM: 8 GiB > | initcall sequence fffe0260 failed at call 402160ec (err=-19) > | ### ERROR ### Please RESET the board ### > > on that base rev already! > My compiler is gcc (SUSE Linux) 13.0.1 20230421 (prerelease) > [revision f980561c60b0446cc427595198d7f3f4f90e0924], FWIW. > OpenSBI is 1.2 > > A simple switch back to an older branch (based on 6a11fdf0536e02ac) > produces a working U-Boot again. > > Am I missing something? > > Torsten
Re: The latest U-boot reports an error when running on StarFive visionfive2 1.3B board
On 2023/5/31 2:11, Simon Glass wrote: > Hi Yanhong, > > Please can you send this to the mailing list and cc me? > > Regards, > Simon > > On Tue, 16 May 2023 at 20:48, yanhong wang > wrote: >> >> Hi Simon Glass, >> >> Running the latest U-boot on the StarFive VisionFive 2 1.3B board prompts >> the following error message: >> >> U-Boot 2023.07-rc2-00133-g6e1852ca2c (May 17 2023 - 09:08:48 +0800) >> >> CPU: rv64imafdc_zba_zbb >> Model: StarFive VisionFive 2 v1.3B >> DRAM: 8 GiB >> initcall sequence fffe08b0 failed at call 4021611e (err=-19) >> ### ERROR ### Please RESET the board ### >> >> Roll back the most recent submission, and finally confirm that one of the >> submission affected [commit ID: 55171aedda88d12666e2a1bbc661dea1bec65337]. >> The author of this submission is you, so I sent this email to learn more >> about the specific situation. >> >> Do you have any suggestions to solution this issue? >> >> >> Best Regards. >> >> yanhong.w...@starfivetech.com
[PATCH v4 11/11] configs: starfive: Enable ID EEPROM configuration
Enabled ID_EEPROM and I2C configuration for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
configs/starfive_visionfive2_defconfig | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
index c57708199d..570a1f53a1 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="StarFive #"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x818
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -23,6 +24,7 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
+# CONFIG_OF_BOARD_FIXUP is not set
CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_BOOT=y
@@ -34,6 +36,8 @@ CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr
${fdtcontroladdr};"
CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_ID_EEPROM=y
+CONFIG_SYS_EEPROM_BUS_NUM=5
CONFIG_SPL_MAX_SIZE=0x4
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_BSS_START_ADDR=0x804
@@ -45,21 +49,34 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8000
CONFIG_SYS_SPL_MALLOC_SIZE=0x40
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
+CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_SIZE=512
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_TFTPPUT=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_JH7110=y
-# CONFIG_I2C is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0X50
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
--
2.17.1
[PATCH v4 10/11] configs: starfive: Enable ethernet configuration for StarFive VisionFive2
Enable DWC_ETH_QOS and PHY_MOTORCOMM configuration to support ethernet
function for StarFive VisionFive 2 board,including versions 1.2A and
1.3B.
Signed-off-by: Yanhong Wang
---
configs/starfive_visionfive2_defconfig | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
index ffbc4b9476..c57708199d 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000
CONFIG_SF_DEFAULT_SPEED=1
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b"
+CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2"
CONFIG_SPL_TEXT_BASE=0x800
CONFIG_SYS_PROMPT="StarFive #"
CONFIG_OF_LIBFDT_OVERLAY=y
@@ -31,7 +31,7 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
-CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
+CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SPL_MAX_SIZE=0x4
@@ -54,6 +54,8 @@ CONFIG_SYS_BOOTM_LEN=0x400
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_TFTPPUT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_JH7110=y
@@ -66,6 +68,13 @@ CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_STARFIVE=y
+CONFIG_RGMII=y
+CONFIG_RMII=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
--
2.17.1
[PATCH v4 09/11] doc: board: starfive: Reword the make defconfig information
The defconfig file name for StarFive VisionFive2 has been changed, and
the documentation description has also changed.
Signed-off-by: Yanhong Wang
---
doc/board/starfive/visionfive2.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/doc/board/starfive/visionfive2.rst
b/doc/board/starfive/visionfive2.rst
index 4d43ac9729..951e0d80fb 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -62,7 +62,7 @@ Now build the U-Boot SPL and U-Boot proper
.. code-block:: console
cd
- make starfive_visionfive2_13b_defconfig
+ make starfive_visionfive2_defconfig
make
OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
@@ -118,7 +118,7 @@ Program the SD card
sudo cp u-boot.itb /mnt/
sudo cp Image.gz /mnt/
sudo cp initramfs.cpio.gz /mnt/
- sudo cp jh7110-starfive-visionfive-2-v1.3b.dtb /mnt/
+ sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
sudo umount /mnt
Booting
@@ -264,7 +264,7 @@ Sample boot log from StarFive VisionFive2 board
StarFive #fatload mmc 1:3 ${kernel_addr_r} Image.gz
6429424 bytes read in 394 ms (15.6 MiB/s)
- StarFive #fatload mmc 1:3 ${fdt_addr_r}
jh7110-starfive-visionfive-2-v1.3b.dtb
+ StarFive #fatload mmc 1:3 ${fdt_addr_r} jh7110-starfive-visionfive-2.dtb
11285 bytes read in 5 ms (2.2 MiB/s)
StarFive #fatload mmc 1:3 ${ramdisk_addr_r} initramfs.cpio.gz
152848495 bytes read in 9271 ms (15.7 MiB/s)
--
2.17.1
[PATCH v4 07/11] riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B
The difference between 1.2A and 1.3B is dynamically configured according
to the PCB version, and there is no difference on the board device tree,
so the same DT file can be used.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/Makefile | 3 +-
... jh7110-starfive-visionfive-2-u-boot.dtsi} | 25 ++-
.../jh7110-starfive-visionfive-2-v1.2a.dts| 12
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 ---
...b.dts => jh7110-starfive-visionfive-2.dts} | 3 +-
5 files changed, 26 insertions(+), 86 deletions(-)
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi =>
jh7110-starfive-visionfive-2-u-boot.dtsi} (66%)
delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
delete mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts =>
jh7110-starfive-visionfive-2.dts} (65%)
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 79a58694f5..7940fe466d 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,8 +7,7 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.3b.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.2a.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
similarity index 66%
rename from arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
rename to arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 3c322c5c97..2afcec30b8 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
*/
#include "binman.dtsi"
@@ -67,3 +67,26 @@
};
};
+ {
+ itb {
+ fit {
+ images {
+ fdt-1 {
+ description = "NAME";
+ load = <0x4040>;
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ conf-1 {
+ fdt = "fdt-1";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
deleted file mode 100644
index b9d26d7af7..00
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-/dts-v1/;
-#include "jh7110-starfive-visionfive-2.dtsi"
-
-/ {
- model = "StarFive VisionFive 2 v1.2A";
- compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
-};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
deleted file mode 100644
index 3c322c5c97..00
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-#include "binman.dtsi"
-#include "jh7110-u-boot.dtsi"
-/ {
- chosen {
- bootph-pre-ram;
- };
-
- firmware {
- spi0 =
- bootph-pre-ram;
- };
-
- config {
- bootph-pre-ram;
- u-boot,spl-payload-offset = <0x10>;
- };
-
- memory@4000 {
- bootph-pre-ram;
- };
-};
-
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-
- nor-flash@0 {
- bootph-pre-ram;
- };
-};
-
- {
- bootph-pre-ram;
-};
-
-_pins {
- bootph-pre-ram;
- mmc0-pins-rest {
- bootph-pre-ra
[PATCH v4 08/11] riscv: dts: starfive: Add support eeprom device tree node
Add support "atmel,24c04" eeprom for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
.../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 14 ++
arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 8 +++-
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 2afcec30b8..13f69da31e 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -67,6 +67,20 @@
};
};
+_pins {
+ bootph-pre-ram;
+ i2c-pins {
+ bootph-pre-ram;
+ };
+};
+
+ {
+ bootph-pre-ram;
+ eeprom@50 {
+ bootph-pre-ram;
+ };
+};
+
{
itb {
fit {
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index 0272369b24..710b082766 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -120,6 +120,12 @@
pinctrl-names = "default";
pinctrl-0 = <_pins>;
status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
};
{
@@ -350,4 +356,4 @@
reg = <0>;
};
};
-};
\ No newline at end of file
+};
--
2.17.1
[PATCH v4 06/11] riscv: dts: jh7110: Add ethernet device tree nodes
Add ethernet device tree node to support StarFive ethernet driver for
the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
---
.../dts/jh7110-starfive-visionfive-2.dtsi | 34 +
arch/riscv/dts/jh7110.dtsi| 69 +++
2 files changed, 103 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..0272369b24 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -17,6 +17,8 @@
i2c2 =
i2c5 =
i2c6 =
+ ethernet0 =
+ ethernet1 =
};
chosen {
@@ -317,3 +319,35 @@
assigned-clock-parents = <>;
assigned-clock-rates = <0>;
};
+
+ {
+ phy-handle = <>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+ {
+ phy-handle = <>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+ };
+};
\ No newline at end of file
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..58e332e9d7 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -235,6 +235,13 @@
#clock-cells = <0>;
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,lpi_en;
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <4>;
+ snps,blen = <256 128 64 32 0 0 0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -539,6 +546,68 @@
status = "disabled";
};
+ gmac0: ethernet@1603 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x1603 0x0 0x1>;
+ clocks = < JH7110_AONCLK_GMAC0_AXI>,
+< JH7110_AONCLK_GMAC0_AHB>,
+< JH7110_SYSCLK_GMAC0_PTP>,
+< JH7110_AONCLK_GMAC0_TX_INV>,
+< JH7110_SYSCLK_GMAC0_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = < JH7110_AONRST_GMAC0_AXI>,
+< JH7110_AONRST_GMAC0_AHB>;
+ reset-names = "stmmaceth", "ahb";
+ interrupts = <7>, <6>, <5>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <8>;
+ rx-fifo-depth = <2048>;
+ tx-fifo-depth = <2048>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <_axi_setup>;
+ snps,tso;
+ snps,en-tx-lpi-clockgating;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ starfive,syscon = <_syscon 0xc 0x12>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@1604 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x1604 0x0 0x1>;
+ clocks = < JH7110_SYSCLK_GMAC1_AXI>,
+< JH7110_SYSCLK_GMAC1_AHB>,
+< JH7110_SYSCLK_GMAC1_PTP>,
+< JH7110_SYSCLK_GMAC1_TX_INV>,
+< JH7110_SYSCLK_GMAC1_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = < JH7110_SYS
[PATCH v4 05/11] board: starfive: Dynamic configuration of DT for 1.2A and 1.3B
The main difference between StarFive VisionFive 2 1.2A and 1.3B is gmac.
You can read the PCB version of the current board by
get_pcb_revision_from_eeprom(), and then dynamically configure the
difference of gmac in spl_perform_fixups() according to different PCB
versions, so that one DT and one defconfig can support both 1.2A and
1.3B versions, which is more user-friendly.
Signed-off-by: Yanhong Wang
---
board/starfive/visionfive2/spl.c | 157 ++
.../visionfive2/starfive_visionfive2.c| 13 ++
2 files changed, 170 insertions(+)
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index db0b4cb433..7acd3995aa 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -5,16 +5,173 @@
*/
#include
+#include
#include
#include
#include
+#include
+#include
+#include
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
#define JH7110_CLK_CPU_ROOT_SHIFT 24
#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
+struct starfive_vf2_pro {
+ const char *path;
+ const char *name;
+ const char *value;
+};
+
+static const struct starfive_vf2_pro starfive_vera[] = {
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0", "rx-internal-delay-ps",
+ "1900"},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0", "tx-internal-delay-ps",
+ "1350"}
+};
+
+static const struct starfive_vf2_pro starfive_verb[] = {
+ {"/soc/ethernet@1603", "starfive,tx-use-rgmii-clk", NULL},
+ {"/soc/ethernet@1604", "starfive,tx-use-rgmii-clk", NULL},
+
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-1000-inverted", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "rx-internal-delay-ps", "1900"},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "tx-internal-delay-ps", "1500"},
+
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ { "/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "rx-internal-delay-ps", "0"},
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "tx-internal-delay-ps", "0"},
+};
+
+void spl_fdt_fixup_version_a(void *fdt)
+{
+ u32 phandle;
+ u8 i;
+ int offset;
+ int ret;
+
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+ "StarFive VisionFive 2 v1.2A");
+
+ offset = fdt_path_offset(fdt, "/soc/clock-controller@1302");
+ phandle = fdt_get_phandle(fdt, offset);
+ offset = fdt_path_offset(fdt, "/soc/ethernet@1604");
+
+ fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks",
JH7110_SYSCLK_GMAC1_TX);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks",
JH7110_SYSCLK_GMAC1_RX);
+
+ fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_SYSCLK_GMAC1_RMII_RTX);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_SYSCLK_GMAC1_RMII_RTX);
+
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@1604"),
+ "phy-mode", "rmii");
+
+ for (i = 0; i < ARRAY_SIZE(starfive_vera); i++) {
+ offset = fdt_path_offset(fdt, starfive_vera[i].path);
+
+ if (starfive_vera[i].value)
+ ret = fdt_setprop_u32(fdt, offset,
starfive_vera[i].name,
+ dectoul(starfive_vera[i].value,
NULL));
+ else
+ ret = fdt_setprop_empty(fdt, offset,
starfive_vera[i].name);
+
+ if (ret) {
+ pr_err("%s set prop %s fail.\n", __func__,
starf
[PATCH v4 03/11] eeprom: starfive: Enable ID EEPROM configuration
Enabled ID_EEPROM configuration for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
arch/riscv/include/asm/arch-jh7110/eeprom.h | 13 +
board/starfive/visionfive2/Makefile | 1 +
.../visionfive2/visionfive2-i2c-eeprom.c | 561 ++
3 files changed, 575 insertions(+)
create mode 100644 arch/riscv/include/asm/arch-jh7110/eeprom.h
create mode 100644 board/starfive/visionfive2/visionfive2-i2c-eeprom.c
diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h
b/arch/riscv/include/asm/arch-jh7110/eeprom.h
new file mode 100644
index 00..f354d5c60c
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#ifndef _ASM_RISCV_EEPROM_H
+#define _ASM_RISCV_EEPROM_H
+
+u8 get_pcb_revision_from_eeprom(void);
+u32 get_ddr_size_from_eeprom(void);
+
+#endif /* _ASM_RISCV_EEPROM_H */
diff --git a/board/starfive/visionfive2/Makefile
b/board/starfive/visionfive2/Makefile
index 66c854df39..c7ba4f7ed6 100644
--- a/board/starfive/visionfive2/Makefile
+++ b/board/starfive/visionfive2/Makefile
@@ -5,3 +5,4 @@
obj-y := starfive_visionfive2.o
obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_ID_EEPROM) += visionfive2-i2c-eeprom.o
diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
new file mode 100644
index 00..befe7888c4
--- /dev/null
+++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
@@ -0,0 +1,561 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define FORMAT_VERSION 0x2
+#define PCB_VERSION0xB1
+#define BOM_VERSION'A'
+/*
+ * BYTES_PER_EEPROM_PAGE: the 24FC04H datasheet says that data can
+ * only be written in page mode, which means 16 bytes at a time:
+ * 16-Byte Page Write Buffer
+ */
+#define BYTES_PER_EEPROM_PAGE 16
+
+/*
+ * EEPROM_WRITE_DELAY_MS: the 24FC04H datasheet says it takes up to
+ * 5ms to complete a given write:
+ * Write Cycle Time (byte or page) ro Page Write Time 5 ms, Maximum
+ */
+#define EEPROM_WRITE_DELAY_MS 5000
+/*
+ * StarFive OUI. Registration Date is 20xx-xx-xx
+ */
+#define STARFIVE_OUI_PREFIX"6C:CF:39:"
+#define STARFIVE_DEFAULT_MAC0 "6C:CF:39:6C:DE:AD"
+#define STARFIVE_DEFAULT_MAC1 "6C:CF:39:6C:DE:AE"
+
+/* Magic number at the first four bytes of EEPROM HATs */
+#define STARFIVE_EEPROM_HATS_SIG "SFVF" /* StarFive VisionFive */
+
+#define STARFIVE_EEPROM_HATS_SIZE_MAX 256 /* Header + Atom1&4(v1) */
+#define STARFIVE_EEPROM_WP_OFFSET 0 /* Read only field */
+#define STARFIVE_EEPROM_ATOM1_PSTR "VF7110A1-2228-D008E000-0001\0"
+#define STARFIVE_EEPROM_ATOM1_PSTR_SIZE32
+#define STARFIVE_EEPROM_ATOM1_SN_OFFSET23
+#define STARFIVE_EEPROM_ATOM1_VSTR "StarFive Technology Co., Ltd.\0\0\0"
+#define STARFIVE_EEPROM_ATOM1_VSTR_SIZE32
+
+#define MAGIC_NUMBER_BYTES 4
+#define MAC_ADDR_BYTES 6
+#define MAC_ADDR_STRLEN17
+
+/*
+ * Atom Types
+ * 0x = invalid
+ * 0x0001 = vendor info
+ * 0x0002 = GPIO map
+ * 0x0003 = Linux device tree blob
+ * 0x0004 = manufacturer custom data
+ * 0x0005-0xfffe = reserved for future use
+ * 0x = invalid
+ */
+
+#define HATS_ATOM_INVALID 0x
+#define HATS_ATOM_VENDOR 0x0001
+#define HATS_ATOM_GPIO 0x0002
+#define HATS_ATOM_DTB 0x0003
+#define HATS_ATOM_CUSTOM 0x0004
+#define HATS_ATOM_INVALID_END 0x
+
+struct eeprom_header {
+ char signature[MAGIC_NUMBER_BYTES]; /* ASCII table signature */
+ u8 version; /* EEPROM data format version */
+ /* (0x00 reserved, 0x01 = first version) */
+ u8 reversed;/* 0x00, Reserved field */
+ u16 numatoms; /* total atoms in EEPROM */
+ u32 eeplen; /* total length in bytes of all eeprom data */
+ /* (including this header) */
+};
+
+struct eeprom_atom_header {
+ u16 type;
+ u16 count;
+ u32 dlen;
+};
+
+struct eeprom_atom1_data {
+ u8 uuid[16];
+ u16 pid;
+ u16 pver;
+ u8 vslen;
+ u8 pslen;
+ uchar vstr[STARFIVE_EEPROM_ATOM1_VSTR_SIZE];
+ uchar pstr[STARFIVE_EEPROM_ATOM1_PSTR_SIZE]; /* product SN */
+};
+
+struct starfive_eeprom_atom1 {
+ struct eeprom_atom_header header;
+ struct eeprom_atom1_data data;
+ u16 crc;
+};
+
+struct eeprom_atom4_data {
+ u16 version;
+ u8 pcb_revision;/* PCB version */
+ u8 bom_revision;/* BOM version */
+ u8 mac0_addr[MAC_ADDR_B
[PATCH v4 04/11] ram: starfive: Read memory size information from EEPROM
StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of
DDR capacity includes 2G/4G/8G, a DT can not support multiple
capacities, so the capacity size information is recorded to EEPROM, when
DDR initialization required capacity size information is read from
EEPROM.
If there is no information in EEPROM, it is initialized with the default
size defined in DT.
Signed-off-by: Yanhong Wang
---
arch/riscv/cpu/jh7110/spl.c | 32 -
drivers/ram/starfive/starfive_ddr.c | 2 --
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 104f0fe949..72adcefa0e 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -3,19 +3,49 @@
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Author: Yanhong Wang
*/
-
+#include
+#include
#include
#include
#include
+#include
#include
+#include
#define CSR_U74_FEATURE_DISABLE0x7c1
#define L2_LIM_MEM_END 0x81FUL
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool check_ddr_size(phys_size_t size)
+{
+ switch (size) {
+ case SZ_2:
+ case SZ_4:
+ case SZ_8:
+ case SZ_16:
+ return true;
+ default:
+ return false;
+ }
+}
+
int spl_soc_init(void)
{
int ret;
struct udevice *dev;
+ phys_size_t size;
+
+ ret = fdtdec_setup_mem_size_base();
+ if (ret)
+ return ret;
+
+ /* Read the definition of the DDR size from eeprom, and if not,
+* use the definition in DT
+*/
+ size = (get_ddr_size_from_eeprom() >> 16) & 0xFF;
+ if (check_ddr_size(size))
+ gd->ram_size = size << 30;
/* DDR init */
ret = uclass_get_device(UCLASS_RAM, 0, );
diff --git a/drivers/ram/starfive/starfive_ddr.c
b/drivers/ram/starfive/starfive_ddr.c
index 553f2ce6f4..a0a3d6b33d 100644
--- a/drivers/ram/starfive/starfive_ddr.c
+++ b/drivers/ram/starfive/starfive_ddr.c
@@ -72,8 +72,6 @@ static int starfive_ddr_probe(struct udevice *dev)
u64 rate;
int ret;
- /* Read memory base and size from DT */
- fdtdec_setup_mem_size_base();
priv->info.base = gd->ram_base;
priv->info.size = gd->ram_size;
--
2.17.1
[PATCH v4 00/11] Add ethernet driver for StarFive JH7110 SoC
This series of patches base on the latest branch/master,and
adds ethernet support for the StarFive JH7110 RISC-V SoC.
The series includes EEPROM, PHY and MAC drivers. The PHY model is
YT8531 (from Motorcomm Inc), and the MAC version is dwmac-5.20
(from Synopsys DesignWare).
The implementation of the phy driver is ported from linux, but it
has been adjusted for the u-boot framework.
EEPROM stores board-related information, such as DDR capacity,
PCB version, MAC address, etc.
The main difference between StarFive VisionFive 2 1.2A and 1.3B is
gmac, but the difference in gmac is not defined in DT, but reads the
PCB version from EEPROM, and then dynamically configures the difference
of gmac according to different PCB versions, which is compatible
with 1.2A and 1.3B versions, which is more user-friendly.
The PHY and MAC driver has been tested on the StarFive VisionFive 2 1.2A
and 1.3B boards and works normally.
For more information and support,you can visit RVspace wiki[1].
[1] https://wiki.rvspace.org/
v4:
- Reworded the definition of the 'pbuf' variable in visionfive2-i2c-eeprom.c
from a const pointer to const union.
- Added the section (".data") attribute to the 'pbuf' and 'has_been_read'
global
variables in visionfive2-i2-eeprom.c.
v3:
- Added EEPROM support.
- Combine the board device tree of 1.2A and 1.3B into one.
- Removed the delay configuration of gmac phy clock from DT.
- Dynamically configure gmac differences of 1.2A and 1.3B to DT according to
the PCB version.
- DDR capacity information is read from EEPROM first, if not, it is defined by
default in DT.
v2:
- Reworded the phy driver. Added platform private data struct to save the
configuration data read from dts.
- Reworded the MAC driver. Added platform private data struct to save the
configuration data read from dts.
Previous versions:
v1 -
https://patchwork.ozlabs.org/project/uboot/cover/20230317010536.17860-1-yanhong.w...@starfivetech.com/
v2 -
https://patchwork.ozlabs.org/project/uboot/cover/20230329102720.25439-1-yanhong.w...@starfivetech.com/
v3 -
https://patchwork.ozlabs.org/project/uboot/cover/20230428022515.29393-1-yanhong.w...@starfivetech.com/
Yanhong Wang (11):
net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
net: dwc_eth_qos: Add StarFive ethernet driver glue layer
eeprom: starfive: Enable ID EEPROM configuration
ram: starfive: Read memory size information from EEPROM
board: starfive: Dynamic configuration of DT for 1.2A and 1.3B
riscv: dts: jh7110: Add ethernet device tree nodes
riscv: dts: jh7110: Combine the board device tree files of 1.2A and
1.3B
riscv: dts: starfive: Add support eeprom device tree node
doc: board: starfive: Reword the make defconfig information
configs: starfive: Enable ethernet configuration for StarFive
VisionFive2
configs: starfive: Enable ID EEPROM configuration
arch/riscv/cpu/jh7110/spl.c | 32 +-
arch/riscv/dts/Makefile | 3 +-
... jh7110-starfive-visionfive-2-u-boot.dtsi} | 39 +-
.../jh7110-starfive-visionfive-2-v1.2a.dts| 12 -
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 ---
...b.dts => jh7110-starfive-visionfive-2.dts} | 3 +-
.../dts/jh7110-starfive-visionfive-2.dtsi | 40 ++
arch/riscv/dts/jh7110.dtsi| 69 +++
arch/riscv/include/asm/arch-jh7110/eeprom.h | 13 +
board/starfive/visionfive2/Makefile | 1 +
board/starfive/visionfive2/spl.c | 157 +
.../visionfive2/starfive_visionfive2.c| 13 +
.../visionfive2/visionfive2-i2c-eeprom.c | 561 ++
configs/starfive_visionfive2_defconfig| 32 +-
doc/board/starfive/visionfive2.rst| 6 +-
drivers/net/Kconfig | 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c| 249
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/motorcomm.c | 437 ++
drivers/ram/starfive/starfive_ddr.c | 2 -
24 files changed, 1665 insertions(+), 95 deletions(-)
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi =>
jh7110-starfive-visionfive-2-u-boot.dtsi} (58%)
delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
delete mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts =>
jh7110-starfive-visionfive-2.dts} (65%)
create mode 100644 arch/riscv/include/asm/arch-jh7110/eeprom.h
create mode 100644 board/starfive/visionfive2/visionfive2-i2c-eeprom.c
create mode 100644 drivers/net/dwc_eth_qos_starfive.c
create mode 100644 drivers/net/phy/motorcomm.c
base-commit: 62df7a39442902a712595
[PATCH v4 02/11] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.
Signed-off-by: Yanhong Wang
Reviewed-by: Ramon Fried
---
drivers/net/Kconfig| 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c | 249 +
5 files changed, 264 insertions(+)
create mode 100644 drivers/net/dwc_eth_qos_starfive.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 09039a283e..5540f0ea18 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -249,6 +249,13 @@ config DWC_ETH_QOS_QCOM
The Synopsys Designware Ethernet QOS IP block with specific
configuration used in Qcom QCS404 SoC.
+config DWC_ETH_QOS_STARFIVE
+ bool "Synopsys DWC Ethernet QOS device support for STARFIVE"
+ depends on DWC_ETH_QOS
+ help
+ The Synopsys Designware Ethernet QOS IP block with specific
+ configuration used in STARFIVE JH7110 soc.
+
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 46a40e2ed9..d4af253b6f 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
+obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9bbba6eed0..1e92bd9ca9 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1725,6 +1725,12 @@ static const struct udevice_id eqos_ids[] = {
.data = (ulong)_qcom_config
},
#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
+ {
+ .compatible = "starfive,jh7110-dwmac",
+ .data = (ulong)_jh7110_config
+ },
+#endif
{ }
};
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index fddbe9336c..a6b719af80 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -289,3 +289,4 @@ int eqos_null_ops(struct udevice *dev);
extern struct eqos_config eqos_imx_config;
extern struct eqos_config eqos_qcom_config;
+extern struct eqos_config eqos_jh7110_config;
diff --git a/drivers/net/dwc_eth_qos_starfive.c
b/drivers/net/dwc_eth_qos_starfive.c
new file mode 100644
index 00..5be8ac0f1a
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_starfive.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dwc_eth_qos.h"
+
+#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
+#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
+#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
+
+struct starfive_platform_data {
+ struct regmap *regmap;
+ struct reset_ctl_bulk resets;
+ struct clk_bulk clks;
+ phy_interface_t interface;
+ u32 offset;
+ u32 shift;
+ bool tx_use_rgmii_clk;
+};
+
+static int eqos_interface_init_jh7110(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data = pdata->priv_pdata;
+ struct ofnode_phandle_args args;
+ unsigned int mode;
+ int ret;
+
+ switch (data->interface) {
+ case PHY_INTERFACE_MODE_RMII:
+ mode = STARFIVE_DWMAC_PHY_INFT_RMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
+2, 0, );
+ if (ret)
+ return ret;
+
+ if (args.args_count != 2)
+ return -EINVAL;
+
+ data->offset = args.args[0];
+ data->shift = args.args[1];
+ data->regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
+ if (IS_ERR(data->regmap)) {
+ ret = PTR_ERR(data->regmap);
+ pr_err("Failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ return regmap_update_bits(data->regmap, data->offset,
+ STARFIVE_DWMAC_PHY_INFT_FIELD << data->shift,
+ mode << data->shift);
+}
+
+static int eqos_set_tx_clk_speed_jh7110(struct
[PATCH v4 01/11] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have verified the driver on StarFive VisionFive2 board. Signed-off-by: Yanhong Wang Reviewed-by: Ramon Fried --- drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile| 1 + drivers/net/phy/motorcomm.c | 437 3 files changed, 444 insertions(+) create mode 100644 drivers/net/phy/motorcomm.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 24158776f5..0c3c39a550 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -220,6 +220,12 @@ config PHY_MICREL_KSZ8XXX endif # PHY_MICREL +config PHY_MOTORCOMM + tristate "Motorcomm PHYs" + help + Enables support for Motorcomm network PHYs. + Currently supports the YT8531 Gigabit Ethernet PHYs. + config PHY_MSCC bool "Microsemi Corp Ethernet PHYs support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 85d17f109c..2487f366e1 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o +obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c new file mode 100644 index 00..e822fd76f2 --- /dev/null +++ b/drivers/net/phy/motorcomm.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Motorcomm 8531 PHY driver. + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include + +#define PHY_ID_YT8531 0x4f51e91b +#define PHY_ID_MASKGENMASK(31, 0) + +/* Extended Register's Address Offset Register */ +#define YTPHY_PAGE_SELECT 0x1E + +/* Extended Register's Data Register */ +#define YTPHY_PAGE_DATA0x1F + +#define YTPHY_SYNCE_CFG_REG0xA012 + +#define YTPHY_DTS_OUTPUT_CLK_DIS 0 +#define YTPHY_DTS_OUTPUT_CLK_25M 2500 +#define YTPHY_DTS_OUTPUT_CLK_125M 12500 + +#define YT8531_SCR_SYNCE_ENABLEBIT(6) +/* 1b0 output 25m clock *default* + * 1b1 output 125m clock + */ +#define YT8531_SCR_CLK_FRE_SEL_125MBIT(4) +#define YT8531_SCR_CLK_SRC_MASKGENMASK(3, 1) +#define YT8531_SCR_CLK_SRC_PLL_125M0 +#define YT8531_SCR_CLK_SRC_UTP_RX 1 +#define YT8531_SCR_CLK_SRC_SDS_RX 2 +#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 +#define YT8531_SCR_CLK_SRC_REF_25M 4 +#define YT8531_SCR_CLK_SRC_SSC_25M 5 + +/* 1b0 use original tx_clk_rgmii *default* + * 1b1 use inverted tx_clk_rgmii. + */ +#define YT8531_RC1R_TX_CLK_SEL_INVERTEDBIT(14) +#define YT8531_RC1R_RX_DELAY_MASK GENMASK(13, 10) +#define YT8531_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) +#define YT8531_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) +#define YT8531_RC1R_RGMII_0_000_NS 0 +#define YT8531_RC1R_RGMII_0_150_NS 1 +#define YT8531_RC1R_RGMII_0_300_NS 2 +#define YT8531_RC1R_RGMII_0_450_NS 3 +#define YT8531_RC1R_RGMII_0_600_NS 4 +#define YT8531_RC1R_RGMII_0_750_NS 5 +#define YT8531_RC1R_RGMII_0_900_NS 6 +#define YT8531_RC1R_RGMII_1_050_NS 7 +#define YT8531_RC1R_RGMII_1_200_NS 8 +#define YT8531_RC1R_RGMII_1_350_NS 9 +#define YT8531_RC1R_RGMII_1_500_NS 10 +#define YT8531_RC1R_RGMII_1_650_NS 11 +#define YT8531_RC1R_RGMII_1_800_NS 12 +#define YT8531_RC1R_RGMII_1_950_NS 13 +#define YT8531_RC1R_RGMII_2_100_NS 14 +#define YT8531_RC1R_RGMII_2_250_NS 15 + +/* Phy gmii clock gating Register */ +#define YT8531_CLOCK_GATING_REG0xC +#define YT8531_CGR_RX_CLK_EN BIT(12) + +/* Specific Status Register */ +#define YTPHY_SPECIFIC_STATUS_REG 0x11 +#define YTPHY_DUPLEX_MASK BIT(13) +#define YTPHY_DUPLEX_SHIFT 13 +#define YTPHY_SPEED_MODE_MASK GENMASK(15, 14) +#define YTPHY_SPEED_MODE_SHIFT 14 + +#define YT8531_EXTREG_SLEEP_CONTROL1_REG 0x27 +#define YT8531_ESC1R_SLEEP_SW BIT(15) +#define YT8531_ESC1R_PLLON_SLP BIT(14) + +#define YT8531_RGMII_CONFIG1_REG 0xA003 + +#define YT8531_CHIP_CONFIG_REG 0xA001 +#define YT8531_CCR_SW_RST BIT(15) +/* 1b0 disable 1.9ns rxc clock delay *default* + * 1b1 enable 1.9ns rxc clock delay + */ +#define Y
Re: [PATCH v1 1/2] arch: riscv: jh7110: Split the zeroing of L2 LIM on JH7110
On 2023/5/21 19:42, Bo Gan wrote: > Hi Yanhong and others, > > I've made up my own version and addressed my concerns in this patch: > > https://patchwork.ozlabs.org/project/uboot/patch/1684668616-358043-1-git-send-email-ganbo...@gmail.com/ > Hi Bo Gan, Sorry very much, when I submitted this patch, I didn't confirm that you had already submitted it, so the current situation has occurred. I will terminate the submission of this patch. > Some descriptions would be similar, as they are from my previous response to > Heinrich: > https://lists.denx.de/pipermail/u-boot/2023-May/518359.html > The description of L2 LIM in the U74 datasheet is much the same as your previous response to Heinrich, so your previous response is referenced in the description section of this patch. This patch submission does not include a cover letter, and the content of the reference is not explained, I am very sorry. > Also please note that this patch is based on > https://patchwork.ozlabs.org/project/uboot/patch/1684650044-313122-1-git-send-email-ganbo...@gmail.com/ > > It addressed another issue with riscv stack initialization on all platforms. > Please let me know if you have any suggestions. Thanks!
[PATCH v1 2/2] configs: starfive_visionfive2_defconfig: Update CONFIG_SPL_STACK
SPL runs on the L2 LIM, which is 2M in size mapped at 0x800.This region consists of 16 0x2 sized regions, each one can be used as either L2 cache way or SRAM (not both).From top to bottom, you have way 0-15.The way 0 is always enabled, so SPL can only use at most 0x1e bytes of memory.So, update the value of the CONFIG_SPL_STACK to 0x81C. Signed-off-by: Yanhong Wang --- configs/starfive_visionfive2_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index ffbc4b9476..fc3d27bbec 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -13,7 +13,7 @@ CONFIG_SYS_PROMPT="StarFive #" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y -CONFIG_SPL_STACK=0x818 +CONFIG_SPL_STACK=0x81C CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -- 2.17.1
[PATCH v1 1/2] arch: riscv: jh7110: Split the zeroing of L2 LIM on JH7110
The per-hart stack,malloc space and global variable 'gd' sits between
__bss_end and L2_LIM_MEM_END.Zeroing this region could overwrite the
hart's stack, and other harts' stacks.If it were to save and restore
`ra` register, then we would crash in function epilogue. Also, we are
having data-races here, because harts are writing over each other's
stack.
So we should split the zeroing of L2 LIM into different places just
before the region is to be used. For stacks,let each hart clearing its
own stack, and for the malloc space, we can do so during malloc
initialization. The global variable 'gd' is initialized in the
board_init_f_init_reserve function.
Signed-off-by: Yanhong Wang
---
arch/riscv/cpu/jh7110/spl.c | 6 +++---
arch/riscv/cpu/start.S | 14 ++
common/init/board_init.c| 1 +
3 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 104f0fe949..6a48fba63d 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -10,7 +10,6 @@
#include
#define CSR_U74_FEATURE_DISABLE0x7c1
-#define L2_LIM_MEM_END 0x81FUL
int spl_soc_init(void)
{
@@ -42,13 +41,14 @@ void harts_early_init(void)
csr_write(CSR_U74_FEATURE_DISABLE, 0);
/* clear L2 LIM memory
-* set __bss_end to 0x81F region to zero
+* set __bss_end to stack end region to zero
* The L2 Cache Controller supports ECC. ECC is applied to SRAM.
* If it is not cleared, the ECC part is invalid, and an ECC error
* will be reported when reading data.
*/
ptr = (ulong *)&__bss_end;
- len = L2_LIM_MEM_END - (ulong)&__bss_end;
+ len = CONFIG_SPL_STACK - CONFIG_VAL(SYS_MALLOC_F_LEN) - sizeof(*gd) -
+ CONFIG_NR_CPUS * BIT(CONFIG_STACK_SIZE_SHIFT) -
(ulong)&__bss_end;
remain = len % sizeof(ulong);
len /= sizeof(ulong);
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index dad22bfea8..46da9ec503 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -118,6 +118,20 @@ call_board_init_f_0:
mv sp, a0
#endif
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) && \
+ defined(CONFIG_STARFIVE_JH7110)
+
+ /* Set the stack region to zero */
+ li t0, 1
+ slli t1, t0, CONFIG_STACK_SIZE_SHIFT
+ mv t0, sp
+ sub t1, t0, t1
+clear_stack:
+ SREGzero, 0(t1)
+ addit1, t1, REGBYTES
+ blt t1, t0, clear_stack
+#endif
+
/* Configure proprietary settings and customized CSRs of harts */
call_harts_early_init:
jal harts_early_init
diff --git a/common/init/board_init.c b/common/init/board_init.c
index 96ffb79a98..46e4e4abc7 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -162,6 +162,7 @@ void board_init_f_init_reserve(ulong base)
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
/* go down one 'early malloc arena' */
gd->malloc_base = base;
+ memset((void *)base, 0, CONFIG_VAL(SYS_MALLOC_F_LEN));
#endif
if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
--
2.17.1
Re: [PATCH v5 01/17] riscv: cpu: jh7110: Add support for jh7110 SoC
On 2023/5/12 13:50, Bo Gan wrote:
> On 3/28/23 8:42 PM, Yanhong Wang wrote:
>> +void harts_early_init(void)
>> +{
>> + ulong *ptr;
>> + u8 *tmp;
>> + ulong len, remain;
>> + /*
>> + * Feature Disable CSR
>> + *
>> + * Clear feature disable CSR to '0' to turn on all features for
>> + * each core. This operation must be in M-mode.
>> + */
>> + if (CONFIG_IS_ENABLED(RISCV_MMODE))
>> + csr_write(CSR_U74_FEATURE_DISABLE, 0);
>> +
>> + /* clear L2 LIM memory
>> + * set __bss_end to 0x81F region to zero
>> + * The L2 Cache Controller supports ECC. ECC is applied to SRAM.
>> + * If it is not cleared, the ECC part is invalid, and an ECC error
>> + * will be reported when reading data.
>> + */
>> + ptr = (ulong *)&__bss_end;
>> + len = L2_LIM_MEM_END - (ulong)&__bss_end;
>> + remain = len % sizeof(ulong);
>> + len /= sizeof(ulong);
>> +
>> + while (len--)
>> + *ptr++ = 0;
>> +
>> + /* clear the remain bytes */
>> + if (remain) {
>> + tmp = (u8 *)ptr;
>> + while (remain--)
>> + *tmp++ = 0;
>> + }
>> +}
> Hi Yanhong, I know this is already merged, but it looks wrong to
> me.`harts_early_init`
> will be called by all harts in SPL. The per-hart stack sits between __bss_end
> and L2_LIM_MEM_END.
> Zeroing this region could overwrite the hart's stack, and other harts'
> stacks. The current
> implementation works likely because harts_early_init doesn't use any stack
> space, but it's up to
> the compiler and we can't guarantee that. If it were to save and restore `ra`
> register, then we
> would crash in function epilogue. Also, we are having data-races here,
> because harts are writing
> over each other's stack.
>
> My advice is that we should split the zeroing of L2 LIM into different places
> just before the
> region is to be used. For stacks, we can let each hart clearing its own
> stack, and for the malloc
> space, we can do so during malloc initialization. Doing so also gives us the
> benefit of catching
> the read of uninitialized data. In this approach, the L2_LIM_MEM_END macro is
> not needed anymore.
Hi，Bo Gan， I agree with you, there is some problem with the initialization of
the L2 LIM,
so, as you suggested, we should split the zeroing of L2 LIM into different
places.
Something like：
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 72adcefa0e..574ffc3d33 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -13,7 +13,6 @@
#include
#define CSR_U74_FEATURE_DISABLE0x7c1
-#define L2_LIM_MEM_END 0x81FUL
DECLARE_GLOBAL_DATA_PTR;
@@ -61,7 +60,7 @@ void harts_early_init(void)
{
ulong *ptr;
u8 *tmp;
- ulong len, remain;
+ ulong len, remain, init_end;
/*
* Feature Disable CSR
*
@@ -77,8 +76,10 @@ void harts_early_init(void)
* If it is not cleared, the ECC part is invalid, and an ECC error
* will be reported when reading data.
*/
+ init_end = CONFIG_SPL_STACK -CONFIG_VAL(SYS_MALLOC_F_LEN) - sizeof(*gd)
+ - CONFIG_NR_CPUS * BIT(CONFIG_STACK_SIZE_SHIFT);
ptr = (ulong *)&__bss_end;
- len = L2_LIM_MEM_END - (ulong)&__bss_end;
+ len = init_end - (ulong)&__bss_end;
remain = len % sizeof(ulong);
len /= sizeof(ulong);
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index dad22bfea8..46da9ec503 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -118,6 +118,20 @@ call_board_init_f_0:
mv sp, a0
#endif
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) && \
+ defined(CONFIG_STARFIVE_JH7110)
+
+ /* Set the stack region to zero */
+ li t0, 1
+ slli t1, t0, CONFIG_STACK_SIZE_SHIFT
+ mv t0, sp
+ sub t1, t0, t1
+clear_stack:
+ SREGzero, 0(t1)
+ addit1, t1, REGBYTES
+ blt t1, t0, clear_stack
+#endif
+
/* Configure proprietary settings and customized CSRs of harts */
call_harts_early_init:
jal harts_early_init
diff --git a/common/init/board_init.c b/common/init/board_init.c
index 96ffb79a98..46e4e4abc7 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -162,6 +162,7 @@ void board_init_f_init_reserve(ulong base)
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
/* go down one 'early malloc arena' */
gd->malloc_base = base;
+ memset((void *)base, 0, CONFIG_VAL(SYS_MALLOC_F_LEN));
#endif
if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
Re: [PATCH v5 00/17] Basic StarFive JH7110 RISC-V SoC support
On 2023/5/2 21:24, Heinrich Schuchardt wrote: > On 5/2/23 15:11, Andreas Schwab wrote: >> On Mai 02 2023, Matthias Brugger wrote: >> >>> I'm not sure I get your point. The devicetree will be passed to the kernel >>> via a pointer in a register, the kernel does not need to load the >>> devicetree into memory, it will use the one passed by U-Boot. >> >> But U-Boot needs to load it, and the kernel is the authority in >> providing it. >> > > To make it a bit clearer: > > Several U-Boot boot methods use the value of environment variable $fdtfile to > load a device-tree from file. The same holds true for the boot.scr file > created by Debian's flash-kernel package. > > A good solution would be to read the EEPROM to determine the exact board > version, to set $fdtfile accordingly and update U-Boots control dtb as needed. > The patcheset have implemented the reading of PCB versions from EEPROM and the configuration of gmac device tree nodes according to different PCB versions, which can achieve a bin file compatible with both versions 1.2A and 1.3B. The patcheset link: https://patchwork.ozlabs.org/project/uboot/cover/20230428022515.29393-1-yanhong.w...@starfivetech.com/ > Best regards > > Heinrich
[PATCH v3 11/11] configs: starfive: Enable ID EEPROM configuration
Enabled ID_EEPROM and I2C configuration for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
configs/starfive_visionfive2_defconfig | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
index dbd42e78d0..47559070c2 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -11,6 +11,7 @@ CONFIG_SPL_TEXT_BASE=0x800
CONFIG_SYS_PROMPT="StarFive #"
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x818
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -21,6 +22,7 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
+# CONFIG_OF_BOARD_FIXUP is not set
CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_BOOT=y
@@ -32,6 +34,8 @@ CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr
${fdtcontroladdr};"
CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_ID_EEPROM=y
+CONFIG_SYS_EEPROM_BUS_NUM=5
CONFIG_SPL_MAX_SIZE=0x4
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_BSS_START_ADDR=0x804
@@ -43,21 +47,34 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8000
CONFIG_SYS_SPL_MALLOC_SIZE=0x40
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
+CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_SIZE=512
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_TFTPPUT=y
+CONFIG_OF_BOARD=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_JH7110=y
-# CONFIG_I2C is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0X50
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
--
2.17.1
[PATCH v3 10/11] configs: starfive: Enable ethernet configuration for StarFive VisionFive2
Enable DWC_ETH_QOS and PHY_MOTORCOMM configuration to support ethernet
function for StarFive VisionFive 2 board,including versions 1.2A and
1.3B.
Signed-off-by: Yanhong Wang
---
configs/starfive_visionfive2_defconfig | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
index 550d0ff3ab..dbd42e78d0 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b"
+CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2"
CONFIG_SPL_TEXT_BASE=0x800
CONFIG_SYS_PROMPT="StarFive #"
CONFIG_DM_RESET=y
@@ -21,15 +21,15 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
-CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
+CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SPL_MAX_SIZE=0x4
@@ -52,6 +52,8 @@ CONFIG_SYS_BOOTM_LEN=0x400
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_TFTPPUT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_JH7110=y
@@ -65,6 +67,13 @@ CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_STARFIVE=y
+CONFIG_RGMII=y
+CONFIG_RMII=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
--
2.17.1
[PATCH v3 09/11] doc: board: starfive: Reword the make defconfig information
The defconfig file name for StarFive VisionFive2 has been changed, and
the documentation description has also changed.
Signed-off-by: Yanhong Wang
---
doc/board/starfive/visionfive2.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/doc/board/starfive/visionfive2.rst
b/doc/board/starfive/visionfive2.rst
index 22d2a31ff5..a2374486b5 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -60,7 +60,7 @@ Now build the U-Boot SPL and U-Boot proper
.. code-block:: console
cd
- make starfive_visionfive2_13b_defconfig
+ make starfive_visionfive2_defconfig
make
OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
@@ -111,7 +111,7 @@ Program the SD card
sudo cp u-boot.itb /mnt/
sudo cp Image.gz /mnt/
sudo cp initramfs.cpio.gz /mnt/
- sudo cp jh7110-starfive-visionfive-2-v1.3b.dtb /mnt/
+ sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
sudo umount /mnt
Booting
@@ -255,7 +255,7 @@ Sample boot log from StarFive VisionFive2 board
StarFive #fatload mmc 1:3 ${kernel_addr_r} Image.gz
6429424 bytes read in 394 ms (15.6 MiB/s)
- StarFive #fatload mmc 1:3 ${fdt_addr_r}
jh7110-starfive-visionfive-2-v1.3b.dtb
+ StarFive #fatload mmc 1:3 ${fdt_addr_r} jh7110-starfive-visionfive-2.dtb
11285 bytes read in 5 ms (2.2 MiB/s)
StarFive #fatload mmc 1:3 ${ramdisk_addr_r} initramfs.cpio.gz
152848495 bytes read in 9271 ms (15.7 MiB/s)
--
2.17.1
[PATCH v3 08/11] riscv: dts: starfive: Add support eeprom device tree node
Add support "atmel,24c04" eeprom for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
.../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 14 ++
arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 8 +++-
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 2afcec30b8..13f69da31e 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -67,6 +67,20 @@
};
};
+_pins {
+ bootph-pre-ram;
+ i2c-pins {
+ bootph-pre-ram;
+ };
+};
+
+ {
+ bootph-pre-ram;
+ eeprom@50 {
+ bootph-pre-ram;
+ };
+};
+
{
itb {
fit {
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index 0272369b24..710b082766 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -120,6 +120,12 @@
pinctrl-names = "default";
pinctrl-0 = <_pins>;
status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
};
{
@@ -350,4 +356,4 @@
reg = <0>;
};
};
-};
\ No newline at end of file
+};
--
2.17.1
[PATCH v3 07/11] riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B
The difference between 1.2A and 1.3B is dynamically configured according
to the PCB version, and there is no difference on the board device tree,
so the same DT file can be used.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/Makefile | 3 +-
... jh7110-starfive-visionfive-2-u-boot.dtsi} | 25 ++-
.../jh7110-starfive-visionfive-2-v1.2a.dts| 12
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 ---
...b.dts => jh7110-starfive-visionfive-2.dts} | 3 +-
5 files changed, 26 insertions(+), 86 deletions(-)
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi =>
jh7110-starfive-visionfive-2-u-boot.dtsi} (66%)
delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
delete mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts =>
jh7110-starfive-visionfive-2.dts} (65%)
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 79a58694f5..7940fe466d 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,8 +7,7 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.3b.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.2a.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
similarity index 66%
rename from arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
rename to arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 3c322c5c97..2afcec30b8 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
*/
#include "binman.dtsi"
@@ -67,3 +67,26 @@
};
};
+ {
+ itb {
+ fit {
+ images {
+ fdt-1 {
+ description = "NAME";
+ load = <0x4040>;
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ conf-1 {
+ fdt = "fdt-1";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
deleted file mode 100644
index b9d26d7af7..00
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-/dts-v1/;
-#include "jh7110-starfive-visionfive-2.dtsi"
-
-/ {
- model = "StarFive VisionFive 2 v1.2A";
- compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
-};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
deleted file mode 100644
index 3c322c5c97..00
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-#include "binman.dtsi"
-#include "jh7110-u-boot.dtsi"
-/ {
- chosen {
- bootph-pre-ram;
- };
-
- firmware {
- spi0 =
- bootph-pre-ram;
- };
-
- config {
- bootph-pre-ram;
- u-boot,spl-payload-offset = <0x10>;
- };
-
- memory@4000 {
- bootph-pre-ram;
- };
-};
-
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-
- nor-flash@0 {
- bootph-pre-ram;
- };
-};
-
- {
- bootph-pre-ram;
-};
-
-_pins {
- bootph-pre-ram;
- mmc0-pins-rest {
- bootph-pre-ra
[PATCH v3 06/11] riscv: dts: jh7110: Add ethernet device tree nodes
Add ethernet device tree node to support StarFive ethernet driver for
the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
---
.../dts/jh7110-starfive-visionfive-2.dtsi | 34 +
arch/riscv/dts/jh7110.dtsi| 69 +++
2 files changed, 103 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..0272369b24 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -17,6 +17,8 @@
i2c2 =
i2c5 =
i2c6 =
+ ethernet0 =
+ ethernet1 =
};
chosen {
@@ -317,3 +319,35 @@
assigned-clock-parents = <>;
assigned-clock-rates = <0>;
};
+
+ {
+ phy-handle = <>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+ {
+ phy-handle = <>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+ };
+};
\ No newline at end of file
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..58e332e9d7 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -235,6 +235,13 @@
#clock-cells = <0>;
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,lpi_en;
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <4>;
+ snps,blen = <256 128 64 32 0 0 0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -539,6 +546,68 @@
status = "disabled";
};
+ gmac0: ethernet@1603 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x1603 0x0 0x1>;
+ clocks = < JH7110_AONCLK_GMAC0_AXI>,
+< JH7110_AONCLK_GMAC0_AHB>,
+< JH7110_SYSCLK_GMAC0_PTP>,
+< JH7110_AONCLK_GMAC0_TX_INV>,
+< JH7110_SYSCLK_GMAC0_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = < JH7110_AONRST_GMAC0_AXI>,
+< JH7110_AONRST_GMAC0_AHB>;
+ reset-names = "stmmaceth", "ahb";
+ interrupts = <7>, <6>, <5>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <8>;
+ rx-fifo-depth = <2048>;
+ tx-fifo-depth = <2048>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <_axi_setup>;
+ snps,tso;
+ snps,en-tx-lpi-clockgating;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ starfive,syscon = <_syscon 0xc 0x12>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@1604 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x1604 0x0 0x1>;
+ clocks = < JH7110_SYSCLK_GMAC1_AXI>,
+< JH7110_SYSCLK_GMAC1_AHB>,
+< JH7110_SYSCLK_GMAC1_PTP>,
+< JH7110_SYSCLK_GMAC1_TX_INV>,
+< JH7110_SYSCLK_GMAC1_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = < JH7110_SYS
[PATCH v3 05/11] board: starfive: Dynamic configuration of DT for 1.2A and 1.3B
The main difference between StarFive VisionFive 2 1.2A and 1.3B is gmac.
You can read the PCB version of the current board by
get_pcb_revision_from_eeprom(), and then dynamically configure the
difference of gmac in spl_perform_fixups() according to different PCB
versions, so that one DT and one defconfig can support both 1.2A and
1.3B versions, which is more user-friendly.
Signed-off-by: Yanhong Wang
---
board/starfive/visionfive2/spl.c | 157 ++
.../visionfive2/starfive_visionfive2.c| 13 ++
2 files changed, 170 insertions(+)
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index db0b4cb433..7acd3995aa 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -5,16 +5,173 @@
*/
#include
+#include
#include
#include
#include
+#include
+#include
+#include
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
#define JH7110_CLK_CPU_ROOT_SHIFT 24
#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
+struct starfive_vf2_pro {
+ const char *path;
+ const char *name;
+ const char *value;
+};
+
+static const struct starfive_vf2_pro starfive_vera[] = {
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0", "rx-internal-delay-ps",
+ "1900"},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0", "tx-internal-delay-ps",
+ "1350"}
+};
+
+static const struct starfive_vf2_pro starfive_verb[] = {
+ {"/soc/ethernet@1603", "starfive,tx-use-rgmii-clk", NULL},
+ {"/soc/ethernet@1604", "starfive,tx-use-rgmii-clk", NULL},
+
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-1000-inverted", NULL},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "rx-internal-delay-ps", "1900"},
+ {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+ "tx-internal-delay-ps", "1500"},
+
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ { "/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "rx-internal-delay-ps", "0"},
+ {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+ "tx-internal-delay-ps", "0"},
+};
+
+void spl_fdt_fixup_version_a(void *fdt)
+{
+ u32 phandle;
+ u8 i;
+ int offset;
+ int ret;
+
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+ "StarFive VisionFive 2 v1.2A");
+
+ offset = fdt_path_offset(fdt, "/soc/clock-controller@1302");
+ phandle = fdt_get_phandle(fdt, offset);
+ offset = fdt_path_offset(fdt, "/soc/ethernet@1604");
+
+ fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks",
JH7110_SYSCLK_GMAC1_TX);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks",
JH7110_SYSCLK_GMAC1_RX);
+
+ fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_SYSCLK_GMAC1_RMII_RTX);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_SYSCLK_GMAC1_RMII_RTX);
+
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@1604"),
+ "phy-mode", "rmii");
+
+ for (i = 0; i < ARRAY_SIZE(starfive_vera); i++) {
+ offset = fdt_path_offset(fdt, starfive_vera[i].path);
+
+ if (starfive_vera[i].value)
+ ret = fdt_setprop_u32(fdt, offset,
starfive_vera[i].name,
+ dectoul(starfive_vera[i].value,
NULL));
+ else
+ ret = fdt_setprop_empty(fdt, offset,
starfive_vera[i].name);
+
+ if (ret) {
+ pr_err("%s set prop %s fail.\n", __func__,
starf
[PATCH v3 03/11] eeprom: starfive: Enable ID EEPROM configuration
Enabled ID_EEPROM configuration for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang
---
arch/riscv/include/asm/arch-jh7110/eeprom.h | 13 +
board/starfive/visionfive2/Makefile | 1 +
.../visionfive2/visionfive2-i2c-eeprom.c | 560 ++
3 files changed, 574 insertions(+)
create mode 100644 arch/riscv/include/asm/arch-jh7110/eeprom.h
create mode 100644 board/starfive/visionfive2/visionfive2-i2c-eeprom.c
diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h
b/arch/riscv/include/asm/arch-jh7110/eeprom.h
new file mode 100644
index 00..f354d5c60c
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#ifndef _ASM_RISCV_EEPROM_H
+#define _ASM_RISCV_EEPROM_H
+
+u8 get_pcb_revision_from_eeprom(void);
+u32 get_ddr_size_from_eeprom(void);
+
+#endif /* _ASM_RISCV_EEPROM_H */
diff --git a/board/starfive/visionfive2/Makefile
b/board/starfive/visionfive2/Makefile
index 66c854df39..c7ba4f7ed6 100644
--- a/board/starfive/visionfive2/Makefile
+++ b/board/starfive/visionfive2/Makefile
@@ -5,3 +5,4 @@
obj-y := starfive_visionfive2.o
obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_ID_EEPROM) += visionfive2-i2c-eeprom.o
diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
new file mode 100644
index 00..2d92ee52b6
--- /dev/null
+++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
@@ -0,0 +1,560 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define FORMAT_VERSION 0x2
+#define PCB_VERSION0xB1
+#define BOM_VERSION'A'
+/*
+ * BYTES_PER_EEPROM_PAGE: the 24FC04H datasheet says that data can
+ * only be written in page mode, which means 16 bytes at a time:
+ * 16-Byte Page Write Buffer
+ */
+#define BYTES_PER_EEPROM_PAGE 16
+
+/*
+ * EEPROM_WRITE_DELAY_MS: the 24FC04H datasheet says it takes up to
+ * 5ms to complete a given write:
+ * Write Cycle Time (byte or page) ro Page Write Time 5 ms, Maximum
+ */
+#define EEPROM_WRITE_DELAY_MS 5000
+/*
+ * StarFive OUI. Registration Date is 20xx-xx-xx
+ */
+#define STARFIVE_OUI_PREFIX"6C:CF:39:"
+#define STARFIVE_DEFAULT_MAC0 "6C:CF:39:6C:DE:AD"
+#define STARFIVE_DEFAULT_MAC1 "6C:CF:39:6C:DE:AE"
+
+/* Magic number at the first four bytes of EEPROM HATs */
+#define STARFIVE_EEPROM_HATS_SIG "SFVF" /* StarFive VisionFive */
+
+#define STARFIVE_EEPROM_HATS_SIZE_MAX 256 /* Header + Atom1&4(v1) */
+#define STARFIVE_EEPROM_WP_OFFSET 0 /* Read only field */
+#define STARFIVE_EEPROM_ATOM1_PSTR "VF7110A1-2228-D008E000-0001\0"
+#define STARFIVE_EEPROM_ATOM1_PSTR_SIZE32
+#define STARFIVE_EEPROM_ATOM1_SN_OFFSET23
+#define STARFIVE_EEPROM_ATOM1_VSTR "StarFive Technology Co., Ltd.\0\0\0"
+#define STARFIVE_EEPROM_ATOM1_VSTR_SIZE32
+
+#define MAGIC_NUMBER_BYTES 4
+#define MAC_ADDR_BYTES 6
+#define MAC_ADDR_STRLEN17
+
+/*
+ * Atom Types
+ * 0x = invalid
+ * 0x0001 = vendor info
+ * 0x0002 = GPIO map
+ * 0x0003 = Linux device tree blob
+ * 0x0004 = manufacturer custom data
+ * 0x0005-0xfffe = reserved for future use
+ * 0x = invalid
+ */
+
+#define HATS_ATOM_INVALID 0x
+#define HATS_ATOM_VENDOR 0x0001
+#define HATS_ATOM_GPIO 0x0002
+#define HATS_ATOM_DTB 0x0003
+#define HATS_ATOM_CUSTOM 0x0004
+#define HATS_ATOM_INVALID_END 0x
+
+struct eeprom_header {
+ char signature[MAGIC_NUMBER_BYTES]; /* ASCII table signature */
+ u8 version; /* EEPROM data format version */
+ /* (0x00 reserved, 0x01 = first version) */
+ u8 reversed;/* 0x00, Reserved field */
+ u16 numatoms; /* total atoms in EEPROM */
+ u32 eeplen; /* total length in bytes of all eeprom data */
+ /* (including this header) */
+};
+
+struct eeprom_atom_header {
+ u16 type;
+ u16 count;
+ u32 dlen;
+};
+
+struct eeprom_atom1_data {
+ u8 uuid[16];
+ u16 pid;
+ u16 pver;
+ u8 vslen;
+ u8 pslen;
+ uchar vstr[STARFIVE_EEPROM_ATOM1_VSTR_SIZE];
+ uchar pstr[STARFIVE_EEPROM_ATOM1_PSTR_SIZE]; /* product SN */
+};
+
+struct starfive_eeprom_atom1 {
+ struct eeprom_atom_header header;
+ struct eeprom_atom1_data data;
+ u16 crc;
+};
+
+struct eeprom_atom4_data {
+ u16 version;
+ u8 pcb_revision;/* PCB version */
+ u8 bom_revision;/* BOM version */
+ u8 mac0_addr[MAC_ADDR_B
[PATCH v3 04/11] ram: starfive: Read memory size information from EEPROM
StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of
DDR capacity includes 2G/4G/8G, a DT can not support multiple
capacities, so the capacity size information is recorded to EEPROM, when
DDR initialization required capacity size information is read from
EEPROM.
If there is no information in EEPROM, it is initialized with the default
size defined in DT.
Signed-off-by: Yanhong Wang
---
arch/riscv/cpu/jh7110/spl.c | 32 -
drivers/ram/starfive/starfive_ddr.c | 2 --
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 104f0fe949..72adcefa0e 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -3,19 +3,49 @@
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Author: Yanhong Wang
*/
-
+#include
+#include
#include
#include
#include
+#include
#include
+#include
#define CSR_U74_FEATURE_DISABLE0x7c1
#define L2_LIM_MEM_END 0x81FUL
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool check_ddr_size(phys_size_t size)
+{
+ switch (size) {
+ case SZ_2:
+ case SZ_4:
+ case SZ_8:
+ case SZ_16:
+ return true;
+ default:
+ return false;
+ }
+}
+
int spl_soc_init(void)
{
int ret;
struct udevice *dev;
+ phys_size_t size;
+
+ ret = fdtdec_setup_mem_size_base();
+ if (ret)
+ return ret;
+
+ /* Read the definition of the DDR size from eeprom, and if not,
+* use the definition in DT
+*/
+ size = (get_ddr_size_from_eeprom() >> 16) & 0xFF;
+ if (check_ddr_size(size))
+ gd->ram_size = size << 30;
/* DDR init */
ret = uclass_get_device(UCLASS_RAM, 0, );
diff --git a/drivers/ram/starfive/starfive_ddr.c
b/drivers/ram/starfive/starfive_ddr.c
index 553f2ce6f4..a0a3d6b33d 100644
--- a/drivers/ram/starfive/starfive_ddr.c
+++ b/drivers/ram/starfive/starfive_ddr.c
@@ -72,8 +72,6 @@ static int starfive_ddr_probe(struct udevice *dev)
u64 rate;
int ret;
- /* Read memory base and size from DT */
- fdtdec_setup_mem_size_base();
priv->info.base = gd->ram_base;
priv->info.size = gd->ram_size;
--
2.17.1
[PATCH v3 02/11] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.
Signed-off-by: Yanhong Wang
---
drivers/net/Kconfig| 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c | 249 +
5 files changed, 264 insertions(+)
create mode 100644 drivers/net/dwc_eth_qos_starfive.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 09039a283e..5540f0ea18 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -249,6 +249,13 @@ config DWC_ETH_QOS_QCOM
The Synopsys Designware Ethernet QOS IP block with specific
configuration used in Qcom QCS404 SoC.
+config DWC_ETH_QOS_STARFIVE
+ bool "Synopsys DWC Ethernet QOS device support for STARFIVE"
+ depends on DWC_ETH_QOS
+ help
+ The Synopsys Designware Ethernet QOS IP block with specific
+ configuration used in STARFIVE JH7110 soc.
+
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 46a40e2ed9..d4af253b6f 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
+obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index ec58697b31..8060a4e782 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1713,6 +1713,12 @@ static const struct udevice_id eqos_ids[] = {
.data = (ulong)_qcom_config
},
#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
+ {
+ .compatible = "starfive,jh7110-dwmac",
+ .data = (ulong)_jh7110_config
+ },
+#endif
{ }
};
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index fddbe9336c..a6b719af80 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -289,3 +289,4 @@ int eqos_null_ops(struct udevice *dev);
extern struct eqos_config eqos_imx_config;
extern struct eqos_config eqos_qcom_config;
+extern struct eqos_config eqos_jh7110_config;
diff --git a/drivers/net/dwc_eth_qos_starfive.c
b/drivers/net/dwc_eth_qos_starfive.c
new file mode 100644
index 00..5be8ac0f1a
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_starfive.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dwc_eth_qos.h"
+
+#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
+#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
+#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
+
+struct starfive_platform_data {
+ struct regmap *regmap;
+ struct reset_ctl_bulk resets;
+ struct clk_bulk clks;
+ phy_interface_t interface;
+ u32 offset;
+ u32 shift;
+ bool tx_use_rgmii_clk;
+};
+
+static int eqos_interface_init_jh7110(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data = pdata->priv_pdata;
+ struct ofnode_phandle_args args;
+ unsigned int mode;
+ int ret;
+
+ switch (data->interface) {
+ case PHY_INTERFACE_MODE_RMII:
+ mode = STARFIVE_DWMAC_PHY_INFT_RMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
+2, 0, );
+ if (ret)
+ return ret;
+
+ if (args.args_count != 2)
+ return -EINVAL;
+
+ data->offset = args.args[0];
+ data->shift = args.args[1];
+ data->regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
+ if (IS_ERR(data->regmap)) {
+ ret = PTR_ERR(data->regmap);
+ pr_err("Failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ return regmap_update_bits(data->regmap, data->offset,
+ STARFIVE_DWMAC_PHY_INFT_FIELD << data->shift,
+ mode << data->shift);
+}
+
+static int eqos_set_tx_clk_speed_jh7110(struct udevice *dev)
+{
+
[PATCH v3 01/11] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have verified the driver on StarFive VisionFive2 board. Signed-off-by: Yanhong Wang Reviewed-by: Ramon Fried --- drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile| 1 + drivers/net/phy/motorcomm.c | 437 3 files changed, 444 insertions(+) create mode 100644 drivers/net/phy/motorcomm.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 24158776f5..0c3c39a550 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -220,6 +220,12 @@ config PHY_MICREL_KSZ8XXX endif # PHY_MICREL +config PHY_MOTORCOMM + tristate "Motorcomm PHYs" + help + Enables support for Motorcomm network PHYs. + Currently supports the YT8531 Gigabit Ethernet PHYs. + config PHY_MSCC bool "Microsemi Corp Ethernet PHYs support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 85d17f109c..2487f366e1 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o +obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c new file mode 100644 index 00..e822fd76f2 --- /dev/null +++ b/drivers/net/phy/motorcomm.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Motorcomm 8531 PHY driver. + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include + +#define PHY_ID_YT8531 0x4f51e91b +#define PHY_ID_MASKGENMASK(31, 0) + +/* Extended Register's Address Offset Register */ +#define YTPHY_PAGE_SELECT 0x1E + +/* Extended Register's Data Register */ +#define YTPHY_PAGE_DATA0x1F + +#define YTPHY_SYNCE_CFG_REG0xA012 + +#define YTPHY_DTS_OUTPUT_CLK_DIS 0 +#define YTPHY_DTS_OUTPUT_CLK_25M 2500 +#define YTPHY_DTS_OUTPUT_CLK_125M 12500 + +#define YT8531_SCR_SYNCE_ENABLEBIT(6) +/* 1b0 output 25m clock *default* + * 1b1 output 125m clock + */ +#define YT8531_SCR_CLK_FRE_SEL_125MBIT(4) +#define YT8531_SCR_CLK_SRC_MASKGENMASK(3, 1) +#define YT8531_SCR_CLK_SRC_PLL_125M0 +#define YT8531_SCR_CLK_SRC_UTP_RX 1 +#define YT8531_SCR_CLK_SRC_SDS_RX 2 +#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 +#define YT8531_SCR_CLK_SRC_REF_25M 4 +#define YT8531_SCR_CLK_SRC_SSC_25M 5 + +/* 1b0 use original tx_clk_rgmii *default* + * 1b1 use inverted tx_clk_rgmii. + */ +#define YT8531_RC1R_TX_CLK_SEL_INVERTEDBIT(14) +#define YT8531_RC1R_RX_DELAY_MASK GENMASK(13, 10) +#define YT8531_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) +#define YT8531_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) +#define YT8531_RC1R_RGMII_0_000_NS 0 +#define YT8531_RC1R_RGMII_0_150_NS 1 +#define YT8531_RC1R_RGMII_0_300_NS 2 +#define YT8531_RC1R_RGMII_0_450_NS 3 +#define YT8531_RC1R_RGMII_0_600_NS 4 +#define YT8531_RC1R_RGMII_0_750_NS 5 +#define YT8531_RC1R_RGMII_0_900_NS 6 +#define YT8531_RC1R_RGMII_1_050_NS 7 +#define YT8531_RC1R_RGMII_1_200_NS 8 +#define YT8531_RC1R_RGMII_1_350_NS 9 +#define YT8531_RC1R_RGMII_1_500_NS 10 +#define YT8531_RC1R_RGMII_1_650_NS 11 +#define YT8531_RC1R_RGMII_1_800_NS 12 +#define YT8531_RC1R_RGMII_1_950_NS 13 +#define YT8531_RC1R_RGMII_2_100_NS 14 +#define YT8531_RC1R_RGMII_2_250_NS 15 + +/* Phy gmii clock gating Register */ +#define YT8531_CLOCK_GATING_REG0xC +#define YT8531_CGR_RX_CLK_EN BIT(12) + +/* Specific Status Register */ +#define YTPHY_SPECIFIC_STATUS_REG 0x11 +#define YTPHY_DUPLEX_MASK BIT(13) +#define YTPHY_DUPLEX_SHIFT 13 +#define YTPHY_SPEED_MODE_MASK GENMASK(15, 14) +#define YTPHY_SPEED_MODE_SHIFT 14 + +#define YT8531_EXTREG_SLEEP_CONTROL1_REG 0x27 +#define YT8531_ESC1R_SLEEP_SW BIT(15) +#define YT8531_ESC1R_PLLON_SLP BIT(14) + +#define YT8531_RGMII_CONFIG1_REG 0xA003 + +#define YT8531_CHIP_CONFIG_REG 0xA001 +#define YT8531_CCR_SW_RST BIT(15) +/* 1b0 disable 1.9ns rxc clock delay *default* + * 1b1 enable 1.9ns rxc clock delay + */ +#define Y
[PATCH v3 00/11] Add ethernet driver for StarFive JH7110 SoC
This series of patches base on the latest branch/master,and
adds ethernet support for the StarFive JH7110 RISC-V SoC.
The series includes EEPROM, PHY and MAC drivers. The PHY model is
YT8531 (from Motorcomm Inc), and the MAC version is dwmac-5.20
(from Synopsys DesignWare).
The implementation of the phy driver is ported from linux, but it
has been adjusted for the u-boot framework.
EEPROM stores board-related information, such as DDR capacity,
PCB version, MAC address, etc.
The main difference between StarFive VisionFive 2 1.2A and 1.3B is
gmac, but the difference in gmac is not defined in DT, but reads the
PCB version from EEPROM, and then dynamically configures the difference
of gmac according to different PCB versions, which is compatible
with 1.2A and 1.3B versions, which is more user-friendly.
The PHY and MAC driver has been tested on the StarFive VisionFive 2 1.2A
and 1.3B boards and works normally.
For more information and support,you can visit RVspace wiki[1].
[1] https://wiki.rvspace.org/
v3:
- Added EEPROM support.
- Combine the board device tree of 1.2A and 1.3B into one.
- Removed the delay configuration of gmac phy clock from DT.
- Dynamically configure gmac differences of 1.2A and 1.3B to DT according to
the PCB version.
- DDR capacity information is read from EEPROM first, if not, it is defined by
default in DT.
v2:
- Reworded the phy driver. Added platform private data struct to save the
configuration data read from dts.
- Reworded the MAC driver. Added platform private data struct to save the
configuration data read from dts.
Previous versions:
v1 -
https://patchwork.ozlabs.org/project/uboot/cover/20230317010536.17860-1-yanhong.w...@starfivetech.com/
v2 -
https://patchwork.ozlabs.org/project/uboot/cover/20230329102720.25439-1-yanhong.w...@starfivetech.com/
Yanhong Wang (11):
net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
net: dwc_eth_qos: Add StarFive ethernet driver glue layer
eeprom: starfive: Enable ID EEPROM configuration
ram: starfive: Read memory size information from EEPROM
board: starfive: Dynamic configuration of DT for 1.2A and 1.3B
riscv: dts: jh7110: Add ethernet device tree nodes
riscv: dts: jh7110: Combine the board device tree files of 1.2A and
1.3B
riscv: dts: starfive: Add support eeprom device tree node
doc: board: starfive: Reword the make defconfig information
configs: starfive: Enable ethernet configuration for StarFive
VisionFive2
configs: starfive: Enable ID EEPROM configuration
arch/riscv/cpu/jh7110/spl.c | 32 +-
arch/riscv/dts/Makefile | 3 +-
... jh7110-starfive-visionfive-2-u-boot.dtsi} | 39 +-
.../jh7110-starfive-visionfive-2-v1.2a.dts| 12 -
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 ---
...b.dts => jh7110-starfive-visionfive-2.dts} | 3 +-
.../dts/jh7110-starfive-visionfive-2.dtsi | 40 ++
arch/riscv/dts/jh7110.dtsi| 69 +++
arch/riscv/include/asm/arch-jh7110/eeprom.h | 13 +
board/starfive/visionfive2/Makefile | 1 +
board/starfive/visionfive2/spl.c | 157 +
.../visionfive2/starfive_visionfive2.c| 13 +
.../visionfive2/visionfive2-i2c-eeprom.c | 560 ++
configs/starfive_visionfive2_defconfig| 34 +-
doc/board/starfive/visionfive2.rst| 6 +-
drivers/net/Kconfig | 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c| 249
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/motorcomm.c | 437 ++
drivers/ram/starfive/starfive_ddr.c | 2 -
24 files changed, 1665 insertions(+), 96 deletions(-)
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi =>
jh7110-starfive-visionfive-2-u-boot.dtsi} (58%)
delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
delete mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts =>
jh7110-starfive-visionfive-2.dts} (65%)
create mode 100644 arch/riscv/include/asm/arch-jh7110/eeprom.h
create mode 100644 board/starfive/visionfive2/visionfive2-i2c-eeprom.c
create mode 100644 drivers/net/dwc_eth_qos_starfive.c
create mode 100644 drivers/net/phy/motorcomm.c
base-commit: c9c2c95d4cd27fe0cd41fe13a863899d268f973c
prerequisite-patch-id: dee366bfbaa4e2bebd4b874d187d267b427a812d
--
2.17.1
[PATCH] board: starfive: Fixed errors reported when executing get_maintainer.pl
Fixed errors reported when executing 'scripts/get_maintainer.pl -f configs/starfive_visionfive2_defconfig'. Invalid MAINTAINERS address: 'startfive' Signed-off-by: Yanhong Wang --- board/starfive/visionfive2/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS index c5369086d8..600ff9575b 100644 --- a/board/starfive/visionfive2/MAINTAINERS +++ b/board/starfive/visionfive2/MAINTAINERS @@ -1,5 +1,5 @@ STARFIVE JH7110 VISIONFIVE2 BOARD -M: startfive +M: Yanhong Wang S: Maintained F: arch/riscv/include/asm/arch-jh7110/ F: board/starfive/visionfive2/ -- 2.17.1
Re: [RFC] riscv: visionfive2: use OF_BOARD_SETUP
On 2023/4/20 15:43, Torsten Duwe wrote:
> Hi Leo, thanks for the quick reply!
>
> On Thu, 20 Apr 2023 06:33:57 +
> Leo Liang wrote:
>
>> Hi, Torsten, Matthias,
>>
>> On Wed, Apr 19, 2023 at 02:34:03PM +0200, Matthias Brugger wrote:
>> >
>> >
>> > On 19/04/2023 13:28, Torsten Duwe wrote:
>
>> > > This is only a proof of concept; let me know if you like it and I
>> > > can add the other 12 DT patches to adjust_for_rev13b(), or maybe
>> > > start with 1.3b as the default and go the other way, or something
>> > > in between.
>
>> LGTM as well!
>
> Thank you very much! Again, this is only a PoC; if you agree with the
> concept, I clean it up and fill in the complete DT patching.
>
> Questions: shall I default to 1.3B and patch older 1.2A, or vice versa,
> or do it like your (starfive) patch set and start with something
> "neutral" and then patch both ways? And, more important, what is the
> correct interpretation of the board revision byte -- I assume it's
> offset 0x76 in the EEPROM? Is it always? Is ">= 0xB2" the correct
> discriminator?
>
Hi Torsten,
The attached is the driver of VisionFive2 EEPROM, which is only a preliminary
draft,
and it is still being improved [the function has been tested, it is normal],
and
it contains the definition of the EEPROM data format.
> Torsten// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023 StarFive Technology Co., Ltd.
* Author: Yanhong Wang
*/
#include
#include
#include
#include
#include
#include
#include
#define FORMAT_VERSION 0x2
#define PCB_VERSION 0xB1
#define BOM_VERSION 'A'
/*
* BYTES_PER_EEPROM_PAGE: the 24FC04H datasheet says that data can
* only be written in page mode, which means 16 bytes at a time:
* 16-Byte Page Write Buffer
*/
#define BYTES_PER_EEPROM_PAGE 16
/*
* EEPROM_WRITE_DELAY_MS: the 24FC04H datasheet says it takes up to
* 5ms to complete a given write:
* Write Cycle Time (byte or page) ro Page Write Time 5 ms, Maximum
*/
#define EEPROM_WRITE_DELAY_MS 5000
/*
* StarFive OUI. Registration Date is 20xx-xx-xx
*/
#define STARFIVE_OUI_PREFIX "6C:CF:39:"
#define STARFIVE_DEFAULT_MAC0 "6C:CF:39:6C:DE:AD"
#define STARFIVE_DEFAULT_MAC1 "6C:CF:39:6C:DE:AE"
/* Magic number at the first four bytes of EEPROM HATs */
#define STARFIVE_EEPROM_HATS_SIG"SFVF" /* StarFive VisionFive */
#define STARFIVE_EEPROM_HATS_SIZE_MAX 256 /* Header + Atom1&4(v1) */
#define STARFIVE_EEPROM_WP_OFFSET 0 /* Read only field */
#define STARFIVE_EEPROM_ATOM1_PSTR "VF7110A1-2228-D008E000-0001\0"
#define STARFIVE_EEPROM_ATOM1_PSTR_SIZE 32
#define STARFIVE_EEPROM_ATOM1_SN_OFFSET 23
#define STARFIVE_EEPROM_ATOM1_VSTR "StarFive Technology Co., Ltd.\0\0\0"
#define STARFIVE_EEPROM_ATOM1_VSTR_SIZE 32
#define MAGIC_NUMBER_BYTES 4
#define MAC_ADDR_BYTES 6
#define MAC_ADDR_STRLEN 17
/*
* Atom Types
* 0x = invalid
* 0x0001 = vendor info
* 0x0002 = GPIO map
* 0x0003 = Linux device tree blob
* 0x0004 = manufacturer custom data
* 0x0005-0xfffe = reserved for future use
* 0x = invalid
*/
#define HATS_ATOM_INVALID 0x
#define HATS_ATOM_VENDOR0x0001
#define HATS_ATOM_GPIO 0x0002
#define HATS_ATOM_DTB 0x0003
#define HATS_ATOM_CUSTOM0x0004
#define HATS_ATOM_INVALID_END 0x
struct eeprom_header {
char signature[MAGIC_NUMBER_BYTES]; /* ASCII table signature */
u8 version; /* EEPROM data format version */
/* (0x00 reserved, 0x01 = first version) */
u8 reversed;/* 0x00, Reserved field */
u16 numatoms; /* total atoms in EEPROM */
u32 eeplen; /* total length in bytes of all eeprom data */
/* (including this header) */
};
struct eeprom_atom_header {
u16 type;
u16 count;
u32 dlen;
};
struct eeprom_atom1_data {
u8 uuid[16];
u16 pid;
u16 pver;
u8 vslen;
u8 pslen;
uchar vstr[STARFIVE_EEPROM_ATOM1_VSTR_SIZE];
uchar pstr[STARFIVE_EEPROM_ATOM1_PSTR_SIZE]; /* product SN */
};
struct starfive_eeprom_atom1 {
struct eeprom_atom_header header;
struct eeprom_atom1_data data;
u16 crc;
};
struct eeprom_atom4_data {
u16 version;
u8 pcb_revision;/* PCB version */
u8 bom_revision;/* BOM version */
u8 mac0_addr[MAC_ADDR_BYTES]; /* Ethernet0 MAC */
u8 mac1_addr[MAC_ADDR_BYTES]; /* Ethernet1 MAC */
u8 reserved[2];
};
struct starfive_eeprom_atom4 {
struct eeprom_atom_header he
Re: [PATCH v5 00/17] Basic StarFive JH7110 RISC-V SoC support
On 2023/4/13 17:03, Torsten Duwe wrote: > On Thu, 13 Apr 2023 10:05:28 +0800 > yanhong wang wrote: > >> the definition of DT refers to Linux and is consistent with the definition >> framework of Linux. > > This is one of the desired goals, to avoid confusion, usually. But note there > are already the > -u-boot.dtsi files; in this case it would be vice-versa: U-Boot could be > simple, the kernel > required a different treatment. As long as the resulting tree matches the > hardware! > >> The difference between 1.2A and 1.3B is the PHY type and phy clock delay >> configuration, >> which are reflected in DT, and the difference in defconfig is the >> configuration of the DT file. >> >> Is defconfig defined separately or merged? > > You are the implementer, this is your decision. You make a proposal, and it > will get accepted > or not. We only make suggestions, with the intention to improve the code. > Thanks. A defconfig matches a piece of hardware, which is more developer-friendly and less confusing, so defconfig is better defined separately. >> The EEPROM is being prepared and will be submitted as soon as possible. Is >> it necessary to >> incorporate EEPROM into this submission? >> >> When eeprom is supported, the MAC address will be read from eeprom. The >> board reversion >> can be read from eeprom, but phy clock delay configuration cannot be read >> from eeprom, only in DT. > > But the board revision number in EEPROM can be used to differentiate between > 1.2 and 1.3, right? > Yes, board reversion read from eeprom can distinguish between 1.2A and 1.3B. 1.2A and 1.3B are two sets of hardware, and the differences between the hardware are defined by DT, which is more concise and clear. > When I look at the code and my test results, this is my proposal to pull this > in, in order to > simplify things and avoid duplication. Whether you do so is up to you, see > above. Let me recap: > > * the device tree *must* match the hardware at hand. > > * the differences are minor and could be patched, Copy is error prone > and causes extra work. > > It is my firm conviction that this patch set does not introduce hardware > variants, and it would be > the task of the ethernet driver patch set to split the code (DT+defconfig) OR > to provide a patching > method. Maybe I find a few cycles to look at the EEPROM. > > Torsten
Re: [PATCH v5 00/17] Basic StarFive JH7110 RISC-V SoC support
On 2023/4/13 1:50, Torsten Duwe wrote: > On Wed, 29 Mar 2023 18:16:20 +0800 > yanhong wang wrote: > >> >> >> On 2023/3/29 17:41, Torsten Duwe wrote: >> > On Wed, 29 Mar 2023 11:42:07 +0800 >> > Yanhong Wang wrote: >> > >> >> v5: >> > [...] >> >> - Splitted starfive_visionfive2_defconfig into >> >> starfive_visionfive2_12a_defconfig >> >> and starfive_visionfive2_13b_defconfig. >> > >> > Is this really necessary? It puts another burden on people building U-Boot, >> > distribution networks, and last but not least users, who will need to pick >> > the >> > correct binary blob, after trying to find out which board they actually >> > have. >> > >> > Even past versions can detect the installed RAM correctly and will modify >> > the DT accordingly, I assume? Why not make an inquiry on GMAC1_MDIO to tell >> > whether it's a YT8512C (->v1.2A) or another YT8531C (->v1.3B), in the >> > ethernet >> > patch set, and likewise update the device tree dynamically then? > > At a second look, this is a bit tricky: a device tree is already needed for > the network > initialisation. That one would need to be good enough to get at the PHYs, and > flexible > enough to be patched into shape later. But see below... > >> There is only one defconfig in V4, and dts is separate for versions 1.2a and >> 1.3b. >> Andreas Schwab suggested that defconfig is also defined separately, so the >> definition >> of defconfig in V5 is also separated. >> >> The discussion process as follows: >> >> https://patchwork.ozlabs.org/project/uboot/patch/20230316025332.3297-18-yanhong.w...@starfivetech.com/ >> >> Do you have any better suggestion on whether defconfig is defined separately? > > Andreas' concern is the match between the device tree and the actual hardware, > as far as it matters for (driver) software. So, different hardware => > different DT. > > However, AFAICT there is no difference until network comes into play, right? > And even > then, it is only the types of PHYs and their wiring, correct? > Yes, before gmac and phy were added, everything was the same except for 'model', but the definition of DT refers to Linux and is consistent with the definition framework of Linux. The difference between 1.2A and 1.3B is the PHY type and phy clock delay configuration, which are reflected in DT, and the difference in defconfig is the configuration of the DT file. Is defconfig defined separately or merged? > From the other thread: can we enable the EEPROM reading code first, to get > the proper > MAC addresses for the hardware, and also read the board revision, similar to > get_pcb_revision_from_eeprom() from the HiFive unmatched? And then use fixup > functions > from common/fdt_support.c to adapt the device tree details to the detected > board? > The EEPROM is being prepared and will be submitted as soon as possible. Is it necessary to incorporate EEPROM into this submission? When eeprom is supported, the MAC address will be read from eeprom. The board reversion can be read from eeprom, but phy clock delay configuration cannot be read from eeprom, only in DT. > Torsten
Re: [PATCH v2 2/5] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
On 2023/3/30 4:02, Simon Glass wrote:
> Hi Yanhong,
>
> On Wed, 29 Mar 2023 at 23:29, Yanhong Wang
> wrote:
>>
>> The StarFive ETHQOS hardware has its own clock and reset,so add a
>> corresponding glue driver to configure them.
>>
>> Signed-off-by: Yanhong Wang
>> ---
>> drivers/net/Kconfig| 7 +
>> drivers/net/Makefile | 1 +
>> drivers/net/dwc_eth_qos.c | 6 +
>> drivers/net/dwc_eth_qos.h | 1 +
>> drivers/net/dwc_eth_qos_starfive.c | 249 +
>> 5 files changed, 264 insertions(+)
>> create mode 100644 drivers/net/dwc_eth_qos_starfive.c
>>
>
> [..]
>
>> +static struct eqos_ops eqos_jh7110_ops = {
>> + .eqos_inval_desc = eqos_inval_desc_generic,
>> + .eqos_flush_desc = eqos_flush_desc_generic,
>> + .eqos_inval_buffer = eqos_inval_buffer_generic,
>> + .eqos_flush_buffer = eqos_flush_buffer_generic,
>> + .eqos_probe_resources = eqos_probe_resources_jh7110,
>> + .eqos_remove_resources = eqos_remove_resources_jh7110,
>> + .eqos_stop_resets = eqos_stop_resets_jh7110,
>> + .eqos_start_resets = eqos_start_resets_jh7110,
>> + .eqos_stop_clks = eqos_stop_clks_jh7110,
>> + .eqos_start_clks = eqos_start_clks_jh7110,
>> + .eqos_calibrate_pads = eqos_null_ops,
>> + .eqos_disable_calibration = eqos_null_ops,
>> + .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_jh7110,
>> + .eqos_get_enetaddr = eqos_null_ops,
>> + .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_jh7110
>> +};
>
> What is eqos_ops? Why is this layer needed in U-Boot?
>
The JH7110 uses the Synopsys Designware Ethernet QOS (Quality Of Service) IP
block,
the driver implementation uses 'dwc_eth_qos.c,' but there are some differences
in clock and reset, so there is a corresponding glue layer. This glue layer
references
the implementation of 'dwc_eth_qos_imx.c' and 'dwc_eth_qos_qcom.c'.
> Can you not use driver model directly?
> If you use the driver model directly, many of the implementations are the
> same
as "dwc_eth_qos.c", so to avoid duplicate implementations, just add the glue
layer.
> Regards,
> Simon
[PATCH v2 2/5] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.
Signed-off-by: Yanhong Wang
---
drivers/net/Kconfig| 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_starfive.c | 249 +
5 files changed, 264 insertions(+)
create mode 100644 drivers/net/dwc_eth_qos_starfive.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index ceadee98a1..161289d00f 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -249,6 +249,13 @@ config DWC_ETH_QOS_QCOM
The Synopsys Designware Ethernet QOS IP block with specific
configuration used in Qcom QCS404 SoC.
+config DWC_ETH_QOS_STARFIVE
+ bool "Synopsys DWC Ethernet QOS device support for STARFIVE"
+ depends on DWC_ETH_QOS
+ help
+ The Synopsys Designware Ethernet QOS IP block with specific
+ configuration used in STARFIVE JH7110 soc.
+
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 75daa5e694..69af678757 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
+obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 112deb546d..9aecd56e73 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1718,6 +1718,12 @@ static const struct udevice_id eqos_ids[] = {
.data = (ulong)_qcom_config
},
#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
+ {
+ .compatible = "starfive,jh7110-dwmac",
+ .data = (ulong)_jh7110_config
+ },
+#endif
{ }
};
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index fddbe9336c..a6b719af80 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -289,3 +289,4 @@ int eqos_null_ops(struct udevice *dev);
extern struct eqos_config eqos_imx_config;
extern struct eqos_config eqos_qcom_config;
+extern struct eqos_config eqos_jh7110_config;
diff --git a/drivers/net/dwc_eth_qos_starfive.c
b/drivers/net/dwc_eth_qos_starfive.c
new file mode 100644
index 00..5be8ac0f1a
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_starfive.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dwc_eth_qos.h"
+
+#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
+#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
+#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
+
+struct starfive_platform_data {
+ struct regmap *regmap;
+ struct reset_ctl_bulk resets;
+ struct clk_bulk clks;
+ phy_interface_t interface;
+ u32 offset;
+ u32 shift;
+ bool tx_use_rgmii_clk;
+};
+
+static int eqos_interface_init_jh7110(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct starfive_platform_data *data = pdata->priv_pdata;
+ struct ofnode_phandle_args args;
+ unsigned int mode;
+ int ret;
+
+ switch (data->interface) {
+ case PHY_INTERFACE_MODE_RMII:
+ mode = STARFIVE_DWMAC_PHY_INFT_RMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
+2, 0, );
+ if (ret)
+ return ret;
+
+ if (args.args_count != 2)
+ return -EINVAL;
+
+ data->offset = args.args[0];
+ data->shift = args.args[1];
+ data->regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
+ if (IS_ERR(data->regmap)) {
+ ret = PTR_ERR(data->regmap);
+ pr_err("Failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ return regmap_update_bits(data->regmap, data->offset,
+ STARFIVE_DWMAC_PHY_INFT_FIELD << data->shift,
+ mode << data->shift);
+}
+
+static int eqos_set_tx_clk_speed_jh7110(struct udevice *dev)
+{
+
[PATCH v2 1/5] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have verified the driver on StarFive VisionFive2 board. Signed-off-by: Yanhong Wang --- drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile| 1 + drivers/net/phy/motorcomm.c | 450 drivers/net/phy/phy.c | 4 +- include/phy.h | 1 + 5 files changed, 461 insertions(+), 1 deletion(-) create mode 100644 drivers/net/phy/motorcomm.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 5eaff053a0..aba718566a 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -212,6 +212,12 @@ config PHY_MICREL_KSZ8XXX endif # PHY_MICREL +config PHY_MOTORCOMM + tristate "Motorcomm PHYs" + help + Enables support for Motorcomm network PHYs. + Currently supports the YT8531 Gigabit Ethernet PHYs. + config PHY_MSCC bool "Microsemi Corp Ethernet PHYs support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index d38e99e717..e9523fed2e 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_PHY_MARVELL) += marvell.o obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o +obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c new file mode 100644 index 00..6e37700adc --- /dev/null +++ b/drivers/net/phy/motorcomm.c @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Motorcomm 8531 PHY driver. + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include + +#define PHY_ID_YT8531 0x4f51e91b +#define PHY_ID_MASKGENMASK(31, 0) + +/* Extended Register's Address Offset Register */ +#define YTPHY_PAGE_SELECT 0x1E + +/* Extended Register's Data Register */ +#define YTPHY_PAGE_DATA0x1F + +#define YTPHY_SYNCE_CFG_REG0xA012 + +#define YTPHY_DTS_OUTPUT_CLK_DIS 0 +#define YTPHY_DTS_OUTPUT_CLK_25M 2500 +#define YTPHY_DTS_OUTPUT_CLK_125M 12500 + +#define YT8531_SCR_SYNCE_ENABLEBIT(6) +/* 1b0 output 25m clock *default* + * 1b1 output 125m clock + */ +#define YT8531_SCR_CLK_FRE_SEL_125MBIT(4) +#define YT8531_SCR_CLK_SRC_MASKGENMASK(3, 1) +#define YT8531_SCR_CLK_SRC_PLL_125M0 +#define YT8531_SCR_CLK_SRC_UTP_RX 1 +#define YT8531_SCR_CLK_SRC_SDS_RX 2 +#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 +#define YT8531_SCR_CLK_SRC_REF_25M 4 +#define YT8531_SCR_CLK_SRC_SSC_25M 5 + +/* 1b0 use original tx_clk_rgmii *default* + * 1b1 use inverted tx_clk_rgmii. + */ +#define YT8531_RC1R_TX_CLK_SEL_INVERTEDBIT(14) +#define YT8531_RC1R_RX_DELAY_MASK GENMASK(13, 10) +#define YT8531_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) +#define YT8531_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) +#define YT8531_RC1R_RGMII_0_000_NS 0 +#define YT8531_RC1R_RGMII_0_150_NS 1 +#define YT8531_RC1R_RGMII_0_300_NS 2 +#define YT8531_RC1R_RGMII_0_450_NS 3 +#define YT8531_RC1R_RGMII_0_600_NS 4 +#define YT8531_RC1R_RGMII_0_750_NS 5 +#define YT8531_RC1R_RGMII_0_900_NS 6 +#define YT8531_RC1R_RGMII_1_050_NS 7 +#define YT8531_RC1R_RGMII_1_200_NS 8 +#define YT8531_RC1R_RGMII_1_350_NS 9 +#define YT8531_RC1R_RGMII_1_500_NS 10 +#define YT8531_RC1R_RGMII_1_650_NS 11 +#define YT8531_RC1R_RGMII_1_800_NS 12 +#define YT8531_RC1R_RGMII_1_950_NS 13 +#define YT8531_RC1R_RGMII_2_100_NS 14 +#define YT8531_RC1R_RGMII_2_250_NS 15 + +/* Phy gmii clock gating Register */ +#define YT8531_CLOCK_GATING_REG0xC +#define YT8531_CGR_RX_CLK_EN BIT(12) + +/* Specific Status Register */ +#define YTPHY_SPECIFIC_STATUS_REG 0x11 +#define YTPHY_DUPLEX_MASK BIT(13) +#define YTPHY_DUPLEX_SHIFT 13 +#define YTPHY_SPEED_MODE_MASK GENMASK(15, 14) +#define YTPHY_SPEED_MODE_SHIFT 14 + +#define YT8531_EXTREG_SLEEP_CONTROL1_REG 0x27 +#define YT8531_ESC1R_SLEEP_SW BIT(15) +#define YT8531_ESC1R_PLLON_SLP BIT(14) + +#define YT8531_RGMII_CONFIG1_REG 0xA003 + +#define YT8531_CHIP_CONFIG_REG 0xA001 +#define YT8531_CCR_SW_RST BIT(15) +/* 1b0 disable 1.9ns rxc clock delay *default* + *
[PATCH v2 5/5] configs: starfive: Enable ethernet configuration for StarFive VisionFive 2
Enable DWC_ETH_QOS and PHY_MOTORCOMM configuration to support ethernet function for StarFive VisionFive 2 board,including versions 1.2A and 1.3B. Signed-off-by: Yanhong Wang --- configs/starfive_visionfive2_12a_defconfig | 12 +++- configs/starfive_visionfive2_13b_defconfig | 12 +++- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/configs/starfive_visionfive2_12a_defconfig b/configs/starfive_visionfive2_12a_defconfig index e0f98292ff..1340701c69 100644 --- a/configs/starfive_visionfive2_12a_defconfig +++ b/configs/starfive_visionfive2_12a_defconfig @@ -21,8 +21,8 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000 CONFIG_ARCH_RV64I=y CONFIG_CMODEL_MEDANY=y CONFIG_RISCV_SMODE=y -CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_QSPI_BOOT=y CONFIG_SD_BOOT=y CONFIG_USE_BOOTARGS=y @@ -52,6 +52,9 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_MEMINFO=y CONFIG_CMD_TFTPPUT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_JH7110=y @@ -65,6 +68,13 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_STARFIVE=y +CONFIG_RGMII=y +CONFIG_RMII=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y diff --git a/configs/starfive_visionfive2_13b_defconfig b/configs/starfive_visionfive2_13b_defconfig index 550d0ff3ab..a6415a6cde 100644 --- a/configs/starfive_visionfive2_13b_defconfig +++ b/configs/starfive_visionfive2_13b_defconfig @@ -21,8 +21,8 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000 CONFIG_ARCH_RV64I=y CONFIG_CMODEL_MEDANY=y CONFIG_RISCV_SMODE=y -CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_QSPI_BOOT=y CONFIG_SD_BOOT=y CONFIG_USE_BOOTARGS=y @@ -52,6 +52,9 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_MEMINFO=y CONFIG_CMD_TFTPPUT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_JH7110=y @@ -65,6 +68,13 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_STARFIVE=y +CONFIG_RGMII=y +CONFIG_RMII=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y -- 2.17.1
[PATCH v2 3/5] riscv: dts: jh7110: Add ethernet device tree nodes
Add ethernet device tree node to support StarFive ethernet driver for
the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/jh7110.dtsi | 69 ++
1 file changed, 69 insertions(+)
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..58e332e9d7 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -235,6 +235,13 @@
#clock-cells = <0>;
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,lpi_en;
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <4>;
+ snps,blen = <256 128 64 32 0 0 0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -539,6 +546,68 @@
status = "disabled";
};
+ gmac0: ethernet@1603 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x1603 0x0 0x1>;
+ clocks = < JH7110_AONCLK_GMAC0_AXI>,
+< JH7110_AONCLK_GMAC0_AHB>,
+< JH7110_SYSCLK_GMAC0_PTP>,
+< JH7110_AONCLK_GMAC0_TX_INV>,
+< JH7110_SYSCLK_GMAC0_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = < JH7110_AONRST_GMAC0_AXI>,
+< JH7110_AONRST_GMAC0_AHB>;
+ reset-names = "stmmaceth", "ahb";
+ interrupts = <7>, <6>, <5>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <8>;
+ rx-fifo-depth = <2048>;
+ tx-fifo-depth = <2048>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <_axi_setup>;
+ snps,tso;
+ snps,en-tx-lpi-clockgating;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ starfive,syscon = <_syscon 0xc 0x12>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@1604 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x1604 0x0 0x1>;
+ clocks = < JH7110_SYSCLK_GMAC1_AXI>,
+< JH7110_SYSCLK_GMAC1_AHB>,
+< JH7110_SYSCLK_GMAC1_PTP>,
+< JH7110_SYSCLK_GMAC1_TX_INV>,
+< JH7110_SYSCLK_GMAC1_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = < JH7110_SYSRST_GMAC1_AXI>,
+< JH7110_SYSRST_GMAC1_AHB>;
+ reset-names = "stmmaceth", "ahb";
+ interrupts = <78>, <77>, <76>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <8>;
+ rx-fifo-depth = <2048>;
+ tx-fifo-depth = <2048>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <_axi_setup>;
+ snps,tso;
+ snps,en-tx-lpi-clockgating;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ starfive,syscon = <_syscon 0x90 0x2>;
+ status = "disabled";
+ };
+
aoncrg: clock-controller@1700 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x1700 0x0 0x1>;
--
2.17.1
[PATCH v2 4/5] riscv: dts: starfive: Add phy clock delay configuration for StarFive VisionFive2 board
The StarFive VisionFive2 board include 1.2A and 1.3B version.
v1.3B uses motorcomm YT8531(rgmii-id phy) x2, phy clock need delay and
inverse configurations.
v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs phy clock
delay configurations.
v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to switch rx and
tx to external clock sources.
Signed-off-by: Yanhong Wang
---
.../jh7110-starfive-visionfive-2-v1.2a.dts| 13 +++
.../jh7110-starfive-visionfive-2-v1.3b.dts| 27 +++
.../dts/jh7110-starfive-visionfive-2.dtsi | 34 +++
3 files changed, 74 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
index b9d26d7af7..918e77220a 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
@@ -10,3 +10,16 @@
model = "StarFive VisionFive 2 v1.2A";
compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
};
+
+ {
+ phy-mode = "rmii";
+ assigned-clocks = < JH7110_SYSCLK_GMAC1_TX>,
+ < JH7110_SYSCLK_GMAC1_RX>;
+ assigned-clock-parents = < JH7110_SYSCLK_GMAC1_RMII_RTX>,
+< JH7110_SYSCLK_GMAC1_RMII_RTX>;
+};
+
+ {
+ rx-internal-delay-ps = <1900>;
+ tx-internal-delay-ps = <1350>;
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
index 3b3b3453a1..0fcd6ab80f 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
@@ -10,3 +10,30 @@
model = "StarFive VisionFive 2 v1.3B";
compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
};
+
+ {
+ starfive,tx-use-rgmii-clk;
+ assigned-clocks = < JH7110_AONCLK_GMAC0_TX>;
+ assigned-clock-parents = < JH7110_AONCLK_GMAC0_RMII_RTX>;
+};
+
+ {
+ starfive,tx-use-rgmii-clk;
+ assigned-clocks = < JH7110_SYSCLK_GMAC1_TX>;
+ assigned-clock-parents = < JH7110_SYSCLK_GMAC1_RMII_RTX>;
+};
+
+ {
+ motorcomm,tx-clk-adj-enabled;
+ motorcomm,tx-clk-100-inverted;
+ motorcomm,tx-clk-1000-inverted;
+ rx-internal-delay-ps = <1900>;
+ tx-internal-delay-ps = <1500>;
+};
+
+ {
+ motorcomm,tx-clk-adj-enabled;
+ motorcomm,tx-clk-100-inverted;
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <0>;
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..3c1148ae2d 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -17,6 +17,8 @@
i2c2 =
i2c5 =
i2c6 =
+ ethernet0 =
+ ethernet1 =
};
chosen {
@@ -317,3 +319,35 @@
assigned-clock-parents = <>;
assigned-clock-rates = <0>;
};
+
+ {
+ phy-handle = <>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+ {
+ phy-handle = <>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+ };
+};
--
2.17.1
[PATCH v2 0/5] Add ethernet driver for StarFive JH7110 SoC
This series adds ethernet support for the StarFive JH7110 RISC-V SoC. The series includes PHY and MAC drivers. The PHY model is YT8531 (from Motorcomm Inc), and the MAC version is dwmac-5.20 (from Synopsys DesignWare). The implementation of the phy driver is ported from linux, but it has been adjusted for the u-boot framework. The PHY and MAC driver has been tested on the StarFive VisionFive 2 1.2A and 1.3B boards and works normally. For more information and support,you can visit RVspace wiki[1]. This patchset should be applied after the patchset [2]. [1] https://wiki.rvspace.org/ [2] https://patchwork.ozlabs.org/project/uboot/cover/20230329034224.26545-1-yanhong.w...@starfivetech.com/ v2: - Reworded the phy driver. Added platform private data struct to save the configuration data read from dts. - Reworded the MAC driver. Added platform private data struct to save the configuration data read from dts. Previous versions: v1 - https://patchwork.ozlabs.org/project/uboot/cover/20230317010536.17860-1-yanhong.w...@starfivetech.com/ Yanhong Wang (5): net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy net: dwc_eth_qos: Add StarFive ethernet driver glue layer riscv: dts: jh7110: Add ethernet device tree nodes riscv: dts: starfive: Add phy clock delay configuration for StarFive VisionFive2 board configs: starfive: Enable ethernet configuration for StarFive VisionFive 2 .../jh7110-starfive-visionfive-2-v1.2a.dts| 13 + .../jh7110-starfive-visionfive-2-v1.3b.dts| 27 ++ .../dts/jh7110-starfive-visionfive-2.dtsi | 34 ++ arch/riscv/dts/jh7110.dtsi| 69 +++ configs/starfive_visionfive2_12a_defconfig| 12 +- configs/starfive_visionfive2_13b_defconfig| 12 +- drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 6 + drivers/net/dwc_eth_qos.h | 1 + drivers/net/dwc_eth_qos_starfive.c| 249 ++ drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/motorcomm.c | 450 ++ drivers/net/phy/phy.c | 4 +- include/phy.h | 1 + 16 files changed, 890 insertions(+), 3 deletions(-) create mode 100644 drivers/net/dwc_eth_qos_starfive.c create mode 100644 drivers/net/phy/motorcomm.c base-commit: d7c2e87a0b8025314ae7dd62a8add292b7524e0b -- 2.17.1
Re: [PATCH v5 00/17] Basic StarFive JH7110 RISC-V SoC support
On 2023/3/29 17:41, Torsten Duwe wrote: > On Wed, 29 Mar 2023 11:42:07 +0800 > Yanhong Wang wrote: > >> v5: > [...] >> - Splitted starfive_visionfive2_defconfig into >> starfive_visionfive2_12a_defconfig >> and starfive_visionfive2_13b_defconfig. > > Is this really necessary? It puts another burden on people building U-Boot, > distribution networks, and last but not least users, who will need to pick the > correct binary blob, after trying to find out which board they actually have. > > Even past versions can detect the installed RAM correctly and will modify > the DT accordingly, I assume? Why not make an inquiry on GMAC1_MDIO to tell > whether it's a YT8512C (->v1.2A) or another YT8531C (->v1.3B), in the ethernet > patch set, and likewise update the device tree dynamically then? > There is only one defconfig in V4, and dts is separate for versions 1.2a and 1.3b. Andreas Schwab suggested that defconfig is also defined separately, so the definition of defconfig in V5 is also separated. The discussion process as follows: https://patchwork.ozlabs.org/project/uboot/patch/20230316025332.3297-18-yanhong.w...@starfivetech.com/ Do you have any better suggestion on whether defconfig is defined separately? > Torsten
[PATCH v5 16/17] riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree
Add initial device tree for StarFive VisionFive v2 board.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
arch/riscv/dts/Makefile | 3 +-
...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 69
.../jh7110-starfive-visionfive-2-v1.2a.dts| 12 +
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69
.../jh7110-starfive-visionfive-2-v1.3b.dts| 12 +
.../dts/jh7110-starfive-visionfive-2.dtsi | 319 ++
6 files changed, 483 insertions(+), 1 deletion(-)
create mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
create mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index c576c55767..79a58694f5 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,7 +7,8 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.3b.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.2a.dtb
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
new file mode 100644
index 00..0b20be0f10
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ spi0 =
+ u-boot,dm-spl;
+ };
+
+ config {
+ u-boot,dm-spl;
+ u-boot,spl-payload-offset = <0x10>;
+ };
+
+ memory@4000 {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+
+ nor-flash@0 {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_pins {
+ u-boot,dm-spl;
+ mmc0-pins-rest {
+ u-boot,dm-spl;
+ };
+};
+
+_pins {
+ u-boot,dm-spl;
+ mmc1-pins0 {
+ u-boot,dm-spl;
+ };
+
+ mmc1-pins1 {
+ u-boot,dm-spl;
+ };
+};
+
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
new file mode 100644
index 00..b9d26d7af7
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 v1.2A";
+ compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
new file mode 100644
index 00..0b20be0f10
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ spi0 =
+ u-boot,dm-spl;
+ };
+
+ config {
+ u-boot,dm-spl;
+ u-boot,spl-payload-offset = <0x10>;
+ };
+
+ memory@4000 {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+
+ nor-flash@0 {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_pins {
+ u-boot,dm-spl;
+ mmc0-pins-rest {
+ u-boot,dm-spl;
+ };
+};
+
+_pins {
+ u-boot,dm-spl;
+ mmc1-pins0 {
+ u-boot,dm-spl;
+ };
+
+ mmc1-pins1 {
+ u-boot,dm-spl;
+ };
+};
+
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
new file mode 100644
index 00..3b3b34
[PATCH v5 17/17] configs: starfive: add defconfig for StarFive VisionFvie2 1.2A and 1.3B
This is the initial basic config for StarFive VisionFive v2 board. It
includes consol, Norflash, sdio, ddr etc.
Include starfive_visionfive2_12a_defconfig and
starfive_visionfive2_13b_defconfig, matching the 1.2A and 1.3B boards.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
configs/starfive_visionfive2_12a_defconfig | 79 ++
configs/starfive_visionfive2_13b_defconfig | 79 ++
2 files changed, 158 insertions(+)
create mode 100644 configs/starfive_visionfive2_12a_defconfig
create mode 100644 configs/starfive_visionfive2_13b_defconfig
diff --git a/configs/starfive_visionfive2_12a_defconfig
b/configs/starfive_visionfive2_12a_defconfig
new file mode 100644
index 00..e0f98292ff
--- /dev/null
+++ b/configs/starfive_visionfive2_12a_defconfig
@@ -0,0 +1,79 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x80
+CONFIG_SYS_MALLOC_F_LEN=0x1
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.2a"
+CONFIG_SPL_TEXT_BASE=0x800
+CONFIG_SYS_PROMPT="StarFive #"
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_STACK=0x818
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
+CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
+CONFIG_ARCH_RV64I=y
+CONFIG_CMODEL_MEDANY=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_QSPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
+CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_BSS_START_ADDR=0x804
+CONFIG_SPL_BSS_MAX_SIZE=0x1
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x40
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
+CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_JH7110=y
+# CONFIG_I2C is not set
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_SF_DEFAULT_SPEED=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_SPL_PINCONF=y
+CONFIG_SPL_PINCTRL_STARFIVE=y
+CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
+CONFIG_PINCTRL_STARFIVE=y
+# CONFIG_RAM_SIFIVE is not set
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER_EARLY=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/starfive_visionfive2_13b_defconfig
b/configs/starfive_visionfive2_13b_defconfig
new file mode 100644
index 00..550d0ff3ab
--- /dev/null
+++ b/configs/starfive_visionfive2_13b_defconfig
@@ -0,0 +1,79 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x80
+CONFIG_SYS_MALLOC_F_LEN=0x1
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b"
+CONFIG_SPL_TEXT_BASE=0x800
+CONFIG_SYS_PROMPT="StarFive #"
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_STACK=0x818
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
+CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
+CONFIG_ARCH_RV64I=y
+CONFIG_CMODEL_MEDANY=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_QSPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
+CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_BSS_START_ADDR=0x804
+CONFIG_SPL_BSS_MAX_SIZE=0x1
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x40
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
[PATCH v5 15/17] riscv: dts: jh7110: Add initial u-boot device tree
Add initial u-boot device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
arch/riscv/dts/jh7110-u-boot.dtsi | 99 +++
1 file changed, 99 insertions(+)
create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi
b/arch/riscv/dts/jh7110-u-boot.dtsi
new file mode 100644
index 00..31ca054f54
--- /dev/null
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include
+
+/ {
+ cpus: cpus {
+ u-boot,dm-spl;
+
+ S7_0: cpu@0 {
+ u-boot,dm-spl;
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ U74_1: cpu@1 {
+ u-boot,dm-spl;
+ cpu1_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ U74_2: cpu@2 {
+ u-boot,dm-spl;
+ cpu2_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ U74_3: cpu@3 {
+ u-boot,dm-spl;
+ cpu3_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ U74_4: cpu@4 {
+ u-boot,dm-spl;
+ cpu4_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ };
+
+ soc {
+ u-boot,dm-spl;
+
+ clint: timer@200 {
+ u-boot,dm-spl;
+ };
+
+ dmc: dmc@1570 {
+ u-boot,dm-spl;
+ compatible = "starfive,jh7110-dmc";
+ reg = <0x0 0x1570 0x0 0x1>,
+ <0x0 0x1300 0x0 0x1>;
+ resets = < JH7110_SYSRST_DDR_AXI>,
+ < JH7110_SYSRST_DDR_OSC>,
+ < JH7110_SYSRST_DDR_APB>;
+ reset-names = "axi", "osc", "apb";
+ clocks = < JH7110_SYSCLK_PLL1_OUT>;
+ clock-names = "pll1_out";
+ clock-frequency = <2133>;
+ };
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_rmii_refin {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ starfive,sys-syscon = <_syscon>;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_syscon {
+ u-boot,dm-spl;
+};
+
+_0 {
+ status = "okay";
+};
--
2.17.1
[PATCH v5 14/17] riscv: dts: jh7110: Add initial StarFive JH7110 device tree
Add initial device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
arch/riscv/dts/jh7110.dtsi | 573 +
1 file changed, 573 insertions(+)
create mode 100644 arch/riscv/dts/jh7110.dtsi
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
new file mode 100644
index 00..bd60879615
--- /dev/null
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -0,0 +1,573 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include
+#include
+
+/ {
+ compatible = "starfive,jh7110";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ S7_0: cpu@0 {
+ compatible = "sifive,s7", "riscv";
+ reg = <0>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <16384>;
+ next-level-cache = <>;
+ riscv,isa = "rv64imac_zba_zbb";
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_1: cpu@1 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <1>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ riscv,isa = "rv64imafdc_zba_zbb";
+ tlb-split;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_2: cpu@2 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <2>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ riscv,isa = "rv64imafdc_zba_zbb";
+ tlb-split;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_3: cpu@3 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <3>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+
[PATCH v5 13/17] board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig
Add board support for StarFive VisionFive v2. Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- arch/riscv/Kconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 48ca4ff4c4..f6ed05906a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -24,6 +24,9 @@ config TARGET_SIFIVE_UNMATCHED bool "Support SiFive Unmatched Board" select SYS_CACHE_SHIFT_6 +config TARGET_STARFIVE_VISIONFIVE2 + bool "Support StarFive VisionFive2 Board" + config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 @@ -65,12 +68,14 @@ source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" +source "board/starfive/visionfive2/Kconfig" # platform-specific options below source "arch/riscv/cpu/andesv5/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" +source "arch/riscv/cpu/jh7110/Kconfig" # architecture-specific options below -- 2.17.1
[PATCH v5 12/17] board: starfive: Add Kconfig for StarFive VisionFive v2 Board
Add Kconfig to select the basic functions for StarFive VisionFive v2 Board. Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- board/starfive/visionfive2/Kconfig | 53 ++ 1 file changed, 53 insertions(+) create mode 100644 board/starfive/visionfive2/Kconfig diff --git a/board/starfive/visionfive2/Kconfig b/board/starfive/visionfive2/Kconfig new file mode 100644 index 00..2186a93964 --- /dev/null +++ b/board/starfive/visionfive2/Kconfig @@ -0,0 +1,53 @@ +if TARGET_STARFIVE_VISIONFIVE2 + +config SYS_CPU + default "jh7110" + +config SYS_BOARD + default "visionfive2" + +config SYS_VENDOR + default "starfive" + +config SYS_CONFIG_NAME + default "starfive-visionfive2" + +config TEXT_BASE + default 0x4020 if SPL + default 0x4000 if !RISCV_SMODE + default 0x4020 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x0800 + +config SPL_OPENSBI_LOAD_ADDR + default 0x8000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select STARFIVE_JH7110 + select SUPPORT_SPL + select BINMAN + imply CMD_CPU + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_GPIO + imply CMD_GPT + imply CMD_MMC + imply CMD_NET + imply CMD_PING + imply CMD_SF + imply DM_GPIO + imply DOS_PARTITION + imply EFI_PARTITION + imply MII + imply IP_DYN + imply ISO_PARTITION + imply PARTITION_TYPE_GUID + imply PHY_LIB + imply PHY_MSCC + +endif -- 2.17.1
[PATCH v5 09/17] ram: starfive: add ddr driver
Add driver for StarFive JH7110 to support ddr initialization in SPL.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
drivers/ram/Kconfig |1 +
drivers/ram/Makefile|4 +-
drivers/ram/starfive/Kconfig|5 +
drivers/ram/starfive/Makefile | 11 +
drivers/ram/starfive/ddrcsr_boot.c | 339 +
drivers/ram/starfive/ddrphy_start.c | 279
drivers/ram/starfive/ddrphy_train.c | 383 ++
drivers/ram/starfive/ddrphy_utils.c | 1955 +++
drivers/ram/starfive/starfive_ddr.c | 161 +++
drivers/ram/starfive/starfive_ddr.h | 65 +
10 files changed, 3202 insertions(+), 1 deletion(-)
create mode 100644 drivers/ram/starfive/Kconfig
create mode 100644 drivers/ram/starfive/Makefile
create mode 100644 drivers/ram/starfive/ddrcsr_boot.c
create mode 100644 drivers/ram/starfive/ddrphy_start.c
create mode 100644 drivers/ram/starfive/ddrphy_train.c
create mode 100644 drivers/ram/starfive/ddrphy_utils.c
create mode 100644 drivers/ram/starfive/starfive_ddr.c
create mode 100644 drivers/ram/starfive/starfive_ddr.h
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index e085119963..1acf212f87 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -112,3 +112,4 @@ source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
source "drivers/ram/octeon/Kconfig"
+source "drivers/ram/starfive/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 83948e2c43..2b9429cfee 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -20,5 +20,7 @@ obj-$(CONFIG_K3_DDRSS) += k3-ddrss/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
obj-$(CONFIG_RAM_SIFIVE) += sifive/
-
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/
+endif
obj-$(CONFIG_ARCH_OCTEON) += octeon/
diff --git a/drivers/ram/starfive/Kconfig b/drivers/ram/starfive/Kconfig
new file mode 100644
index 00..80c790066f
--- /dev/null
+++ b/drivers/ram/starfive/Kconfig
@@ -0,0 +1,5 @@
+config SPL_STARFIVE_DDR
+ bool "StarFive DDR driver in SPL"
+ depends on SPL_RAM && STARFIVE_JH7110
+ help
+ This enables DDR support for the platforms based on StarFive JH7110
SoC.
diff --git a/drivers/ram/starfive/Makefile b/drivers/ram/starfive/Makefile
new file mode 100644
index 00..1df42c377b
--- /dev/null
+++ b/drivers/ram/starfive/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 StarFive, Inc
+#
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_start.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_train.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive_ddr.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_utils.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrcsr_boot.o
+endif
\ No newline at end of file
diff --git a/drivers/ram/starfive/ddrcsr_boot.c
b/drivers/ram/starfive/ddrcsr_boot.c
new file mode 100644
index 00..f2dd55f74a
--- /dev/null
+++ b/drivers/ram/starfive/ddrcsr_boot.c
@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "starfive_ddr.h"
+
+#define REGOFFSET(offset) ((offset) / 4)
+
+static const struct ddr_reg_cfg ddr_csr_cfg[] = {
+ {0x0, 0x0,0x0001, REGSETALL},
+ {0xf00, 0x0,0x40001030, (OFFSET_SEL | F_SET | REG4G |
REG8G)},
+ {0xf00, 0x0,0x40001030, (OFFSET_SEL | F_SET | REG2G)},
+ {0xf04, 0x0,0x0001, (OFFSET_SEL | F_SET | REG4G |
REG8G)},
+ {0xf04, 0x0,0x0081, (OFFSET_SEL | F_SET | REG2G)},
+ {0xf10, 0x0,0x0040, (OFFSET_SEL | REGSETALL)},
+ {0xf14, 0x0,0x043f, (OFFSET_SEL | REGSETALL)},
+ {0xf18, 0x0,0x, (OFFSET_SEL | REGSETALL)},
+ {0xf30, 0x0,0x1f41, (OFFSET_SEL | REGSETALL)},
+ {0xf34, 0x0,0x1f41, (OFFSET_SEL | F_SET | REG4G |
REG8G)},
+ {0x110, 0x0,0xc001, (OFFSET_SEL | REGSETALL)},
+ {0x114, 0x0,0x, (OFFSET_SEL | REGSETALL)},
+ {0x10c, 0x0,0x0505, REGSETALL},
+ {0x11c, 0x0,0x, REGSETALL},
+ {0x500, 0x0,0x0201, REGSETALL},
+ {0x514, 0x0,0x0100, REGSETALL},
+ {0x6a8, 0x0,0x0004, REGSETALL},
+ {0xea8, 0x0,0x0004, REGSETALL},
+ {0x504, 0x0,0x4000, REGSETALL}
+};
+
+static const struct ddr_reg_cfg ddr_csr_cfg1[] = {
+ {0x310, 0x0,0x0002, REGSETALL},
+ {0x310, 0x0,0x00020001, REGSETALL},
+ {
[PATCH v5 10/17] board: starfive: add StarFive VisionFive v2 board support
Add board support for StarFive VisionFive v2.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
board/starfive/visionfive2/MAINTAINERS| 7 +
board/starfive/visionfive2/Makefile | 7 +
board/starfive/visionfive2/spl.c | 87
.../visionfive2/starfive_visionfive2.c| 40 ++
doc/board/index.rst | 1 +
doc/board/starfive/index.rst | 9 +
doc/board/starfive/visionfive2.rst| 492 ++
include/configs/starfive-visionfive2.h| 49 ++
8 files changed, 692 insertions(+)
create mode 100644 board/starfive/visionfive2/MAINTAINERS
create mode 100644 board/starfive/visionfive2/Makefile
create mode 100644 board/starfive/visionfive2/spl.c
create mode 100644 board/starfive/visionfive2/starfive_visionfive2.c
create mode 100644 doc/board/starfive/index.rst
create mode 100644 doc/board/starfive/visionfive2.rst
create mode 100644 include/configs/starfive-visionfive2.h
diff --git a/board/starfive/visionfive2/MAINTAINERS
b/board/starfive/visionfive2/MAINTAINERS
new file mode 100644
index 00..c5369086d8
--- /dev/null
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -0,0 +1,7 @@
+STARFIVE JH7110 VISIONFIVE2 BOARD
+M: startfive
+S: Maintained
+F: arch/riscv/include/asm/arch-jh7110/
+F: board/starfive/visionfive2/
+F: include/configs/starfive-visionfive2.h
+F: configs/starfive_visionfive2_defconfig
diff --git a/board/starfive/visionfive2/Makefile
b/board/starfive/visionfive2/Makefile
new file mode 100644
index 00..66c854df39
--- /dev/null
+++ b/board/starfive/visionfive2/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+#
+
+obj-y := starfive_visionfive2.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
new file mode 100644
index 00..db0b4cb433
--- /dev/null
+++ b/board/starfive/visionfive2/spl.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
+#define JH7110_CLK_CPU_ROOT_SHIFT 24
+#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
+
+int spl_board_init_f(void)
+{
+ int ret;
+
+ ret = spl_soc_init();
+ if (ret) {
+ debug("JH7110 SPL init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+u32 spl_boot_device(void)
+{
+ u32 mode;
+
+ mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
+ & JH7110_BOOT_MODE_SELECT_MASK;
+ switch (mode) {
+ case 0:
+ return BOOT_DEVICE_SPI;
+
+ case 1:
+ return BOOT_DEVICE_MMC2;
+
+ case 2:
+ return BOOT_DEVICE_MMC1;
+
+ case 3:
+ return BOOT_DEVICE_UART;
+
+ default:
+ debug("Unsupported boot device 0x%x.\n", mode);
+ return BOOT_DEVICE_NONE;
+ }
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ ret = spl_early_init();
+ if (ret)
+ panic("spl_early_init() failed: %d\n", ret);
+
+ riscv_cpu_setup(NULL, NULL);
+ preloader_console_init();
+
+ /* Set the parent clock of cpu_root clock to pll0,
+* it must be initialized here
+*/
+ clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_CPU_ROOT_OFFSET,
+ JH7110_CLK_CPU_ROOT_MASK,
+ BIT(JH7110_CLK_CPU_ROOT_SHIFT));
+
+ ret = spl_board_init_f();
+ if (ret) {
+ debug("spl_board_init_f init failed: %d\n", ret);
+ return;
+ }
+}
+
+#if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ /* boot using first FIT config */
+ return 0;
+}
+#endif
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c
b/board/starfive/visionfive2/starfive_visionfive2.c
new file mode 100644
index 00..613fe793c4
--- /dev/null
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+
+#define JH7110_L2_PREFETCHER_BASE_ADDR 0x203
+#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000
+
+/* enable U74-mc hart1~hart4 prefetcher */
+static void enable_prefetcher(void)
+{
+ u8 hart;
+ u32 *reg;
+
+ /* JH7110 use U74MC CORE IP, it include five cores(one S7 and four U7),
+* but only U7 cores support prefetcher configuration
+*/
+ for (hart = 1; hart < 5; hart++) {
+ reg
[PATCH v5 11/17] riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC
Add Kconfig to select the basic functions for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- arch/riscv/cpu/jh7110/Kconfig | 28 1 file changed, 28 insertions(+) create mode 100644 arch/riscv/cpu/jh7110/Kconfig diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig new file mode 100644 index 00..3f145415eb --- /dev/null +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 StarFive Technology Co., Ltd. + +config STARFIVE_JH7110 + bool + select ARCH_EARLY_INIT_R + select CLK_JH7110 + select CPU + select CPU_RISCV + select RAM + select RESET_JH7110 + select SUPPORT_SPL + select SPL_RAM if SPL + select SPL_STARFIVE_DDR + select PINCTRL_STARFIVE_JH7110 + imply MMC + imply MMC_BROKEN_CD + imply MMC_SPI + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply SIFIVE_CACHE + imply SIFIVE_CCACHE + imply SMP + imply SPI + imply SPL_CPU + imply SPL_LOAD_FIT + imply SPL_OPENSBI + imply SPL_SIFIVE_CLINT -- 2.17.1
[PATCH v5 08/17] pinctrl: starfive: Add StarFive JH7110 driver
From: Kuan Lim Lee Add pinctrl driver for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee Signed-off-by: Emil Renner Berthing Signed-off-by: Jianlong Huang Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/starfive/Kconfig | 28 ++ drivers/pinctrl/starfive/Makefile | 6 + drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 113 + drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 399 ++ drivers/pinctrl/starfive/pinctrl-starfive.c | 398 + drivers/pinctrl/starfive/pinctrl-starfive.h | 55 +++ 8 files changed, 1001 insertions(+) create mode 100644 drivers/pinctrl/starfive/Kconfig create mode 100644 drivers/pinctrl/starfive/Makefile create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.h diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b6ef2acced..75b3ff47a2 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -359,5 +359,6 @@ source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/rockchip/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" +source "drivers/pinctrl/starfive/Kconfig" endmenu diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 3b167d099f..852adee4b4 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -32,3 +32,4 @@ obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o obj-$(CONFIG_$(SPL_)PINCTRL_STMFX) += pinctrl-stmfx.o obj-y += broadcom/ obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o +obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/ diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig new file mode 100644 index 00..1b859c863e --- /dev/null +++ b/drivers/pinctrl/starfive/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SPL_PINCTRL_STARFIVE + bool "Support Pinctrl driver for StarFive SoC in SPL" + depends on SPL_PINCTRL_FULL && STARFIVE_JH7110 + help + Enable support pin control driver for StarFive SoC. + +config SPL_PINCTRL_STARFIVE_JH7110 + bool "Support Pinctrl and GPIO driver for StarFive JH7110 SoC in SPL" + depends on SPL_PINCTRL_STARFIVE + help + Enable support pinctrl and gpio driver for StarFive JH7110 in SPL. + +config PINCTRL_STARFIVE + bool "Pinctrl driver for StarFive SoC" + depends on PINCTRL_FULL && STARFIVE_JH7110 + help + Say yes here to support pin control on the StarFive RISC-V SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. + +config PINCTRL_STARFIVE_JH7110 + bool "Pinctrl and GPIO driver for StarFive JH7110 SoC" + depends on PINCTRL_STARFIVE + help + This selects the pinctrl driver for JH7110 starfive. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile new file mode 100644 index 00..a4a12069b3 --- /dev/null +++ b/drivers/pinctrl/starfive/Makefile @@ -0,0 +1,6 @@ + +# SPDX-License-Identifier: GPL-2.0 +# Core +obj-$(CONFIG_$(SPL_TPL_)PINCTRL_STARFIVE) += pinctrl-starfive.o +# SoC Drivers +obj-$(CONFIG_$(SPL_TPL_)PINCTRL_STARFIVE_JH7110) += pinctrl-jh7110-sys.o pinctrl-jh7110-aon.o diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c new file mode 100644 index 00..2d739906e2 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl / GPIO driver for StarFive JH7110 SoC + * + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Lee Kuan Lim + * Author: Jianlong Huang + */ + +#include +#include +#include + +#include +#include "pinctrl-starfive.h" + +#define JH7110_AON_NGPIO 4 +#define JH7110_AON_GC_BASE 64 + +/* registers */ +#define JH7110_AON_DOEN0x0 +#define JH7110_AON_DOUT0x4 +#define JH7110_AON_GPI 0x8 +#define JH7110_AON_GPIOIN 0x2c + +#define JH7110_AON_GPIOEN 0xc +#define JH7110_AON_GPIOIS 0x10 +#define JH7110_AON_GPIOIC 0x14 +#define JH7110_AON_GPIOIBE 0x18 +#define JH7110_AON_GPIOIEV 0x1c +#define JH7110_AON_GPIOIE 0x20 +#define JH7110_AON_GPIORIS 0x28 +#define JH7110_AON_GPIOMIS 0x28 +
[PATCH v5 06/17] clk: starfive: Add StarFive JH7110 clock driver
Add a DM clock driver for StarFive JH7110 SoC.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/starfive/Kconfig | 17 +
drivers/clk/starfive/Makefile | 4 +
drivers/clk/starfive/clk-jh7110-pll.c | 321 ++
drivers/clk/starfive/clk-jh7110.c | 603 ++
drivers/clk/starfive/clk.h| 57 +++
7 files changed, 1004 insertions(+)
create mode 100644 drivers/clk/starfive/Kconfig
create mode 100644 drivers/clk/starfive/Makefile
create mode 100644 drivers/clk/starfive/clk-jh7110-pll.c
create mode 100644 drivers/clk/starfive/clk-jh7110.c
create mode 100644 drivers/clk/starfive/clk.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 09aa97ee8c..4d60c84aad 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -235,6 +235,7 @@ source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sifive/Kconfig"
+source "drivers/clk/starfive/Kconfig"
source "drivers/clk/stm32/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/ti/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index c274cda77c..66f5860356 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
obj-y += analogbits/
obj-y += imx/
+obj-$(CONFIG_CLK_JH7110) += starfive/
obj-y += tegra/
obj-y += ti/
obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
new file mode 100644
index 00..9399ef6d51
--- /dev/null
+++ b/drivers/clk/starfive/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+config SPL_CLK_JH7110
+ bool "SPL clock support for JH7110"
+ depends on STARFIVE_JH7110 && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM support for clock driver in JH7110.
+
+config CLK_JH7110
+ bool "StarFive JH7110 clock support"
+ depends on STARFIVE_JH7110
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for StarFive JH7110 SoC platform.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
new file mode 100644
index 00..ec0d157094
--- /dev/null
+++ b/drivers/clk/starfive/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += clk-jh7110.o
+obj-y += clk-jh7110-pll.o
diff --git a/drivers/clk/starfive/clk-jh7110-pll.c
b/drivers/clk/starfive/clk-jh7110-pll.c
new file mode 100644
index 00..02e6d9000e
--- /dev/null
+++ b/drivers/clk/starfive/clk-jh7110-pll.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022-23 StarFive Technology Co., Ltd.
+ *
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define UBOOT_DM_CLK_JH7110_PLLX "jh7110_clk_pllx"
+
+#define PLL_PD_OFF 1
+#define PLL_PD_ON 0
+
+#define CLK_DDR_BUS_MASK GENMASK(29, 24)
+#define CLK_DDR_BUS_OFFSET 0xAC
+#define CLK_DDR_BUS_OSC_DIV2 0
+#define CLK_DDR_BUS_PLL1_DIV2 1
+#define CLK_DDR_BUS_PLL1_DIV4 2
+#define CLK_DDR_BUS_PLL1_DIV8 3
+
+struct clk_jh7110_pllx {
+ struct clk clk;
+ void __iomem*base;
+ void __iomem*sysreg;
+ enum starfive_pll_type type;
+ const struct starfive_pllx_offset *offset;
+ const struct starfive_pllx_rate *rate_table;
+ int rate_count;
+};
+
+#define getbits_le32(addr, mask) ((in_le32(addr) & (mask)) >> __ffs((mask)))
+
+#define PLLX_SET(offset, mask, val) do {\
+ reg = readl((ulong *)((ulong)pll->base + (offset))); \
+ reg &= ~(mask); \
+ reg |= (mask) & ((val) << __ffs(mask)); \
+ writel(reg, (ulong *)((ulong)pll->base + (offset))); \
+ } while (0)
+
+#define PLLX_RATE(_rate, _pd, _fd) \
+ { \
+ .rate = (_rate), \
+ .prediv = (_pd),\
+ .fbdiv = (_fd),\
+ }
+
+#define to_clk_pllx(_clk) container_of(_clk, struct clk_jh7110_pllx, clk)
+
+static const struct starfive_pllx_rate jh7110_pll0_tbl[] = {
+ PLLX_RATE(37500UL, 8, 125),
+ PLLX_RATE(5UL, 6, 125),
+ PLLX_RATE(62500UL, 24, 625),
+ PLLX_RATE(75000UL, 4, 125),
+ PLLX_RATE(87500UL, 24, 875),
+ PLLX_RATE(10UL, 3, 125),
+ PLLX_RATE(125000UL, 12, 625),
+ PLLX_RATE(137500UL, 24, 1375),
+
[PATCH v5 07/17] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions
From: Jianlong Huang Add pinctrl definitions for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee Signed-off-by: Emil Renner Berthing Signed-off-by: Jianlong Huang Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- .../pinctrl/pinctrl-starfive-jh7110.h | 427 ++ 1 file changed, 427 insertions(+) create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h new file mode 100644 index 00..f273547e7b --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h @@ -0,0 +1,427 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2022 Emil Renner Berthing + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__ +#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__ + +/* + * mux bits: + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | + * | din| dout | doen | function | gpio nr | + * + * dout: output signal + * doen: output enable signal + * din: optional input signal, 0xff = none + * function: + * gpio nr: gpio number, 0 - 63 + */ +#define GPIOMUX(n, dout, doen, din) ( \ + (((din) & 0xff) << 24) | \ + (((dout) & 0xff) << 16) | \ + (((doen) & 0x3f) << 10) | \ + ((n) & 0x3f)) + +#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff)) + +/* sys_iomux pin */ +#definePAD_GPIO00 +#definePAD_GPIO11 +#definePAD_GPIO22 +#definePAD_GPIO33 +#definePAD_GPIO44 +#definePAD_GPIO55 +#definePAD_GPIO66 +#definePAD_GPIO77 +#definePAD_GPIO88 +#definePAD_GPIO99 +#definePAD_GPIO10 10 +#definePAD_GPIO11 11 +#definePAD_GPIO12 12 +#definePAD_GPIO13 13 +#definePAD_GPIO14 14 +#definePAD_GPIO15 15 +#definePAD_GPIO16 16 +#definePAD_GPIO17 17 +#definePAD_GPIO18 18 +#definePAD_GPIO19 19 +#definePAD_GPIO20 20 +#definePAD_GPIO21 21 +#definePAD_GPIO22 22 +#definePAD_GPIO23 23 +#definePAD_GPIO24 24 +#definePAD_GPIO25 25 +#definePAD_GPIO26 26 +#definePAD_GPIO27 27 +#definePAD_GPIO28 28 +#definePAD_GPIO29 29 +#definePAD_GPIO30 30 +#definePAD_GPIO31 31 +#definePAD_GPIO32 32 +#definePAD_GPIO33 33 +#definePAD_GPIO34 34 +#definePAD_GPIO35 35 +#definePAD_GPIO36 36 +#definePAD_GPIO37 37 +#definePAD_GPIO38 38 +#definePAD_GPIO39 39 +#definePAD_GPIO40 40 +#definePAD_GPIO41 41 +#definePAD_GPIO42 42 +#definePAD_GPIO43 43 +#definePAD_GPIO44 44 +#definePAD_GPIO45 45 +#definePAD_GPIO46 46 +#definePAD_GPIO47 47 +#definePAD_GPIO48 48 +#definePAD_GPIO49 49 +#definePAD_GPIO50 50 +#definePAD_GPIO51 51 +#definePAD_GPIO52 52 +#definePAD_GPIO53 53 +#definePAD_GPIO54 54 +#definePAD_GPIO55 55 +#definePAD_GPIO56 56 +#definePAD_GPIO57 57 +#definePAD_GPIO58 58 +#definePAD_GPIO59 59 +#definePAD_GPIO60 60 +#definePAD_GPIO61 61 +#definePAD_GPIO62 62 +#definePAD_GPIO63 63 +#definePAD_SD0_CLK 64 +#definePAD_SD0_CMD 65 +#definePAD_SD0_DATA0 66 +#definePAD_SD0_DATA1 67 +#definePAD_SD0_DATA2 68 +#definePAD_SD0_DATA3 69 +#definePAD_SD0_DATA4 70 +#definePAD_SD0_DATA5 71 +#definePAD_SD0_DATA6 72 +#definePAD_SD0_DATA7 73 +#definePAD_SD0_STRB74 +#definePAD_GMAC1_MDC 75 +#definePAD_GMAC1_MDIO 76 +#definePAD_GMAC1_RXD0 77 +#definePAD_GMAC1_RXD1 78 +#definePAD_GMAC1_RXD2 79 +#definePAD_GMAC1_RXD3 80 +#definePAD_GMAC1_RXDV 81 +#definePAD_GMAC1_RXC 82 +#definePAD_GMAC1_TXD0 83 +#definePAD_GMAC1_TXD1 84 +#definePAD_GMAC1_TXD2 85 +#definePAD_GMAC1_TXD3 86 +#definePAD_GMAC1_TXEN 87 +#definePAD_GMAC1_TXC 88 +#definePAD_QSPI_SCLK 89 +#definePAD_QSPI_CS090 +#definePAD_QSPI_DATA0 91 +#definePAD_QSPI_DATA1 92 +#definePAD_QSPI_DATA2 93 +#definePAD_QSPI_DATA3 94 + +/* aon_iomux pin */ +#definePAD_TESTEN 0 +#define
[PATCH v5 04/17] reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC
Add a DM reset driver for StarFive JH7110 SoC.
Note that the register base address of reset controller is the
same with the clock controller. Therefore, there is no device
tree node alone for reset driver.It binds device node in
the clock driver
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
drivers/reset/Kconfig| 16
drivers/reset/Makefile | 1 +
drivers/reset/reset-jh7110.c | 158 +++
3 files changed, 175 insertions(+)
create mode 100644 drivers/reset/reset-jh7110.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index e4039d7474..73bbd30692 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -172,6 +172,22 @@ config RESET_SIFIVE
different hw blocks like DDR, gemgxl. With this driver we leverage
U-Boot's reset framework to reset these hardware blocks.
+config RESET_JH7110
+ bool "Reset driver for StarFive JH7110 SoC"
+ depends on DM_RESET && STARFIVE_JH7110
+ default y
+ help
+ Support for reset controller on StarFive
+ JH7110 SoCs.
+
+config SPL_RESET_JH7110
+ bool "SPL Reset driver for StarFive JH7110 SoC"
+ depends on SPL && STARFIVE_JH7110
+ default y
+ help
+ Support for reset controller on StarFive
+ JH7110 SoCs in SPL.
+
config RESET_SYSCON
bool "Enable generic syscon reset driver support"
depends on DM_RESET
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 6c8b45ecba..6801268180 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -32,3 +32,4 @@ obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
obj-$(CONFIG_RESET_AT91) += reset-at91.o
+obj-$(CONFIG_$(SPL_TPL_)RESET_JH7110) += reset-jh7110.o
diff --git a/drivers/reset/reset-jh7110.c b/drivers/reset/reset-jh7110.c
new file mode 100644
index 00..d6bdf6bb00
--- /dev/null
+++ b/drivers/reset/reset-jh7110.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct jh7110_reset_priv {
+ void __iomem *reg;
+ u32 assert;
+ u32 status;
+ u32 resets;
+};
+
+struct reset_info {
+ const char *compat;
+ const u32 nr_resets;
+ const u32 assert_offset;
+ const u32 status_offset;
+};
+
+static const struct reset_info jh7110_rst_info[] = {
+ {
+ .compat = "starfive,jh7110-syscrg",
+ .nr_resets = JH7110_SYSRST_END,
+ .assert_offset = 0x2F8,
+ .status_offset = 0x308,
+ },
+ {
+ .compat = "starfive,jh7110-aoncrg",
+ .nr_resets = JH7110_AONRST_END,
+ .assert_offset = 0x38,
+ .status_offset = 0x3C,
+ },
+ {
+ .compat = "starfive,jh7110-stgcrg",
+ .nr_resets = JH7110_STGRST_END,
+ .assert_offset = 0x74,
+ .status_offset = 0x78,
+ }
+};
+
+static const struct reset_info *jh7110_reset_get_cfg(const char *compat)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(jh7110_rst_info); i++)
+ if (!strcmp(compat, jh7110_rst_info[i].compat))
+ return _rst_info[i];
+
+ return NULL;
+}
+
+static int jh7110_reset_trigger(struct jh7110_reset_priv *priv,
+ unsigned long id, bool assert)
+{
+ ulong group;
+ u32 mask, value, done = 0;
+ ulong addr;
+
+ group = id / 32;
+ mask = BIT(id % 32);
+
+ if (!assert)
+ done ^= mask;
+
+ addr = (ulong)priv->reg + priv->assert + group * sizeof(u32);
+ value = readl((ulong *)addr);
+
+ if (assert)
+ value |= mask;
+ else
+ value &= ~mask;
+
+ writel(value, (ulong *)addr);
+ addr = (ulong)priv->reg + priv->status + group * sizeof(u32);
+
+ return readl_poll_timeout((ulong *)addr, value,
+ (value & mask) == done, 1000);
+}
+
+static int jh7110_reset_assert(struct reset_ctl *rst)
+{
+ struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+ jh7110_reset_trigger(priv, rst->id, true);
+
+ return 0;
+}
+
+static int jh7110_reset_deassert(struct reset_ctl *rst)
+{
+ struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+ jh7110_reset_trigger(priv, rst->id, false);
+
+ return 0;
+}
+
+static int jh7110_reset_free(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int jh7110_reset_request(struct reset_ctl *rst)
+{
+ struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+ if
[PATCH v5 05/17] dt-bindings: clock: Add StarFive JH7110 clock definitions
Add all clock outputs for the StarFive JH7110 clock generator. Signed-off-by: Yanhong Wang Acked-by: Sean Anderson Tested-by: Conor Dooley --- .../dt-bindings/clock/starfive,jh7110-crg.h | 257 ++ 1 file changed, 257 insertions(+) create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h new file mode 100644 index 00..77b70e7a83 --- /dev/null +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -0,0 +1,257 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ + +#define JH7110_SYSCLK_CPU_ROOT 0 +#define JH7110_SYSCLK_CPU_CORE 1 +#define JH7110_SYSCLK_CPU_BUS 2 +#define JH7110_SYSCLK_GPU_ROOT 3 +#define JH7110_SYSCLK_PERH_ROOT4 +#define JH7110_SYSCLK_BUS_ROOT 5 +#define JH7110_SYSCLK_NOCSTG_BUS 6 +#define JH7110_SYSCLK_AXI_CFG0 7 +#define JH7110_SYSCLK_STG_AXIAHB 8 +#define JH7110_SYSCLK_AHB0 9 +#define JH7110_SYSCLK_AHB1 10 +#define JH7110_SYSCLK_APB_BUS 11 +#define JH7110_SYSCLK_APB0 12 +#define JH7110_SYSCLK_PLL0_DIV213 +#define JH7110_SYSCLK_PLL1_DIV214 +#define JH7110_SYSCLK_PLL2_DIV215 +#define JH7110_SYSCLK_AUDIO_ROOT 16 +#define JH7110_SYSCLK_MCLK_INNER 17 +#define JH7110_SYSCLK_MCLK 18 +#define JH7110_SYSCLK_MCLK_OUT 19 +#define JH7110_SYSCLK_ISP_2X 20 +#define JH7110_SYSCLK_ISP_AXI 21 +#define JH7110_SYSCLK_GCLK022 +#define JH7110_SYSCLK_GCLK123 +#define JH7110_SYSCLK_GCLK224 +#define JH7110_SYSCLK_CORE 25 +#define JH7110_SYSCLK_CORE126 +#define JH7110_SYSCLK_CORE227 +#define JH7110_SYSCLK_CORE328 +#define JH7110_SYSCLK_CORE429 +#define JH7110_SYSCLK_DEBUG30 +#define JH7110_SYSCLK_RTC_TOGGLE 31 +#define JH7110_SYSCLK_TRACE0 32 +#define JH7110_SYSCLK_TRACE1 33 +#define JH7110_SYSCLK_TRACE2 34 +#define JH7110_SYSCLK_TRACE3 35 +#define JH7110_SYSCLK_TRACE4 36 +#define JH7110_SYSCLK_TRACE_COM37 +#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 +#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 +#define JH7110_SYSCLK_OSC_DIV2 40 +#define JH7110_SYSCLK_PLL1_DIV441 +#define JH7110_SYSCLK_PLL1_DIV842 +#define JH7110_SYSCLK_DDR_BUS 43 +#define JH7110_SYSCLK_DDR_AXI 44 +#define JH7110_SYSCLK_GPU_CORE 45 +#define JH7110_SYSCLK_GPU_CORE_CLK 46 +#define JH7110_SYSCLK_GPU_SYS_CLK 47 +#define JH7110_SYSCLK_GPU_APB 48 +#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 +#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 +#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 +#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 +#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 +#define JH7110_SYSCLK_HIFI4_CORE 54 +#define JH7110_SYSCLK_HIFI4_AXI55 +#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN56 +#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 +#define JH7110_SYSCLK_VOUT_SRC 58 +#define JH7110_SYSCLK_VOUT_AXI 59 +#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 +#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB61 +#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI62 +#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK63 +#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 +#define JH7110_SYSCLK_JPEGC_AXI65 +#define JH7110_SYSCLK_CODAJ12_AXI 66 +#define JH7110_SYSCLK_CODAJ12_CORE 67 +#define JH7110_SYSCLK_CODAJ12_APB 68 +#define JH7110_SYSCLK_VDEC_AXI 69 +#define JH7110_SYSCLK_WAVE511_AXI 70 +#define JH7110_SYSCLK_WAVE511_BPU 71 +#define JH7110_SYSCLK_WAVE511_VCE 72 +#define JH7110_SYSCLK_WAVE511_APB 73 +#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 +#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN75 +#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 +#define JH7110_SYSCLK_VENC_AXI 77 +#define JH7110_SYSCLK_WAVE420L_AXI 78 +#define JH7110_SYSCLK_WAVE420L_BPU 79 +#define JH7110_SYSCLK_WAVE420L_VCE 80 +#define JH7110_SYSCLK_WAVE420L_APB
[PATCH v5 03/17] dt-bindings: reset: Add StarFive JH7110 reset definitions
Add resets for the StarFive JH7110 system(SYS),system-top-group(STG) and always-on(AON) reset controller. Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- .../dt-bindings/reset/starfive,jh7110-crg.h | 183 ++ 1 file changed, 183 insertions(+) create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h new file mode 100644 index 00..1d596581da --- /dev/null +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ + +/* SYSCRG resets */ +#define JH7110_SYSRST_JTAG2APB 0 +#define JH7110_SYSRST_SYSCON 1 +#define JH7110_SYSRST_IOMUX_APB2 +#define JH7110_SYSRST_BUS 3 +#define JH7110_SYSRST_DEBUG4 +#define JH7110_SYSRST_CORE05 +#define JH7110_SYSRST_CORE16 +#define JH7110_SYSRST_CORE27 +#define JH7110_SYSRST_CORE38 +#define JH7110_SYSRST_CORE49 +#define JH7110_SYSRST_CORE0_ST 10 +#define JH7110_SYSRST_CORE1_ST 11 +#define JH7110_SYSRST_CORE2_ST 12 +#define JH7110_SYSRST_CORE3_ST 13 +#define JH7110_SYSRST_CORE4_ST 14 +#define JH7110_SYSRST_TRACE0 15 +#define JH7110_SYSRST_TRACE1 16 +#define JH7110_SYSRST_TRACE2 17 +#define JH7110_SYSRST_TRACE3 18 +#define JH7110_SYSRST_TRACE4 19 +#define JH7110_SYSRST_TRACE_COM20 +#define JH7110_SYSRST_GPU_APB 21 +#define JH7110_SYSRST_GPU_DOMA 22 +#define JH7110_SYSRST_NOC_BUS_APB_BUS 23 +#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 +#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 +#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 +#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 +#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 +#define JH7110_SYSRST_NOC_BUS_DDRC 29 +#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 +#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 + +#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 +#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33 +#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN34 +#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN35 +#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV36 +#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37 +#define JH7110_SYSRST_DDR_AXI 38 +#define JH7110_SYSRST_DDR_OSC 39 +#define JH7110_SYSRST_DDR_APB 40 +#define JH7110_SYSRST_DOM_ISP_TOP_N41 +#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42 +#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43 +#define JH7110_SYSRST_CODAJ12_AXI 44 +#define JH7110_SYSRST_CODAJ12_CORE 45 +#define JH7110_SYSRST_CODAJ12_APB 46 +#define JH7110_SYSRST_WAVE511_AXI 47 +#define JH7110_SYSRST_WAVE511_BPU 48 +#define JH7110_SYSRST_WAVE511_VCE 49 +#define JH7110_SYSRST_WAVE511_APB 50 +#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51 +#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN52 +#define JH7110_SYSRST_AXIMEM0_AXI 53 +#define JH7110_SYSRST_WAVE420L_AXI 54 +#define JH7110_SYSRST_WAVE420L_BPU 55 +#define JH7110_SYSRST_WAVE420L_VCE 56 +#define JH7110_SYSRST_WAVE420L_APB 57 +#define JH7110_SYSRST_AXIMEM1_AXI 58 +#define JH7110_SYSRST_AXIMEM2_AXI 59 +#define JH7110_SYSRST_INTMEM 60 +#define JH7110_SYSRST_QSPI_AHB 61 +#define JH7110_SYSRST_QSPI_APB 62 +#define JH7110_SYSRST_QSPI_REF 63 + +#define JH7110_SYSRST_SDIO0_AHB64 +#define JH7110_SYSRST_SDIO1_AHB65 +#define JH7110_SYSRST_GMAC1_AXI66 +#define JH7110_SYSRST_GMAC1_AHB67 +#define JH7110_SYSRST_MAILBOX 68 +#define JH7110_SYSRST_SPI0_APB 69 +#define JH7110_SYSRST_SPI1_APB 70 +#define JH7110_SYSRST_SPI2_APB 71 +#define JH7110_SYSRST_SPI3_APB 72 +#define JH7110_SYSRST_SPI4_APB 73 +#define JH7110_SYSRST_SPI5_APB 74 +#define JH7110_SYSRST_SPI6_APB 75 +#define JH7110_SYSRST_I2C0_APB 76 +#define JH7110_SYSRST_I2C1_APB 77 +#define JH7110_SYSRST_I2C2_APB 78 +#define JH7110_SYSRST_I2C3_APB 79 +#define JH7110_SYSRST_I2C4_APB 80 +#define
[PATCH v5 01/17] riscv: cpu: jh7110: Add support for jh7110 SoC
Add StarFive JH7110 SoC to support RISC-V arch.
Signed-off-by: Yanhong Wang
Reviewed-by: Rick Chen
Tested-by: Conor Dooley
---
arch/riscv/cpu/jh7110/Makefile| 10
arch/riscv/cpu/jh7110/cpu.c | 23
arch/riscv/cpu/jh7110/dram.c | 38 ++
arch/riscv/cpu/jh7110/spl.c | 64 +++
arch/riscv/include/asm/arch-jh7110/regs.h | 19 +++
arch/riscv/include/asm/arch-jh7110/spl.h | 12 +
6 files changed, 166 insertions(+)
create mode 100644 arch/riscv/cpu/jh7110/Makefile
create mode 100644 arch/riscv/cpu/jh7110/cpu.c
create mode 100644 arch/riscv/cpu/jh7110/dram.c
create mode 100644 arch/riscv/cpu/jh7110/spl.c
create mode 100644 arch/riscv/include/asm/arch-jh7110/regs.h
create mode 100644 arch/riscv/include/asm/arch-jh7110/spl.h
diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile
new file mode 100644
index 00..951c95631e
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
+obj-y += cpu.o
+obj-y += dram.o
+endif
diff --git a/arch/riscv/cpu/jh7110/cpu.c b/arch/riscv/cpu/jh7110/cpu.c
new file mode 100644
index 00..1d7c026584
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/cpu.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ cache_flush();
+
+ return 0;
+}
diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
new file mode 100644
index 00..2ad3f2044a
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+ /*
+* Ensure that we run from first 4GB so that all
+* addresses used by U-Boot are 32bit addresses.
+*
+* This in-turn ensures that 32bit DMA capable
+* devices work fine because DMA mapping APIs will
+* provide 32bit DMA addresses only.
+*/
+ if (IS_ENABLED(CONFIG_64BIT) && gd->ram_top > SZ_4G)
+ return SZ_4G;
+
+ return gd->ram_top;
+}
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
new file mode 100644
index 00..104f0fe949
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+
+#define CSR_U74_FEATURE_DISABLE0x7c1
+#define L2_LIM_MEM_END 0x81FUL
+
+int spl_soc_init(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ /* DDR init */
+ ret = uclass_get_device(UCLASS_RAM, 0, );
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+void harts_early_init(void)
+{
+ ulong *ptr;
+ u8 *tmp;
+ ulong len, remain;
+ /*
+* Feature Disable CSR
+*
+* Clear feature disable CSR to '0' to turn on all features for
+* each core. This operation must be in M-mode.
+*/
+ if (CONFIG_IS_ENABLED(RISCV_MMODE))
+ csr_write(CSR_U74_FEATURE_DISABLE, 0);
+
+ /* clear L2 LIM memory
+* set __bss_end to 0x81F region to zero
+* The L2 Cache Controller supports ECC. ECC is applied to SRAM.
+* If it is not cleared, the ECC part is invalid, and an ECC error
+* will be reported when reading data.
+*/
+ ptr = (ulong *)&__bss_end;
+ len = L2_LIM_MEM_END - (ulong)&__bss_end;
+ remain = len % sizeof(ulong);
+ len /= sizeof(ulong);
+
+ while (len--)
+ *ptr++ = 0;
+
+ /* clear the remain bytes */
+ if (remain) {
+ tmp = (u8 *)ptr;
+ while (remain--)
+ *tmp++ = 0;
+ }
+}
diff --git a/arch/riscv/include/asm/arch-jh7110/regs.h
b/arch/riscv/include/asm/arch-jh7110/regs.h
new file mode 100644
index 00..05026870a0
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/regs.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C
[PATCH v5 02/17] cache: starfive: Add StarFive JH7110 support
This adds support for the StarFive JH7110 SoC which also
feature this SiFive cache controller.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
drivers/cache/cache-sifive-ccache.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cache/cache-sifive-ccache.c
b/drivers/cache/cache-sifive-ccache.c
index c8766f6242..521df40466 100644
--- a/drivers/cache/cache-sifive-ccache.c
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -62,6 +62,7 @@ static int sifive_ccache_probe(struct udevice *dev)
static const struct udevice_id sifive_ccache_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
{ .compatible = "sifive,fu740-c000-ccache" },
+ { .compatible = "sifive,ccache0" },
{}
};
--
2.17.1
[PATCH v5 00/17] Basic StarFive JH7110 RISC-V SoC support
This series of patches base on the latest branch/master, and add support for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for this to be achieved, the respective DT nodes have been added, and the required defconfigs have been added to the boards' defconfig. What is more, the basic required DM drivers have been added, such as reset, clock, pinctrl, uart, ram etc. Note that the register base address of reset controller is same with the clock controller. Therefore, there is no device tree node alone for reset driver. It binds device node in the clock driver. The u-boot-spl and u-boot has been tested on the StarFive VisionFive 2 1.2A and 1.3B boards which equip with JH7110 SoC and works normally. For more information and support, you can visit RVspace wiki[1]. [1] https://wiki.rvspace.org/ v5: - Fixed the build errors that came from "make htmldocs". - Remove the MMU configuration from the S7 device tree node. - Splitted starfive_visionfive2_defconfig into starfive_visionfive2_12a_defconfig and starfive_visionfive2_13b_defconfig. - Added the implementation of 'get_function' callback function to pinctrl. v4: - Replace compatible string "starfive,jh7110-ccache" with "sifive,ccache0". - Added 'gmac0_tx_inv','gmac1_tx_inv','gmac1_rx' clock registration. - Added enable_caches() call to enable L2 cache in board_init() function. - Moved 'S7_0' device node from board dts to SoC -u-boot.dtsi. - Added 'i2cx' device node to board dts to consistent with linux. - Renamed device node 'sdcard1_pins' to 'mmc1_pins'. v3: - Added doc/board/starfive/visionfive2.rst file. - Added support booting from SD. - Added support pinctrl in SPL. - Reworded dts to consistent with linux. - Added CFG_EXTRA_ENV_SETTINGS configuration. - Reworded starfive_visionfive2_defconfig. - Reworded the clock driver. - Renamed 'starfive-jh7110.h' to 'starfive,jh7110-crg.h'. - Separated 'starfive_visionfive2.dts' to 'jh7110-starfive-visionfive-2-v1.3b.dts' and 'jh7110-starfive-visionfive-2-v1.2a.dts' to consistent with linux. - Added pinmux_property_set callback function implementation in 'pinctrl-starfive.c'. v2: - Renamed file 'jh7110-regs.h' to 'regs.h'. - Reworded the clear L2 LIM memory code in C. - Removed flash init call in 'spl_soc_init' function. - Reworded the clock driver. - Rename the macro 'SET_DIV' to 'ASSIGNED_CLOCK_PARENTS' in 'spl.c'. - Moved the device tree node 'dmc@1570' from 'jh7110-u-boot.dtsi' to 'starfive_visionfive2-u-boot.dtsi' Previous versions: v1 - https://patchwork.ozlabs.org/project/uboot/cover/20221212025020.23778-1-yanhong.w...@starfivetech.com/ v2 - https://patchwork.ozlabs.org/project/uboot/cover/20230118081132.31403-1-yanhong.w...@starfivetech.com/ v3 - https://patchwork.ozlabs.org/project/uboot/patch/20230303032432.7837-2-yanhong.w...@starfivetech.com/ v4 - https://patchwork.ozlabs.org/project/uboot/cover/20230316025332.3297-1-yanhong.w...@starfivetech.com/ Jianlong Huang (1): dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Kuan Lim Lee (1): pinctrl: starfive: Add StarFive JH7110 driver Yanhong Wang (15): riscv: cpu: jh7110: Add support for jh7110 SoC cache: starfive: Add StarFive JH7110 support dt-bindings: reset: Add StarFive JH7110 reset definitions reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC dt-bindings: clock: Add StarFive JH7110 clock definitions clk: starfive: Add StarFive JH7110 clock driver ram: starfive: add ddr driver board: starfive: add StarFive VisionFive v2 board support riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC board: starfive: Add Kconfig for StarFive VisionFive v2 Board board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig riscv: dts: jh7110: Add initial StarFive JH7110 device tree riscv: dts: jh7110: Add initial u-boot device tree riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree configs: starfive: add defconfig for StarFive VisionFvie2 1.2A and 1.3B arch/riscv/Kconfig|5 + arch/riscv/cpu/jh7110/Kconfig | 28 + arch/riscv/cpu/jh7110/Makefile| 10 + arch/riscv/cpu/jh7110/cpu.c | 23 + arch/riscv/cpu/jh7110/dram.c | 38 + arch/riscv/cpu/jh7110/spl.c | 64 + arch/riscv/dts/Makefile |3 +- ...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 69 + .../jh7110-starfive-visionfive-2-v1.2a.dts| 12 + ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 + .../jh7110-starfive-visionfive-2-v1.3b.dts| 12 + .../dts/jh7110-starfive-visionfive-2.dtsi | 319 +++ arch/riscv/dts/jh7110-u-boot.dtsi | 99 + arch/riscv/dts/jh7110.dtsi| 573 + arch/riscv/include/asm/arch-jh7110/regs.h | 19 + arch/riscv/include/asm/arch-jh7110/spl.h | 12 + board/starfive/visionfive2/Kconfig| 53 + board/st
Re: [PATCH v4 14/17] riscv: dts: jh7110: Add initial StarFive JH7110 device tree
On 2023/3/23 6:04, Conor Dooley wrote:
> On Thu, Mar 16, 2023 at 10:53:29AM +0800, Yanhong Wang wrote:
>> Add initial device tree for the JH7110 RISC-V SoC.
>>
>> Signed-off-by: Yanhong Wang
>> Tested-by: Conor Dooley
>
>> +S7_0: cpu@0 {
>> +compatible = "sifive,s7", "riscv";
>> +reg = <0>;
>> +d-cache-block-size = <64>;
>> +d-cache-sets = <64>;
>> +d-cache-size = <8192>;
>> +d-tlb-sets = <1>;
>> +d-tlb-size = <40>;
>> +device_type = "cpu";
>> +i-cache-block-size = <64>;
>> +i-cache-sets = <64>;
>> +i-cache-size = <16384>;
>> +i-tlb-sets = <1>;
>> +i-tlb-size = <40>;
>> +mmu-type = "riscv,sv39";
>
> Copy-pasting from my identical post on linux-riscv:
> Jess pointed out on IRC that this S7 entry looks wrong as it is claiming
> that the S7 has an mmu. I didn't go looking back in the history of
> u74-mc core complex manuals, but the latest version does not show an mmu
> for the S7.
>
Thanks. Check the u74-mc manual, S7 does not support mmu, and will be fixed in
the next version.
The definition of S7 will be consistent with Linux.
> Cheers,
> Conor.
>
>> +next-level-cache = <>;
>> +riscv,isa = "rv64imac_zba_zbb";
>> +tlb-split;
>> +status = "disabled";
>> +
>> +cpu0_intc: interrupt-controller {
>> +compatible = "riscv,cpu-intc";
>> +interrupt-controller;
>> +#interrupt-cells = <1>;
>> +};
>> +};
Re: [PATCH v4 10/17] board: starfive: add StarFive VisionFive v2 board support
On 2023/3/22 9:58, Leo Liang wrote: > Hi YanHong, > > There are some errors when "make htmldocs". > I thought v4 was the final patch set and these are minor build errors, > so I have fixed them up on my side. > > Now that since you are adding new defconfig and spinning a v5 patch set, > could you also fix those build errors that came from "make htmldocs" as well? > > There mostly "Title underline too short." in > "doc/board/starfive/visionfive2.rst" > and an entry of "starfive/index" should be added in "doc/board/index.rst" in > alphabetical order. > > CI results: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/597253#L183 > Thanks for pointing out this build error. Since "make htmldocs" was not executed, no build errors were found.I will fix those build errors that came from "make htmldocs" in the next version. > Best regards, > Leo > > On Thu, Mar 16, 2023 at 10:53:25AM +0800, Yanhong Wang wrote: >> Add board support for StarFive VisionFive v2. >> >> Signed-off-by: Yanhong Wang >> Tested-by: Conor Dooley >> --- >> board/starfive/visionfive2/MAINTAINERS| 7 + >> board/starfive/visionfive2/Makefile | 7 + >> board/starfive/visionfive2/spl.c | 87 >> .../visionfive2/starfive_visionfive2.c| 40 ++ >> doc/board/starfive/index.rst | 9 + >> doc/board/starfive/visionfive2.rst| 492 ++ >> include/configs/starfive-visionfive2.h| 49 ++ >> 7 files changed, 691 insertions(+) >> create mode 100644 board/starfive/visionfive2/MAINTAINERS >> create mode 100644 board/starfive/visionfive2/Makefile >> create mode 100644 board/starfive/visionfive2/spl.c >> create mode 100644 board/starfive/visionfive2/starfive_visionfive2.c >> create mode 100644 doc/board/starfive/index.rst >> create mode 100644 doc/board/starfive/visionfive2.rst >> create mode 100644 include/configs/starfive-visionfive2.h >> >> diff --git a/doc/board/starfive/index.rst b/doc/board/starfive/index.rst >> new file mode 100644 >> index 00..420433ea30 >> --- /dev/null >> +++ b/doc/board/starfive/index.rst >> @@ -0,0 +1,9 @@ >> +.. SPDX-License-Identifier: GPL-2.0+ >> + >> +StarFive >> +== > > Title underline too short. > I will fix. >> + >> +.. toctree:: >> + :maxdepth: 1 >> + >> + visionfive2 >> diff --git a/doc/board/starfive/visionfive2.rst >> b/doc/board/starfive/visionfive2.rst >> new file mode 100644 >> index 00..155358d29e >> --- /dev/null >> +++ b/doc/board/starfive/visionfive2.rst >> @@ -0,0 +1,492 @@ >> +.. SPDX-License-Identifier: GPL-2.0+ >> + >> +StarFive VisionFive2 >> + > > Ditto. > I will fix. >> + >> +JH7110 RISC-V SoC >> +- >> +The JH7110 is 4+1 64-bit RISC-V SoC from StarFive. >> + >> +The StarFive VisionFive2 development platform is based on JH7110 and capable >> +of running Linux. >> + >> +Mainline support >> + >> + >> +The support for following drivers are already enabled: >> + >> +1. ns16550 UART Driver. >> +2. StarFive JH7110 clock Driver. >> +3. StarFive JH7110 reset Driver. >> +4. Cadence QSPI controller Driver. >> +5. MMC SPI Driver for MMC/SD support. >> + >> +Booting from MMC using U-Boot SPL >> +--- >> + > > Ditto. > I will fix. >> +The current U-Boot port is supported in S-mode only and loaded from DRAM. >> + >> +A prior stage M-mode firmware/bootloader (e.g OpenSBI) is required to >> +boot the u-boot.itb in S-mode and provide M-mode runtime services. >> + >> +Currently, the u-boot.itb is used as a dynamic of the OpenSBI FW_DYNAMIC >> +firmware with the latest. >> + >> +Building >> + >> + >> +1. Add the RISC-V toolchain to your PATH. >> +2. Setup ARCH & cross compilation environment variable: >> + >> +.. code-block:: none >> + >> + export CROSS_COMPILE= >> + >> +Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be >> +cloned and built for JH7110 as below: >> + >> +.. code-block:: console >> + >> +git clone https://github.com/riscv/opensbi.git >> +cd opensbi >> +make PLATFORM=generic FW_TEXT_START=0x4000 FW_OPTIONS=0 >> + >> +More detailed description of steps required to build FW_DYNAM
Re: [PATCH v1 0/5] Add Ethernet driver for StarFive JH7110 SoC
On 2023/3/24 20:53, Torsten Duwe wrote: > On Fri, 17 Mar 2023 09:05:31 +0800 > Yanhong Wang wrote: > >> This series adds ethernet support for the StarFive JH7110 RISC-V SoC. >> The series includes PHY and MAC drivers. The PHY model is >> YT8531 (from Motorcomm Inc), and the MAC version is dwmac-5.20 >> (from Synopsys DesignWare). >> >> The implementation of the phy driver is ported from linux, but it >> has been adjusted for the u-boot framework. >> >> The PHY and MAC driver has been tested on the StarFive VisionFive 2 1.2A >> and 1.3B boards and works normally. > > At least a smoke test here succeeded as well, I'm seeing replies to DHCP. > However: > > | Model: StarFive VisionFive 2 v1.3B > [...] > | Net: > | Warning: ethernet@1604 (eth1) using random MAC address - > e2:b9:39:bd:92:24 > | > | Warning: ethernet@1603 (eth0) using random MAC address - > 22:da:dc:e6:2c:17 > | eth0: ethernet@1603, eth1: ethernet@1604 > [...] > > What's missing to read the correct MACs from the EEPROM? > The minimum system of u-boot supporting JH7110 does not contain EEPROM and cannot read the MAC address from EEPROM, so enable the CONFIG_NET_RANDOM_ETHADDR, EEPROM will be supported in the future, and the MAC address will be read from EEPROM. > Torsten > >
Re: [PATCH v4 17/17] configs: starfive: add starfive_visionfive2_defconfig
On 2023/3/23 16:31, Andreas Schwab wrote: > On Mär 22 2023, yanhong wang wrote: > >> On 2023/3/21 21:51, Andreas Schwab wrote: >>> On Mär 21 2023, yanhong wang wrote: >>> >>>> Except for CONFIG_DEFAULT_DEVICE_TREE and CONFIG_DEFAULT_FDT_FILE, >>>> 1.2a and 1.3b versions use the same config. >>>> >>>> Version 1.3b uses the following configuration: >>>> CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b" >>>> >>>> CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb" >>>> >>>> Version 1.2a uses the following configuration: >>>> CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.2a" >>>> >>>> CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.2a.dtb" >>>> >>>> Is it necessary to separate the configs for 1.2a and 1.3b as separate >>>> defconfig files? >>> >>> It makes a difference for when ethernet support is added. >>> >> >> The difference between 1.2a and 1.3b versions is mainly in ethernet, so the >> definition of >> dts is separated. Defconfig file in addition to the differences mentioned >> above, the others >> are the same. Your suggestion is to define defconfig file separately, is >> that right? > > Yes, a 1.2a board will need to use the 1.2a device tree to get a working > ethernet, IIUC. > Okay, I will define the defconfig for 1.2A and 1.3B separately in the next version.
Re: [PATCH v1 1/5] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
On 2023/3/19 4:20, Simon Glass wrote:
> Hi Yanhong,
>
> On Thu, 16 Mar 2023 at 19:06, Yanhong Wang
> wrote:
>>
>> Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have
>> verified the driver on StarFive VisionFive2 board.
>>
>> Signed-off-by: Yanhong Wang
>> ---
>> drivers/net/phy/Kconfig | 6 +
>> drivers/net/phy/Makefile| 1 +
>> drivers/net/phy/motorcomm.c | 409
>> drivers/net/phy/phy.c | 4 +-
>> include/phy.h | 1 +
>> 5 files changed, 420 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/net/phy/motorcomm.c
>>
>> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
>> index 5eaff053a0..aba718566a 100644
>> --- a/drivers/net/phy/Kconfig
>> +++ b/drivers/net/phy/Kconfig
>> @@ -212,6 +212,12 @@ config PHY_MICREL_KSZ8XXX
>>
>> endif # PHY_MICREL
>>
>> +config PHY_MOTORCOMM
>> + tristate "Motorcomm PHYs"
>> + help
>> + Enables support for Motorcomm network PHYs.
>> + Currently supports the YT8531 Gigabit Ethernet PHYs.
>> +
>> config PHY_MSCC
>> bool "Microsemi Corp Ethernet PHYs support"
>>
>> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
>> index d38e99e717..e9523fed2e 100644
>> --- a/drivers/net/phy/Makefile
>> +++ b/drivers/net/phy/Makefile
>> @@ -23,6 +23,7 @@ obj-$(CONFIG_PHY_MARVELL) += marvell.o
>> obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
>> obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
>> obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
>> +obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o
>> obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
>> obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o
>> obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o
>> diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
>> new file mode 100644
>> index 00..c7e44cfb63
>> --- /dev/null
>> +++ b/drivers/net/phy/motorcomm.c
>> @@ -0,0 +1,409 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>
> [..]
>
>> +static u32 ytphy_get_delay_reg_value(struct phy_device *phydev,
>> +const char *prop_name,
>> +const struct ytphy_cfg_reg_map *tbl,
>> +int tb_size,
>> +u16 *rxc_dly_en,
>> +u32 dflt)
>> +{
>> + int tb_size_half = tb_size / 2;
>> + u32 val;
>> + int i;
>> +
>> + if (ofnode_read_u32(phydev->node, prop_name, ))
>> + goto err_dts_val;
>
> Please move to your ofdata_to_plat() method.
>
> Also, use dev_read_u32() when you have a device.
>
> [.]
>
The ethernet-phy@x node is a sub-node of the ethernet@y node, and
the phy driver is not registered through U_BOOT_DRIVER, there is
no matching dev structure, so the method dev_read_u32() unavailable.
The phy driver is not registered through U_BOOT_DRIVER, and the
of_to_plat() method in the driver structure unavailable.
>> +static int yt8531_startup(struct phy_device *phydev)
>> +{
>> + bool tx_clk_adj_enabled = false;
>> + bool tx_clk_1000_inverted = false;
>> + bool tx_clk_100_inverted = false;
>> + bool tx_clk_10_inverted = false;
>> + u16 val = 0;
>> + int ret;
>> +
>> + ret = genphy_update_link(phydev);
>> + if (ret)
>> + return ret;
>> +
>> + ret = yt8531_parse_status(phydev);
>> + if (ret)
>> + return ret;
>> +
>> + if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-adj-enabled"))
>> + tx_clk_adj_enabled = true;
>
> priv->tx_clk_adj_enabled = ofnode_read_bool(...)
>
Define a motorocomm_priv structure to save the configuration of phy,
roughly as follows:
motorocomm_priv = malloc(...);
phydev->priv = motorocomm_priv;
motorocomm_priv->tx_clk_adj_enabled = ofnode_read_bool(...);
Is this ok?
> Please fix globally
>
> Regards,
> Simon
Re: [PATCH v4 16/17] riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree
On 2023/3/21 5:25, Conor Dooley wrote: > On Thu, Mar 16, 2023 at 10:53:31AM +0800, Yanhong Wang wrote: >> Add initial device tree for StarFive VisionFive v2 board. >> >> Signed-off-by: Yanhong Wang >> Tested-by: Conor Dooley > > btw, are you running some sort of cc suppression argument to > send-email? There's not much reason to do so for submissions to a public > ML, and it would be nice to get subsequent revisions of a patchset that > I have given a tested-by for in my inbox. > Yes, the --suppress-cc=all parameter was added to the send-email. Do you suggest canceling this parameter? > Curious, > Conor.
Re: [PATCH v4 17/17] configs: starfive: add starfive_visionfive2_defconfig
On 2023/3/21 21:51, Andreas Schwab wrote: > On Mär 21 2023, yanhong wang wrote: > >> Except for CONFIG_DEFAULT_DEVICE_TREE and CONFIG_DEFAULT_FDT_FILE, >> 1.2a and 1.3b versions use the same config. >> >> Version 1.3b uses the following configuration: >> CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b" >> CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb" >> >> Version 1.2a uses the following configuration: >> CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.2a" >> CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.2a.dtb" >> >> Is it necessary to separate the configs for 1.2a and 1.3b as separate >> defconfig files? > > It makes a difference for when ethernet support is added. > The difference between 1.2a and 1.3b versions is mainly in ethernet, so the definition of dts is separated. Defconfig file in addition to the differences mentioned above, the others are the same. Your suggestion is to define defconfig file separately, is that right? If so, I will define the defconfig files of 1.2a and 1.3b independently in the next version.
Re: [PATCH v4 17/17] configs: starfive: add starfive_visionfive2_defconfig
On 2023/3/20 22:28, Andreas Schwab wrote: > On Mär 16 2023, Yanhong Wang wrote: > >> This is the initial basic config for StarFive VisionFive v2 board. It >> includes consol, Norflash, sdio, ddr etc. > > Are you also planning to add a config for the 1.2a version? > Except for CONFIG_DEFAULT_DEVICE_TREE and CONFIG_DEFAULT_FDT_FILE, 1.2a and 1.3b versions use the same config. Version 1.3b uses the following configuration: CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b" CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb" Version 1.2a uses the following configuration: CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.2a" CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.2a.dtb" Is it necessary to separate the configs for 1.2a and 1.3b as separate defconfig files? Best Regards. Yanhong.
Re: [PATCH v1 2/5] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
On 2023/3/19 4:20, Simon Glass wrote:
> Hi Yanhong,
>
> On Thu, 16 Mar 2023 at 19:07, Yanhong Wang
> wrote:
>>
>> The StarFive ETHQOS hardware has its own clock and reset,so add a
>> corresponding glue driver to configure them.
>>
>> Signed-off-by: Yanhong Wang
>> ---
>> drivers/net/Kconfig| 7 +
>> drivers/net/Makefile | 1 +
>> drivers/net/dwc_eth_qos.c | 6 +
>> drivers/net/dwc_eth_qos.h | 2 +
>> drivers/net/dwc_eth_qos_starfive.c | 306 +
>> 5 files changed, 322 insertions(+)
>> create mode 100644 drivers/net/dwc_eth_qos_starfive.c
>
>>[..]
>
>> diff --git a/drivers/net/dwc_eth_qos_starfive.c
>> b/drivers/net/dwc_eth_qos_starfive.c
>> new file mode 100644
>> index 00..eeb45981bd
>> --- /dev/null
>> +++ b/drivers/net/dwc_eth_qos_starfive.c
>> @@ -0,0 +1,306 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
>> + * Author: Yanhong Wang
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "dwc_eth_qos.h"
>> +
>> +#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
>> +#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
>> +#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
>> +
>> +static int eqos_interface_init_jh7110(struct udevice *dev,
>> + phy_interface_t interface_type)
>> +{
>> + struct regmap *regmap;
>> + struct ofnode_phandle_args args;
>> + unsigned int mode;
>> + int ret;
>> +
>> + switch (interface_type) {
>> + case PHY_INTERFACE_MODE_RMII:
>> + mode = STARFIVE_DWMAC_PHY_INFT_RMII;
>> + break;
>> +
>> + case PHY_INTERFACE_MODE_RGMII:
>> + case PHY_INTERFACE_MODE_RGMII_ID:
>> + mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
>> + break;
>> +
>> + default:
>> + return -EINVAL;
>> + }
>> +
>> + ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
>> +2, 0, );
>
> You must read the DT in an ofdata_to_plat() method (or probe() if that
> doesn't suit). Put it in a struct.
>
> You must not read it constantly at runtime throughout your driver. It
> is slow and error-prone.
> [..]
>
Thanks. I will define a platform data structure for saving device-related
configurations in the next version.
>> +
>> +struct eqos_config __maybe_unused eqos_jh7110_config = {
>> + .reg_access_always_ok = false,
>> + .mdio_wait = 10,
>> + .swr_wait = 50,
>> + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
>> + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
>> + .axi_bus_width = EQOS_AXI_WIDTH_64,
>> + .interface = dev_read_phy_mode,
>> + .ops = _jh7110_ops
>> +};
>> --
>> 2.17.1
>>
>
> What is that data for? Please add a comment.
>
The definition of these parameters refers to IMX platform, I will double
confirm whether the definition of
these parameters is accurate, and add corresponding comments in the next
version.
> Regards,
> SImom
Re: [PATCH v1 1/5] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
On 2023/3/19 4:20, Simon Glass wrote:
> Hi Yanhong,
>
> On Thu, 16 Mar 2023 at 19:06, Yanhong Wang
> wrote:
>>
>> Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have
>> verified the driver on StarFive VisionFive2 board.
>>
>> Signed-off-by: Yanhong Wang
>> ---
>> drivers/net/phy/Kconfig | 6 +
>> drivers/net/phy/Makefile| 1 +
>> drivers/net/phy/motorcomm.c | 409
>> drivers/net/phy/phy.c | 4 +-
>> include/phy.h | 1 +
>> 5 files changed, 420 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/net/phy/motorcomm.c
>>
>> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
>> index 5eaff053a0..aba718566a 100644
>> --- a/drivers/net/phy/Kconfig
>> +++ b/drivers/net/phy/Kconfig
>> @@ -212,6 +212,12 @@ config PHY_MICREL_KSZ8XXX
>>
>> endif # PHY_MICREL
>>
>> +config PHY_MOTORCOMM
>> + tristate "Motorcomm PHYs"
>> + help
>> + Enables support for Motorcomm network PHYs.
>> + Currently supports the YT8531 Gigabit Ethernet PHYs.
>> +
>> config PHY_MSCC
>> bool "Microsemi Corp Ethernet PHYs support"
>>
>> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
>> index d38e99e717..e9523fed2e 100644
>> --- a/drivers/net/phy/Makefile
>> +++ b/drivers/net/phy/Makefile
>> @@ -23,6 +23,7 @@ obj-$(CONFIG_PHY_MARVELL) += marvell.o
>> obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
>> obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
>> obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
>> +obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o
>> obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
>> obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o
>> obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o
>> diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
>> new file mode 100644
>> index 00..c7e44cfb63
>> --- /dev/null
>> +++ b/drivers/net/phy/motorcomm.c
>> @@ -0,0 +1,409 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>
> [..]
>
>> +static u32 ytphy_get_delay_reg_value(struct phy_device *phydev,
>> +const char *prop_name,
>> +const struct ytphy_cfg_reg_map *tbl,
>> +int tb_size,
>> +u16 *rxc_dly_en,
>> +u32 dflt)
>> +{
>> + int tb_size_half = tb_size / 2;
>> + u32 val;
>> + int i;
>> +
>> + if (ofnode_read_u32(phydev->node, prop_name, ))
>> + goto err_dts_val;
>
> Please move to your ofdata_to_plat() method.
>
> Also, use dev_read_u32() when you have a device.
>
> [.]
>
Thanks. I will define a platform data structure for saving device-related
configurations in the next version.
>> +static int yt8531_startup(struct phy_device *phydev)
>> +{
>> + bool tx_clk_adj_enabled = false;
>> + bool tx_clk_1000_inverted = false;
>> + bool tx_clk_100_inverted = false;
>> + bool tx_clk_10_inverted = false;
>> + u16 val = 0;
>> + int ret;
>> +
>> + ret = genphy_update_link(phydev);
>> + if (ret)
>> + return ret;
>> +
>> + ret = yt8531_parse_status(phydev);
>> + if (ret)
>> + return ret;
>> +
>> + if (ofnode_read_bool(phydev->node, "motorcomm,tx-clk-adj-enabled"))
>> + tx_clk_adj_enabled = true;
>
> priv->tx_clk_adj_enabled = ofnode_read_bool(...)
>
> Please fix globally
>
Ok. I will fixed.
> Regards,
> Simon
[PATCH v1 2/5] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.
Signed-off-by: Yanhong Wang
---
drivers/net/Kconfig| 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 6 +
drivers/net/dwc_eth_qos.h | 2 +
drivers/net/dwc_eth_qos_starfive.c | 306 +
5 files changed, 322 insertions(+)
create mode 100644 drivers/net/dwc_eth_qos_starfive.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index ceadee98a1..161289d00f 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -249,6 +249,13 @@ config DWC_ETH_QOS_QCOM
The Synopsys Designware Ethernet QOS IP block with specific
configuration used in Qcom QCS404 SoC.
+config DWC_ETH_QOS_STARFIVE
+ bool "Synopsys DWC Ethernet QOS device support for STARFIVE"
+ depends on DWC_ETH_QOS
+ help
+ The Synopsys Designware Ethernet QOS IP block with specific
+ configuration used in STARFIVE JH7110 soc.
+
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 75daa5e694..69af678757 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
+obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 112deb546d..9aecd56e73 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1718,6 +1718,12 @@ static const struct udevice_id eqos_ids[] = {
.data = (ulong)_qcom_config
},
#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
+ {
+ .compatible = "starfive,jh7110-dwmac",
+ .data = (ulong)_jh7110_config
+ },
+#endif
{ }
};
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index fddbe9336c..20450497a9 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -279,6 +279,7 @@ struct eqos_priv {
bool clk_ck_enabled;
unsigned int tx_fifo_sz, rx_fifo_sz;
u32 reset_delays[3];
+ struct reset_ctl reset_ahb;
};
void eqos_inval_desc_generic(void *desc);
@@ -289,3 +290,4 @@ int eqos_null_ops(struct udevice *dev);
extern struct eqos_config eqos_imx_config;
extern struct eqos_config eqos_qcom_config;
+extern struct eqos_config eqos_jh7110_config;
diff --git a/drivers/net/dwc_eth_qos_starfive.c
b/drivers/net/dwc_eth_qos_starfive.c
new file mode 100644
index 00..eeb45981bd
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_starfive.c
@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dwc_eth_qos.h"
+
+#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
+#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
+#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
+
+static int eqos_interface_init_jh7110(struct udevice *dev,
+ phy_interface_t interface_type)
+{
+ struct regmap *regmap;
+ struct ofnode_phandle_args args;
+ unsigned int mode;
+ int ret;
+
+ switch (interface_type) {
+ case PHY_INTERFACE_MODE_RMII:
+ mode = STARFIVE_DWMAC_PHY_INFT_RMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
+2, 0, );
+ if (ret)
+ return ret;
+
+ if (args.args_count != 2)
+ return -EINVAL;
+
+ regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+ pr_err("Failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ return regmap_update_bits(regmap, args.args[0],
+ STARFIVE_DWMAC_PHY_INFT_FIELD << args.args[1],
+ mode << args.args[1]);
+}
+
+static int eqos_set_tx_clk_speed_jh7110(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct clk *pclk, *c;
+ ulong rate;
+ int ret;
+
+ /* Generally, the rgmii_tx clock is provided by the
[PATCH v1 1/5] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have verified the driver on StarFive VisionFive2 board. Signed-off-by: Yanhong Wang --- drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile| 1 + drivers/net/phy/motorcomm.c | 409 drivers/net/phy/phy.c | 4 +- include/phy.h | 1 + 5 files changed, 420 insertions(+), 1 deletion(-) create mode 100644 drivers/net/phy/motorcomm.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 5eaff053a0..aba718566a 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -212,6 +212,12 @@ config PHY_MICREL_KSZ8XXX endif # PHY_MICREL +config PHY_MOTORCOMM + tristate "Motorcomm PHYs" + help + Enables support for Motorcomm network PHYs. + Currently supports the YT8531 Gigabit Ethernet PHYs. + config PHY_MSCC bool "Microsemi Corp Ethernet PHYs support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index d38e99e717..e9523fed2e 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_PHY_MARVELL) += marvell.o obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o +obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c new file mode 100644 index 00..c7e44cfb63 --- /dev/null +++ b/drivers/net/phy/motorcomm.c @@ -0,0 +1,409 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Motorcomm 8531 PHY driver. + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include + +#define PHY_ID_YT8531 0x4f51e91b +#define PHY_ID_MASKGENMASK(31, 0) + +/* Extended Register's Address Offset Register */ +#define YTPHY_PAGE_SELECT 0x1E + +/* Extended Register's Data Register */ +#define YTPHY_PAGE_DATA0x1F + +#define YTPHY_SYNCE_CFG_REG0xA012 + +#define YTPHY_DTS_OUTPUT_CLK_DIS 0 +#define YTPHY_DTS_OUTPUT_CLK_25M 2500 +#define YTPHY_DTS_OUTPUT_CLK_125M 12500 + +#define YT8531_SCR_SYNCE_ENABLEBIT(6) +/* 1b0 output 25m clock *default* + * 1b1 output 125m clock + */ +#define YT8531_SCR_CLK_FRE_SEL_125MBIT(4) +#define YT8531_SCR_CLK_SRC_MASKGENMASK(3, 1) +#define YT8531_SCR_CLK_SRC_PLL_125M0 +#define YT8531_SCR_CLK_SRC_UTP_RX 1 +#define YT8531_SCR_CLK_SRC_SDS_RX 2 +#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 +#define YT8531_SCR_CLK_SRC_REF_25M 4 +#define YT8531_SCR_CLK_SRC_SSC_25M 5 + +/* 1b0 use original tx_clk_rgmii *default* + * 1b1 use inverted tx_clk_rgmii. + */ +#define YT8531_RC1R_TX_CLK_SEL_INVERTEDBIT(14) +#define YT8531_RC1R_RX_DELAY_MASK GENMASK(13, 10) +#define YT8531_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) +#define YT8531_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) +#define YT8531_RC1R_RGMII_0_000_NS 0 +#define YT8531_RC1R_RGMII_0_150_NS 1 +#define YT8531_RC1R_RGMII_0_300_NS 2 +#define YT8531_RC1R_RGMII_0_450_NS 3 +#define YT8531_RC1R_RGMII_0_600_NS 4 +#define YT8531_RC1R_RGMII_0_750_NS 5 +#define YT8531_RC1R_RGMII_0_900_NS 6 +#define YT8531_RC1R_RGMII_1_050_NS 7 +#define YT8531_RC1R_RGMII_1_200_NS 8 +#define YT8531_RC1R_RGMII_1_350_NS 9 +#define YT8531_RC1R_RGMII_1_500_NS 10 +#define YT8531_RC1R_RGMII_1_650_NS 11 +#define YT8531_RC1R_RGMII_1_800_NS 12 +#define YT8531_RC1R_RGMII_1_950_NS 13 +#define YT8531_RC1R_RGMII_2_100_NS 14 +#define YT8531_RC1R_RGMII_2_250_NS 15 + +/* Phy gmii clock gating Register */ +#define YT8531_CLOCK_GATING_REG0xC +#define YT8531_CGR_RX_CLK_EN BIT(12) + +/* Specific Status Register */ +#define YTPHY_SPECIFIC_STATUS_REG 0x11 +#define YTPHY_DUPLEX_MASK BIT(13) +#define YTPHY_DUPLEX_SHIFT 13 +#define YTPHY_SPEED_MODE_MASK GENMASK(15, 14) +#define YTPHY_SPEED_MODE_SHIFT 14 + +#define YT8531_EXTREG_SLEEP_CONTROL1_REG 0x27 +#define YT8531_ESC1R_SLEEP_SW BIT(15) +#define YT8531_ESC1R_PLLON_SLP BIT(14) + +#define YT8531_RGMII_CONFIG1_REG 0xA003 + +#define YT8531_CHIP_CONFIG_REG 0xA001 +#define YT8531_CCR_SW_RST BIT(15) +/* 1b0 disable 1.9ns rxc clock delay *default* + * 1b1 en
[PATCH v1 5/5] configs: starfive: Enable ethernet configuration for StarFive VisionFive 2
Enable DWC_ETH_QOS and PHY_MOTORCOMM configuration to support ethernet function for StarFive VisionFive 2 board. Signed-off-by: Yanhong Wang --- configs/starfive_visionfive2_defconfig | 13 + 1 file changed, 13 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 550d0ff3ab..18f0d8fd27 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -52,6 +52,9 @@ CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_MEMINFO=y CONFIG_CMD_TFTPPUT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_JH7110=y @@ -65,6 +68,15 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PHY_MOTORCOMM=y +# CONFIG_PHY_MSCC is not set +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_STARFIVE=y +CONFIG_RGMII=y +# CONFIG_MII is not set +CONFIG_RMII=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y @@ -72,6 +84,7 @@ CONFIG_SPL_PINCONF=y CONFIG_SPL_PINCTRL_STARFIVE=y CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y CONFIG_PINCTRL_STARFIVE=y +# CONFIG_POWER is not set # CONFIG_RAM_SIFIVE is not set CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y -- 2.17.1
[PATCH v1 0/5] Add Ethernet driver for StarFive JH7110 SoC
This series adds ethernet support for the StarFive JH7110 RISC-V SoC. The series includes PHY and MAC drivers. The PHY model is YT8531 (from Motorcomm Inc), and the MAC version is dwmac-5.20 (from Synopsys DesignWare). The implementation of the phy driver is ported from linux, but it has been adjusted for the u-boot framework. The PHY and MAC driver has been tested on the StarFive VisionFive 2 1.2A and 1.3B boards and works normally. For more information and support,you can visit RVspace wiki[1]. This patchset should be applied after the patchset [2]. [1] https://wiki.rvspace.org/ [2] https://patchwork.ozlabs.org/project/uboot/cover/20230316025332.3297-1-yanhong.w...@starfivetech.com/ Yanhong Wang (5): net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy net: dwc_eth_qos: Add StarFive ethernet driver glue layer riscv: dts: jh7110: Add ethernet device tree nodes riscv: dts: starfive: Add phy clock delay configuration for StarFive VisionFive2 board configs: starfive: Enable ethernet configuration for StarFive VisionFive 2 .../jh7110-starfive-visionfive-2-v1.2a.dts| 13 + .../jh7110-starfive-visionfive-2-v1.3b.dts| 27 ++ .../dts/jh7110-starfive-visionfive-2.dtsi | 34 ++ arch/riscv/dts/jh7110.dtsi| 69 +++ configs/starfive_visionfive2_defconfig| 13 + drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 6 + drivers/net/dwc_eth_qos.h | 2 + drivers/net/dwc_eth_qos_starfive.c| 306 + drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/motorcomm.c | 409 ++ drivers/net/phy/phy.c | 4 +- include/phy.h | 1 + 15 files changed, 898 insertions(+), 1 deletion(-) create mode 100644 drivers/net/dwc_eth_qos_starfive.c create mode 100644 drivers/net/phy/motorcomm.c base-commit: 3ad7642443aee9369726844ffcfe5b9ae68c259e -- 2.17.1
[PATCH v1 4/5] riscv: dts: starfive: Add phy clock delay configuration for StarFive VisionFive2 board
The StarFive VisionFive2 board include 1.2A and 1.3B version.
v1.3B uses motorcomm YT8531(rgmii-id phy) x2, phy clock need delay and
inverse configurations.
v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs phy clock
delay configurations.
v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to switch rx and
tx to external clock sources.
Signed-off-by: Yanhong Wang
---
.../jh7110-starfive-visionfive-2-v1.2a.dts| 13 +++
.../jh7110-starfive-visionfive-2-v1.3b.dts| 27 +++
.../dts/jh7110-starfive-visionfive-2.dtsi | 34 +++
3 files changed, 74 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
index b9d26d7af7..918e77220a 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
@@ -10,3 +10,16 @@
model = "StarFive VisionFive 2 v1.2A";
compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
};
+
+ {
+ phy-mode = "rmii";
+ assigned-clocks = < JH7110_SYSCLK_GMAC1_TX>,
+ < JH7110_SYSCLK_GMAC1_RX>;
+ assigned-clock-parents = < JH7110_SYSCLK_GMAC1_RMII_RTX>,
+< JH7110_SYSCLK_GMAC1_RMII_RTX>;
+};
+
+ {
+ rx-internal-delay-ps = <1900>;
+ tx-internal-delay-ps = <1350>;
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
index 3b3b3453a1..0fcd6ab80f 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
@@ -10,3 +10,30 @@
model = "StarFive VisionFive 2 v1.3B";
compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
};
+
+ {
+ starfive,tx-use-rgmii-clk;
+ assigned-clocks = < JH7110_AONCLK_GMAC0_TX>;
+ assigned-clock-parents = < JH7110_AONCLK_GMAC0_RMII_RTX>;
+};
+
+ {
+ starfive,tx-use-rgmii-clk;
+ assigned-clocks = < JH7110_SYSCLK_GMAC1_TX>;
+ assigned-clock-parents = < JH7110_SYSCLK_GMAC1_RMII_RTX>;
+};
+
+ {
+ motorcomm,tx-clk-adj-enabled;
+ motorcomm,tx-clk-100-inverted;
+ motorcomm,tx-clk-1000-inverted;
+ rx-internal-delay-ps = <1900>;
+ tx-internal-delay-ps = <1500>;
+};
+
+ {
+ motorcomm,tx-clk-adj-enabled;
+ motorcomm,tx-clk-100-inverted;
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <0>;
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..3c1148ae2d 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -17,6 +17,8 @@
i2c2 =
i2c5 =
i2c6 =
+ ethernet0 =
+ ethernet1 =
};
chosen {
@@ -317,3 +319,35 @@
assigned-clock-parents = <>;
assigned-clock-rates = <0>;
};
+
+ {
+ phy-handle = <>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+ {
+ phy-handle = <>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+ };
+};
--
2.17.1
[PATCH v1 3/5] riscv: dts: jh7110: Add ethernet device tree nodes
Add ethernet device tree node to support StarFive ethernet driver for
the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/jh7110.dtsi | 69 ++
1 file changed, 69 insertions(+)
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index d3e9f92987..67267d9024 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -244,6 +244,13 @@
#clock-cells = <0>;
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,lpi_en;
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <4>;
+ snps,blen = <256 128 64 32 0 0 0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -548,6 +555,68 @@
status = "disabled";
};
+ gmac0: ethernet@1603 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x1603 0x0 0x1>;
+ clocks = < JH7110_AONCLK_GMAC0_AXI>,
+< JH7110_AONCLK_GMAC0_AHB>,
+< JH7110_SYSCLK_GMAC0_PTP>,
+< JH7110_AONCLK_GMAC0_TX_INV>,
+< JH7110_SYSCLK_GMAC0_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = < JH7110_AONRST_GMAC0_AXI>,
+< JH7110_AONRST_GMAC0_AHB>;
+ reset-names = "stmmaceth", "ahb";
+ interrupts = <7>, <6>, <5>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <8>;
+ rx-fifo-depth = <2048>;
+ tx-fifo-depth = <2048>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <_axi_setup>;
+ snps,tso;
+ snps,en-tx-lpi-clockgating;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ starfive,syscon = <_syscon 0xc 0x12>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@1604 {
+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+ reg = <0x0 0x1604 0x0 0x1>;
+ clocks = < JH7110_SYSCLK_GMAC1_AXI>,
+< JH7110_SYSCLK_GMAC1_AHB>,
+< JH7110_SYSCLK_GMAC1_PTP>,
+< JH7110_SYSCLK_GMAC1_TX_INV>,
+< JH7110_SYSCLK_GMAC1_GTXC>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+ resets = < JH7110_SYSRST_GMAC1_AXI>,
+< JH7110_SYSRST_GMAC1_AHB>;
+ reset-names = "stmmaceth", "ahb";
+ interrupts = <78>, <77>, <76>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <8>;
+ rx-fifo-depth = <2048>;
+ tx-fifo-depth = <2048>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <_axi_setup>;
+ snps,tso;
+ snps,en-tx-lpi-clockgating;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ starfive,syscon = <_syscon 0x90 0x2>;
+ status = "disabled";
+ };
+
aoncrg: clock-controller@1700 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x1700 0x0 0x1>;
--
2.17.1
[PATCH v4 10/17] board: starfive: add StarFive VisionFive v2 board support
Add board support for StarFive VisionFive v2.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
board/starfive/visionfive2/MAINTAINERS| 7 +
board/starfive/visionfive2/Makefile | 7 +
board/starfive/visionfive2/spl.c | 87
.../visionfive2/starfive_visionfive2.c| 40 ++
doc/board/starfive/index.rst | 9 +
doc/board/starfive/visionfive2.rst| 492 ++
include/configs/starfive-visionfive2.h| 49 ++
7 files changed, 691 insertions(+)
create mode 100644 board/starfive/visionfive2/MAINTAINERS
create mode 100644 board/starfive/visionfive2/Makefile
create mode 100644 board/starfive/visionfive2/spl.c
create mode 100644 board/starfive/visionfive2/starfive_visionfive2.c
create mode 100644 doc/board/starfive/index.rst
create mode 100644 doc/board/starfive/visionfive2.rst
create mode 100644 include/configs/starfive-visionfive2.h
diff --git a/board/starfive/visionfive2/MAINTAINERS
b/board/starfive/visionfive2/MAINTAINERS
new file mode 100644
index 00..c5369086d8
--- /dev/null
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -0,0 +1,7 @@
+STARFIVE JH7110 VISIONFIVE2 BOARD
+M: startfive
+S: Maintained
+F: arch/riscv/include/asm/arch-jh7110/
+F: board/starfive/visionfive2/
+F: include/configs/starfive-visionfive2.h
+F: configs/starfive_visionfive2_defconfig
diff --git a/board/starfive/visionfive2/Makefile
b/board/starfive/visionfive2/Makefile
new file mode 100644
index 00..66c854df39
--- /dev/null
+++ b/board/starfive/visionfive2/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+#
+
+obj-y := starfive_visionfive2.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
new file mode 100644
index 00..db0b4cb433
--- /dev/null
+++ b/board/starfive/visionfive2/spl.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
+#define JH7110_CLK_CPU_ROOT_SHIFT 24
+#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
+
+int spl_board_init_f(void)
+{
+ int ret;
+
+ ret = spl_soc_init();
+ if (ret) {
+ debug("JH7110 SPL init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+u32 spl_boot_device(void)
+{
+ u32 mode;
+
+ mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
+ & JH7110_BOOT_MODE_SELECT_MASK;
+ switch (mode) {
+ case 0:
+ return BOOT_DEVICE_SPI;
+
+ case 1:
+ return BOOT_DEVICE_MMC2;
+
+ case 2:
+ return BOOT_DEVICE_MMC1;
+
+ case 3:
+ return BOOT_DEVICE_UART;
+
+ default:
+ debug("Unsupported boot device 0x%x.\n", mode);
+ return BOOT_DEVICE_NONE;
+ }
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ ret = spl_early_init();
+ if (ret)
+ panic("spl_early_init() failed: %d\n", ret);
+
+ riscv_cpu_setup(NULL, NULL);
+ preloader_console_init();
+
+ /* Set the parent clock of cpu_root clock to pll0,
+* it must be initialized here
+*/
+ clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_CPU_ROOT_OFFSET,
+ JH7110_CLK_CPU_ROOT_MASK,
+ BIT(JH7110_CLK_CPU_ROOT_SHIFT));
+
+ ret = spl_board_init_f();
+ if (ret) {
+ debug("spl_board_init_f init failed: %d\n", ret);
+ return;
+ }
+}
+
+#if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ /* boot using first FIT config */
+ return 0;
+}
+#endif
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c
b/board/starfive/visionfive2/starfive_visionfive2.c
new file mode 100644
index 00..613fe793c4
--- /dev/null
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+
+#define JH7110_L2_PREFETCHER_BASE_ADDR 0x203
+#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000
+
+/* enable U74-mc hart1~hart4 prefetcher */
+static void enable_prefetcher(void)
+{
+ u8 hart;
+ u32 *reg;
+
+ /* JH7110 use U74MC CORE IP, it include five cores(one S7 and four U7),
+* but only U7 cores support prefetcher configuration
+*/
+ for (hart = 1; hart < 5; hart++) {
+ reg = (void *)(u64)(JH7110_L2_PREFETCHER_BASE_ADDR
+
[PATCH v4 09/17] ram: starfive: add ddr driver
Add driver for StarFive JH7110 to support ddr initialization in SPL.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
drivers/ram/Kconfig |1 +
drivers/ram/Makefile|4 +-
drivers/ram/starfive/Kconfig|5 +
drivers/ram/starfive/Makefile | 11 +
drivers/ram/starfive/ddrcsr_boot.c | 339 +
drivers/ram/starfive/ddrphy_start.c | 279
drivers/ram/starfive/ddrphy_train.c | 383 ++
drivers/ram/starfive/ddrphy_utils.c | 1955 +++
drivers/ram/starfive/starfive_ddr.c | 161 +++
drivers/ram/starfive/starfive_ddr.h | 65 +
10 files changed, 3202 insertions(+), 1 deletion(-)
create mode 100644 drivers/ram/starfive/Kconfig
create mode 100644 drivers/ram/starfive/Makefile
create mode 100644 drivers/ram/starfive/ddrcsr_boot.c
create mode 100644 drivers/ram/starfive/ddrphy_start.c
create mode 100644 drivers/ram/starfive/ddrphy_train.c
create mode 100644 drivers/ram/starfive/ddrphy_utils.c
create mode 100644 drivers/ram/starfive/starfive_ddr.c
create mode 100644 drivers/ram/starfive/starfive_ddr.h
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index e085119963..1acf212f87 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -112,3 +112,4 @@ source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
source "drivers/ram/octeon/Kconfig"
+source "drivers/ram/starfive/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 83948e2c43..2b9429cfee 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -20,5 +20,7 @@ obj-$(CONFIG_K3_DDRSS) += k3-ddrss/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
obj-$(CONFIG_RAM_SIFIVE) += sifive/
-
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/
+endif
obj-$(CONFIG_ARCH_OCTEON) += octeon/
diff --git a/drivers/ram/starfive/Kconfig b/drivers/ram/starfive/Kconfig
new file mode 100644
index 00..80c790066f
--- /dev/null
+++ b/drivers/ram/starfive/Kconfig
@@ -0,0 +1,5 @@
+config SPL_STARFIVE_DDR
+ bool "StarFive DDR driver in SPL"
+ depends on SPL_RAM && STARFIVE_JH7110
+ help
+ This enables DDR support for the platforms based on StarFive JH7110
SoC.
diff --git a/drivers/ram/starfive/Makefile b/drivers/ram/starfive/Makefile
new file mode 100644
index 00..1df42c377b
--- /dev/null
+++ b/drivers/ram/starfive/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 StarFive, Inc
+#
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_start.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_train.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive_ddr.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_utils.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrcsr_boot.o
+endif
\ No newline at end of file
diff --git a/drivers/ram/starfive/ddrcsr_boot.c
b/drivers/ram/starfive/ddrcsr_boot.c
new file mode 100644
index 00..f2dd55f74a
--- /dev/null
+++ b/drivers/ram/starfive/ddrcsr_boot.c
@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "starfive_ddr.h"
+
+#define REGOFFSET(offset) ((offset) / 4)
+
+static const struct ddr_reg_cfg ddr_csr_cfg[] = {
+ {0x0, 0x0,0x0001, REGSETALL},
+ {0xf00, 0x0,0x40001030, (OFFSET_SEL | F_SET | REG4G |
REG8G)},
+ {0xf00, 0x0,0x40001030, (OFFSET_SEL | F_SET | REG2G)},
+ {0xf04, 0x0,0x0001, (OFFSET_SEL | F_SET | REG4G |
REG8G)},
+ {0xf04, 0x0,0x0081, (OFFSET_SEL | F_SET | REG2G)},
+ {0xf10, 0x0,0x0040, (OFFSET_SEL | REGSETALL)},
+ {0xf14, 0x0,0x043f, (OFFSET_SEL | REGSETALL)},
+ {0xf18, 0x0,0x, (OFFSET_SEL | REGSETALL)},
+ {0xf30, 0x0,0x1f41, (OFFSET_SEL | REGSETALL)},
+ {0xf34, 0x0,0x1f41, (OFFSET_SEL | F_SET | REG4G |
REG8G)},
+ {0x110, 0x0,0xc001, (OFFSET_SEL | REGSETALL)},
+ {0x114, 0x0,0x, (OFFSET_SEL | REGSETALL)},
+ {0x10c, 0x0,0x0505, REGSETALL},
+ {0x11c, 0x0,0x, REGSETALL},
+ {0x500, 0x0,0x0201, REGSETALL},
+ {0x514, 0x0,0x0100, REGSETALL},
+ {0x6a8, 0x0,0x0004, REGSETALL},
+ {0xea8, 0x0,0x0004, REGSETALL},
+ {0x504, 0x0,0x4000, REGSETALL}
+};
+
+static const struct ddr_reg_cfg ddr_csr_cfg1[] = {
+ {0x310, 0x0,0x0002, REGSETALL},
+ {0x310, 0x0,0x00020001, REGSETALL},
+ {
[PATCH v4 15/17] riscv: dts: jh7110: Add initial u-boot device tree
Add initial u-boot device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
arch/riscv/dts/jh7110-u-boot.dtsi | 99 +++
1 file changed, 99 insertions(+)
create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi
b/arch/riscv/dts/jh7110-u-boot.dtsi
new file mode 100644
index 00..31ca054f54
--- /dev/null
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include
+
+/ {
+ cpus: cpus {
+ u-boot,dm-spl;
+
+ S7_0: cpu@0 {
+ u-boot,dm-spl;
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ U74_1: cpu@1 {
+ u-boot,dm-spl;
+ cpu1_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ U74_2: cpu@2 {
+ u-boot,dm-spl;
+ cpu2_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ U74_3: cpu@3 {
+ u-boot,dm-spl;
+ cpu3_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ U74_4: cpu@4 {
+ u-boot,dm-spl;
+ cpu4_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ };
+
+ soc {
+ u-boot,dm-spl;
+
+ clint: timer@200 {
+ u-boot,dm-spl;
+ };
+
+ dmc: dmc@1570 {
+ u-boot,dm-spl;
+ compatible = "starfive,jh7110-dmc";
+ reg = <0x0 0x1570 0x0 0x1>,
+ <0x0 0x1300 0x0 0x1>;
+ resets = < JH7110_SYSRST_DDR_AXI>,
+ < JH7110_SYSRST_DDR_OSC>,
+ < JH7110_SYSRST_DDR_APB>;
+ reset-names = "axi", "osc", "apb";
+ clocks = < JH7110_SYSCLK_PLL1_OUT>;
+ clock-names = "pll1_out";
+ clock-frequency = <2133>;
+ };
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_rmii_refin {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ starfive,sys-syscon = <_syscon>;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_syscon {
+ u-boot,dm-spl;
+};
+
+_0 {
+ status = "okay";
+};
--
2.17.1
[PATCH v4 16/17] riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree
Add initial device tree for StarFive VisionFive v2 board.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
arch/riscv/dts/Makefile | 3 +-
...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 69
.../jh7110-starfive-visionfive-2-v1.2a.dts| 12 +
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69
.../jh7110-starfive-visionfive-2-v1.3b.dts| 12 +
.../dts/jh7110-starfive-visionfive-2.dtsi | 319 ++
6 files changed, 483 insertions(+), 1 deletion(-)
create mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
create mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index c576c55767..79a58694f5 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,7 +7,8 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.3b.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.2a.dtb
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
new file mode 100644
index 00..0b20be0f10
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ spi0 =
+ u-boot,dm-spl;
+ };
+
+ config {
+ u-boot,dm-spl;
+ u-boot,spl-payload-offset = <0x10>;
+ };
+
+ memory@4000 {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+
+ nor-flash@0 {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_pins {
+ u-boot,dm-spl;
+ mmc0-pins-rest {
+ u-boot,dm-spl;
+ };
+};
+
+_pins {
+ u-boot,dm-spl;
+ mmc1-pins0 {
+ u-boot,dm-spl;
+ };
+
+ mmc1-pins1 {
+ u-boot,dm-spl;
+ };
+};
+
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
new file mode 100644
index 00..b9d26d7af7
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 v1.2A";
+ compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
new file mode 100644
index 00..0b20be0f10
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ spi0 =
+ u-boot,dm-spl;
+ };
+
+ config {
+ u-boot,dm-spl;
+ u-boot,spl-payload-offset = <0x10>;
+ };
+
+ memory@4000 {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+
+ nor-flash@0 {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_pins {
+ u-boot,dm-spl;
+ mmc0-pins-rest {
+ u-boot,dm-spl;
+ };
+};
+
+_pins {
+ u-boot,dm-spl;
+ mmc1-pins0 {
+ u-boot,dm-spl;
+ };
+
+ mmc1-pins1 {
+ u-boot,dm-spl;
+ };
+};
+
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
new file mode 100644
index 00..3b3b34
[PATCH v4 11/17] riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC
Add Kconfig to select the basic functions for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- arch/riscv/cpu/jh7110/Kconfig | 28 1 file changed, 28 insertions(+) create mode 100644 arch/riscv/cpu/jh7110/Kconfig diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig new file mode 100644 index 00..3f145415eb --- /dev/null +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 StarFive Technology Co., Ltd. + +config STARFIVE_JH7110 + bool + select ARCH_EARLY_INIT_R + select CLK_JH7110 + select CPU + select CPU_RISCV + select RAM + select RESET_JH7110 + select SUPPORT_SPL + select SPL_RAM if SPL + select SPL_STARFIVE_DDR + select PINCTRL_STARFIVE_JH7110 + imply MMC + imply MMC_BROKEN_CD + imply MMC_SPI + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply SIFIVE_CACHE + imply SIFIVE_CCACHE + imply SMP + imply SPI + imply SPL_CPU + imply SPL_LOAD_FIT + imply SPL_OPENSBI + imply SPL_SIFIVE_CLINT -- 2.17.1
[PATCH v4 13/17] board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig
Add board support for StarFive VisionFive v2. Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- arch/riscv/Kconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 48ca4ff4c4..f6ed05906a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -24,6 +24,9 @@ config TARGET_SIFIVE_UNMATCHED bool "Support SiFive Unmatched Board" select SYS_CACHE_SHIFT_6 +config TARGET_STARFIVE_VISIONFIVE2 + bool "Support StarFive VisionFive2 Board" + config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 @@ -65,12 +68,14 @@ source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" +source "board/starfive/visionfive2/Kconfig" # platform-specific options below source "arch/riscv/cpu/andesv5/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" +source "arch/riscv/cpu/jh7110/Kconfig" # architecture-specific options below -- 2.17.1
[PATCH v4 14/17] riscv: dts: jh7110: Add initial StarFive JH7110 device tree
Add initial device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
arch/riscv/dts/jh7110.dtsi | 582 +
1 file changed, 582 insertions(+)
create mode 100644 arch/riscv/dts/jh7110.dtsi
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
new file mode 100644
index 00..d3e9f92987
--- /dev/null
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -0,0 +1,582 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include
+#include
+
+/ {
+ compatible = "starfive,jh7110";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ S7_0: cpu@0 {
+ compatible = "sifive,s7", "riscv";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <8192>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <16384>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ riscv,isa = "rv64imac_zba_zbb";
+ tlb-split;
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_1: cpu@1 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <1>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ riscv,isa = "rv64imafdc_zba_zbb";
+ tlb-split;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_2: cpu@2 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <2>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ riscv,isa = "rv64imafdc_zba_zbb";
+ tlb-split;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_3: cpu@3 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <3>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40&
[PATCH v4 17/17] configs: starfive: add starfive_visionfive2_defconfig
This is the initial basic config for StarFive VisionFive v2 board. It
includes consol, Norflash, sdio, ddr etc.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
configs/starfive_visionfive2_defconfig | 79 ++
1 file changed, 79 insertions(+)
create mode 100644 configs/starfive_visionfive2_defconfig
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
new file mode 100644
index 00..550d0ff3ab
--- /dev/null
+++ b/configs/starfive_visionfive2_defconfig
@@ -0,0 +1,79 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x80
+CONFIG_SYS_MALLOC_F_LEN=0x1
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b"
+CONFIG_SPL_TEXT_BASE=0x800
+CONFIG_SYS_PROMPT="StarFive #"
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_STACK=0x818
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
+CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
+CONFIG_ARCH_RV64I=y
+CONFIG_CMODEL_MEDANY=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_QSPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
+CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_BSS_START_ADDR=0x804
+CONFIG_SPL_BSS_MAX_SIZE=0x1
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x40
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
+CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_JH7110=y
+# CONFIG_I2C is not set
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_SF_DEFAULT_SPEED=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_SPL_PINCONF=y
+CONFIG_SPL_PINCTRL_STARFIVE=y
+CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
+CONFIG_PINCTRL_STARFIVE=y
+# CONFIG_RAM_SIFIVE is not set
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER_EARLY=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--
2.17.1
[PATCH v4 12/17] board: starfive: Add Kconfig for StarFive VisionFive v2 Board
Add Kconfig to select the basic functions for StarFive VisionFive v2 Board. Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- board/starfive/visionfive2/Kconfig | 53 ++ 1 file changed, 53 insertions(+) create mode 100644 board/starfive/visionfive2/Kconfig diff --git a/board/starfive/visionfive2/Kconfig b/board/starfive/visionfive2/Kconfig new file mode 100644 index 00..2186a93964 --- /dev/null +++ b/board/starfive/visionfive2/Kconfig @@ -0,0 +1,53 @@ +if TARGET_STARFIVE_VISIONFIVE2 + +config SYS_CPU + default "jh7110" + +config SYS_BOARD + default "visionfive2" + +config SYS_VENDOR + default "starfive" + +config SYS_CONFIG_NAME + default "starfive-visionfive2" + +config TEXT_BASE + default 0x4020 if SPL + default 0x4000 if !RISCV_SMODE + default 0x4020 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x0800 + +config SPL_OPENSBI_LOAD_ADDR + default 0x8000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select STARFIVE_JH7110 + select SUPPORT_SPL + select BINMAN + imply CMD_CPU + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_GPIO + imply CMD_GPT + imply CMD_MMC + imply CMD_NET + imply CMD_PING + imply CMD_SF + imply DM_GPIO + imply DOS_PARTITION + imply EFI_PARTITION + imply MII + imply IP_DYN + imply ISO_PARTITION + imply PARTITION_TYPE_GUID + imply PHY_LIB + imply PHY_MSCC + +endif -- 2.17.1
