Re: [U-Boot-Users] [PATCH] I2C Dummy Driver
Wolfgang Denk schrieb:
> In message <[EMAIL PROTECTED]> you wrote:
>
>> Signed-off-by: Ricardo Ribalda Delgado <[EMAIL PROTECTED]>
>>
>
> What is the intention or practical use of this dummy driver?
>
>
>
I think we could use it well for mounting different memory
configurations on the same base board.
This happens frequently due to different size requests from customers or
chip-replacement.
Actually I'll have to compile u-boot for each memory config ... very bad.
Getting the data out of flash (environment or small dedicated sector)
would be fine.
Creating valid eeprom entries for use as SPD is another thing of ocurse.
>> --- a/drivers/i2c/Makefile
>> +++ b/drivers/i2c/Makefile
>> @@ -30,6 +30,7 @@ COBJS-y += omap1510_i2c.o
>>
> ...
>
>> +COBJS-y += dummy_i2c.o
>>
>
> Please make "COBJS-$(CONFIG_DUMMY_I2C) += dummy_i2c.o" and ...
>
>
>> diff --git a/drivers/i2c/dummy_i2c.c b/drivers/i2c/dummy_i2c.c
>> new file mode 100644
>> index 000..04f6edb
>> --- /dev/null
>> +++ b/drivers/i2c/dummy_i2c.c
>> @@ -0,0 +1,84 @@
>>
> ...
>
>
>> +(C) Copyright 2008
>> +Ricado Ribalda, Universidad Autonoma de Madrid,
>> ricardo.ribaldauam.es , ricardo.ribaldagmail.com
>>
>
> [Line too long]
>
>
>> +This program is free software: you can redistribute it and/or modify
>> +it under the terms of the GNU General Public License as published by
>> +the Free Software Foundation, either version 3 of the License, or
>> +(at your option) any later version.
>>
>
> [ GPLv2 needed]
>
>
>> +#if defined(CONFIG_DUMMY_I2C)
>>
>
> ... drop this #ifdef / #endif
>
>
>> +
>> +#include
>> +u8
>> i2c_dummy_buffer[256]={0x80,0x8,0x8,0x0D,0x0A,0x60,0x40,0x0,0x5,0x3D,0x50,0x0,0x82,0x10,0x0,0x0,0x0C,0x4,0x18,0x1,0x4,0x0,0x1,0x50,0x50,0x0,0x0,0x3C,0x28,0x3C,0x2D,0x40,0x25,0x37,0x10,0x22,0x3C,0x1E,0x1E,0x0,0x0,0x3C,0x69,0x80,0x1E,0x28,0x0,0x0,0x0,
>> 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x12,0xC9,0x2C,'0','0','0','0','0','0','0',0x0,'4','H','T','F','3','2','6','4','H','Y','-','5','3','E','D','3',0x3,0x0,0x0,0x0,0x0};
>>
>
> Line way too long.
>
> Maybe you also want to explain where these magic data is coming from
> or what it means?
>
>
>> +if (alen!=1)
>>
>
> if (alen != 1)
>
>
>> +return -1;
>> +
>> +if (addr+len>0xff)
>>
>
> if (addr+len > 0xff)
>
>
>> +return -1;
>> +
>> +for(i=0;i>
>
> for (i=0; i
>
>> +buffer[i]=i2c_dummy_buffer[i+addr];
>>
>
> buffer[i] = i2c_dummy_buffer[i+addr];
>
> etc., please.
>
>
> Best regards,
>
> Wolfgang Denk
>
>
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
-
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[U-Boot-Users] [PATCH v4] Add MVBC_P board
The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
Please see doc/README.mvbc_p for details.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
Grant,
please have a look at v4 which additionally adresses Wolfgangs comments.
Let me know if anything is still incorrect.
regards,
Andre
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
CREDITS |2 +-
MAINTAINERS |1 +
MAKEALL |1 +
Makefile |7 +
board/matrix_vision/mvbc_p/Makefile | 50
board/matrix_vision/mvbc_p/config.mk | 30 +++
board/matrix_vision/mvbc_p/fpga.c| 177 ++
board/matrix_vision/mvbc_p/fpga.h| 34 +++
board/matrix_vision/mvbc_p/mvbc_p.c | 325 ++
board/matrix_vision/mvbc_p/mvbc_p.h | 43
board/matrix_vision/mvbc_p/mvbc_p_autoscript | 44
doc/README.mvbc_p| 74 ++
include/configs/MVBC_P.h | 316 +
include/mpc5xxx.h| 29 +++
14 files changed, 1132 insertions(+), 1 deletions(-)
diff --git a/CREDITS b/CREDITS
index aa57682..b1c10fd 100644
--- a/CREDITS
+++ b/CREDITS
@@ -426,7 +426,7 @@ D: FADS823 configuration, MPC823 video support, I2C,
wireless keyboard, lots mor
N: Andre Schwarz
E: [EMAIL PROTECTED]
-D: Support for Matrix Vision boards (MVBLM7)
+D: Support for Matrix Vision boards (MVBLM7/MVBC_P)
N: Robert Schwebel
E: [EMAIL PROTECTED]
diff --git a/MAINTAINERS b/MAINTAINERS
index a3d70b1..9af5730 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -373,6 +373,7 @@ Peter De Schrijver <[EMAIL PROTECTED]>
Andre Schwarz <[EMAIL PROTECTED]>
+ mvbc_p MPC5200
mvblm7 MPC8343
Timur Tabi <[EMAIL PROTECTED]>
diff --git a/MAKEALL b/MAKEALL
index 9f80b3d..75261c1 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -48,6 +48,7 @@ LIST_5xxx=" \
mecp5200\
motionpro \
munices \
+ MVBC_P \
o2dnt \
pf5200 \
PM520 \
diff --git a/Makefile b/Makefile
index ac3f98f..e963e0f 100644
--- a/Makefile
+++ b/Makefile
@@ -743,6 +743,13 @@ uc101_config: unconfig
motionpro_config: unconfig
@$(MKCONFIG) motionpro ppc mpc5xxx motionpro
+MVBC_P_config: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/mvbc_p
+ @ >$(obj)include/config.h
+ @[ -z "$(findstring MVBC_P,$@)" ] || \
+ { echo "#define CONFIG_MVBC_P">>$(obj)include/config.h; }
+ @$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p matrix_vision
#
## MPC512x Systems
diff --git a/board/matrix_vision/mvbc_p/Makefile
b/board/matrix_vision/mvbc_p/Makefile
new file mode 100644
index 000..ea72f77
--- /dev/null
+++ b/board/matrix_vision/mvbc_p/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# (C) Copyright 2004-2008
+# Matrix-Vision GmbH, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o fpga.o
+
+SRCS:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS:= $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/matrix_vision/mvbc_p/config.mk
b/board/matrix_vision/mvbc_p/config.mk
new file mo
[U-Boot-Users] [PATCH v3] Add MVBC_P board
The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
Please see doc/README.mvbc_p for details.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
Grant,
please find attached v3 with further mods :
- change all pointer ops to in_* out_*
- move GPIO bit defines into mpc5xxx.h
- move board to company subdir
Common usage of the fpga.c (Kim's proposal) will be patched separately along
with an mvBL-M7 board movement to company subdir.
Please let me know if there's still somehting that needs fixing.
regards,
Andre
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
CREDITS |2 +-
MAINTAINERS |1 +
MAKEALL |1 +
Makefile |8 +
board/matrix_vision/mvbc_p/Makefile | 50
board/matrix_vision/mvbc_p/config.mk | 30 +++
board/matrix_vision/mvbc_p/fpga.c| 177 ++
board/matrix_vision/mvbc_p/fpga.h| 34 +++
board/matrix_vision/mvbc_p/mvbc_p.c | 325 ++
board/matrix_vision/mvbc_p/mvbc_p.h | 43
board/matrix_vision/mvbc_p/mvbc_p_autoscript | 44
doc/README.mvbc_p| 74 ++
include/configs/MVBC_P.h | 316 +
include/mpc5xxx.h| 29 +++
14 files changed, 1133 insertions(+), 1 deletions(-)
diff --git a/CREDITS b/CREDITS
index aa57682..b1c10fd 100644
--- a/CREDITS
+++ b/CREDITS
@@ -426,7 +426,7 @@ D: FADS823 configuration, MPC823 video support, I2C,
wireless keyboard, lots mor
N: Andre Schwarz
E: [EMAIL PROTECTED]
-D: Support for Matrix Vision boards (MVBLM7)
+D: Support for Matrix Vision boards (MVBLM7/MVBC_P)
N: Robert Schwebel
E: [EMAIL PROTECTED]
diff --git a/MAINTAINERS b/MAINTAINERS
index a3d70b1..9af5730 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -373,6 +373,7 @@ Peter De Schrijver <[EMAIL PROTECTED]>
Andre Schwarz <[EMAIL PROTECTED]>
+ mvbc_p MPC5200
mvblm7 MPC8343
Timur Tabi <[EMAIL PROTECTED]>
diff --git a/MAKEALL b/MAKEALL
index 9f80b3d..75261c1 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -48,6 +48,7 @@ LIST_5xxx=" \
mecp5200\
motionpro \
munices \
+ MVBC_P \
o2dnt \
pf5200 \
PM520 \
diff --git a/Makefile b/Makefile
index ac3f98f..e1d2f7a 100644
--- a/Makefile
+++ b/Makefile
@@ -743,6 +743,14 @@ uc101_config: unconfig
motionpro_config: unconfig
@$(MKCONFIG) motionpro ppc mpc5xxx motionpro
+MVBC_P_config: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/mvbc_p
+ @ >$(obj)include/config.h
+ @[ -z "$(findstring MVBC_P,$@)" ] || \
+ { echo "#define CONFIG_MVBC_P">>$(obj)include/config.h; \
+ }
+ @$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p matrix_vision
#
## MPC512x Systems
diff --git a/board/matrix_vision/mvbc_p/Makefile
b/board/matrix_vision/mvbc_p/Makefile
new file mode 100644
index 000..7ae34cf
--- /dev/null
+++ b/board/matrix_vision/mvbc_p/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# (C) Copyright 2004-2008
+# Matrix-Vision GmbH, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o fpga.o
+
+SRCS:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS:= $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(O
[U-Boot-Users] [PATCH v2] Add MVBC_P board
The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
Please see doc/README.mvbc_p for details.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
Grant,
I've modified the patch to meet the requested changes on the list from Kim and
Wolfgang.
- Add MK_STR define inside header and use it for environment
- get rid of sync instruction by using out_* accessors
- get rid of various ifdefs since they are not used anyway
- get rid of unused function hw_watchdog_reset()
Hope this helps in applying this patch.
regards,
Andre
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
CREDITS|2 +-
MAINTAINERS|1 +
MAKEALL|1 +
Makefile |8 +
board/mvbc_p/Makefile | 50 ++
board/mvbc_p/config.mk | 30
board/mvbc_p/fpga.c| 177 +
board/mvbc_p/fpga.h| 34
board/mvbc_p/mvbc_p.c | 333
board/mvbc_p/mvbc_p.h | 72 +
board/mvbc_p/mvbc_p_autoscript | 44 ++
doc/README.mvbc_p | 74 +
include/configs/MVBC_P.h | 316 ++
13 files changed, 1141 insertions(+), 1 deletions(-)
diff --git a/CREDITS b/CREDITS
index aa57682..b1c10fd 100644
--- a/CREDITS
+++ b/CREDITS
@@ -426,7 +426,7 @@ D: FADS823 configuration, MPC823 video support, I2C,
wireless keyboard, lots mor
N: Andre Schwarz
E: [EMAIL PROTECTED]
-D: Support for Matrix Vision boards (MVBLM7)
+D: Support for Matrix Vision boards (MVBLM7/MVBC_P)
N: Robert Schwebel
E: [EMAIL PROTECTED]
diff --git a/MAINTAINERS b/MAINTAINERS
index a3d70b1..9af5730 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -373,6 +373,7 @@ Peter De Schrijver <[EMAIL PROTECTED]>
Andre Schwarz <[EMAIL PROTECTED]>
+ mvbc_p MPC5200
mvblm7 MPC8343
Timur Tabi <[EMAIL PROTECTED]>
diff --git a/MAKEALL b/MAKEALL
index 9f80b3d..75261c1 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -48,6 +48,7 @@ LIST_5xxx=" \
mecp5200\
motionpro \
munices \
+ MVBC_P \
o2dnt \
pf5200 \
PM520 \
diff --git a/Makefile b/Makefile
index ac3f98f..c8bc307 100644
--- a/Makefile
+++ b/Makefile
@@ -743,6 +743,14 @@ uc101_config: unconfig
motionpro_config: unconfig
@$(MKCONFIG) motionpro ppc mpc5xxx motionpro
+MVBC_P_config: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/mvbc_p
+ @ >$(obj)include/config.h
+ @[ -z "$(findstring MVBC_P,$@)" ] || \
+ { echo "#define CONFIG_MVBC_P">>$(obj)include/config.h; \
+ }
+ @$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p
#
## MPC512x Systems
diff --git a/board/mvbc_p/Makefile b/board/mvbc_p/Makefile
new file mode 100644
index 000..7ae34cf
--- /dev/null
+++ b/board/mvbc_p/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# (C) Copyright 2004-2008
+# Matrix-Vision GmbH, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o fpga.o
+
+SRCS:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS:= $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/mvbc_p/config.mk b/board/mvbc_p/config.mk
new file mode 100644
index 000..1
Re: [U-Boot-Users] [PATCH] Add MVBC_P board
Kim,
I forgot to mention that both fpga.c are _not_ the same.
They are using different FPGA sizes _and_ different I/Os on different cpu.
It's not possible for me to use a common file for the short term.
Maybe later when the FPGA interface got mature ...
regards,
Andre
Kim Phillips schrieb:
> On Fri, 04 Jul 2008 09:42:24 +0200
> Andre Schwarz <[EMAIL PROTECTED]> wrote:
>
> Hello Andre,
>
>
>> board/mvbc_p/fpga.c| 177
>> board/mvbc_p/fpga.h| 34
>>
>
> couldn't help but notice this file is equal to board/mvblm7/fpga.c.
> Perhaps it's time to add your board/$(VENDOR)/common directory and put
> both this file and its header there. This way you can make your code
> more maintainable by avoiding duplicating it all over the place.
>
>
>> +@$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p
>>
>
> assuming $VENDOR == matrix-vision or something (your choice), you'd
> have to modify the above line like so:
>
> - @$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p
> + @$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p matrix-vision
>
> to enable building your (now a single copy) fpga.c.
>
>
>> +#ifdef CONFIG_OF_LIBFDT
>> +#include
>> +#endif
>>
>
> it'd be nice to get rid of ifdeffing CONFIG_OF_LIBFDT all over the
> place, assuming, of course, you won't be supporting booting a
> non-fdt-aware OS.
>
>
>> +gpio->simple_ddr = SIMPLE_DDR;
>> +gpio->simple_dvo = SIMPLE_DVO;
>> +gpio->simple_ode = SIMPLE_ODE;
>> +gpio->simple_gpioe = SIMPLE_GPIOEN;
>> +
>> +gpio->sint_ode = SINT_ODE;
>> +gpio->sint_ddr = SINT_DDR;
>> +gpio->sint_dvo = SINT_DVO;
>> +gpio->sint_inten = SINT_INTEN;
>> +gpio->sint_itype = SINT_ITYPE;
>> +gpio->sint_gpioe = SINT_GPIOEN;
>> +
>> +*(vu_char *)MPC5XXX_WU_GPIO_ODE = WKUP_ODE;
>> +*(vu_char *)MPC5XXX_WU_GPIO_DIR = WKUP_DIR;
>> +*(vu_char *)MPC5XXX_WU_GPIO_DATA_O = WKUP_DO | ARB_X_EN;
>> +*(vu_char *)MPC5XXX_WU_GPIO_ENABLE = WKUP_EN;
>> +
>> +printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
>> +printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe);
>> +__asm__ volatile ("sync");
>> +}
>>
>
> same comment Wolfgang made; use in_* out_* accessor fns.
>
>
>> +void hw_watchdog_reset(void)
>> +{
>> +*(u8*) (0xff05) = 0;
>>
>
> is this a magic number/needs a #define somewhere?
>
>
>> +#define MV_FPGA_DATA"0xff86"
>> +#define MV_FPGA_SIZE"0x3c886"
>> +#define MV_KERNEL_ADDR "0xffc0"
>> +#define MV_INITRD_ADDR "0xff90"
>> +#define MV_INITRD_LENGTH"0x0030"
>> +#define MV_SCRATCH_ADDR "0x"
>> +#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
>> +#define MV_AUTOSCR_ADDR "0xff84"
>> +#define MV_AUTOSCR_ADDR2"0xff85"
>> +#define MV_DTB_ADDR "0xfffc"
>>
>
> please use MK_STR (see other config files, e.g. MPC8313).
>
>
>> +
>> +#define CONFIG_SHOW_BOOT_PROGRESS 1
>> +
>> +#define MV_KERNEL_ADDR_RAM "0x0010"
>> +#define MV_DTB_ADDR_RAM "0x0060"
>> +#define MV_INITRD_ADDR_RAM "0x0100"
>> +
>> +/* pass open firmware flat tree */
>> +#define CONFIG_OF_LIBFDT1
>> +#define CONFIG_OF_BOARD_SETUP 1
>> +
>> +#define OF_CPU "PowerPC,[EMAIL PROTECTED]"
>> +#define OF_SOC "[EMAIL PROTECTED]"
>> +#define OF_TBCLK(bd->bi_busfreq / 4)
>>
>
> I thought we had done away with the above three (FLAT_TREE now
> obsolete). Oh, I see now: 5xxx still uses it in LIBFDT code. Bad 5xxx!
>
> Kim
>
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
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Re: [U-Boot-Users] [PATCH] Add MVBC_P board
Kim,
thanks for the hints.
Kim Phillips schrieb:
> On Fri, 04 Jul 2008 09:42:24 +0200
> Andre Schwarz <[EMAIL PROTECTED]> wrote:
>
> Hello Andre,
>
>
>> board/mvbc_p/fpga.c| 177
>> board/mvbc_p/fpga.h| 34
>>
>
> couldn't help but notice this file is equal to board/mvblm7/fpga.c.
> Perhaps it's time to add your board/$(VENDOR)/common directory and put
> both this file and its header there. This way you can make your code
> more maintainable by avoiding duplicating it all over the place.
>
>
yes.
>> +@$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p
>>
>
> assuming $VENDOR == matrix-vision or something (your choice), you'd
> have to modify the above line like so:
>
> - @$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p
> + @$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p matrix-vision
>
> to enable building your (now a single copy) fpga.c.
>
>
Of course you're right - but I'd like to add all boards first in order
_not_ to mix patches for different boards.
Maybe we can do this _after_ adding this board ?
If this is not ok I'll fix it right now ...
>> +#ifdef CONFIG_OF_LIBFDT
>> +#include
>> +#endif
>>
>
> it'd be nice to get rid of ifdeffing CONFIG_OF_LIBFDT all over the
> place, assuming, of course, you won't be supporting booting a
> non-fdt-aware OS.
>
>
ok.
>> +gpio->simple_ddr = SIMPLE_DDR;
>> +gpio->simple_dvo = SIMPLE_DVO;
>> +gpio->simple_ode = SIMPLE_ODE;
>> +gpio->simple_gpioe = SIMPLE_GPIOEN;
>> +
>> +gpio->sint_ode = SINT_ODE;
>> +gpio->sint_ddr = SINT_DDR;
>> +gpio->sint_dvo = SINT_DVO;
>> +gpio->sint_inten = SINT_INTEN;
>> +gpio->sint_itype = SINT_ITYPE;
>> +gpio->sint_gpioe = SINT_GPIOEN;
>> +
>> +*(vu_char *)MPC5XXX_WU_GPIO_ODE = WKUP_ODE;
>> +*(vu_char *)MPC5XXX_WU_GPIO_DIR = WKUP_DIR;
>> +*(vu_char *)MPC5XXX_WU_GPIO_DATA_O = WKUP_DO | ARB_X_EN;
>> +*(vu_char *)MPC5XXX_WU_GPIO_ENABLE = WKUP_EN;
>> +
>> +printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
>> +printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe);
>> +__asm__ volatile ("sync");
>> +}
>>
>
> same comment Wolfgang made; use in_* out_* accessor fns.
>
>
yes - as already mentioned I'll wait for some more feedback before
re-submitting a modified patch.
>> +void hw_watchdog_reset(void)
>> +{
>> +*(u8*) (0xff05) = 0;
>>
>
> is this a magic number/needs a #define somewhere?
>
ok.
>
>> +#define MV_FPGA_DATA"0xff86"
>> +#define MV_FPGA_SIZE"0x3c886"
>> +#define MV_KERNEL_ADDR "0xffc0"
>> +#define MV_INITRD_ADDR "0xff90"
>> +#define MV_INITRD_LENGTH"0x0030"
>> +#define MV_SCRATCH_ADDR "0x"
>> +#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
>> +#define MV_AUTOSCR_ADDR "0xff84"
>> +#define MV_AUTOSCR_ADDR2"0xff85"
>> +#define MV_DTB_ADDR "0xfffc"
>>
>
> please use MK_STR (see other config files, e.g. MPC8313).
>
>
hmm...
Is there a functional difference/advantage or simply coding style ?
>> +
>> +#define CONFIG_SHOW_BOOT_PROGRESS 1
>> +
>> +#define MV_KERNEL_ADDR_RAM "0x0010"
>> +#define MV_DTB_ADDR_RAM "0x0060"
>> +#define MV_INITRD_ADDR_RAM "0x0100"
>> +
>> +/* pass open firmware flat tree */
>> +#define CONFIG_OF_LIBFDT1
>> +#define CONFIG_OF_BOARD_SETUP 1
>> +
>> +#define OF_CPU "PowerPC,[EMAIL PROTECTED]"
>> +#define OF_SOC "[EMAIL PROTECTED]"
>> +#define OF_TBCLK(bd->bi_busfreq / 4)
>>
>
> I thought we had done away with the above three (FLAT_TREE now
> obsolete). Oh, I see now: 5xxx still uses it in LIBFDT code. Bad 5xxx!
>
> Kim
>
As always I have to rely on some recent board implementation since I
don't have time to dig into each line of code involved. Wouldn't it be a
good thing if the custodian removes all #defines as soon as it gets
obsolete ?
regards,
Andre
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
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Re: [U-Boot-Users] [PATCH] Add MVBC_P board
Wolfgang,
thanks - I'll wait for further comments and send an update.
regards,
Andre
Wolfgang Grandegger schrieb:
> Andre Schwarz wrote:
>> The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
>> controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
>> Please see doc/README.mvbc_p for details.
>
> One general remark. Please use the in_*() and out_*() accessor functions
> to access I/O space. This will make most of your asm("sync");
> instructions obsolete.
>
> Wolfgang.
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[U-Boot-Users] [PATCH] Add MVBC_P board
The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
Please see doc/README.mvbc_p for details.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
CREDITS|2 +-
MAINTAINERS|1 +
MAKEALL|1 +
Makefile |8 +
board/mvbc_p/Makefile | 50 ++
board/mvbc_p/config.mk | 30
board/mvbc_p/fpga.c| 177
board/mvbc_p/fpga.h| 34
board/mvbc_p/mvbc_p.c | 345
board/mvbc_p/mvbc_p.h | 72 +
board/mvbc_p/mvbc_p_autoscript | 44 +
doc/README.mvbc_p | 74 +
include/configs/MVBC_P.h | 310
13 files changed, 1147 insertions(+), 1 deletions(-)
diff --git a/CREDITS b/CREDITS
index aa57682..b1c10fd 100644
--- a/CREDITS
+++ b/CREDITS
@@ -426,7 +426,7 @@ D: FADS823 configuration, MPC823 video support, I2C,
wireless keyboard, lots mor
N: Andre Schwarz
E: [EMAIL PROTECTED]
-D: Support for Matrix Vision boards (MVBLM7)
+D: Support for Matrix Vision boards (MVBLM7/MVBC_P)
N: Robert Schwebel
E: [EMAIL PROTECTED]
diff --git a/MAINTAINERS b/MAINTAINERS
index a3d70b1..9af5730 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -373,6 +373,7 @@ Peter De Schrijver <[EMAIL PROTECTED]>
Andre Schwarz <[EMAIL PROTECTED]>
+ mvbc_p MPC5200
mvblm7 MPC8343
Timur Tabi <[EMAIL PROTECTED]>
diff --git a/MAKEALL b/MAKEALL
index 32caab7..ca9202b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -48,6 +48,7 @@ LIST_5xxx=" \
mecp5200\
motionpro \
munices \
+ MVBC_P \
o2dnt \
pf5200 \
PM520 \
diff --git a/Makefile b/Makefile
index 8bfc891..c6d0eda 100644
--- a/Makefile
+++ b/Makefile
@@ -743,6 +743,14 @@ uc101_config: unconfig
motionpro_config: unconfig
@$(MKCONFIG) motionpro ppc mpc5xxx motionpro
+MVBC_P_config: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/mvbc_p
+ @ >$(obj)include/config.h
+ @[ -z "$(findstring MVBC_P,$@)" ] || \
+ { echo "#define CONFIG_MVBC_P">>$(obj)include/config.h; \
+ }
+ @$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p
#
## MPC512x Systems
diff --git a/board/mvbc_p/Makefile b/board/mvbc_p/Makefile
new file mode 100644
index 000..d4344dd
--- /dev/null
+++ b/board/mvbc_p/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# (C) Copyright 2004-2006
+# Matrix-Vision GmbH, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o fpga.o
+
+SRCS:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS:= $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/mvbc_p/config.mk b/board/mvbc_p/config.mk
new file mode 100644
index 000..1c2a13e
--- /dev/null
+++ b/board/mvbc_p/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Softw
[U-Boot-Users] [PATCH] update e1000 ifdef
Change ifdef to match "MVBC_P" board name.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
Ben,
this is a mini-patch and should do no harm.
Since MVBC_1G has gone to oblivion and the new board is named MVBC_P.
I'll submit the board patch in a few minutes.
Thanks,
Andre
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
drivers/net/e1000.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index c31029a..754a0bb 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -3031,7 +3031,7 @@ e1000_initialize(bd_t * bis)
free(nic);
return 0;
}
-#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
+#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_P))
if (e1000_validate_eeprom_checksum(nic) < 0) {
printf("The EEPROM Checksum Is Not Valid\n");
free(hw);
-
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Re: [U-Boot-Users] e1000 problem @ current u-boot
Wolfgang, of course I meant no offense - of course your patch is harmless. The System (network camera) is running for nearly 2 years now. Last working version has been u-boot 1.2.x with a 2.6.19 kernel. Since we've moved to the latest kernel we need a more recent u-boot. This is what I did - and e1000 no longer works. Of course I diff'ed the network stuff - no obvious changes at all. So I wonder if the problem is elsewhere and if e1000 is still working in general. As you say this is obviously true - thanks. regards, Andre Wolfgang Grandegger schrieb: > Andre Schwarz wrote: >> Wolfgang, >> >> as far as I can see on the list you sent the latest patches for the >> e1000 driver. > > My patches just added some device ids, > > >> My e1000 (82541ER) stopped working on a MPC5200 based board with latest >> u-boot. >> I have a similar problem on another board ... >> >> Is your e1000 working properly on the latest u-boot ? > > Yes, on a MPC8548 board. I have not tested it on the MPC5200. > >> Do I need any additional defines or environment settings to get it >> working again ? >> >> Obviously it is - again :-[ - my fault or is related to my build system. > > I think there are some known problems with PCI on boards with a > MPC5200 Rev. A processor, e.g. my EEPRO100 card does not work on it. > What exactly does not work? > > Wolfgang. MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] e1000 problem @ current u-boot
Wolfgang, as far as I can see on the list you sent the latest patches for the e1000 driver. My e1000 (82541ER) stopped working on a MPC5200 based board with latest u-boot. I have a similar problem on another board ... Is your e1000 working properly on the latest u-boot ? Do I need any additional defines or environment settings to get it working again ? Obviously it is - again :-[ - my fault or is related to my build system. Any help is welcome. regards, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] update mvBL-M7 board config
update mvBL-M7 config file to use UBOOT_VERSION and define
CONFIG_HIGH_BATS.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
board/mvblm7/mvblm7.c|2 +-
include/configs/MVBLM7.h |5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/board/mvblm7/mvblm7.c b/board/mvblm7/mvblm7.c
index 41cb39d..3129703 100644
--- a/board/mvblm7/mvblm7.c
+++ b/board/mvblm7/mvblm7.c
@@ -90,7 +90,7 @@ phys_size_t initdram(int board_type)
int checkboard(void)
{
- puts("Board: Matrix Vision mvBlueLYNX-M7 " MV_VERSION "\n");
+ puts("Board: Matrix Vision mvBlueLYNX-M7\n");
return 0;
}
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 349ca14..50e188f 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -27,7 +27,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define MV_VERSION "v1.0.1"
+#include
/*
* High Level Configuration Options
@@ -336,6 +336,7 @@
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 HID2_HBE
+#define CONFIG_HIGH_BATS 1
/* DDR */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
@@ -446,7 +447,7 @@
"mv_dtb_addr=" MV_DTB_ADDR "\0" \
"mv_dtb_addr_ram=" MV_DTB_ADDR_RAM "\0" \
"dtb_name=" MV_DTB_NAME "\0"\
- "mv_version=" MV_VERSION "\0" \
+ "mv_version=" U_BOOT_VERSION "\0" \
"dhcp_client_id=" MV_CI "\0"\
"dhcp_vendor-class-identifier=" MV_VCI "\0" \
"netretry=no\0" \
-
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Re: [U-Boot-Users] TSEC/PHY @ MPC834x stopped working
Kim Phillips schrieb: > On Wed, 02 Jul 2008 18:01:01 +0200 > Andre Schwarz <[EMAIL PROTECTED]> wrote: > > >> this is a fully configured board, i.e. serial# and ethaddr/eth1addr set >> up correctly. >> >> I'll give the bisect a try a soon as there'll be some time. >> >> > just to clarify, are you using the mainline u-boot.git tree, or > u-boot-mpc83xx.git? you should be using the latter until I ask WD to > pull. Actually, if you can confirm it corrects your problem, I have no > reason to delay it further (I was waiting for WD to get back from > vacation). > > Kim > Kim, I'm running from mainline. Do you want me to give u-boot-mpc83xx.git a try ? After all I think the problem is lurking on my hardware/network somewhere. I need some more time ... regards, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] TSEC/PHY @ MPC834x stopped working
Jerry, I don't understand this. The code is far from using the device tree - the dtb is fetched by tftp right after bootp. It's the initial bootp/dhcp that doesn't work regards, Andre Jerry Van Baren schrieb: > Kim Phillips wrote: >> On Wed, 02 Jul 2008 16:36:11 +0200 >> Andre Schwarz <[EMAIL PROTECTED]> wrote: >> >>> Ben, >>> >>> thanks for your quick reply. >>> Looks like you're right - nothing changed regarding network yet. >>> >>> Maybe it's a cpu specific problem. >>> Kim ? Can you help here ? >>> >> >> I know of nothing (barring this being the ETHADDR not specified >> problem) that could have caused this. Can you try using git-bisect? >> >> Kim > > Some people were caught by the somewhat recent requirement for an > /aliases node and properties pointing to the "real" ethernet node > (which is a Good Thing[tm] because it makes the code board agnostic, > pushes the board configuration into the .dts where it belongs). > > I don't associate Andre's assertion: >> Obviously the MII interface stopped working, i.e. all reads give 0xFF. > with the symptoms caused by a missing /aliases node. Maybe, maybe > not, could be my lack of experience. > > Best regards, > gvb > MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] TSEC/PHY @ MPC834x stopped working
Kim Phillips schrieb: > On Wed, 02 Jul 2008 16:36:11 +0200 > Andre Schwarz <[EMAIL PROTECTED]> wrote: > > >> Ben, >> >> thanks for your quick reply. >> Looks like you're right - nothing changed regarding network yet. >> >> Maybe it's a cpu specific problem. >> Kim ? Can you help here ? >> >> > > I know of nothing (barring this being the ETHADDR not specified > problem) that could have caused this. Can you try using git-bisect? > > Kim > Kim, this is a fully configured board, i.e. serial# and ethaddr/eth1addr set up correctly. I'll give the bisect a try a soon as there'll be some time. regards, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] TSEC/PHY @ MPC834x stopped working
Ben, thanks for your quick reply. Looks like you're right - nothing changed regarding network yet. Maybe it's a cpu specific problem. Kim ? Can you help here ? regards, Andre Ben Warren schrieb: > Hi Andre, > > On Wed, Jul 2, 2008 at 7:03 AM, Andre Schwarz > <[EMAIL PROTECTED]> wrote: > >> Ben, >> >> after pulling u-boot today ethernet stopped working on my MPC8343 based >> board (mvBL-M7). >> I'm using a Vitesse VSC8601 RGMII phy on TSEC0-1. >> >> I know there's some rewriting/clean-up going on ... >> >> > Yeah, but none of that's in the main source tree. > > >> What do I have to do to get it working again ? >> Any new defines introduced lately ? >> >> Obviously the MII interface stopped working, i.e. all reads give 0xFF. >> Switching back to older U-boot (3-4 weeks ago) works fine. >> > > Looking here: > http://git.denx.de/?p=u-boot.git;a=history;f=drivers/net/tsec.c;h=6e0f2c6fd081baa19d80a985717d470a1f78bc2d;hb=HEAD > > nothing new has been added except support for a new PHY, and that was > about 5 weeks ago. > >> Any help is welcome. >> >> > Sorry, I don't have access to my MPC8349 board right now or I'd try to > help more usefully. Maybe you can post some more information. > > >> regards, >> Andre >> >> MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: >> Amtsgericht Stuttgart, HRB 271090 >> Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner >> >> > regards, > Ben > MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] TSEC/PHY @ MPC834x stopped working
Ben, after pulling u-boot today ethernet stopped working on my MPC8343 based board (mvBL-M7). I'm using a Vitesse VSC8601 RGMII phy on TSEC0-1. I know there's some rewriting/clean-up going on ... What do I have to do to get it working again ? Any new defines introduced lately ? Obviously the MII interface stopped working, i.e. all reads give 0xFF. Switching back to older U-boot (3-4 weeks ago) works fine. Any help is welcome. regards, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] fix non-working mvBL-M7
Add missing #define CONFIG_HIGH_BATS in mvBL-M7 board config file. Add default MAC to enable netboot during production. Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]> --- MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner include/configs/MVBLM7.h |5 - 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 349ca14..8c0e8b6 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -27,7 +27,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define MV_VERSION "v1.0.1" +#define MV_VERSION "v1.0.2" /* * High Level Configuration Options @@ -215,6 +215,7 @@ #define CONFIG_TSEC2 #define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0 #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_FEC1_PHY_NORXERR #define CFG_TSEC1_OFFSET 0x24000 @@ -224,6 +225,7 @@ #define TSEC1_FLAGS(TSEC_GIGABIT|TSEC_REDUCED) #define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR b6:b4:45:eb:fb:c2 #define CONFIG_TSEC2_NAME "TSEC1" #define CONFIG_FEC2_PHY_NORXERR #define CFG_TSEC2_OFFSET 0x25000 @@ -336,6 +338,7 @@ #define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* DDR */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] broken changes @ MPC83xx
gotcha - that's it ! It's _really_ hard to keep things working these days ... many thanks, Andre Tor Krill schrieb: > Hi Andre, > > I had a similar problem a while back. > > Adding the new define: > > #define CONFIG_HIGH_BATS 1 /* High BATs supported */ > > To my config solved the problem. > > /Tor > > On 6/23/2008, "Andre Schwarz" <[EMAIL PROTECTED]> wrote: > > >> Kim, >> >> after being back from holiday and pulling the lates u-boot today >> (v1.3.3) my MPC8343 based board (mvBL-M7) doesn't work any longer. >> Not a single character is put out on serial - yet build is not >> complaining about anything and System.map looks quite normal. >> >> Any ideas what commit can cause this ? >> >> Am I missing any #defines introduced lately ? >> >> >> regards, >> Andre >> >> MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: >> Amtsgericht Stuttgart, HRB 271090 >> Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner >> >> - >> Check out the new SourceForge.net Marketplace. >> It's the best place to buy or sell services for >> just about anything Open Source. >> http://sourceforge.net/services/buy/index.php >> ___ >> U-Boot-Users mailing list >> U-Boot-Users@lists.sourceforge.net >> https://lists.sourceforge.net/lists/listinfo/u-boot-users >> >> MATRIX VISION GmbH, Talstra�e 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Gesch�ftsf�hrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] broken changes @ MPC83xx
Kim, after being back from holiday and pulling the lates u-boot today (v1.3.3) my MPC8343 based board (mvBL-M7) doesn't work any longer. Not a single character is put out on serial - yet build is not complaining about anything and System.map looks quite normal. Any ideas what commit can cause this ? Am I missing any #defines introduced lately ? regards, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] fix system config overwrite @ MPC834x and MPC8313
During 83xx setup the "System I/O configuration register high" gets
overwritten with user defined value if CFG_SICRH is defined.
Regarding to the MPC834x manual (Table 5-28 reve.1) bits 28+29 of SICRH
must keep their reset value regardless of configuration.
On my board (using RGMII) those bits are set after reset - yet it's
unclear where they come from.
The patch keeps both bits on MPC834x and MPC8313.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
cpu/mpc83xx/cpu_init.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index fb184d8..3a9a302 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -59,6 +59,8 @@ static void config_qe_ioports(void)
*/
void cpu_init_f (volatile immap_t * im)
{
+ u32 tmp_sicrh = 0;
+
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
@@ -181,7 +183,11 @@ void cpu_init_f (volatile immap_t * im)
/* System General Purpose Register */
#ifdef CFG_SICRH
- im->sysconf.sicrh = CFG_SICRH;
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8313)
+ /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
+ tmp_sicrh = im->sysconf.sicrh & 0x000C;
+#endif
+ im->sysconf.sicrh = CFG_SICRH | tmp_sicrh;
#endif
#ifdef CFG_SICRL
im->sysconf.sicrl = CFG_SICRL;
-
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[U-Boot-Users] [PATCH 2/2] add MPC8343 based board mvBlueLYNX-M7
Add MPC8343 based board mvBlueLYNX-M7. It's a single board stereo camera system. Please read doc/README.mvblm7 for details. Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]> --- MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner MAKEALL|1 + Makefile |3 + board/mvblm7/Makefile | 48 ++ board/mvblm7/config.mk | 25 ++ board/mvblm7/fpga.c| 188 board/mvblm7/fpga.h| 34 +++ board/mvblm7/mvblm7.c | 157 + board/mvblm7/mvblm7.h | 21 + board/mvblm7/mvblm7_autoscript | 37 board/mvblm7/pci.c | 165 +++ 10 files changed, 679 insertions(+), 0 deletions(-) diff --git a/MAKEALL b/MAKEALL index 3cb1d24..c751586 100755 --- a/MAKEALL +++ b/MAKEALL @@ -331,6 +331,7 @@ LIST_83xx=" \ MPC8360ERDK_66 \ MPC837XEMDS \ MPC837XERDB \ + MVBLM7 \ sbc8349 \ TQM834x \ " diff --git a/Makefile b/Makefile index cc988e1..fd9c949 100644 --- a/Makefile +++ b/Makefile @@ -2107,6 +2107,9 @@ MPC837XEMDS_HOST_config: unconfig MPC837XERDB_config:unconfig @$(MKCONFIG) -a MPC837XERDB ppc mpc83xx mpc837xerdb freescale +MVBLM7_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7 + sbc8349_config:unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 diff --git a/board/mvblm7/Makefile b/board/mvblm7/Makefile new file mode 100644 index 000..84cd14a --- /dev/null +++ b/board/mvblm7/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o fpga.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +# + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/mvblm7/config.mk b/board/mvblm7/config.mk new file mode 100644 index 000..1d85f4f --- /dev/null +++ b/board/mvblm7/config.mk @@ -0,0 +1,25 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +TEXT_BASE = 0xFFF0 diff --git a/board/mvblm7/fpga.c b/board/mvblm7/fpga.c new file mode 100644 index 000..a60af01 --- /dev/null +++ b/board/mvblm7/fpga.c @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, [EMAIL PROTECTED] + * Keith Outwater, [EMAIL PROTECTED] + * + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, [EMAIL PROTECTED] + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify
[U-Boot-Users] [PATCH 1/2] add MPC8343 based board mvBlueLYNX-M7
Add MPC8343 based board mvBlueLYNX-M7. It's a single board stereo camera system. Please read doc/README.mvblm7 for details. Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]> --- MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner CREDITS |4 + MAINTAINERS |4 + doc/README.mvblm7| 85 include/configs/MVBLM7.h | 481 ++ 4 files changed, 574 insertions(+), 0 deletions(-) diff --git a/CREDITS b/CREDITS index e84ef38..aa57682 100644 --- a/CREDITS +++ b/CREDITS @@ -424,6 +424,10 @@ N: Paolo Scaffardi E: [EMAIL PROTECTED] D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more +N: Andre Schwarz +E: [EMAIL PROTECTED] +D: Support for Matrix Vision boards (MVBLM7) + N: Robert Schwebel E: [EMAIL PROTECTED] D: Support for csb226, logodl and innokom boards (PXA2xx) diff --git a/MAINTAINERS b/MAINTAINERS index d3dfd48..357cab3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -371,6 +371,10 @@ Peter De Schrijver <[EMAIL PROTECTED]> ML2 PPC4xx +Andre Schwarz <[EMAIL PROTECTED]> + + mvblm7 MPC8343 + Timur Tabi <[EMAIL PROTECTED]> MPC8349E-mITX MPC8349 diff --git a/doc/README.mvblm7 b/doc/README.mvblm7 new file mode 100644 index 000..52b9df7 --- /dev/null +++ b/doc/README.mvblm7 @@ -0,0 +1,85 @@ +Matrix Vision mvBlueLYNX-M7 (mvBL-M7) +- + +1. Board Description + + The mvBL-M7 is a 120x120mm single board computing platform + with strong focus on stereo image processing applications. + + Power Supply is either VDC 12-48V or Pover over Ethernet (PoE) + on any port (requires add-on board). + +2 System Components + +2.1CPU + Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb. + 512MByte DDR-II memory @ 133MHz. + 8 MByte Nor Flash on local bus. + 2 Vitesse VSC8601 RGMII ethernet Phys. + 1 USB host controller over ULPI I/F. + 2 serial ports. Console running on ttyS0 @ 115200 8N1. + 1 SD-Card slot connected to SPI. + System configuration (HRCW) is taken from I2C EEPROM. + +2.2PCI + A miniPCI Type-III socket is present. PCI clock fixed at 66MHz. + +2.3FPGA + Altera Cyclone-II EP2C20/35 with PCI DMA engines. + Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces. + Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash. + +2.3.1 I/O @ FPGA + 2x8 Outputs : Infineon High-Side Switches to Main Supply. + 2x8 Inputs : Programmable input threshold + trigger capabilities + 2 dedicated flash interfaces for illuminator boards. + Cross trigger for chaining several boards. + +2.4I2C + Bus1: + MAX5381 DAC @ 0x60 for 1st digital input threshold. + LM75 @ 0x90 for temperature monitoring. + EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. + 1st image sensor interface (slave adresses depend on sensor) + Bus2: + MAX5381 DAC @ 0x60 for 2nd digital input threshold. + 2nd image sensor interface (slave adresses depend on sensor) + +3 Flash layout. + + reset vector is 0xFFF00100, i.e. "HIGHBOOT". + + FF80environment + FF802000redundant environment + FF804000u-boot script image + FF806000redundant u-boot script image + FF808000device tree blob + FF80A000redundant device tree blob + FF80C000tbd. + FF80E000tbd. + FF81kernel + FFC0root FS + FFF0u-boot + FFF8FPGA raw bit file + + mtd partitions are propagated to linux kernel via device tree blob. + +4 Booting + + On startup the bootscript @ FF804000 is executed. This script can be + exchanged easily. Default boot mode is "boot from flash", i.e. system + works stand-alone. + + This behaviour depends on some environment variables : + + "netboot" : yes ->try dhcp/bootp and boot from network. + A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for + DHCP server configuration, e.g. to provide different images to + different devices. + + During netboot the system tries to get 3 image files: + 1. Kernel - name + data is given during BOOTP. + 2. Initrd - name is stored in "initrd_name" + 3. device tree blob - name is stored in "dtb_name" + Fallback files are the flash versions. + diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h n
Re: [U-Boot-Users] build failure in tools - missing CFG_ENV_SIZE ?
Martin, thanks for the info. The misbehaviour surely has its cause on my system setup. I simply don't know why ... it's driving me mad. Just wanted to port another board from my local v1.3.1 and submit a patch during this merge window. But the e1000 driver isn't working anymore. Making a diff gives "files are identical". There's something utterly wrong ... time to go home and prepare for soccer :-( cheers, Andre Martin Krause schrieb: > Hi Andre, > > [EMAIL PROTECTED] wrote on : > >> Wolfgang Denk schrieb: >> >>> In message <[EMAIL PROTECTED]> you wrote: >>> >>> thanks for your verification. Trying to do it your way gives : nova u-boot-clean # CROSS_COMPILE=ppc_6xx- sh MAKEALL TQM5200 MPC8349ITX Configuring for TQM5200 board... In file included from environment.c:30: /home/u-boot-clean/include/environment.h:107: error: 'CFG_ENV_SIZE' undeclared here (not in a function) > > I'm also able to build (top of) U-Boot for the TQM5200 with > ELDK4.1: > > [EMAIL PROTECTED]:~/git/u-boot_denx> echo $CROSS_COMPILE > ppc_82xx- > [EMAIL PROTECTED]:~/git/u-boot_denx> ./MAKEALL TQM5200 > Configuring for TQM5200 board... > md5.c: In function `MD5Update': > md5.c:95: warning: implicit declaration of function `memmove' > md5.c: In function `MD5Final': > md5.c:143: warning: implicit declaration of function `memset' > sha1.c: In function `sha1_update': > sha1.c:249: warning: implicit declaration of function `memcpy' > sha1.c: In function `sha1_hmac': > sha1.c:360: warning: implicit declaration of function `memset' >textdata bss dec hex filename > 326532 32456 315024 674012 a48dc ./u-boot > [EMAIL PROTECTED]:~/git/u-boot_denx> > > I don't know, why I get the warnings (they appeared first several > weeks ago, and I get it for every build, since then). But since the > resulting U-Boot runs fine, there was no pressure (and no time) > to dig for the reason of the warnings ... > > Best Regards, > Martin Krause > > -- > TQ-Systems GmbH > Muehlstrasse 2, Gut Delling, D-82229 Seefeld > Amtsgericht Muenchen, HRB 105 018, UST-IdNr. DE 811 607 913 > Geschaeftsfuehrer: Dipl.-Ing. (FH) Detlef Schneider, Dipl.-Ing. (FH) Ruediger > Stahl > http://www.tq-group.com > MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] build failure in tools - missing CFG_ENV_SIZE ?
Wolfgang Denk schrieb: > In message <[EMAIL PROTECTED]> you wrote: > >> thanks for your verification. Trying to do it your way gives : >> >> nova u-boot-clean # CROSS_COMPILE=ppc_6xx- sh MAKEALL TQM5200 MPC8349ITX >> Configuring for TQM5200 board... >> In file included from environment.c:30: >> /home/u-boot-clean/include/environment.h:107: error: 'CFG_ENV_SIZE' >> undeclared here (not in a function) >> > > So what exactly is the difference between your source tree and > toolchain and mine? > > I'm running ELDK 4.1 and latest u-boot from git. >> Unfortunately I'm not a Makefile expert ... do you have any ideas ? >> > > I don't see why or which changes would be necessary as it's working > fine here... > > How am I supposed to know if you do not ? :-( I'll stick to the local change of the #include statement. > Best regards, > > Wolfgang Denk > > cheers, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] build failure in tools - missing CFG_ENV_SIZE ?
Wolfgang, thanks for your verification. Trying to do it your way gives : nova u-boot-clean # CROSS_COMPILE=ppc_6xx- sh MAKEALL TQM5200 MPC8349ITX Configuring for TQM5200 board... In file included from environment.c:30: /home/u-boot-clean/include/environment.h:107: error: 'CFG_ENV_SIZE' undeclared here (not in a function) make[1]: *** [environment.o] Error 1 make: *** [tools] Error 2 ppc_6xx-size: './u-boot': No such file Configuring for MPC8349ITX board... In file included from environment.c:30: /home/u-boot-clean/include/environment.h:107: error: 'CFG_ENV_SIZE' undeclared here (not in a function) make[1]: *** [environment.o] Error 1 make: *** [tools] Error 2 ppc_6xx-size: './u-boot': No such file Obviously it's a problem regarding include mechanism. Changing line 28 in common/environment.c ( -> "../include/config.h") gives positive result : nova u-boot-clean # CROSS_COMPILE=ppc_6xx- sh MAKEALL TQM5200 MPC8349ITX Configuring for TQM5200 board... textdata bss dec hex filename 326532 32464 315024 674020 a48e4 ./u-boot Configuring for MPC8349ITX board... textdata bss dec hex filename 217741 15388 223684 456813 6f86d ./u-boot Unfortunately I'm not a Makefile expert ... do you have any ideas ? regards, Andre Wolfgang Denk schrieb: > In message <[EMAIL PROTECTED]> you wrote: > >> after getting a clean u-boot clone (1.3.3 today) I get a compile error >> in "tools" subdir. >> >> I've tried 2 different boards making a "TQM5200_config" and >> "MPC8349ITX_config" - just to make sure ... >> >> "make CROSS_COMPILE=3Dppc_6xx- " >> >> cross-compiler is gcc 4.0 as shipped with ELDK 4.1. >> > > Hm. Let's see: > > -> MAKEALL TQM5200 MPC8349ITX > Configuring for TQM5200 board... >textdata bss dec hex filename > 326532 32456 315024 674012 a48dc ./u-boot > Configuring for MPC8349ITX board... >textdata bss dec hex filename > 217741 15388 223684 456813 6f86d ./u-boot > > That's U-Boot 1.3.3-00117-g8155efb > > >> Can someome help me out please ? >> > > Sorry, I cannot reproduce the problem. > > Best regards, > > Wolfgang Denk > > MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] build failure in tools - missing CFG_ENV_SIZE ?
All, after getting a clean u-boot clone (1.3.3 today) I get a compile error in "tools" subdir. I've tried 2 different boards making a "TQM5200_config" and "MPC8349ITX_config" - just to make sure ... "make CROSS_COMPILE=ppc_6xx- " cross-compiler is gcc 4.0 as shipped with ELDK 4.1. Am I missing something ? Since environment.c includes config.h which pulls in board config everything should be fine. Can someome help me out please ? make[1]: Entering directory `/home/u-boot.git/tools' gcc -g -idirafter /home/u-boot.git/include -idirafter /home/u-boot.git/include2 -idirafter /home/u-boot.git/include -DTEXT_BASE=0xFC00 -DUSE_HOSTCC -c -o environment.o environment.c In file included from environment.c:30: /home/u-boot.git/include/environment.h:107: error: 'CFG_ENV_SIZE' undeclared here (not in a function) make[1]: *** [environment.o] Error 1 make[1]: Leaving directory `/home/u-boot.git/tools' make: *** [tools] Error 2 regards, Andre Schwarz MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 2/2] add MPC8343 based board mvBlueLYNX-M7
Add MPC8343 based board mvBlueLYNX-M7. It's a single board stereo camera system. Please read doc/README.mvblm7 for details. Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]> -- MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner board/mvblm7/Makefile | 48 ++ board/mvblm7/config.mk | 25 + board/mvblm7/fpga.c| 191 board/mvblm7/fpga.h| 34 +++ board/mvblm7/mvblm7.c | 135 board/mvblm7/mvblm7.h | 21 + board/mvblm7/mvblm7_autoscript | 37 board/mvblm7/pci.c | 160 + 8 files changed, 651 insertions(+), 0 deletions(-) diff --git a/board/mvblm7/Makefile b/board/mvblm7/Makefile new file mode 100644 index 000..84cd14a --- /dev/null +++ b/board/mvblm7/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o fpga.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +# + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/mvblm7/config.mk b/board/mvblm7/config.mk new file mode 100644 index 000..1d85f4f --- /dev/null +++ b/board/mvblm7/config.mk @@ -0,0 +1,25 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +TEXT_BASE = 0xFFF0 diff --git a/board/mvblm7/fpga.c b/board/mvblm7/fpga.c new file mode 100644 index 000..5eaa037 --- /dev/null +++ b/board/mvblm7/fpga.c @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, [EMAIL PROTECTED] + * Keith Outwater, [EMAIL PROTECTED] + * + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, [EMAIL PROTECTED] + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include "fpga.h" +#include "mvblm7.h" + +#ifdef CONFIG_FPGA + +#ifdef FPGA_DEBUG +#define fpga_debug(fmt,
Re: [U-Boot-Users] [PATCH 1/2] add MPC8343 based board mvBlueLYNX-M7
Add MPC8343 based board mvBlueLYNX-M7. It's a single board stereo camera system. Please read doc/README.mvblm7 for details. Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]> -- MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner CREDITS |5 +++ MAINTAINERS |4 ++ MAKEALL |1 + Makefile |3 ++ doc/README.mvblm7 | 85 + 5 files changed, 98 insertions(+), 0 deletions(-) diff --git a/CREDITS b/CREDITS index e84ef38..713f58a 100644 --- a/CREDITS +++ b/CREDITS @@ -424,6 +424,11 @@ N: Paolo Scaffardi E: [EMAIL PROTECTED] D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more +N: Andre Schwarz +E: [EMAIL PROTECTED] +D: Support for BlueLYNX and BlueCOUGAR series +W: www.matrix-vision.com + N: Robert Schwebel E: [EMAIL PROTECTED] D: Support for csb226, logodl and innokom boards (PXA2xx) diff --git a/MAINTAINERS b/MAINTAINERS index 58f833c..7d0d1b1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -367,6 +367,10 @@ Peter De Schrijver <[EMAIL PROTECTED]> ML2 PPC4xx +Andre Schwarz <[EMAIL PROTECTED]> + + mvblm7 MPC8343 + Timur Tabi <[EMAIL PROTECTED]> MPC8349E-mITX MPC8349 diff --git a/MAKEALL b/MAKEALL index 791eabc..7bf8e52 100755 --- a/MAKEALL +++ b/MAKEALL @@ -329,6 +329,7 @@ LIST_83xx=" \ MPC8360ERDK_66 \ MPC837XEMDS \ MPC837XERDB \ + MVBLM7 \ sbc8349 \ TQM834x \ " diff --git a/Makefile b/Makefile index 167a717..0535c0b 100644 --- a/Makefile +++ b/Makefile @@ -2096,6 +2096,9 @@ MPC837XEMDS_HOST_config: unconfig MPC837XERDB_config:unconfig @$(MKCONFIG) -a MPC837XERDB ppc mpc83xx mpc837xerdb freescale +MVBLM7_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7 + sbc8349_config:unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 diff --git a/doc/README.mvblm7 b/doc/README.mvblm7 new file mode 100644 index 000..fb86b5a --- /dev/null +++ b/doc/README.mvblm7 @@ -0,0 +1,85 @@ +Matrix Vision mvBlueLYNX-M7 (mvBL-M7) +- + +1. Board Description + + The mvBL-M7 is a 120x120mm single board computing platform + with strong focus on stereo image processing applications. + + Power Supply is either VDC 12-48V or Pover over Ethernet (PoE) + on any port (requires add-on board). + +2 System Components + +2.1CPU + Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb. + 512MByte DDR-II memory @ 133MHz. + 8 MByte Nor Flash on local bus. + 2 Vitesse VSC8601 RGMII ethernet Phys. + 1 USB host controller over ULPI I/F. + 2 serial ports. Console running on ttyS0 @ 115200 8N1. + 1 SD-Card slot connected to SPI. + System configuration (HRCW) is taken from I2C EEPROM. + +2.2PCI + A miniPCI Type-III socket is present. PCI clock fixed at 66MHz. + +2.3FPGA + Altera Cyclone-II EP2C20/35 with PCI DMA engines. + Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces. + Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash. + +2.3.1 I/O @ FPGA + 2x8 Outputs : Infineon High-Side Switches to Main Supply. + 2x8 Inputs : Programmable input threshold + trigger capabilities + 2 dedicated flash interfaces for illuminator boards. + Cross trigger for chaining several boards. + +2.4I2C + Bus1: + MAX5381 DAC @ 0x60 for 1st digital input threshold. + LM75 @ 0x90 for temperature monitoring. + EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. + 1st image sensor interface (slave adresses depend on sensor) + Bus2: + MAX5381 DAC @ 0x60 for 2nd digital input threshold. + 2nd image sensor interface (slave adresses depend on sensor) + +3 Flash layout. + + reset vector is 0xFFF00100, i.e. "HIGHBOOT". + + FF80environment + FF802000redundant environment + FF804000u-boot script image + FF806000redundant u-boot script image + FF808000device tree blob + FF80A000redundant device tree blob + FF80C000tbd. + FF80E000tbd. + FF81kernel + FFC0root FS + FFF0u-boot + FFF8FPGA raw bit file + + mtd partitions are propagated to linux kernel via device tree blob. + +4 Booting + + On startup the bootscript @ FF804000 is executed. This script can be + exchanged easily. Default boot mode is "b
Re: [U-Boot-Users] Memory Size issue @ MPC83xx
Wolfgang, thanks for the hint - unfortunately the issue is not solved, yet. Obviously I've missed something... U-boot is working fine with both 256MB and 512MB RAM. The kernel crashes with memory > 256MB. Do I need to set up a 2nd BAT for mapping main memory before booting linux in any case ? Do you now of any kernel related issues/missing configs ? I know this is off-topic to this list - but maybe you can help me out. regards, Andre Wolfgang Denk schrieb: > In message <[EMAIL PROTECTED]> you wrote: > >> my MPC8343 based system is running fine, but I'm not able to use more >> than 256MB of memory. >> >> Is this a general or known issue ? >> > > You may want to search for CONFIG_VERY_BIG_RAM and > CONFIG_MAX_MEM_MAPPED, see for example "lib_ppc/board.c". > > > Best regards, > > Wolfgang Denk > > MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] add config options for VSC8601 RGMII PHY - 2nd try
The Vitesse VSC8601 RGMII PHY has internal delay for both Rx
and Tx clock lines. They are configured using 2 bits in extended
register 0x17.
Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have
been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
--
drivers/net/tsec.c |6 ++
drivers/net/tsec.h |3 +++
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 9d22aa3..06250ae 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -1277,6 +1277,12 @@ struct phy_info phy_info_VSC8601 = {
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
#ifdef CFG_VSC8601_SKEWFIX
{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX)
+{MIIM_EXT_PAGE_ACCESS,1,NULL},
+#define VSC8101_SKEW(CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12)
+{MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
+{MIIM_EXT_PAGE_ACCESS,0,NULL},
+#endif
#endif
{miim_end,}
},
diff --git a/drivers/net/tsec.h b/drivers/net/tsec.h
index cfa7d1a..213a809 100644
--- a/drivers/net/tsec.h
+++ b/drivers/net/tsec.h
@@ -112,6 +112,8 @@
#define MIIM_GBIT_CONTROL0x9
#define MIIM_GBIT_CONTROL_INIT0xe00
+#define MIIM_EXT_PAGE_ACCESS0x1f
+
/* Broadcom BCM54xx -- taken from linux sungem_phy */
#define MIIM_BCM54xx_AUXSTATUS0x19
#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK0x0700
@@ -163,6 +165,7 @@
/* Vitesse VSC8601 Extended PHY Control Register 1 */
#define MIIM_VSC8601_EPHY_CON0x17
#define MIIM_VSC8601_EPHY_CON_INIT_SKEW0x1120
+#define MIIM_VSC8601_SKEW_CTRL0x1c
/* 88E1011 PHY Status Register */
#define MIIM_88E1011_PHY_STATUS 0x11
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Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
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Re: [U-Boot-Users] [PATCH] add config options for VSC8601 RGMII PHY
Ben Warren schrieb: > André Schwarz wrote: >> Andy, >> >> it's no problem to re-send a "more suitable" patch as soon as Ben has >> finished the re-work. I'll wait for him and send an updated version >> to the list. >> >> >> > It's better to get this in now if you don't mind. > > regards, > Ben I don't mind and will send it a a new patch. Cheers, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] add config options for VSC8601 RGMII PHY
Andy,
thanks for your comments.
Andy Fleming schrieb:
> On Thu, Apr 24, 2008 at 9:45 AM, Andre Schwarz
> <[EMAIL PROTECTED]> wrote:
>
>
>> {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
>> +#if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX)
>> +{MIIM_EXT_PAGE_ACCESS,1,NULL},
>> +#define VSC8101_SKEW(CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12)
>> +{MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
>> +{MIIM_EXT_PAGE_ACCESS,0,NULL},
>> +#endif
>> #endif
>>
>
>
> I'm not sure this is the best solution to this. It seems like it
> wouldn't scale well. Either we need to set a bit somewhere that the
> phy driver can read (and thereby determine how to configure the skew),
> or we need to set the value to write in the board config file. I'm
> partial to the first solution, as it encapsulates the information
> inside the code that deals with it.
>
> [...]
>
>
I don't understand "scale well". What should be scalable ?
Of course using a function would be better.
I silently assumed that the other bits are set to zero which is true
after reset.
There are only two other bits : Packet size and 10M preamble mode.
Both should be left untouched, i.e. "0".
>> /* Broadcom BCM54xx -- taken from linux sungem_phy */
>> #define MIIM_BCM54xx_AUXSTATUS0x19
>> #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK0x0700
>> @@ -163,6 +165,8 @@
>> /* Vitesse VSC8601 Extended PHY Control Register 1 */
>> #define MIIM_VSC8601_EPHY_CON0x17
>> #define MIIM_VSC8601_EPHY_CON_INIT_SKEW0x1120
>> +#define MIIM_VSC8601_SKEW_CTRL0x1c
>> +#define MIIM_VSC8601_EPHY_CON_INIT_SKEW0x1120
>>
>
> Am I crazy, or did you just doubly define MIIM_VSC8601_EPHY_CON_INIT_SKEW?
>
This obviously is a mistake - sorry.
regards,
Andre
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Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
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[U-Boot-Users] [PATCH] add config options for VSC8601 RGMII PHY
The Vitesse VSC8601 RGMII PHY has internal delay for both Rx
and Tx clock lines. They are configured using 2 bits in extended
register 0x17.
Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have
been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
--
drivers/net/tsec.c |6 ++
drivers/net/tsec.h |4
2 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 9d22aa3..06250ae 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -1277,6 +1277,12 @@ struct phy_info phy_info_VSC8601 = {
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
#ifdef CFG_VSC8601_SKEWFIX
{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX)
+{MIIM_EXT_PAGE_ACCESS,1,NULL},
+#define VSC8101_SKEW(CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12)
+{MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
+{MIIM_EXT_PAGE_ACCESS,0,NULL},
+#endif
#endif
{miim_end,}
},
diff --git a/drivers/net/tsec.h b/drivers/net/tsec.h
index cfa7d1a..e8776b0 100644
--- a/drivers/net/tsec.h
+++ b/drivers/net/tsec.h
@@ -112,6 +112,8 @@
#define MIIM_GBIT_CONTROL0x9
#define MIIM_GBIT_CONTROL_INIT0xe00
+#define MIIM_EXT_PAGE_ACCESS0x1f
+
/* Broadcom BCM54xx -- taken from linux sungem_phy */
#define MIIM_BCM54xx_AUXSTATUS0x19
#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK0x0700
@@ -163,6 +165,8 @@
/* Vitesse VSC8601 Extended PHY Control Register 1 */
#define MIIM_VSC8601_EPHY_CON0x17
#define MIIM_VSC8601_EPHY_CON_INIT_SKEW0x1120
+#define MIIM_VSC8601_SKEW_CTRL0x1c
+#define MIIM_VSC8601_EPHY_CON_INIT_SKEW0x1120
/* 88E1011 PHY Status Register */
#define MIIM_88E1011_PHY_STATUS 0x11
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Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
-
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Don't miss this year's exciting event. There's still time to save $100.
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Re: [U-Boot-Users] [PATCH] Add Vitesse 8601 support to TSEC driver
Tor,
at last I could solve my "strange" behaviour.
Actually the PHY definitely uses both 2 bit definitions of Rx and Tx Skew at
"RGMII Skew Control Reg" 0x1c - which are set up by eeprom or strapping.
Due to noise or strapping resistor mismatch these setting are not always
like
I want them to be.
Setting bit 8 in "Extended PHY Control 1" @ 0x17 activates the delay lines.
Obviously your Skew values did match.
I'll send a patch to configure the delay.
Cheers,
Andre
Tor Krill schrieb:
> Hi,
>
> On 4/17/2008, "Andre Schwarz" <[EMAIL PROTECTED]> wrote:
>
>
>> Tor,
>>
>> after all my VSC8601 is up and running on MPC8343 :-)
>>
>> I'm sorry to say that I don't find this patch ok after going through the
>> manuals :
>>
>> Register 0x17 is a very coarse setting. If the capabilities of the PHY
>> should be taken into account and be configurable we should use the skew
>> control in extended register 0x1c. This should be definable -
>> CFG_VSC8601_SKEWFIX simply applies maximum skew ...
>>
>
> Sure it certainly could have been done in a more configurable way. But
> you have to decide what you need. For us this was an apropriate level
> atm that scratched our itch. If we where to expose every setting from
> the start we still would not have been done ;)
>
>
>> After all changing the bits in register 0x17 _require_ a soft reset by
>> asserting bit 15 in register 0 before they are going to work.
>>
>> Obviously this patch has no effect at all.
>> Do you reset the PHY manually after this configuration ?
>>
>
> According to our datasheet (dated july 2006) only changes of bit 12 in
> this register needs a software reset to take. We don't reset the phy
> after changing this and the change obviously work (we have tested and
> verified that it won't work without the change).
>
>
>> This PHY definitely needs a proper setup function since there are quite
>> interesting registers which need read-modify-write.
>>
>> What do you think ?
>>
>
> Perhaps a patch to improve what you find missing?
>
> /Tor
>
>
>> Kim Phillips schrieb:
>>
>>> On Mon, 31 Mar 2008 10:01:34 -0400
>>> Ben Warren <[EMAIL PROTECTED]> wrote:
>>>
>>>
>>>
>>>> Tor Krill wrote:
>>>>
>>>>
>>>>> Add phy_info for Vitesse VSC8601.
>>>>> Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing
>>>>> compensation.
>>>>>
>>>>> Signed-off-by: Tor Krill <[EMAIL PROTECTED]>
>>>>>
>>>>>
>>>>>
>>>> Acked-by: Ben Warren <[EMAIL PROTECTED]>
>>>>
>>>>
>>> I don't have a Vitesse 8601, so technically I can't ack it, but I can:
>>>
>>> Reviewed-by: Kim Phillips <[EMAIL PROTECTED]>
>>>
>>> minor nit: it would be nice if the following:
>>>
>>>
>>>
>>>>> +#ifdef CFG_VSC8601_SKEWFIX
>>>>> +
>>>>> {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
>>>>> +#endif
>>>>>
>>>>>
>>> were made to have spaces after commas, and flow onto a separate
>>> line so as to not be a 96 char line..
>>>
>>> Kim
>>>
>>> -
>>> Check out the new SourceForge.net Marketplace.
>>> It's the best place to buy or sell services for
>>> just about anything Open Source.
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>>>
>>
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>> Amtsgericht Stuttgart, HRB 271090
>> Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
>>
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[U-Boot-Users] PCI stopped working on MPC8343
Last week my PCI bus has been running fine showing all devices. Right now no devices are shown on the bus. I'm using CONFIG_83XX_GENERIC_PCI with common setup code for PCI. Nothing changed from my side during the last 2 weeks. Did I miss any changes in u-boot ? regards, Andre Schwarz Matrix Vision MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] fix system config overwrite @ MPC834x
Kim, doing a git-pull gives "Already up-to-date." The patch is produced with "git-diff --patch-with-stat cpu/mpc83xx/cpu_init.c" Am I doing anything wrong ? Since all my patches have problems in getting applied there's obviously a problem on my side ... regards, Andre Kim Phillips schrieb: On Thu, 17 Apr 2008 19:28:17 +0200 Andre Schwarz <[EMAIL PROTECTED]> wrote: Kim, Hello Andre, I can't apply this: Applying fix system config overwrite @ MPC834x error: patch failed: cpu/mpc83xx/cpu_init.c:59 error: cpu/mpc83xx/cpu_init.c: patch does not apply Patch failed at 0001. When you have resolved this problem run "git-am --resolved". If you would prefer to skip this patch, instead run "git-am --skip". during 83xx setup the "System I/O configuration register high" gets overwritten with user defined value if CFG_SICRH is defined. Regarding to the MPC834x manual (Table 5-28 reve.1) bits 28+29 of SICRH must keep their reset value regardless of configuration. On my board (using RGMII) those bits are set after reset - yet it's unclear where they come from. The patch keeps both bits on MPC834x. Cheers, Andre Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]> -- fyi, commit message text you don't want applied in the tree history (such as "Kim," and "Cheers, Andre") goes here, below the '---' line. /* System General Purpose Register */ #ifdef CFG_SICRH -im->sysconf.sicrh = CFG_SICRH; +#ifdef CONFIG_MPC834X +/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ +tmp_sicrh = im->sysconf.sicrh & 0x000C; +#endif +im->sysconf.sicrh = CFG_SICRH | tmp_sicrh; #endif also, can you extend the ifdef to include CONFIG_MPC8313 in addition to the MPC834X? That's the only other one that could use this fix. Thanks, Kim MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] Add Vitesse 8601 support to TSEC driver
Tor,
after all my VSC8601 is up and running on MPC8343 :-)
I'm sorry to say that I don't find this patch ok after going through the
manuals :
Register 0x17 is a very coarse setting. If the capabilities of the PHY
should be taken into account and be configurable we should use the skew
control in extended register 0x1c. This should be definable -
CFG_VSC8601_SKEWFIX simply applies maximum skew ...
After all changing the bits in register 0x17 _require_ a soft reset by
asserting bit 15 in register 0 before they are going to work.
Obviously this patch has no effect at all.
Do you reset the PHY manually after this configuration ?
This PHY definitely needs a proper setup function since there are quite
interesting registers which need read-modify-write.
What do you think ?
regards,
Andre
Kim Phillips schrieb:
On Mon, 31 Mar 2008 10:01:34 -0400
Ben Warren <[EMAIL PROTECTED]> wrote:
Tor Krill wrote:
Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing
compensation.
Signed-off-by: Tor Krill <[EMAIL PROTECTED]>
Acked-by: Ben Warren <[EMAIL PROTECTED]>
I don't have a Vitesse 8601, so technically I can't ack it, but I can:
Reviewed-by: Kim Phillips <[EMAIL PROTECTED]>
minor nit: it would be nice if the following:
+#ifdef CFG_VSC8601_SKEWFIX
+
{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#endif
were made to have spaces after commas, and flow onto a separate
line so as to not be a 96 char line..
Kim
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[U-Boot-Users] [PATCH] fix system config overwrite @ MPC834x
Kim,
during 83xx setup the "System I/O configuration register high" gets
overwritten
with user defined value if CFG_SICRH is defined.
Regarding to the MPC834x manual (Table 5-28 reve.1) bits 28+29 of SICRH
must keep
their reset value regardless of configuration.
On my board (using RGMII) those bits are set after reset - yet it's
unclear where they come from.
The patch keeps both bits on MPC834x.
Cheers,
Andre
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
--
cpu/mpc83xx/cpu_init.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index fba5b02..66cc1c2 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -59,6 +59,8 @@ static void config_qe_ioports(void)
*/
void cpu_init_f (volatile immap_t * im)
{
+u32 tmp_sicrh = 0;
+
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
@@ -181,7 +183,11 @@ void cpu_init_f (volatile immap_t * im)
/* System General Purpose Register */
#ifdef CFG_SICRH
-im->sysconf.sicrh = CFG_SICRH;
+#ifdef CONFIG_MPC834X
+/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
+tmp_sicrh = im->sysconf.sicrh & 0x000C;
+#endif
+im->sysconf.sicrh = CFG_SICRH | tmp_sicrh;
#endif
#ifdef CFG_SICRL
im->sysconf.sicrl = CFG_SICRL;
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Re: [U-Boot-Users] I2C @ MPC8343
Ben, I'm a little confused right now and need to have a closer look. The EEPRM is a M24C64 from ST with extended adressing modes. There might be something going wrong during probe or initial adressing. I'll post as soon as there are more useful results ... thanks, Andre Ben Warren schrieb: Hi Andre, On Thu, Apr 10, 2008 at 4:37 AM, Andre Schwarz <[EMAIL PROTECTED]> wrote: All, in my current system the I2C bus is not working properly on a MPC8343 in u-boot v1.3.2. i2c board config includes : #define CONFIG_HARD_I2C #undef CONFIG_SOFT_I2C #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_CMD_TREE #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 #define CFG_I2C_SPEED 10 #define CFG_I2C_SLAVE 0x7F chip probing works fine. mvBL-M7> i2c probe Valid chip addresses: 30 48 50 68 reading the Chips gives all "ff" mvBL-M7> i2c md 50 0 10 : ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Observing the I2C bus wires show that everything _works excellent_ : 100kHz speed as well as all data seems ok - but u-boot shows "ff". The fact that probing works and your scope shows bits toggling leads me to believe that your command syntax is the problem. Please try something like: "i2c md 50.1 0 10". I2C syntax is a bit goofy - you often have to specify the bus width. I've used 1.3.2 successfully on an MPC8349 (same as yours) with and without Timur's speed patches. regards, Ben MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] I2C @ MPC8343
Wolfgang, I have indeed a LM75 on this bus - but it's not adressed. The same I2C bus works fine on linux-2.6.25 including LM75 and EEPROM. The oszi shows complete transactions with valid data. I think it is as software issue. Thanks, Andre [EMAIL PROTECTED] schrieb: Hi, On 10 Apr 2008 at 13:08, Martin Krause wrote: After some tries (i2c md ..) the bus hangs and no more transactions can be seen on the bus. One reason for a hanging bus could be a lost clock pulse. This could happen, if the low->high rise time of the bus signal is longer than the clock pulse width. For testing you could try a lower bus clock (10 kHz for example). sorry if I did not follow the discussion up to here. As I stumbled over it yesterday, I just want to give another example how to hang a bus. There are devices (namely LM75) that claim to be I2C devices but do not care about I2C specification. In case of LM75, a read must always be 16 bit (2 bytes), in case of reading only 1 byte the device does not interpret the missing ACK correctly and, in case the last byte read is '0', it will block the bus until some more (worst case 8) SCL pulses follow. Maybe something like this could also happen in your case? Regards, Wolfgang MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] I2C @ MPC8343
Martin, thanks for your hints. Martin Krause schrieb: Hi Andre, [EMAIL PROTECTED] wrote on : All, in my current system the I2C bus is not working properly on a MPC8343 in u-boot v1.3.2. i2c board config includes : #define CONFIG_HARD_I2C #undef CONFIG_SOFT_I2C #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_CMD_TREE #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 #define CFG_I2C_SPEED 10 #define CFG_I2C_SLAVE 0x7F chip probing works fine. mvBL-M7> i2c probe Valid chip addresses: 30 48 50 68 reading the Chips gives all "ff" mvBL-M7> i2c md 50 0 10 Uh, it seems I lag behind in U-Boot evolution. I know this "i2c md" command as "imd"? : ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Devices with address 50 normally are EEPROMs. If this device is an EEPROM, are you sure it contains data other than 0xff? Yes - it's the configuration data of the CPU. I can see the transaction on the bus - all data is correct. U-boot shows 0xff. The number of address bytes a device needs is varying. Your could look up the correct address length in the datasheet of your device, or try it manually: imd 50.0 0 10 imd 50.1 0 10 imd 50.2 0 10 One of this should work. no - only 0xff. Scope shows valid I2C transactions with correct data. Observing the I2C bus wires show that everything _works excellent_ : 100kHz speed as well as all data seems ok - but u-boot shows "ff". BTW: Fetching HRCW from I2C is also working fine. After some tries (i2c md ..) the bus hangs and no more transactions can be seen on the bus. One reason for a hanging bus could be a lost clock pulse. This could happen, if the low->high rise time of the bus signal is longer than the clock pulse width. For testing you could try a lower bus clock (10 kHz for example). rise time is ~200ns. Best Regards, Martin Krause -- TQ-Systems GmbH Muehlstrasse 2, Gut Delling, D-82229 Seefeld Amtsgericht Muenchen, HRB 105 018, UST-IdNr. DE 811 607 913 Geschaeftsfuehrer: Dipl.-Ing. (FH) Detlef Schneider, Dipl.-Ing. (FH) Ruediger Stahl http://www.tq-group.com MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] I2C @ MPC8343
All, in my current system the I2C bus is not working properly on a MPC8343 in u-boot v1.3.2. i2c board config includes : #define CONFIG_HARD_I2C #undef CONFIG_SOFT_I2C #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_CMD_TREE #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 #define CFG_I2C_SPEED 10 #define CFG_I2C_SLAVE 0x7F chip probing works fine. mvBL-M7> i2c probe Valid chip addresses: 30 48 50 68 reading the Chips gives all "ff" mvBL-M7> i2c md 50 0 10 : ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Observing the I2C bus wires show that everything _works excellent_ : 100kHz speed as well as all data seems ok - but u-boot shows "ff". BTW: Fetching HRCW from I2C is also working fine. After some tries (i2c md ..) the bus hangs and no more transactions can be seen on the bus. regards, Andre Schwarz Matrix Vision MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] add MPC8343 based board mvBlueLYNX-M7 aka mvblm7
MPC8343 based stereo camera system with Cyclone-II FPGA and miniPCI Slot. CPU utilizes dual 10/100/1000 Ethernet using Vitesse VSC8601 RGMII Phys and USB over ULPI. 512MB Micron DDR-II memory, 8MB Flash on LocalBus, SD over SPU and 32MB NAND @ FPGA. Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]> -- diff --git a/CREDITS b/CREDITS index e84ef38..713f58a 100644 --- a/CREDITS +++ b/CREDITS @@ -424,6 +424,11 @@ N: Paolo Scaffardi E: [EMAIL PROTECTED] D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more +N: Andre Schwarz +E: [EMAIL PROTECTED] +D: Support for BlueLYNX and BlueCOUGAR series +W: www.matrix-vision.com + N: Robert Schwebel E: [EMAIL PROTECTED] D: Support for csb226, logodl and innokom boards (PXA2xx) diff --git a/MAKEALL b/MAKEALL index 2a872ac..f21c34e 100755 --- a/MAKEALL +++ b/MAKEALL @@ -327,6 +327,7 @@ LIST_83xx=" \ MPC8360ERDK_66 \ MPC837XEMDS \ MPC837XERDB \ + MVBLM7 \ sbc8349 \ TQM834x \ " diff --git a/Makefile b/Makefile index a7f886b..3f217fe 100644 --- a/Makefile +++ b/Makefile @@ -2084,6 +2084,9 @@ sbc8349_config: unconfig TQM834x_config:unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x +MVBLM7_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7 + # ## MPC85xx Systems diff --git a/board/mvblm7/Makefile b/board/mvblm7/Makefile new file mode 100644 index 000..84cd14a --- /dev/null +++ b/board/mvblm7/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o fpga.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +# + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/mvblm7/config.mk b/board/mvblm7/config.mk new file mode 100644 index 000..a659203 --- /dev/null +++ b/board/mvblm7/config.mk @@ -0,0 +1,29 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC8349E-mITX and MPC8349E-mITX-GP +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +TEXT_BASE = 0xFFF0 diff --git a/board/mvblm7/fpga.c b/board/mvblm7/fpga.c new file mode 100644 index 000..d286ef1 --- /dev/null +++ b/board/mvblm7/fpga.c @@ -0,0 +1,185 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, [EMAIL PROTECTED] + * Keith Outwater, [EMAIL PROTECTED] + * + * (C) Copyright 2006 + * Andre Schwarz, Matrix Vision GmbH, [EMAIL PROTECTED] + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) a
Re: [U-Boot-Users] MPC8343 PCI setup
Tor Krill schrieb:
On 4/3/2008, "Andre Schwarz" <[EMAIL PROTECTED]> wrote:
All,
Hi Andre and others,
currently I'm trying to bring up a mpc8343 based system.
Latest u-boot v1.3.2 is running fine.
The MPC8343 has a single 32-Bit PCI Bus running at 66MHz.
Connected are a FPGA (IDSEL 11 + IRQ0) and a miniPCI Slot (IDSEL12 +
IRQ1).
Unfortunately the kernel panics during/after PCI setup.
Not sure if this is related. But i got strange problems with PCI after
the patch "Add CONFIG_PCI_SKIP_HOST_BRIDGE config option"
(55774b512fdf63c..) was added.
My symptoms where missed interrupts on sata dma in Linux. U-boot where
however fine. Adding the above config solved my problems. Not really
sure why i experienced this. We have no PCI bridge on our board.
/Tor
Tor,
thanks for your reply.
I'm also not sure if it's a PCI issue anymore ...
Kernel config has been reduced to a minimum : no PCI, no netwoking, i2c,
spi ...
dts has been reduced to the CPU, soc and ipic.
U-Boot fills out dtb correctly - as far as I can see.
Kernel crashes on various "of_" functions.
There's also strange messages :
WARNING: Estimating decrementer frequency (not found)
WARNING: Estimating processor frequency (not found)
They're coming from "generic_calibrate_decr()" in kernel/time.c.
Looks like there something basically wrong with my dtb
location/processing, since the "timebase-frequency" is present and valid :
cpus {
#address-cells = <0x0001>;
#size-cells = <0x>;
PowerPC,[EMAIL PROTECTED] {
device_type = "cpu";
reg = <0x>;
d-cache-line-size = <0x0020>;
i-cache-line-size = <0x0020>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
timebase-frequency = <0x03f940aa>;
bus-frequency = <0x0fe502a8>;
clock-frequency = <0x17d783fc>;
};
};
Any hints ?
regards,
Andre
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[U-Boot-Users] MPC8343 PCI setup
All,
currently I'm trying to bring up a mpc8343 based system.
Latest u-boot v1.3.2 is running fine.
The MPC8343 has a single 32-Bit PCI Bus running at 66MHz.
Connected are a FPGA (IDSEL 11 + IRQ0) and a miniPCI Slot (IDSEL12 +
IRQ1).
Unfortunately the kernel panics during/after PCI setup.
As always I expect my device tree to be wrong or at least is missing
something.
I startet with "mpc834x_mds.dts", removed the 2nd PCI and switched to
"PowerPC,[EMAIL PROTECTED]".
u-boot shows this pci node :
[EMAIL PROTECTED] {
cell-index = <0x0001>;
interrupt-map-mask = [00 00 f8 00 00 00 00 00 00 00 00
00 00 00 00 07];
interrupt-map = [00 00 58 00 00 00 00 00 00 00 00 00 00
00 00 01 00 00 00 01 00 00 00 30 00 00 00 08 00 00
60 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 01 00 00 00 11 00 00
00 08];
interrupt-parent = <0x0001>;
interrupts = <0x0042 0x0008>;
bus-range = <0x 0x>;
ranges = [02 00 00 00 00 00 00 00 90 00 00 00 90 00 00
00 00 00 00 00 10 00 00 00 42 00 00 00 00 00 00 00 8
0 00 00 00 80 00 00 00 00 00 00 00 10 00 00 00 01 00 00 00 00 00 00 00
00 00 00 00 e2 00 00 00 00 00 00 00 00 10 00 00];
clock-frequency = <0x03f940aa>;
#interrupt-cells = <0x0001>;
#size-cells = <0x0002>;
#address-cells = <0x0003>;
reg = <0xe0008500 0x0100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
Booting the kernel :
Using mvBlueLYNX-M7 machine description
Linux version 2.6.25-rc7-01000-ga1ba6f0-dirty ([EMAIL PROTECTED]) (gcc version
4.0.0 (DENX ELDK 4.1 4.0.0)) #23 PREEMPT Thu Apr 3 1
6:46:17 CEST 2008
Found initrd at 0xc3978000:0xc3c0
console [udbg0] enabled
setup_arch: bootmem
mvblm7_setup_arch()
Adding PCI host bridge /[EMAIL PROTECTED]
Found MPC83xx PCI host bridge at 0xe0008500. Firmware bus
number: 0->0
->Hose at 0xc02bf000, cfg_addr=0xfdffd300,cfg_data=0xfdffd304
PCI host bridge /[EMAIL PROTECTED] (primary) ranges:
MEM 0x9000..0x9fff -> 0x9000
MEM 0x8000..0x8fff -> 0x8000 Prefetch
IO 0xe200..0xe20f -> 0x
Unable to handle kernel paging request for data at address 0x0000
Call trace gives address last called function "of_device_is_compatible".
Any help is welcome !
regards,
Andre Schwarz
Matrix Vision
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Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
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Re: [U-Boot-Users] [PATCH] Add Vitesse 8601 support to TSEC driver
Andy Fleming schrieb: On Tue, Apr 1, 2008 at 9:08 AM, Andre Schwarz <[EMAIL PROTECTED]> wrote: Tor, after investigating the tsec code I'm wondering how your PHY works in RGMII mode ... I think that there are some things missing, e.g. taking RGMII into account during tsec_init. /* Init ECNTRL */ regs->ecntrl = ECNTRL_INIT_SETTINGS; If you look carefully, you'll notice that ecntrl's RPM bit is read-only. Those bits are configured by POR pin strappings. sorry, my documentation (MPC8349EARM rev.1) declares this register read-write. Of course it will be configured by the HRCW but can be overwritten afterwards. If this is not true it's a documentation bug. Thank you for bringing this to my attention. It is almost certainly a bug. If you look at the 8349ERM (rather than the 8349EARM), you'll see that the bits are read-only (except for R100, which tsec.c does modify based on the link type). I will file a bug with the docs people. I've x-checked and printed the register after init. You're right - it's read only and the RPM bit is set. But the ECNTL register description @ 15.5.3.1.4 says "read/write" to all bits ... You may be more familiar with the UEC, which doesn't automatically detect the link type, but is otherwise fairly similar to the tsec. What do you mean ? I'm trying to get two VSC8601 RGMII PHYs running on a MPC8343B ... sorry, I forgot which ethernet controller you were using, and I'm not as familiar with the 83xx family as the 85xx family. Some of our parts have the QUICC Engine, which has an ethernet controller with some similar registers to the TSEC's. I was guessing that was why you thought those bits were writable, rather than a documentation bug, but clearly I was wrong. :) no problem. Andre Andy Andy MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] Add Vitesse 8601 support to TSEC driver
Andy Fleming schrieb: On Tue, Apr 1, 2008 at 8:33 AM, Andre Schwarz <[EMAIL PROTECTED]> wrote: Tor, after investigating the tsec code I'm wondering how your PHY works in RGMII mode ... I think that there are some things missing, e.g. taking RGMII into account during tsec_init. /* Init ECNTRL */ regs->ecntrl = ECNTRL_INIT_SETTINGS; If you look carefully, you'll notice that ecntrl's RPM bit is read-only. Those bits are configured by POR pin strappings. sorry, my documentation (MPC8349EARM rev.1) declares this register read-write. Of course it will be configured by the HRCW but can be overwritten afterwards. If this is not true it's a documentation bug. You may be more familiar with the UEC, which doesn't automatically detect the link type, but is otherwise fairly similar to the tsec. What do you mean ? I'm trying to get two VSC8601 RGMII PHYs running on a MPC8343B ... Andy regards, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] Add Vitesse 8601 support to TSEC driver
Tor,
after investigating the tsec code I'm wondering how your PHY works in
RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into
account during tsec_init.
/* Init ECNTRL */
regs->ecntrl = ECNTRL_INIT_SETTINGS;
This will clear bit 27 which indicates RGMII as set up by the HRCW.
I would expect something like
if ( priv->flags & TSEC_REDUCED )
regs->ecntrl |= ECNTRL_RPM;
afterwards.
Before I'll start doing double work again : Have you some unposted
patches regarding RGMII on TSEC ?
Am I missing something ?
@Kim : Did you ever run a MPC834x with a RGMII PHY ? Is it known to work ?
regards,
Andre
Tor Krill schrieb:
> Add phy_info for Vitesse VSC8601.
> Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing
> compensation.
>
> Signed-off-by: Tor Krill <[EMAIL PROTECTED]>
> ---
> drivers/net/tsec.c | 30 ++
> drivers/net/tsec.h |5 +
> 2 files changed, 35 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
> index 431a8d2..9d22aa3 100644
> --- a/drivers/net/tsec.c
> +++ b/drivers/net/tsec.c
> @@ -1267,6 +1267,35 @@ struct phy_info phy_info_VSC8244 = {
> },
> };
>
> +struct phy_info phy_info_VSC8601 = {
> + 0x7042,
> + "Vitesse VSC8601",
> + 4,
> + (struct phy_cmd[]){ /* config */
> + /* Override PHY config settings */
> + /* Configure some basic stuff */
> + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
> +#ifdef CFG_VSC8601_SKEWFIX
> +
> {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
> +#endif
> + {miim_end,}
> + },
> + (struct phy_cmd[]){ /* startup */
> + /* Read the Status (2x to make sure link is
> right) */
> + {MIIM_STATUS, miim_read, NULL},
> + /* Auto-negotiate */
> + {MIIM_STATUS, miim_read, &mii_parse_sr},
> + /* Read the status */
> + {MIIM_VSC8244_AUX_CONSTAT, miim_read,
> + &mii_parse_vsc8244},
> + {miim_end,}
> + },
> + (struct phy_cmd[]){ /* shutdown */
> + {miim_end,}
> + },
> +};
> +
> +
> struct phy_info phy_info_dm9161 = {
> 0x0181b88,
> "Davicom DM9161E",
> @@ -1462,6 +1491,7 @@ struct phy_info *phy_info[] = {
> &phy_info_dm9161,
> &phy_info_lxt971,
> &phy_info_VSC8244,
> + &phy_info_VSC8601,
> &phy_info_dp83865,
> &phy_info_rtl8211b,
> &phy_info_generic,
> diff --git a/drivers/net/tsec.h b/drivers/net/tsec.h
> index d4dc15a..cfa7d1a 100644
> --- a/drivers/net/tsec.h
> +++ b/drivers/net/tsec.h
> @@ -159,6 +159,11 @@
> #define MIIM_VSC8244_LED_CON0x1b
> #define MIIM_VSC8244_LEDCON_INIT0xF011
>
> +/* Entry for Vitesse VSC8601 regs starts here (Not complete) */
> +/* Vitesse VSC8601 Extended PHY Control Register 1 */
> +#define MIIM_VSC8601_EPHY_CON0x17
> +#define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
> +
> /* 88E1011 PHY Status Register */
> #define MIIM_88E1011_PHY_STATUS 0x11
> #define MIIM_88E1011_PHYSTAT_SPEED 0xc000
>
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Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
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Re: [U-Boot-Users] [PATCH] Add Vitesse 8601 support to TSEC driver
Kim,
would it help if we donate one or two boards to the custodians ?
Or do you have no time at all for specific testing ?
After bring-up + validation I could offer 1-2 MPC8343B based boards with
2x VSC8601.
The system also has a miniPCI Slot, USB-A and 512MB DDR-II Micron memory.
Please let me know if you're interested.
regards,
Andre Schwarz
Matrix Vision
Kim Phillips schrieb:
On Mon, 31 Mar 2008 10:01:34 -0400
Ben Warren <[EMAIL PROTECTED]> wrote:
Tor Krill wrote:
Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing
compensation.
Signed-off-by: Tor Krill <[EMAIL PROTECTED]>
Acked-by: Ben Warren <[EMAIL PROTECTED]>
I don't have a Vitesse 8601, so technically I can't ack it, but I can:
Reviewed-by: Kim Phillips <[EMAIL PROTECTED]>
minor nit: it would be nice if the following:
+#ifdef CFG_VSC8601_SKEWFIX
+
{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#endif
were made to have spaces after commas, and flow onto a separate
line so as to not be a 96 char line..
Kim
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Re: [U-Boot-Users] MPC83xx HRCW
Jerry Van Baren schrieb: > Andre Schwarz wrote: >> Jerry Van Baren schrieb: >>> Andre Schwarz wrote: >>>> In "cpu/mpc83xx/start.S" there is a comment : >>>> >>>> /* >>>> * The Hard Reset Configuration Word (HRCW) table is in the first 64 >>>> * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 >>>> * times so the processor can fetch it out of flash whether the flash >>>> * is 8, 16, 32, or 64 bits wide (hardware trickery). >>>> */ >>>> >>>> This does _not_ hold true for all configurations. Flash is simply >>>> one of many options ... >>>> Maybe it's true for the Freescale boards. >>>> >>>> Other sources of the HRCW can be hard-coded strapping pins or an >>>> I2C EEPROM. >>>> >>>> Why is there a need to define the HRCW ? >>>> >>>> regards, >>>> Andre Schwarz >>> >>> Hi Andre, >>> >>> The HRCW in flash (could be other memory or a FPGA register) is a >>> processor feature which a board may or may not use. I am not >>> familiar with the whole 83xx family, but I presume the feature is >>> part of the whole family. >>> >>> As you point out, there are other ways of configuring the processor >>> on power up, and it is board-specific which way is used on the >>> particular board. >>> >>> For the boards that support the HRCW, obviously the definition in >>> the first 64 bytes of flash is necessary. For other boards, it is >>> unnecessary. FWIIW, the Freescale eval boards that I have >>> experience with allow the HRCW to come from flash, i2c, or an FPGA >>> (BCSR). >>> >>> To date, having a potentially unused HRCW definition in memory has >>> not been an issue - people either use it or ignore it. If it is an >>> issue, you could use conditionals to disable it. I'm sure the 83xx >>> custodian (Kim Phillips) would consider patches to do that. ;-) >>> Note that there is a possibility that some of the code assumes the >>> presence of a HRCW, so you would have to inspect and/or regression >>> test as part of a conditionalization patch. >>> >> ok - so should be no problem to #define the HRCW to "0x0" since it >> won't be used at all - just occupies some memory. >> I just wanted to be sure that the #defined HRCW is not used as a >> reference at all in any code ! > > Theoretically, there is no problem. I don't know if there are any > implicit uses of the HRCW - that would be part of the need to inspect > and/or regression test. > > I suspect that the CPU frequency determination code uses it, since > part of the CPU PLL multiplier comes from the HRCW (IIRC - I get > confused between the 82xx and 83xx families sometimes). > Using the HRCW during SystemInit is no problem - but the _real_ one from the CPU register and not a #defined one. The CPU won't start anyway if the HRCW is invalid. I've just #defined my HRCW to "0" without any problems. Sorry for the confusion. regards, Andre > [snip] > > Best regards, > gvb MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] MPC83xx HRCW
In "cpu/mpc83xx/start.S" there is a comment : /* * The Hard Reset Configuration Word (HRCW) table is in the first 64 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 * times so the processor can fetch it out of flash whether the flash * is 8, 16, 32, or 64 bits wide (hardware trickery). */ This does _not_ hold true for all configurations. Flash is simply one of many options ... Maybe it's true for the Freescale boards. Other sources of the HRCW can be hard-coded strapping pins or an I2C EEPROM. Why is there a need to define the HRCW ? regards, Andre Schwarz Matrix Vision MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] DDR-II @ MPC8343A
Kim Phillips schrieb: On Tue, 25 Mar 2008 21:25:45 +0100 Andre Schwarz <[EMAIL PROTECTED]> wrote: I've seen things like this in mpc8349emds code : #if (CFG_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif Is this reasonable ? Why ? that's in the fixed sdram init code, which could be considered reasonably unreasonable by some I suppose, since we can't guarantee the fixed settings will work with whatever memory you decide to use with it. It should work with the memory that comes with the board, though. fixed_sdram is ok - that's what I have and want to use. I'm setting up the proper CFG_DDR_ defines in my header regarding the Manufacturer's spec. btw, the spd code is being used by default on the 834x mds, not this fixed_sdram stuff - it's mostly there for board porting completeness. But it is known to work, isn't it ? Kim regards, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] DDR-II @ MPC8343A
Kim Phillips schrieb: On Tue, 25 Mar 2008 20:41:41 +0100 Andre Schwarz <[EMAIL PROTECTED]> wrote: Kim Phillips schrieb: On Tue, 25 Mar 2008 18:36:47 +0100 Andre Schwarz <[EMAIL PROTECTED]> wrote: As far as I can see there are only DDR-I boards from Freescale. The MDS can do ddr2: U-Boot 1.3.2-00097-gbc508d1 (Mar 25 2008 - 10:47:17) MPC83XX Reset Status: Software Hard, External/Internal Soft, External/Internal Hard CPU: e300c1, MPC8349E, Rev: 30 at 528 MHz, CSB: 264 MHz Board: Freescale MPC8349EMDS I2C: ready SPI: ready DRAM: 256 MB (DDR2, 64-bit, ECC on) ... Hmmm ... I get : U-Boot 1.3.2-00075-gc5f497a-dirty (Mar 25 2008 - 19:55:00) MPC83XX Reset Status: Check Stop, External/Internal Soft, External/Internal Hard CPU: e300c1, MPC8343, Rev: 31 at 399.999 MHz, CSB: 266 MHz Board: Matrix Vision mvBlueLYNX-M7 I2C: ready SPI: ready DRAM: cs0_bnds = 0x000f cs0_config = 0x80844102 DDR:bar=0x DDR:ar=0x801b 256 MB It's a 32-Bit DDR-II without ECC. 2 Chips are soldered to CS0, i.e. no EPROM present. Since I expect something like "(DDR2, 32-Bit, ECC off)" and nothing happens there is obviously something wrong with my memory setup. Is this reasonable ? sounds like memory isn't being configured correctly. Board specific? Having a closer look to the boards show that I'm currently using 2 Micron MT47H256M8HG-3 with 2GBit each yielding a total of 512MByte DDR-II memory this is sad :-( Regarding to part list there should have been 1GBit Elpida chips on it. I've seen things like this in mpc8349emds code : #if (CFG_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif Is this reasonable ? Why ? Or am I simply missing a board specific "board_add_ram_info" ? you can do that if you really, really, really want to see the "(DDR2.." string, but it's optional. I don't want to see it but to understand where it comes from. Am I assuming right that your info string "(DDR2, 64-bit, ECC on)" comes from spd_sdram ? yes. Kim regards, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] DDR-II @ MPC8343A
Kim Phillips schrieb: On Tue, 25 Mar 2008 18:36:47 +0100 Andre Schwarz <[EMAIL PROTECTED]> wrote: All, has anyone set up the DDR-II controller on a Freescale MPC8343A without ? without what? typo - sorry. As far as I can see there are only DDR-I boards from Freescale. The MDS can do ddr2: U-Boot 1.3.2-00097-gbc508d1 (Mar 25 2008 - 10:47:17) MPC83XX Reset Status: Software Hard, External/Internal Soft, External/Internal Hard CPU: e300c1, MPC8349E, Rev: 30 at 528 MHz, CSB: 264 MHz Board: Freescale MPC8349EMDS I2C: ready SPI: ready DRAM: 256 MB (DDR2, 64-bit, ECC on) ... Hmmm ... I get : U-Boot 1.3.2-00075-gc5f497a-dirty (Mar 25 2008 - 19:55:00) MPC83XX Reset Status: Check Stop, External/Internal Soft, External/Internal Hard CPU: e300c1, MPC8343, Rev: 31 at 399.999 MHz, CSB: 266 MHz Board: Matrix Vision mvBlueLYNX-M7 I2C: ready SPI: ready DRAM: cs0_bnds = 0x000f cs0_config = 0x80844102 DDR:bar=0x DDR:ar=0x801b 256 MB It's a 32-Bit DDR-II without ECC. 2 Chips are soldered to CS0, i.e. no EPROM present. Since I expect something like "(DDR2, 32-Bit, ECC off)" and nothing happens there is obviously something wrong with my memory setup. Is this reasonable ? Or am I simply missing a board specific "board_add_ram_info" ? Am I assuming right that your info string "(DDR2, 64-bit, ECC on)" comes from spd_sdram ? Are there any patches not yet posted to handle this ? should work, only diff I see is that the 8343 is 32-bit only. Kim I'll dig a little deeper now and ask more questions tommorow. Thanks for your help ! regards, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] DDR-II @ MPC8343A
All, has anyone set up the DDR-II controller on a Freescale MPC8343A without ? As far as I can see there are only DDR-I boards from Freescale. Are there any patches not yet posted to handle this ? regards, Andre Schwarz Matrix Vision MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] mpc5200 without fec
Grant Likely schrieb:
On Thu, Mar 13, 2008 at 6:50 AM, André Schwarz
<[EMAIL PROTECTED]> wrote:
include fec specific nodes in ft_cpu_setup only if CONFIG_MPC5xxx_FEC is
defined. Systems without FEC, i.e. no fec node in dtb, should be possible.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
Hmm; if there is no fec node; then won't this just fail silently? In
which case; I'd rather avoid adding more inline #ifdefs to the code.
(correct me if I'm wrong)
Cheers,
g.
it fails - but not silently. If you don't care for the error messages on
the console you don't need it.
I don't like _any_ error message :-)
After all it's not a board specific #ifdef ...
---
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c
index e4d6168..dbfdd97 100644
--- a/cpu/mpc5xxx/cpu.c
+++ b/cpu/mpc5xxx/cpu.c
@@ -119,7 +119,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
{
int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4;
char * cpu_path = "/cpus/" OF_CPU;
+#ifdef CONFIG_MPC5xxx_FEC
char * eth_path = "/" OF_SOC "/[EMAIL PROTECTED]";
+#endif
do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq,
1);
@@ -127,7 +129,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq,
1);
do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency",
bd->bi_busfreq*div, 1);
+#ifdef CONFIG_MPC5xxx_FEC
do_fixup_by_path(blob, eth_path, "mac-address", bd->bi_enetaddr, 6, 0);
do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr,
6, 0);
+#endif
}
#endif
-
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Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
-
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Re: [U-Boot-Users] FPGA mess
Heiko Schocher schrieb: Hello Stefan, Stefan Roese wrote: On Thursday 06 March 2008, Andre Schwarz wrote: Stefan Roese schrieb: On Wednesday 05 March 2008, Andre Schwarz wrote: [...] There's a include/ACEX1K.h that introduces two interfaces for obviously the same funtionality. The first one is specific to ACEX1K and the other one is a general cyclone implementation as it should be. Please clean it up too. Maybe we should do a cyclon2.h ? include/ACEX1K.h Obviously there are some confusions about the various file formats and sizes that can be output from Altera's SoPC Builder. Compression is also possible with de-compression on the fly during load ... Of course the defined file sizes should match a raw bit file that represents the true size of the device. Why is ACEX1K and Cyclone not merged ? No idea. If you have some fixes, please send patches. Does _any_ real board use the Altera path ? scanning the config files ... no. alpr seems to use the cyclone2.c code. no - it uses common/ACEX1K.c and common/cyclon2.c is derived from it. No, it doesn't use common/ACEX1K.c. Yes, common/ACEX1K.c was the base for me to make the cyclon2.c. CYC2_ps_load in common/cyclon2.c the nCONFIG pin is never de-asserted during preparation. This code can't work. No idea. I have to admit, that I didn't implement the FPGA booting on this board. But it seems to work fine. yes - because it's a board specific implementation with an "general" interface. ??? What do you mean with "board specific implementation". Its for a cyclon2 FPGA. I am not a FPGA specialist, but I think there were some differences between this FPGAs and so I made a new File ... Is there any interest in getting this fixed ? Sure. But implementing the Altera path in a clean way means discarding the ACEX1K and breaking the alpr borad. I'm quite sure that Wolfgang will reject those changes. Yes, I will reject this too. :) Why you break the alpr board. It uses the common/cyclon2.c? (OK, we should make a include/cyclon2.h and then we can drop the ACEX1K, right?) I admit that I have not followed the ACEX1K down through the interface. But since there is an ACEX1K "#define" in common/altera.c and the serial download of the Cyclone is broken (missing deassertion of nConfig) it looked like alpr used the ACEX1K. As I see now this is not true. We should fix the programming of nConfig and verify on alpr. Then we can remove ACEX1K and prepare for Cyclone-II and -III with a unified loader, corrected chip sizes and variable bitstream formats including endianess. How can we solve this ? By trying to solve it in a compatible way. I added Heiko Schocher to CC too, since he was responsible for the FPGA booting implementation of the alpr board. I have to admit that this was my First and only FPGA Implementation. Stefan, do you know, if we have somewhere an alpr board, so we can do tests with it, if we change code? bye Heiko If would be great if you could test the changes on alpr before applying patches. It looks like no other Altera boards are in the tree ... I have different ones and can do excessive testing. regards, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] new PHY @ e1000 - 2nd try
Add 82541ER device with latest integrated IGP2 PHY.
Introduced CONFIG_E1000_FALLBACK_MAC for NIC bring-up with empty eeprom.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
diff --git a/README b/README
index 491397a..d59d9b3 100644
--- a/README
+++ b/README
@@ -731,6 +731,9 @@ The following options need to be configured:
CONFIG_E1000
Support for Intel 8254x gigabit chips.
+ CONFIG_E1000_FALLBACK_MAC
+ default MAC for empty eeprom after production.
+
CONFIG_EEPRO100
Support for Intel 82557/82559/82559ER chips.
Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index f0741da..4b1a39a 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -1,5 +1,5 @@
/**
-Inter Pro 1000 for ppcboot/das-u-boot
+Intel Pro 1000 for ppcboot/das-u-boot
Drivers are port from Intel's Linux driver e1000-4.3.15
and from Etherboot pro 1000 driver by mrakes at vivato dot net
tested on both gig copper and gig fiber boards
@@ -82,6 +82,7 @@ static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
};
/* Function forward declarations */
@@ -512,6 +513,11 @@ e1000_read_mac_addr(struct eth_device *nic)
/* Invert the last bit if this is the second device */
nic->enetaddr[5] += 1;
}
+#ifdef CONFIG_E1000_FALLBACK_MAC
+ if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 )
+ for ( i=0; i < NODE_ADDRESS_SIZE; i++ )
+ nic->enetaddr[i] = (CONFIG_E1000_FALLBACK_MAC >>
(8*(5-i))) & 0xff;
+#endif
#else
/*
* The AP1000's e1000 has no eeprom; the MAC address is stored in the
@@ -639,6 +645,9 @@ e1000_set_mac_type(struct e1000_hw *hw)
case E1000_DEV_ID_82546EB_FIBER:
hw->mac_type = e1000_82546;
break;
+ case E1000_DEV_ID_82541ER:
+ hw->mac_type = e1000_82541_rev_2;
+ break;
default:
/* Should never have loaded on this device */
return -E1000_ERR_MAC_TYPE;
@@ -2485,6 +2494,36 @@ e1000_phy_reset(struct e1000_hw *hw)
return 0;
}
+static int
+e1000_set_phy_type(struct e1000_hw *hw)
+{
+DEBUGFUNC();
+
+if(hw->mac_type == e1000_undefined)
+return -E1000_ERR_PHY_TYPE;
+
+switch(hw->phy_id) {
+case M88E1000_E_PHY_ID:
+case M88E1000_I_PHY_ID:
+case M88E1011_I_PHY_ID:
+hw->phy_type = e1000_phy_m88;
+break;
+case IGP01E1000_I_PHY_ID:
+if(hw->mac_type == e1000_82541 ||
+ hw->mac_type == e1000_82541_rev_2) {
+hw->phy_type = e1000_phy_igp;
+break;
+}
+/* Fall Through */
+default:
+/* Should never have loaded on this device */
+hw->phy_type = e1000_phy_undefined;
+return -E1000_ERR_PHY_TYPE;
+}
+
+return E1000_SUCCESS;
+}
+
/**
* Probes the expected PHY address for known PHY IDs
*
@@ -2493,6 +2532,7 @@ e1000_phy_reset(struct e1000_hw *hw)
static int
e1000_detect_gig_phy(struct e1000_hw *hw)
{
+ int32_t phy_init_status;
uint16_t phy_id_high, phy_id_low;
int match = FALSE;
@@ -2526,11 +2566,19 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
if (hw->phy_id == M88E1011_I_PHY_ID)
match = TRUE;
break;
+ case e1000_82541_rev_2:
+ if(hw->phy_id == IGP01E1000_I_PHY_ID)
+ match = TRUE;
+
+ break;
default:
DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
return -E1000_ERR_CONFIG;
}
- if (match) {
+
+ phy_init_status = e1000_set_phy_type(hw);
+
+ if ((match) && (phy_init_status == E1000_SUCCESS)) {
DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
return 0;
}
@@ -2985,7 +3033,7 @@ e1000_initialize(bd_t * bis)
free(nic);
return 0;
}
-#ifndef CONFIG_AP1000
+#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
if (e1000_validate_eeprom_checksum(nic) < 0) {
printf("The EEPROM Check
[U-Boot-Users] [PATCH] new PHY @ e1000
Add 82541ER device with latest integrated IGP2 PHY.
Introduced CONFIG_E1000_FALLBACK_MAC for NIC bring-up with empty eeprom.
regards,
Andre Schwarz
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
diff --git a/README b/README
index 491397a..d59d9b3 100644
--- a/README
+++ b/README
@@ -731,6 +731,9 @@ The following options need to be configured:
CONFIG_E1000
Support for Intel 8254x gigabit chips.
+ CONFIG_E1000_FALLBACK_MAC
+ default MAC for empty eeprom after production.
+
CONFIG_EEPRO100
Support for Intel 82557/82559/82559ER chips.
Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index f0741da..47f1bb0 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -1,5 +1,5 @@
/**
-Inter Pro 1000 for ppcboot/das-u-boot
+Intel Pro 1000 for ppcboot/das-u-boot
Drivers are port from Intel's Linux driver e1000-4.3.15
and from Etherboot pro 1000 driver by mrakes at vivato dot net
tested on both gig copper and gig fiber boards
@@ -82,6 +82,7 @@ static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
};
/* Function forward declarations */
@@ -512,6 +513,11 @@ e1000_read_mac_addr(struct eth_device *nic)
/* Invert the last bit if this is the second device */
nic->enetaddr[5] += 1;
}
+#ifdef CONFIG_E1000_FALLBACK_MAC
+ if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 )
+ for ( i=0; i < NODE_ADDRESS_SIZE; i++ )
+ nic->enetaddr[i] = (CONFIG_E1000_FALLBACK_MAC >>
(8*(5-i))) & 0xff;
+#endif
#else
/*
* The AP1000's e1000 has no eeprom; the MAC address is stored in the
@@ -639,6 +645,9 @@ e1000_set_mac_type(struct e1000_hw *hw)
case E1000_DEV_ID_82546EB_FIBER:
hw->mac_type = e1000_82546;
break;
+ case E1000_DEV_ID_82541ER:
+ hw->mac_type = e1000_82541_rev_2;
+ break;
default:
/* Should never have loaded on this device */
return -E1000_ERR_MAC_TYPE;
@@ -2485,6 +2494,36 @@ e1000_phy_reset(struct e1000_hw *hw)
return 0;
}
+static int
+e1000_set_phy_type(struct e1000_hw *hw)
+{
+DEBUGFUNC();
+
+if(hw->mac_type == e1000_undefined)
+return -E1000_ERR_PHY_TYPE;
+
+switch(hw->phy_id) {
+case M88E1000_E_PHY_ID:
+case M88E1000_I_PHY_ID:
+case M88E1011_I_PHY_ID:
+hw->phy_type = e1000_phy_m88;
+break;
+case IGP01E1000_I_PHY_ID:
+if(hw->mac_type == e1000_82541 ||
+ hw->mac_type == e1000_82541_rev_2) {
+hw->phy_type = e1000_phy_igp;
+break;
+}
+/* Fall Through */
+default:
+/* Should never have loaded on this device */
+hw->phy_type = e1000_phy_undefined;
+return -E1000_ERR_PHY_TYPE;
+}
+
+return E1000_SUCCESS;
+}
+
/**
* Probes the expected PHY address for known PHY IDs
*
@@ -2493,6 +2532,7 @@ e1000_phy_reset(struct e1000_hw *hw)
static int
e1000_detect_gig_phy(struct e1000_hw *hw)
{
+ int32_t phy_init_status;
uint16_t phy_id_high, phy_id_low;
int match = FALSE;
@@ -2526,11 +2566,19 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
if (hw->phy_id == M88E1011_I_PHY_ID)
match = TRUE;
break;
+ case e1000_82541_rev_2:
+ if(hw->phy_id == IGP01E1000_I_PHY_ID)
+ match = TRUE;
+
+ break;
default:
DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
return -E1000_ERR_CONFIG;
}
- if (match) {
+
+ phy_init_status = e1000_set_phy_type(hw);
+
+ if ((match) && (phy_init_status == E1000_SUCCESS)) {
DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
return 0;
}
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index 0fbdc90..c72517c 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -71,6 +71,8 @@ typedef enum {
e1000_82540,
e1000_82545,
e1000_82546,
+ e1000_82541,
+ e1000_82541_rev_2,
e1000_num_macs
} e1000_mac_type;
@@ -168,6 +170,13 @@ typedef enum {
e10
[U-Boot-Users] FPGA mess
Stefan, you're listed as maintainer for the alpr board. It's the only board that uses the ACEX1K.c file for FPGA loading... I'm quite sure there are many boards with Altera FPGAs outside and can't believe they have all mounted platform flashes and therefore don't use u-boot for loading the FPGA. Nevertheless those board don't show up in the tree. Maybe they all keep their own patches like me ... There are some points that doesn't seem to work out very well in general. This is where some questions come up (top->down) : common/cmd_fpga: In function do_fpga there's a used environment variable "fpgadata" that obviously stores the location of the bitstream. What sense does this make if the "data_size" parameter (=arg4) is _not_ optional ? Instead the command "fpga load 0 0x..." leads to a load function with zero length. The user always has to supply all 4 args (load, nr, data, size). Of course the loading function could use the pre-defined bitstream size from the header or the device struct... common/altera.c What's that ACEX1K ? Isn't it a Cyclone chip and should use that interface ? Why does this need special treatment throughout the interface ? include/ACEX1K.h Obviously there are some confusions about the various file formats and sizes that can be output from Altera's SoPC Builder. Compression is also possible with de-compression on the fly during load ... Of course the defined file sizes should match a raw bit file that represents the true size of the device. Why is ACEX1K and Cyclone not merged ? Does _any_ real board use the Altera path ? scanning the config files ... no. CYC2_ps_load in common/cyclon2.c the nCONFIG pin is never de-asserted during preparation. This code can't work. Is there any interest in getting this fixed ? What about Liberty's Stratix code ? It's living and working ! regards, Andre Schwarz MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
