[U-Boot-Users] [FYI] mainline gcc vs printf args
probably we may be interested in this topic. http://sourceware.org/ml/binutils/2008-07/msg00370.html mainline gcc vs printf args -- Shinya Kuribayashi NEC Electronics - This SF.Net email is sponsored by the Moblin Your Move Developer's challenge Build the coolest Linux based applications with Moblin SDK win great prizes Grand prize is a trip for two to an Open Source event anywhere in the world http://moblin-contest.org/redirect.php?banner_id=100url=/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [FYI] mainline gcc vs printf args
Wolfgang Denk wrote: In message [EMAIL PROTECTED] you wrote: probably we may be interested in this topic. http://sourceware.org/ml/binutils/2008-07/msg00370.html mainline gcc vs printf args Which exact part of this is it that you think might be interesting? Oops, I might have looked at recent printf format fixes all wrong over this month. [I found Andrew's fix at last.. ] - This SF.Net email is sponsored by the Moblin Your Move Developer's challenge Build the coolest Linux based applications with Moblin SDK win great prizes Grand prize is a trip for two to an Open Source event anywhere in the world http://moblin-contest.org/redirect.php?banner_id=100url=/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [GIT PULL] MIPS updates
Hi Wolfgang, please pull MIPS update. I'd like to make this into v1.3.4-final. Thanks, Shinya --- The following changes since commit 1953d128fd07f07d1c3810a28c0863ea64dae1b6: Michal Simek (1): microblaze: Fix printf() format issues are available in the git repository at: git://git.denx.de/u-boot-mips.git master Wolfgang Ocker (1): mips: Fix baudrate divisor computation on alchemy cpus cpu/mips/au1x00_serial.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) commit dbd32387920e5ad6f9dd58a7b5012bbabe2a6a21 Author: Wolfgang Ocker [EMAIL PROTECTED] Date: Mon Jul 28 16:56:51 2008 +0200 mips: Fix baudrate divisor computation on alchemy cpus Use CFG_MIPS_TIMER_FREQ when computing the baudrate divisor on alchemy cpus. Signed-off-by: Wolfgang Ocker [EMAIL PROTECTED] Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c index 6309794..e8baab5 100644 --- a/cpu/mips/au1x00_serial.c +++ b/cpu/mips/au1x00_serial.c @@ -76,7 +76,7 @@ void serial_setbrg (void) sd = (*sys_powerctrl 0x03) + 2; /* calulate 2x baudrate and round */ - divisorx2 = ((CFG_HZ/(sd * 16 * CONFIG_BAUDRATE))); + divisorx2 = ((CFG_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE))); if (divisorx2 0x01) divisorx2 = divisorx2 + 1; - This SF.Net email is sponsored by the Moblin Your Move Developer's challenge Build the coolest Linux based applications with Moblin SDK win great prizes Grand prize is a trip for two to an Open Source event anywhere in the world http://moblin-contest.org/redirect.php?banner_id=100url=/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] mips: Fix baudrate divisor computation on alchemy cpus
Wolfgang Ocker wrote: Use CFG_MIPS_TIMER_FREQ when computing the baudrate divisor on alchemy cpus. Signed-off-by: Wolfgang Ocker [EMAIL PROTECTED] Thanks, I'll apply and push this out tonight. This patch should go in the upcoming v1.3.4 final. Shinya --- diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c index 6309794..e8baab5 100644 --- a/cpu/mips/au1x00_serial.c +++ b/cpu/mips/au1x00_serial.c @@ -76,7 +76,7 @@ void serial_setbrg (void) sd = (*sys_powerctrl 0x03) + 2; /* calulate 2x baudrate and round */ - divisorx2 = ((CFG_HZ/(sd * 16 * CONFIG_BAUDRATE))); + divisorx2 = ((CFG_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE))); if (divisorx2 0x01) divisorx2 = divisorx2 + 1; - This SF.Net email is sponsored by the Moblin Your Move Developer's challenge Build the coolest Linux based applications with Moblin SDK win great prizes Grand prize is a trip for two to an Open Source event anywhere in the world http://moblin-contest.org/redirect.php?banner_id=100url=/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] mips: When booting Linux images, add'ethaddr' and 'eth1addr' to the environment
McMullan, Jason wrote: On Sun, 2008-07-06 at 14:59 +0900, Shinya Kuribayashi wrote: Jason McMullan wrote: Add 'ethaddr' and 'eth1addr' to the Linux kernel environment if they are set in the U-Boot environment. Looking closely into linux/arch/*, I found that mips is the only architecture which supports the 'ethaddr' kernel parameter. Is this right? What I want to make sure is whether 'ethaddr' is an unusual kernel parameter or not. On our devices, the U-Boot environment is the only place the ethernet MAC address is stored. Since the infrastructure for passing environment variables up to the MIPS Linux kernel existed anyways, I decided that it would be a better plan to use that machanism than to have the kernel dig through the duplicate U-Boot environments. Thanks for the explanations. As Linux/MIPS kernel supports this parameter anyway, it's good for U-Boot to support that, too. Applied, will send to Wolfgang asap. Shinya - Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [GIT PULL] MIPS updates
Please pull MIPS update to pick up the following patch.
The following changes since commit c956717ab25c962ef49d49064dfc73f4edcba1fb:
Wolfgang Denk (1):
Merge branch 'master' of /home/wd/git/u-boot/custodians
are available in the git repository at:
git://git.denx.de/u-boot-mips.git master
Jason McMullan (1):
mips: When booting Linux images, add 'ethaddr' and 'eth1addr' to the
environment
lib_mips/bootm.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/lib_mips/bootm.c b/lib_mips/bootm.c
index f813fc5..8fe3782 100644
--- a/lib_mips/bootm.c
+++ b/lib_mips/bootm.c
@@ -54,6 +54,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc,
char *argv[],
char*commandline = getenv (bootargs);
charenv_buf[12];
int ret;
+ const char *cp;
/* find kernel entry point */
if (images-legacy_hdr_valid) {
@@ -113,6 +114,16 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int
argc, char *argv[],
sprintf (env_buf, 0x%X, (uint) (gd-bd-bi_flashsize));
linux_env_set (flash_size, env_buf);
+ cp = getenv(ethaddr);
+ if (cp != NULL) {
+ linux_env_set(ethaddr, cp);
+ }
+
+ cp = getenv(eth1addr);
+ if (cp != NULL) {
+ linux_env_set(eth1addr, cp);
+ }
+
if (!images-autostart)
return ;
-
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Re: [U-Boot-Users] Release status - things to be done
Wolfgang Denk wrote: * U-Boot mailing list traffic: 2858 05/27 wangjiankun820624 [U-Boot-Users] MIPS: about the function of the octeon_twsi_set_addr8 - for MIPS custodian I'm happy to know there is Octeon port, but I guess that's a local version provided from Cavium Networks to their customers. We don't have it in upstream, and dont' have any comments on that. 3512 06/08 Jason McMullan [U-Boot-Users] [PATCH] mips: When booting Linux images, add 'ethaddr' and 'eth1addr' to the env - for MIPS custodian Hm, I don't see any strong needs to have this. Will reply to Jason on ML, thanks. Shinya - Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH v2] net: Conditional COBJS inclusion of network drivers
Jean-Christophe PLAGNIOL-VILLARD wrote: But even if that is the case, there still might be some build breakage. I've found an error on ARM, I'll send a patch about it soon. Sorry, and thanks in advance. Best Regards, J. -- Shinya Kuribayashi NEC Electronics - Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [MIPS] Convert CPU type name into CONFIG_CPU_*
Wolfgang Denk wrote: In message [EMAIL PROTECTED] you wrote: Well, yes - if it's for compiler/assembler options only, then the board config file is not the correct place for this. I don't think so because 1) CPU type is not board-dependent, and 2) the board config file is not board-specific file, but system config file. CPU type is reasonably one of system configuration, IMO. I cannot follow you here. Especially I have no idea what you mean by system config file. To make sure we use the same terms: THe board config file is the board specific header file include/configs/boardname.h. This file is definitely NOT the correct place to tweak compiler and/or assembler options (not to mention that I don't see how this would be done). I _guess_ you might be referring to the cpu/*/config.mk files, but then the term _board_ config file is wrong. Sorry for confusion. I see all the aboves. P.S. I decided to defer this patch due to some reason. That's another story and will inform the list later. Since I haven't heard again about this I assume this is for the next merge window (or even later). Is this assumption correct, Correct. Shinya - Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH v2] net: Conditional COBJS inclusion of network drivers
Wolfgang Denk wrote: Hm... Are you absolutely sure your changes, especially the CONFIG_CMD_NET and even more the CONFIG_NET_MULTI related ones, do not cause any trouble on any systems? [...] It seems not obvious to me that your change is really harmless, or tested. Could you please comment? Carefully reviewed as much as I could, but yes it's not fully tested. I only did some build tests before patch submission. I expect all board config files, which have one of the existing ethernet driver config, already have CONFIG_CMD_NET and CONFIG_NET_MULTI, too. But even if that is the case, there still might be some build breakage. One of possible down sides of this change, upcomming ports or fully new ports might encounter build failures due to missing symbols caused by the lacks of libnet.a, command/cmd_bdinfo.o or something. [ this could be easily fixed (and must be fixed at the end). ] Avoiding unnecessary build failures like this, hence prefer the tight coupling of net|driver|command configs, please revert the patch. Patch seems already applied to upstream contrary to Wolfgang's comment. Shinya - Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] mips: When booting Linux images, add 'ethaddr' and 'eth1addr' to the environment
Jason McMullan wrote: Add 'ethaddr' and 'eth1addr' to the Linux kernel environment if they are set in the U-Boot environment. I missed this mail, sorry for my late reply. Patch itself looks correct, but let me confirm. Looking closely into linux/arch/*, I found that mips is the only architecture which supports the 'ethaddr' kernel parameter. Is this right? What I want to make sure is whether 'ethaddr' is an unusual kernel parameter or not. I think it's possible to probe MAC address(es) on kernel side, and it's common practice IMO. [ if not so, Linux couldn't work without suitable bootldrs which can pass the 'ethaddr' parameter. It's inconvenient, at least for me. ] However, I don't have strong opinions on this matter. If you still have troubles without this change, or can't probe MAC addresses by Kernel due to some reason, I'll apply the patch. Comments? Shinya - Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] mips: Bring over optimized memset() routine from Linux.
Shinya Kuribayashi wrote: +andia1, 0xff/* spread fillword */ +LONG_SLLt1, a1, 8 +or a1, t1 +LONG_SLLt1, a1, 16 +#if LONGSIZE == 8 +or a1, t1 +LONG_SLLt1, a1, 32 +#endif +or a1, t1 +1: + +FEXPORT(__bzero) +sltiu t0, a2, LONGSIZE/* very small region? */ +bnezt0, .Lsmall_memset + andi t0, a0, LONGMASK/* aligned? */ ^ [further part snipped] Please fix wrong indentations with proper tabs. I know this is exactly the same as Linux's memset, but we prefer to fix it correctly in U-Boot. I found that above is an intended space to indicate that the instruction is in the delay slot. I think it's probably a good old convention in MIPS assembly programming, and would like to leave it as it is, IMHO. Anyway, sorry for my ignorance and please ignore my comments on this. -- Shinya Kuribayashi NEC Electronics - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] mips: Bring over optimized memset() routine from Linux.
Hi Jason, Jason McMullan wrote: This commit pulls over the memset() MIPS routine from Linux 2.6.26, which provides a 10x to 20x speedup over the generic byte-at-a-time routine. This is especially useful on platforms with manual ECC scrubbing, that require all of memory to be written at least once after a power cycle. --- include/asm-mips/string.h |2 +- lib_mips/Makefile |2 +- lib_mips/memset.S | 174 + 3 files changed, 176 insertions(+), 2 deletions(-) create mode 100644 lib_mips/memset.S IIRC, Linux's memset relies on AdEL/AdES exceptions. We have Status.EXL enabled, but don't have proper exception handlers, yet. So my question is does this code always works expectedly, or works with some alignment restriction? And some nitpickings. See below. diff --git a/lib_mips/memset.S b/lib_mips/memset.S new file mode 100644 index 000..f1c07d7 --- /dev/null +++ b/lib_mips/memset.S @@ -0,0 +1,174 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + * Copyright (C) 1998, 1999, 2000 by Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2007 Maciej W. Rozycki + */ +#include asm/asm.h +//#include asm/asm-offsets.h Please remove unused #include. Even '#if 0'-ing is not allowed in U-Boot policy. +#include asm/regdef.h + +#if LONGSIZE == 4 +#define LONG_S_L swl +#define LONG_S_R swr +#else +#define LONG_S_L sdl +#define LONG_S_R sdr +#endif + +#define EX(insn,reg,addr,handler)\ +9: insnreg, addr; \ + .section __ex_table,a;\ + PTR 9b, handler;\ + .previous + + .macro f_fill64 dst, offset, val, fixup + EX(LONG_S, \val, (\offset + 0 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 1 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 2 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 3 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 4 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 5 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 6 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 7 * LONGSIZE)(\dst), \fixup) +#if LONGSIZE == 4 + EX(LONG_S, \val, (\offset + 8 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 9 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 10 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 11 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 12 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 13 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 14 * LONGSIZE)(\dst), \fixup) + EX(LONG_S, \val, (\offset + 15 * LONGSIZE)(\dst), \fixup) +#endif + .endm + +/* + * memset(void *s, int c, size_t n) + * + * a0: start of area to clear + * a1: char to fill with + * a2: size of area to clear + */ + .setnoreorder + .align 5 +LEAF(memset) + beqza1, 1f + move v0, a0 /* result */ ^ + andia1, 0xff/* spread fillword */ + LONG_SLLt1, a1, 8 + or a1, t1 + LONG_SLLt1, a1, 16 +#if LONGSIZE == 8 + or a1, t1 + LONG_SLLt1, a1, 32 +#endif + or a1, t1 +1: + +FEXPORT(__bzero) + sltiu t0, a2, LONGSIZE/* very small region? */ + bnezt0, .Lsmall_memset + andi t0, a0, LONGMASK/* aligned? */ ^ [further part snipped] Please fix wrong indentations with proper tabs. I know this is exactly the same as Linux's memset, but we prefer to fix it correctly in U-Boot. [ I used to do like you did, but changed my mind. Now I think this is better practice. Incoherent indentations with Linux is not a big deal IMO. Just diff -w option blows them away. ] Thanks in advance, -- Shinya Kuribayashi NEC Electronics - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] Add mechanisms for CPU and board-specific Ethernet initialization
Ben Warren wrote: @@ -165,6 +171,10 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_init(); #endif + /* Try CPU-specific initialization first. If it fails or isn't + * present, call the board-specific initialization */ + if (cpu_eth_init(bis) 0 ) Nitpicking: No space before ) please. Huh, don't know how I missed that one. + board_eth_init(bis); Shouldn't this be the other way around? + if (board_eth_init(bis) 0) + eth_eth_init(bis); So that the board init routine can overwrite the cpu init version. Yeah, I think you're right. If board_eth_init() exists, it gets highest priority. Just wondered, does that mean we could only have either cpu_eth_init or board_eth_init at a time? - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] Add mechanisms for CPU and board-specific Ethernet initialization
Stefan Roese wrote: On Tuesday 10 June 2008, Shinya Kuribayashi wrote: Shouldn't this be the other way around? + if (board_eth_init(bis) 0) + eth_eth_init(bis); So that the board init routine can overwrite the cpu init version. Yeah, I think you're right. If board_eth_init() exists, it gets highest priority. Just wondered, does that mean we could only have either cpu_eth_init or board_eth_init at a time? Not really. board_eth_init() could call cpu_eth_init() if necessary. Hm. What is cpu_eth_init for then? Just board_eth_init(bis); seems to be enough for me. I also wonder where is the best place to have cpu_eth_init? I'm not going to argue with you, I'm just thinking about my targets. One of my targets has internal ethernet MAC, and its evaluation board has an on-board external PCI NIC. Another target has internal MAC, but doesn't have PCI NIC. I thought it'll be something like cpu_eth_init(bis); board_eth_init(bis); But again, I don't have strong opinions around here. Please go ahead. Thanks for your comments, Shinya - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 10/10] net: Conditional COBJS inclusino of remainings
Ben Warren wrote: diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index 68901cd..cb21925 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -47,8 +47,6 @@ TODO: Homerun NIC and longrun NIC are not functional, only internal at the #include net.h #include asm/io.h -#ifdef CONFIG_DRIVER_DM9000 - #include dm9000x.h This patch no longer applies due to other changes to the DM9000 driver. Please re-base against the net repo and resubmit. snip Ok. thanks for doing all this Makefile fixing! It's been on my to-do list but you got there first. All others apply cleanly, BTW. These patches were just for the review, not for git-am. I'll revised and submit all-in-one patch soon. Shinya - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH v2] net: Conditional COBJS inclusion of network drivers
Replace COBJS-y with appropriate driver config names.
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
Changes v2:
* Kill more CONFIG_CMD_NET and CONFIG_NET_MULTI defines from
- fsl_mcdmafec.c
- mcffec.c
- netarm_eth.c
* Revised DM9000 part against the net repo.
drivers/net/3c589.c|5 ---
drivers/net/Makefile | 66 ++--
drivers/net/bcm570x.c |5 ---
drivers/net/cs8900.c |8 -
drivers/net/dc2114x.c |6
drivers/net/dm9000x.c |3 --
drivers/net/e1000.c|5 ---
drivers/net/eepro100.c |5 ---
drivers/net/enc28j60.c |3 --
drivers/net/fsl_mcdmafec.c |5 ---
drivers/net/inca-ip_sw.c |5 ---
drivers/net/ks8695eth.c|4 ---
drivers/net/lan91c96.c |9 --
drivers/net/macb.c |5 ---
drivers/net/mcffec.c |7 -
drivers/net/natsemi.c |5 ---
drivers/net/netarm_eth.c |8 -
drivers/net/netconsole.c |5 ---
drivers/net/ns7520_eth.c |5 ---
drivers/net/ns8382x.c |5 ---
drivers/net/ns9750_eth.c |4 ---
drivers/net/pcnet.c|4 ---
drivers/net/plb2800_eth.c |6
drivers/net/rtl8019.c |8 -
drivers/net/rtl8139.c |4 ---
drivers/net/rtl8169.c |5 ---
drivers/net/s3c4510b_eth.c |5 ---
drivers/net/smc9.c |3 --
drivers/net/smc911x.c |5 ---
drivers/net/tigon3.c |5 +--
drivers/net/tsec.c |3 --
drivers/net/tsi108_eth.c |5 ---
drivers/net/uli526x.c |4 ---
drivers/net/vsc7385.c |5 ---
34 files changed, 34 insertions(+), 201 deletions(-)
diff --git a/drivers/net/3c589.c b/drivers/net/3c589.c
index 3f1e770..0cf8dff 100644
--- a/drivers/net/3c589.c
+++ b/drivers/net/3c589.c
@@ -26,8 +26,6 @@
#include command.h
#include net.h
-#ifdef CONFIG_DRIVER_3C589
-
#include 3c589.h
@@ -514,6 +512,3 @@ int eth_send(volatile void *packet, int length) {
return length;
}
-
-
-#endif /* CONFIG_DRIVER_3C589 */
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 5b031c9..84be288 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -25,45 +25,45 @@ include $(TOPDIR)/config.mk
LIB:= $(obj)libnet.a
-COBJS-y += 3c589.o
-COBJS-y += bcm570x.o bcm570x_autoneg.o 5701rls.o
+COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
+COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
-COBJS-y += cs8900.o
-COBJS-y += dc2114x.o
-COBJS-y += dm9000x.o
-COBJS-y += e1000.o
-COBJS-y += eepro100.o
-COBJS-y += enc28j60.o
-COBJS-y += fsl_mcdmafec.o
+COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o
+COBJS-$(CONFIG_TULIP) += dc2114x.o
+COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
+COBJS-$(CONFIG_E1000) += e1000.o
+COBJS-$(CONFIG_EEPRO100) += eepro100.o
+COBJS-$(CONFIG_ENC28J60) += enc28j60.o
+COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o
COBJS-$(CONFIG_GRETH) += greth.o
-COBJS-y += inca-ip_sw.o
-COBJS-y += ks8695eth.o
-COBJS-y += lan91c96.o
-COBJS-y += macb.o
-COBJS-y += mcffec.o
-COBJS-y += natsemi.o
+COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
+COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
+COBJS-$(CONFIG_DRIVER_LAN91C96) += lan91c96.o
+COBJS-$(CONFIG_MACB) += macb.o
+COBJS-$(CONFIG_MCFFEC) += mcffec.o
+COBJS-$(CONFIG_NATSEMI) += natsemi.o
ifeq ($(CONFIG_DRIVER_NE2000),y)
COBJS-y += ne2000.o
COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o
endif
-COBJS-y += netarm_eth.o
-COBJS-y += netconsole.o
-COBJS-y += ns7520_eth.o
-COBJS-y += ns8382x.o
-COBJS-y += ns9750_eth.o
-COBJS-y += pcnet.o
-COBJS-y += plb2800_eth.o
-COBJS-y += rtl8019.o
-COBJS-y += rtl8139.o
-COBJS-y += rtl8169.o
-COBJS-y += s3c4510b_eth.o
-COBJS-y += smc9.o
-COBJS-y += smc911x.o
-COBJS-y += tigon3.o
-COBJS-y += tsec.o
-COBJS-y += tsi108_eth.o
-COBJS-y += uli526x.o
-COBJS-y += vsc7385.o
+COBJS-$(CONFIG_DRIVER_NETARMETH) += netarm_eth.o
+COBJS-$(CONFIG_NETCONSOLE) += netconsole.o
+COBJS-$(CONFIG_DRIVER_NS7520_ETHERNET) += ns7520_eth.o
+COBJS-$(CONFIG_NS8382X) += ns8382x.o
+COBJS-$(CONFIG_DRIVER_NS9750_ETHERNET) += ns9750_eth.o
+COBJS-$(CONFIG_PCNET) += pcnet.o
+COBJS-$(CONFIG_PLB2800_ETHER) += plb2800_eth.o
+COBJS-$(CONFIG_DRIVER_RTL8019) += rtl8019.o
+COBJS-$(CONFIG_RTL8139) += rtl8139.o
+COBJS-$(CONFIG_RTL8169) += rtl8169.o
+COBJS-$(CONFIG_DRIVER_S3C4510_ETH) += s3c4510b_eth.o
+COBJS-$(CONFIG_DRIVER_SMC9) += smc9.o
+COBJS-$(CONFIG_DRIVER_SMC911X) += smc911x.o
+COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o
+COBJS-$(CONFIG_TSEC_ENET) += tsec.o
+COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o
+COBJS-$(CONFIG_ULI526X) += uli526x.o
+COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o
COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
diff --git a/drivers/net/bcm570x.c b/drivers/net/bcm570x.c
index 5ad31d1..6b28b95 100644
--- a/drivers/net/bcm570x.c
+++ b/drivers/net/bcm570x.c
@@ -6,9 +6,6
[U-Boot-Users] drivers/net/Makefile: Conditional COBJS inclusion cleanups
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
This mail contains the whole patch and diffstat.
Separated patches will follow for easy review.
drivers/net/3c589.c|5 ---
drivers/net/Makefile | 66 ++--
drivers/net/bcm570x.c |5 ---
drivers/net/cs8900.c |8 -
drivers/net/dc2114x.c |6
drivers/net/dm9000x.c |3 --
drivers/net/e1000.c|5 ---
drivers/net/eepro100.c |5 ---
drivers/net/enc28j60.c |3 --
drivers/net/fsl_mcdmafec.c |2 -
drivers/net/inca-ip_sw.c |5 ---
drivers/net/ks8695eth.c|4 --
drivers/net/lan91c96.c |9 --
drivers/net/macb.c |5 ---
drivers/net/mcffec.c |3 --
drivers/net/natsemi.c |5 ---
drivers/net/netarm_eth.c |4 --
drivers/net/netconsole.c |5 ---
drivers/net/ns7520_eth.c |5 ---
drivers/net/ns8382x.c |5 ---
drivers/net/ns9750_eth.c |4 --
drivers/net/pcnet.c|4 --
drivers/net/plb2800_eth.c |6
drivers/net/rtl8019.c |8 -
drivers/net/rtl8139.c |4 --
drivers/net/rtl8169.c |5 ---
drivers/net/s3c4510b_eth.c |5 ---
drivers/net/smc9.c |3 --
drivers/net/smc911x.c |5 ---
drivers/net/tigon3.c |5 +--
drivers/net/tsec.c |3 --
drivers/net/tsi108_eth.c |5 ---
drivers/net/uli526x.c |4 --
drivers/net/vsc7385.c |5 ---
34 files changed, 34 insertions(+), 190 deletions(-)
diff --git a/drivers/net/3c589.c b/drivers/net/3c589.c
index 3f1e770..0cf8dff 100644
--- a/drivers/net/3c589.c
+++ b/drivers/net/3c589.c
@@ -26,8 +26,6 @@
#include command.h
#include net.h
-#ifdef CONFIG_DRIVER_3C589
-
#include 3c589.h
@@ -514,6 +512,3 @@ int eth_send(volatile void *packet, int length) {
return length;
}
-
-
-#endif /* CONFIG_DRIVER_3C589 */
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 5b031c9..84be288 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -25,45 +25,45 @@ include $(TOPDIR)/config.mk
LIB:= $(obj)libnet.a
-COBJS-y += 3c589.o
-COBJS-y += bcm570x.o bcm570x_autoneg.o 5701rls.o
+COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
+COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
-COBJS-y += cs8900.o
-COBJS-y += dc2114x.o
-COBJS-y += dm9000x.o
-COBJS-y += e1000.o
-COBJS-y += eepro100.o
-COBJS-y += enc28j60.o
-COBJS-y += fsl_mcdmafec.o
+COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o
+COBJS-$(CONFIG_TULIP) += dc2114x.o
+COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
+COBJS-$(CONFIG_E1000) += e1000.o
+COBJS-$(CONFIG_EEPRO100) += eepro100.o
+COBJS-$(CONFIG_ENC28J60) += enc28j60.o
+COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o
COBJS-$(CONFIG_GRETH) += greth.o
-COBJS-y += inca-ip_sw.o
-COBJS-y += ks8695eth.o
-COBJS-y += lan91c96.o
-COBJS-y += macb.o
-COBJS-y += mcffec.o
-COBJS-y += natsemi.o
+COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
+COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
+COBJS-$(CONFIG_DRIVER_LAN91C96) += lan91c96.o
+COBJS-$(CONFIG_MACB) += macb.o
+COBJS-$(CONFIG_MCFFEC) += mcffec.o
+COBJS-$(CONFIG_NATSEMI) += natsemi.o
ifeq ($(CONFIG_DRIVER_NE2000),y)
COBJS-y += ne2000.o
COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o
endif
-COBJS-y += netarm_eth.o
-COBJS-y += netconsole.o
-COBJS-y += ns7520_eth.o
-COBJS-y += ns8382x.o
-COBJS-y += ns9750_eth.o
-COBJS-y += pcnet.o
-COBJS-y += plb2800_eth.o
-COBJS-y += rtl8019.o
-COBJS-y += rtl8139.o
-COBJS-y += rtl8169.o
-COBJS-y += s3c4510b_eth.o
-COBJS-y += smc9.o
-COBJS-y += smc911x.o
-COBJS-y += tigon3.o
-COBJS-y += tsec.o
-COBJS-y += tsi108_eth.o
-COBJS-y += uli526x.o
-COBJS-y += vsc7385.o
+COBJS-$(CONFIG_DRIVER_NETARMETH) += netarm_eth.o
+COBJS-$(CONFIG_NETCONSOLE) += netconsole.o
+COBJS-$(CONFIG_DRIVER_NS7520_ETHERNET) += ns7520_eth.o
+COBJS-$(CONFIG_NS8382X) += ns8382x.o
+COBJS-$(CONFIG_DRIVER_NS9750_ETHERNET) += ns9750_eth.o
+COBJS-$(CONFIG_PCNET) += pcnet.o
+COBJS-$(CONFIG_PLB2800_ETHER) += plb2800_eth.o
+COBJS-$(CONFIG_DRIVER_RTL8019) += rtl8019.o
+COBJS-$(CONFIG_RTL8139) += rtl8139.o
+COBJS-$(CONFIG_RTL8169) += rtl8169.o
+COBJS-$(CONFIG_DRIVER_S3C4510_ETH) += s3c4510b_eth.o
+COBJS-$(CONFIG_DRIVER_SMC9) += smc9.o
+COBJS-$(CONFIG_DRIVER_SMC911X) += smc911x.o
+COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o
+COBJS-$(CONFIG_TSEC_ENET) += tsec.o
+COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o
+COBJS-$(CONFIG_ULI526X) += uli526x.o
+COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o
COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
diff --git a/drivers/net/bcm570x.c b/drivers/net/bcm570x.c
index 5ad31d1..6b28b95 100644
--- a/drivers/net/bcm570x.c
+++ b/drivers/net/bcm570x.c
@@ -6,9 +6,6 @@
#include common.h
-#if defined(CONFIG_CMD_NET) \
-(!defined(CONFIG_NET_MULTI)) defined(CONFIG_BCM570x)
-
#ifdef CONFIG_BMW
[U-Boot-Users] [PATCH 1/10] net: Conditional COBJS inclusion of bcm570x and tigon3 modules
net: Conditional COBJS inclusion of bcm570x and tigon3 modules From: Shinya Kuribayashi [EMAIL PROTECTED] Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- drivers/net/Makefile |4 ++-- drivers/net/bcm570x.c |5 - drivers/net/tigon3.c |5 + 3 files changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 5b031c9..4274f79 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB:= $(obj)libnet.a COBJS-y += 3c589.o -COBJS-y += bcm570x.o bcm570x_autoneg.o 5701rls.o +COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o COBJS-y += cs8900.o COBJS-y += dc2114x.o @@ -59,7 +59,7 @@ COBJS-y += rtl8169.o COBJS-y += s3c4510b_eth.o COBJS-y += smc9.o COBJS-y += smc911x.o -COBJS-y += tigon3.o +COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o COBJS-y += tsec.o COBJS-y += tsi108_eth.o COBJS-y += uli526x.o diff --git a/drivers/net/bcm570x.c b/drivers/net/bcm570x.c index 5ad31d1..6b28b95 100644 --- a/drivers/net/bcm570x.c +++ b/drivers/net/bcm570x.c @@ -6,9 +6,6 @@ #include common.h -#if defined(CONFIG_CMD_NET) \ -(!defined(CONFIG_NET_MULTI)) defined(CONFIG_BCM570x) - #ifdef CONFIG_BMW #include mpc824x.h #endif @@ -1599,5 +1596,3 @@ PQQ_ENTRY QQ_GetTail (PQQ_CONTAINER pQueue, unsigned int Idx) return pQueue-Array[Idx]; } - -#endif diff --git a/drivers/net/tigon3.c b/drivers/net/tigon3.c index 5f6a4ec..ab448b0 100644 --- a/drivers/net/tigon3.c +++ b/drivers/net/tigon3.c @@ -12,8 +12,7 @@ /**/ #include common.h #include asm/types.h -#if defined(CONFIG_CMD_NET) !defined(CONFIG_NET_MULTI) \ - defined(CONFIG_TIGON3) + #ifdef CONFIG_BMW #include mpc824x.h #endif @@ -5695,5 +5694,3 @@ LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, } return LM_STATUS_SUCCESS; } - -#endif - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 2/10] net: Conditional COBJS inclusion of Realtek modules
net: Conditional COBJS inclusion of Realtek modules From: Shinya Kuribayashi [EMAIL PROTECTED] Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- drivers/net/Makefile |6 +++--- drivers/net/rtl8019.c |8 drivers/net/rtl8139.c |4 drivers/net/rtl8169.c |5 - 4 files changed, 3 insertions(+), 20 deletions(-) diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 4274f79..6413bb1 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -53,9 +53,9 @@ COBJS-y += ns8382x.o COBJS-y += ns9750_eth.o COBJS-y += pcnet.o COBJS-y += plb2800_eth.o -COBJS-y += rtl8019.o -COBJS-y += rtl8139.o -COBJS-y += rtl8169.o +COBJS-$(CONFIG_DRIVER_RTL8019) += rtl8019.o +COBJS-$(CONFIG_RTL8139) += rtl8139.o +COBJS-$(CONFIG_RTL8169) += rtl8169.o COBJS-y += s3c4510b_eth.o COBJS-y += smc9.o COBJS-y += smc911x.o diff --git a/drivers/net/rtl8019.c b/drivers/net/rtl8019.c index 9d62cab..3ddf917 100644 --- a/drivers/net/rtl8019.c +++ b/drivers/net/rtl8019.c @@ -32,10 +32,6 @@ #include rtl8019.h #include net.h -#ifdef CONFIG_DRIVER_RTL8019 - -#if defined(CONFIG_CMD_NET) - /* packet page register access functions */ static unsigned char get_reg (unsigned int regno) @@ -271,7 +267,3 @@ extern int eth_send (volatile void *packet, int length) return 0; } - -#endif /* CONFIG_CMD_NET */ - -#endif /* CONFIG_DRIVER_RTL8019 */ diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index 097f684..4fd20ac 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -77,9 +77,6 @@ #include asm/io.h #include pci.h -#if defined(CONFIG_CMD_NET) defined(CONFIG_NET_MULTI) \ - defined(CONFIG_RTL8139) - #define RTL_TIMEOUT10 #define ETH_FRAME_LEN 1514 @@ -545,4 +542,3 @@ static void rtl_disable(struct eth_device *dev) udelay (100); /* wait 100us */ } } -#endif diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 6c4c9ff..7423bc0 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -58,9 +58,6 @@ #include asm/io.h #include pci.h -#if defined(CONFIG_CMD_NET) defined(CONFIG_NET_MULTI) \ - defined(CONFIG_RTL8169) - #undef DEBUG_RTL8169 #undef DEBUG_RTL8169_TX #undef DEBUG_RTL8169_RX @@ -887,5 +884,3 @@ int rtl8169_initialize(bd_t *bis) } return card_number; } - -#endif - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 3/10] net: Conditional COBJS inclusion of Intel modules
net: Conditional COBJS inclusion of Intel modules From: Shinya Kuribayashi [EMAIL PROTECTED] Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- drivers/net/Makefile |4 ++-- drivers/net/e1000.c|5 - drivers/net/eepro100.c |5 - 3 files changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 6413bb1..432fc10 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -31,8 +31,8 @@ COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o COBJS-y += cs8900.o COBJS-y += dc2114x.o COBJS-y += dm9000x.o -COBJS-y += e1000.o -COBJS-y += eepro100.o +COBJS-$(CONFIG_E1000) += e1000.o +COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-y += enc28j60.o COBJS-y += fsl_mcdmafec.o COBJS-$(CONFIG_GRETH) += greth.o diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index c53c226..8f0e7d5 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -44,9 +44,6 @@ tested on both gig copper and gig fiber boards #include e1000.h -#if defined(CONFIG_CMD_NET) \ -defined(CONFIG_NET_MULTI) defined(CONFIG_E1000) - #define TOUT_LOOP 10 #undef virt_to_bus @@ -3059,5 +3056,3 @@ e1000_initialize(bd_t * bis) } return 1; } - -#endif diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index 96ed271..9de0fb5 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -30,9 +30,6 @@ #undef DEBUG -#if defined(CONFIG_CMD_NET) \ -defined(CONFIG_NET_MULTI) defined(CONFIG_EEPRO100) - /* Ethernet chip registers. */ #define SCBStatus 0 /* Rx/Command Unit Status *Word* */ @@ -944,5 +941,3 @@ static void read_hw_addr (struct eth_device *dev, bd_t * bis) #endif } } - -#endif - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 4/10] net: Conditional COBJS inclusion of INCA-IP switch
net: Conditional COBJS inclusion of INCA-IP switch From: Shinya Kuribayashi [EMAIL PROTECTED] Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- drivers/net/Makefile |2 +- drivers/net/inca-ip_sw.c |5 - 2 files changed, 1 insertions(+), 6 deletions(-) diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 432fc10..35c1490 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -36,7 +36,7 @@ COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-y += enc28j60.o COBJS-y += fsl_mcdmafec.o COBJS-$(CONFIG_GRETH) += greth.o -COBJS-y += inca-ip_sw.o +COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o COBJS-y += ks8695eth.o COBJS-y += lan91c96.o COBJS-y += macb.o diff --git a/drivers/net/inca-ip_sw.c b/drivers/net/inca-ip_sw.c index a079b60..d852a15 100644 --- a/drivers/net/inca-ip_sw.c +++ b/drivers/net/inca-ip_sw.c @@ -26,9 +26,6 @@ #include common.h -#if defined(CONFIG_CMD_NET) \ -defined(CONFIG_NET_MULTI) defined(CONFIG_INCA_IP_SWITCH) - #include malloc.h #include net.h #include asm/inca-ip.h @@ -813,5 +810,3 @@ Fail: return -1; } #endif /* CONFIG_INCA_IP_SWITCH_AMDIX */ - -#endif - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 5/10] net: Conditional COBJS inclusion of National Semiconductor modules
net: Conditional COBJS inclusion of National Semiconductor modules From: Shinya Kuribayashi [EMAIL PROTECTED] Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- drivers/net/Makefile |4 ++-- drivers/net/natsemi.c |5 - drivers/net/ns8382x.c |5 - 3 files changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 35c1490..57c31cb 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -41,7 +41,7 @@ COBJS-y += ks8695eth.o COBJS-y += lan91c96.o COBJS-y += macb.o COBJS-y += mcffec.o -COBJS-y += natsemi.o +COBJS-$(CONFIG_NATSEMI) += natsemi.o ifeq ($(CONFIG_DRIVER_NE2000),y) COBJS-y += ne2000.o COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o @@ -49,7 +49,7 @@ endif COBJS-y += netarm_eth.o COBJS-y += netconsole.o COBJS-y += ns7520_eth.o -COBJS-y += ns8382x.o +COBJS-$(CONFIG_NS8382X) += ns8382x.o COBJS-y += ns9750_eth.o COBJS-y += pcnet.o COBJS-y += plb2800_eth.o diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c index a523959..4aee048 100644 --- a/drivers/net/natsemi.c +++ b/drivers/net/natsemi.c @@ -56,9 +56,6 @@ #include asm/io.h #include pci.h -#if defined(CONFIG_CMD_NET) \ -defined(CONFIG_NET_MULTI) defined(CONFIG_NATSEMI) - /* defines */ #define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/ @@ -878,5 +875,3 @@ natsemi_disable(struct eth_device *dev) /* Restore PME enable bit */ OUTL(dev, SavedClkRun, ClkRun); } - -#endif diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c index c807dd4..0b9a3ae 100644 --- a/drivers/net/ns8382x.c +++ b/drivers/net/ns8382x.c @@ -56,9 +56,6 @@ #include asm/io.h #include pci.h -#if defined(CONFIG_CMD_NET) \ -defined(CONFIG_NET_MULTI) defined(CONFIG_NS8382X) - /* defines */ #define DSIZE 0x0FFF #define ETH_ALEN 6 @@ -859,5 +856,3 @@ ns8382x_disable(struct eth_device *dev) /* Restore PME enable bit */ OUTL(dev, SavedClkRun, ClkRun); } - -#endif - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 6/10] net: Conditional COBJS inclusion of NET+ARM modules
net: Conditional COBJS inclusion of NET+ARM modules
From: Shinya Kuribayashi [EMAIL PROTECTED]
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
drivers/net/Makefile |6 +++---
drivers/net/netarm_eth.c |4
drivers/net/ns7520_eth.c |5 -
drivers/net/ns9750_eth.c |4
4 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 57c31cb..70a6dde 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -46,11 +46,11 @@ ifeq ($(CONFIG_DRIVER_NE2000),y)
COBJS-y += ne2000.o
COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o
endif
-COBJS-y += netarm_eth.o
+COBJS-$(CONFIG_DRIVER_NETARMETH) += netarm_eth.o
COBJS-y += netconsole.o
-COBJS-y += ns7520_eth.o
+COBJS-$(CONFIG_DRIVER_NS7520_ETHERNET) += ns7520_eth.o
COBJS-$(CONFIG_NS8382X) += ns8382x.o
-COBJS-y += ns9750_eth.o
+COBJS-$(CONFIG_DRIVER_NS9750_ETHERNET) += ns9750_eth.o
COBJS-y += pcnet.o
COBJS-y += plb2800_eth.o
COBJS-$(CONFIG_DRIVER_RTL8019) += rtl8019.o
diff --git a/drivers/net/netarm_eth.c b/drivers/net/netarm_eth.c
index ecf45dc..6b635bb 100644
--- a/drivers/net/netarm_eth.c
+++ b/drivers/net/netarm_eth.c
@@ -22,8 +22,6 @@
#include common.h
-
-#ifdef CONFIG_DRIVER_NETARMETH
#include command.h
#include net.h
#include netarm_eth.h
@@ -354,5 +352,3 @@ extern int eth_send (volatile void *packet, int length)
}
#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_NETARMETH */
diff --git a/drivers/net/ns7520_eth.c b/drivers/net/ns7520_eth.c
index a5a20df..37411df 100644
--- a/drivers/net/ns7520_eth.c
+++ b/drivers/net/ns7520_eth.c
@@ -15,8 +15,6 @@
#include common.h
-#if defined(CONFIG_DRIVER_NS7520_ETHERNET)
-
#include net.h /* NetSendPacket */
#include asm/arch/netarm_registers.h
#include asm/arch/netarm_dma_module.h
@@ -846,14 +844,11 @@ extern int ns7520_miiphy_write(char *devname, unsigned
char const addr,
return (ret);
}
#endif /* defined(CONFIG_MII) */
-#endif /* CONFIG_DRIVER_NS7520_ETHERNET */
int ns7520_miiphy_initialize(bd_t *bis)
{
-#if defined(CONFIG_DRIVER_NS7520_ETHERNET)
#if defined(CONFIG_MII)
miiphy_register(ns7520phy, ns7520_miiphy_read, ns7520_miiphy_write);
#endif
-#endif
return 0;
}
diff --git a/drivers/net/ns9750_eth.c b/drivers/net/ns9750_eth.c
index 067ff8e..0559710 100644
--- a/drivers/net/ns9750_eth.c
+++ b/drivers/net/ns9750_eth.c
@@ -37,8 +37,6 @@
#include ns9750_eth.h/* for Ethernet and PHY */
-#ifdef CONFIG_DRIVER_NS9750_ETHERNET
-
/* some definition to make transistion to linux easier */
#define NS9750_DRIVER_NAME eth
@@ -793,5 +791,3 @@ static unsigned int ns9750_mii_poll_busy (void)
return unTimeout;
}
-
-#endif /* CONFIG_DRIVER_NS9750_ETHERNET */
-
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[U-Boot-Users] [GIT PULL] MIPS updates
Please pull MIPS updates to pick up the following patches.
The following changes since commit 8155efbd7ae9c65564ca98affe94631d612ae088:
Wolfgang Denk (1):
Merge branch 'master' of ssh://mercury/home/wd/git/u-boot/master
are available in the git repository at:
git://git.denx.de/u-boot-mips.git master
Shinya Kuribayashi (8):
[MIPS] lib_mips/time.c: Replace CP0 access functions with existing macros
[MIPS] lib_mips/time.c: Fix udelay
[MIPS] lib_mips/time.c: Fix CP0 count register usage and timer routines
[MIPS] Kill unused version.h inclusions
[MIPS] mips_config.mk: Misc fixes
[MIPS] Update asm/addrspace.h header
[MIPS] Rename Alchemy processor configs into CONFIGO_SOC_*
[MIPS] cpu/mips/Makefile: Split [CS]OBJS onto separate lines
board/dbau1x00/lowlevel_init.S |1 -
board/gth2/gth2.c |2 +-
board/gth2/lowlevel_init.S |1 -
board/incaip/incaip.c |2 +-
board/incaip/lowlevel_init.S|1 -
board/pb1x00/lowlevel_init.S|1 -
board/purple/lowlevel_init.S|1 -
board/purple/purple.c | 14 ++--
board/qemu-mips/lowlevel_init.S |1 -
board/tb0229/lowlevel_init.S|1 -
board/tb0229/vr4131-pci.c | 56 ++--
cpu/mips/Makefile | 15 ++--
cpu/mips/asc_serial.c |3 -
cpu/mips/au1x00_eth.c | 12 +--
cpu/mips/au1x00_serial.c|4 -
cpu/mips/au1x00_usb_ohci.c |2 +-
cpu/mips/cache.S|7 +-
cpu/mips/incaip_wdt.S |1 -
cpu/mips/start.S|1 -
drivers/net/inca-ip_sw.c| 28 +++---
include/asm-mips/addrspace.h| 173 +--
include/asm-mips/au1x00.h |6 +-
include/asm-mips/io.h |4 +-
include/configs/dbau1x00.h | 14 ++--
include/configs/gth2.h |8 +-
include/configs/incaip.h|4 +-
include/configs/pb1x00.h| 12 ++-
include/configs/purple.h|3 +-
include/configs/qemu-mips.h |4 +-
include/configs/tb0229.h|4 +-
lib_mips/time.c | 57 ++---
mips_config.mk |7 +-
32 files changed, 263 insertions(+), 187 deletions(-)
diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S
index 27b51f7..13e6bfc 100644
--- a/board/dbau1x00/lowlevel_init.S
+++ b/board/dbau1x00/lowlevel_init.S
@@ -1,7 +1,6 @@
/* Memory sub-system initialization code */
#include config.h
-#include version.h
#include asm/regdef.h
#include asm/au1x00.h
#include asm/mipsregs.h
diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c
index 9bc4d3f..3e56678 100644
--- a/board/gth2/gth2.c
+++ b/board/gth2/gth2.c
@@ -36,7 +36,7 @@ static int wdi_status = 0;
#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
-#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096))
+#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096))
void inline log_serial_char(char c){
char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S
index bf615c1..4c4f0eb 100644
--- a/board/gth2/lowlevel_init.S
+++ b/board/gth2/lowlevel_init.S
@@ -1,7 +1,6 @@
/* Memory sub-system initialization code */
#include config.h
-#include version.h
#include asm/regdef.h
#include asm/au1x00.h
#include asm/mipsregs.h
diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
index c624b3d..dc51373 100644
--- a/board/incaip/incaip.c
+++ b/board/incaip/incaip.c
@@ -63,7 +63,7 @@ long int initdram(int board_type)
/* Can't probe for RAM size unless we are running from Flash.
*/
- if (PHYSADDR(our_address) PHYSADDR(PHYS_FLASH_1))
+ if (CPHYSADDR(our_address) CPHYSADDR(PHYS_FLASH_1))
{
return max_sdram_size();
}
diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S
index 08f7f21..fe525ec 100644
--- a/board/incaip/lowlevel_init.S
+++ b/board/incaip/lowlevel_init.S
@@ -23,7 +23,6 @@
*/
#include config.h
-#include version.h
#include asm/regdef.h
diff --git a/board/pb1x00/lowlevel_init.S b/board/pb1x00/lowlevel_init.S
index 98bb394..b145e43 100644
--- a/board/pb1x00/lowlevel_init.S
+++ b/board/pb1x00/lowlevel_init.S
@@ -1,7 +1,6 @@
/* Memory sub-system initialization code */
#include config.h
-#include version.h
#include asm/regdef.h
#include asm/au1x00.h
#include asm/mipsregs.h
diff --git a/board/purple/lowlevel_init.S b/board/purple/lowlevel_init.S
index b9d03fc..1bd3edb 100644
--- a/board/purple/lowlevel_init.S
+++ b/board/purple/lowlevel_init.S
@@ -23,7 +23,6 @@
*/
#include config.h
-#include version.h
#include asm/regdef.h
#define MC_IOGP0xBF800800
diff --git a/board/purple/purple.c b/board/purple/purple.c
index 89cb906..72d5734 100644
--- a/board/purple/purple.c
+++ b/board/purple/purple.c
@@ -85,16 +85,16 @@ static void
Re: [U-Boot-Users] [PATCH 3/3][MIPS] lib_mips/time.c: Fix improper use of CFG_HZ and timer routines
Wolfgang Denk wrote:
In message [EMAIL PROTECTED] you wrote:
My udelay is already global-variable-free. And as for cycles_per_jiffy
and expirelo, we could make it work like this:
...
-static unsigned int expirelo;
+static unsigned long cycles_per_jiffy = (CONFIG_MIPS_TIMER_FREQ + CFG_HZ /
2) / CFG_HZ;
If it's a constant anyway - then why do we need a variable for it?
Of course, we don't. That was for easy review, will fix.
But I have no clue about timestamp.
Maybe there is a register that is (1) common to all or at least most
of the supported processors we could use for that? If not, then we
I'm afraid there's not such register left.
probably have to use the initial data structure for this.
Looked around board_init_r, and it seems there is no {set,get}_timer
user there. I'm going to leave timestamp as it is at this moment.
Shinya
-
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Re: [U-Boot-Users] [PATCH 3/3][MIPS] lib_mips/time.c: Fix improper use of CFG_HZ and timer routines
probably have to use the initial data structure for this.
Looked around board_init_r, and it seems there is no {set,get}_timer
user there. I'm going to leave timestamp as it is at this moment.
s/board_init_r/board_init_f/
-
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Re: [U-Boot-Users] [PATCH] mips: Add an 'include/asm/errno.h', like all other architectures
Jean-Christophe PLAGNIOL-VILLARD wrote: On 14:09 Tue 27 May , Jason McMullan wrote: All other u-boot architectures have an include/asm/errno.h, so this change adds it to the mips include/asm-mips headers also. Stolen from Linux 2.6.25. Signed-off-by: Jason McMullan [EMAIL PROTECTED] --- include/asm-mips/errno.h | 143 ++ 1 files changed, 143 insertions(+), 0 deletions(-) create mode 100644 include/asm-mips/errno.h Applied, thanks. diff --git a/include/asm-mips/errno.h b/include/asm-mips/errno.h new file mode 100644 index 000..1665a63 --- /dev/null +++ b/include/asm-mips/errno.h @@ -0,0 +1,143 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle + */ +#ifndef _ASM_MIPS_ERRNO_H +#define _ASM_MIPS_ERRNO_H + +/* + * These first 34 error codes are from Linux 2.6, asm-generic/errno-base.h + */ as it said here, is not a good think to add an asm-generis subdir to this king code intead of duplicate it for all arch. That's fine with me. Shinya - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 3/3 v2][MIPS] lib_mips/time.c: Fix CP0 count register usage and timer routines
MIPS port has two problems in timer routines. One is now we assume CFG_HZ equals to CP0 counter frequency, but this is wrong. CFG_HZ has to be 1000 in the U-Boot system. The other is we don't have a proper time management counter like timestamp other ARCHs have. We need the 32-bit millisecond clock counter. This patch introduces timestamp and CYCLES_PER_JIFFY. timestamp is a 32-bit non-overflowing CFG_HZ counter, and CYCLES_PER_JIFFY is the number of calculated CP0 counter cycles in a CFG_HZ. STRATEGY: * Fix improper CFG_HZ value to have 1000 * Use CFG_MIPS_TIMER_FREQ for timer counter frequency, instead. * timer_init: initialize timestamp and set up the first timer expiration. Note that we don't need to initialize CP0 count/compare registers here as they have been already zeroed out on the system reset. Leave them as they are. * get_timer: calculate how many timestamps have been passed, then return base-relative timestamp. Make sure we can easily count missed timestamps regardless of CP0 count/compare value. * get_ticks: return the current timestamp, that is get_timer(0). Most parts are from good old Linux v2.6.16 kernel. v2: - Remove FIXME comments as they turned out to be trivial. - Use CP0 compare register as a global variable for expirelo. - Kill a global variable 'cycles_per_jiffy'. Use #define CYCLES_PER_JIFFY instead. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- include/configs/dbau1x00.h |4 +++- include/configs/gth2.h |4 +++- include/configs/incaip.h|4 +++- include/configs/pb1x00.h|4 +++- include/configs/purple.h|3 ++- include/configs/qemu-mips.h |4 +++- include/configs/tb0229.h|4 +++- lib_mips/time.c | 31 +-- 8 files changed, 45 insertions(+), 13 deletions(-) diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index b2f606f..45ff1e7 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -148,7 +148,9 @@ #error Invalid CPU frequency - must be multiple of 12! #endif -#define CFG_HZ (CFG_MHZ * 100) /* FIXME causes overflow in net.c */ +#define CFG_MIPS_TIMER_FREQ(CFG_MHZ * 100) + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x8000 /* Cached addr */ diff --git a/include/configs/gth2.h b/include/configs/gth2.h index c2a50c1..23618db 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -118,7 +118,9 @@ #define CFG_MHZ500 -#define CFG_HZ (CFG_MHZ * 100) /* FIXME causes overflow in net.c */ +#define CFG_MIPS_TIMER_FREQ(CFG_MHZ * 100) + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x8000 /* Cached addr */ diff --git a/include/configs/incaip.h b/include/configs/incaip.h index 5ca00b3..2e4ee66 100644 --- a/include/configs/incaip.h +++ b/include/configs/incaip.h @@ -118,7 +118,9 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ (incaip_get_cpuclk() / 2) +#define CFG_MIPS_TIMER_FREQ(incaip_get_cpuclk() / 2) + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x8000 diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 810e0f0..181cd11 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -81,7 +81,9 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ 39600 /* FIXME causes overflow in net.c */ +#define CFG_MIPS_TIMER_FREQ39600 + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x8000 /* Cached addr */ diff --git a/include/configs/purple.h b/include/configs/purple.h index 1be4e05..ef92637 100644 --- a/include/configs/purple.h +++ b/include/configs/purple.h @@ -114,7 +114,8 @@ #defineCFG_PROMPT PURPLE # /* Monitor Command Prompt*/ #defineCFG_CBSIZE 256 /* Console I/O Buffer Size */ #defineCFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_HZ (CPU_CLOCK_RATE/2) +#define CFG_MIPS_TIMER_FREQ(CPU_CLOCK_RATE/2) +#define CFG_HZ 1000 #defineCFG_MAXARGS 16 /* max number of command args*/ #defineCFG_LOAD_ADDR 0x8050 /* default load address */ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index d6bcc8e..3dfd218 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -120,7 +120,9 @@ #define CFG_MHZ132 -#define CFG_HZ (CFG_MHZ * 100) +#define CFG_MIPS_TIMER_FREQ(CFG_MHZ * 100) + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x8000 /* Cached addr */ diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h index dadf5d3..fc2357d 100644 --- a/include
[U-Boot-Users] [PATCH v2][MIPS] Update asm/addrspace.h header
v2: drivers/net/inca-ip_sw.c: Fix build errors caused by CPHYSADDR
[MIPS] Update asm/addrspace.h header
From: Shinya Kuribayashi [EMAIL PROTECTED]
- Fix traditional KSEG names
- Replace PHYSADDR with CPHYSADDR
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
board/gth2/gth2.c|2 -
board/incaip/incaip.c|2 -
board/purple/purple.c| 14 ++--
board/tb0229/vr4131-pci.c| 56 +++---
cpu/mips/cache.S |6 +-
drivers/net/inca-ip_sw.c | 28 ---
include/asm-mips/addrspace.h | 167 +++---
include/asm-mips/io.h|4 +
8 files changed, 181 insertions(+), 98 deletions(-)
diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c
index 9bc4d3f..3e56678 100644
--- a/board/gth2/gth2.c
+++ b/board/gth2/gth2.c
@@ -36,7 +36,7 @@ static int wdi_status = 0;
#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
-#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096))
+#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096))
void inline log_serial_char(char c){
char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
index c624b3d..dc51373 100644
--- a/board/incaip/incaip.c
+++ b/board/incaip/incaip.c
@@ -63,7 +63,7 @@ long int initdram(int board_type)
/* Can't probe for RAM size unless we are running from Flash.
*/
- if (PHYSADDR(our_address) PHYSADDR(PHYS_FLASH_1))
+ if (CPHYSADDR(our_address) CPHYSADDR(PHYS_FLASH_1))
{
return max_sdram_size();
}
diff --git a/board/purple/purple.c b/board/purple/purple.c
index 89cb906..72d5734 100644
--- a/board/purple/purple.c
+++ b/board/purple/purple.c
@@ -85,16 +85,16 @@ static void sdram_timing_init (ulong size)
while (p4 32 done == 0) {
WRITE_MC_IOGP_1;
- for (addr = KSEG1 + 0x4000;
-addr KSEG1ADDR (size);
+ for (addr = CKSEG1 + 0x4000;
+addr CKSEG1ADDR (size);
addr = addr + 4) {
*(uint *) addr = 0xaa55aa55;
}
pass = 1;
- for (addr = KSEG1 + 0x4000;
-addr KSEG1ADDR (size) pass == 1;
+ for (addr = CKSEG1 + 0x4000;
+addr CKSEG1ADDR (size) pass == 1;
addr = addr + 4) {
if (*(uint *) addr != 0xaa55aa55)
pass = 0;
@@ -138,7 +138,7 @@ long int initdram(int board_type)
ulong size= (1 (rows + cols)) * (1 (dw - 1)) * CFG_NB;
void (* sdram_init) (ulong);
- sdram_init = (void (*)(ulong)) KSEG0ADDR(sdram_timing_init);
+ sdram_init = (void (*)(ulong)) CKSEG0ADDR(sdram_timing_init);
sdram_init(0x1);
@@ -260,14 +260,14 @@ void copy_code (ulong dest_addr)
/* flush caches
*/
- start = KSEG0;
+ start = CKSEG0;
end = start + CFG_DCACHE_SIZE;
while(start end) {
cache_unroll(start,Index_Writeback_Inv_D);
start += CFG_CACHELINE_SIZE;
}
- start = KSEG0;
+ start = CKSEG0;
end = start + CFG_ICACHE_SIZE;
while(start end) {
cache_unroll(start,Index_Invalidate_I);
diff --git a/board/tb0229/vr4131-pci.c b/board/tb0229/vr4131-pci.c
index 0ee4bf3..4c91923 100644
--- a/board/tb0229/vr4131-pci.c
+++ b/board/tb0229/vr4131-pci.c
@@ -13,34 +13,34 @@
#include pci.h
#include asm/addrspace.h
-#define VR4131_PCIMMAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c00)
-#define VR4131_PCIMMAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c04)
-#define VR4131_PCITAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c08)
-#define VR4131_PCITAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c0c)
-#define VR4131_PCIMIOAWREG (volatile unsigned int*)(KSEG1 + 0x0f000c10)
-#define VR4131_PCICONFDREG (volatile unsigned int*)(KSEG1 + 0x0f000c14)
-#define VR4131_PCICONFAREG (volatile unsigned int*)(KSEG1 + 0x0f000c18)
-#define VR4131_PCIMAILREG (volatile unsigned int*)(KSEG1 + 0x0f000c1c)
-#define VR4131_BUSERRADREG (volatile unsigned int*)(KSEG1 + 0x0f000c24)
-#define VR4131_INTCNTSTAREG(volatile unsigned int*)(KSEG1 + 0x0f000c28)
-#define VR4131_PCIEXACCREG (volatile unsigned int*)(KSEG1 + 0x0f000c2c)
-#define VR4131_PCIRECONTREG(volatile unsigned int*)(KSEG1 + 0x0f000c30)
-#define VR4131_PCIENREG(volatile unsigned int*)(KSEG1 +
0x0f000c34)
-#define VR4131_PCICLKSELREG(volatile unsigned int*)(KSEG1 + 0x0f000c38)
-#define VR4131_PCITRDYREG (volatile unsigned
[U-Boot-Users] [GIT PULL] MIPS updates (updated)
Dear Wolfgang, please pull MIPS updates. This pull request also contains the previous MIPS updates (requested on 2008-05-23) as it's not merged into master. The following changes since commit 1f1554841a4c8e069d331176f0c3059fb2bb8280: Wolfgang Denk (1): Merge branch 'master' of /home/wd/git/u-boot/custodians are available in the git repository at: git://git.denx.de/u-boot-mips.git master Jason McMullan (3): [MIPS] lib_mips/board.c: Add nand_init mips: If CONFIG_CMD_SPI is defined, call spi_init() mips: Add an 'include/asm/errno.h', like all other architectures Shinya Kuribayashi (11): [MIPS] asm/mipsregs.h: CodinygStyle cleanups [MIPS] asm/mipsregs.h: Update register / bit field definitions [MIPS] asm/mipsregs.h: Update coprocessor register access macros [MIPS] lib_mips/time.c: Replace CP0 access functions with existing macros [MIPS] lib_mips/time.c: Fix udelay [MIPS] lib_mips/time.c: Fix CP0 count register usage and timer routines [MIPS] Kill unused version.h inclusions [MIPS] mips_config.mk: Misc fixes [MIPS] Update asm/addrspace.h header [MIPS] Rename Alchemy processor configs into CONFIGO_SOC_* [MIPS] cpu/mips/Makefile: Split [CS]OBJS onto separate lines board/dbau1x00/dbau1x00.c |2 +- board/dbau1x00/lowlevel_init.S |1 - board/gth2/gth2.c |4 +- board/gth2/lowlevel_init.S |1 - board/incaip/incaip.c |2 +- board/incaip/lowlevel_init.S|1 - board/pb1x00/lowlevel_init.S|1 - board/pb1x00/pb1x00.c |2 +- board/purple/lowlevel_init.S|1 - board/purple/purple.c | 14 +- board/qemu-mips/lowlevel_init.S |1 - board/qemu-mips/qemu-mips.c |6 +- board/tb0229/lowlevel_init.S|1 - board/tb0229/vr4131-pci.c | 56 +- cpu/mips/Makefile | 15 +- cpu/mips/asc_serial.c |3 - cpu/mips/au1x00_eth.c | 12 +- cpu/mips/au1x00_serial.c|4 - cpu/mips/au1x00_usb_ohci.c |2 +- cpu/mips/cache.S|7 +- cpu/mips/cpu.c | 10 +- cpu/mips/incaip_wdt.S |1 - cpu/mips/start.S|1 - drivers/net/inca-ip_sw.c| 28 +- include/asm-mips/addrspace.h| 173 -- include/asm-mips/au1x00.h |6 +- include/asm-mips/errno.h| 143 include/asm-mips/io.h |4 +- include/asm-mips/mipsregs.h | 1405 +++ include/configs/dbau1x00.h | 14 +- include/configs/gth2.h |8 +- include/configs/incaip.h|4 +- include/configs/pb1x00.h| 12 +- include/configs/purple.h|3 +- include/configs/qemu-mips.h |4 +- include/configs/tb0229.h|4 +- lib_mips/board.c| 13 + lib_mips/time.c | 57 +- mips_config.mk |7 +- 39 files changed, 1541 insertions(+), 492 deletions(-) create mode 100644 include/asm-mips/errno.h - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 3/3][MIPS] lib_mips/time.c: Fix improper use of CFG_HZ and timer routines
Wolfgang Denk wrote:
Sure. We'll probably need to move timer_init to board_init_r at the end.
I'm not sure if this works. We use udelay() and friends all over the
place - a long time before that.
Hmm.
My udelay is already global-variable-free. And as for cycles_per_jiffy
and expirelo, we could make it work like this:
diff --git a/lib_mips/time.c b/lib_mips/time.c
index f6678e1..d4754e3 100644
--- a/lib_mips/time.c
+++ b/lib_mips/time.c
@@ -27,10 +27,7 @@
static unsigned long timestamp;
/* how many counter cycles in a jiffy */
-static unsigned long cycles_per_jiffy;
-
-/* expirelo is the count value for next CPU timer interrupt */
-static unsigned int expirelo;
+static unsigned long cycles_per_jiffy = (CONFIG_MIPS_TIMER_FREQ + CFG_HZ / 2)
/ CFG_HZ;
/*
* timer without interrupts
@@ -38,9 +35,6 @@ static unsigned int expirelo;
int timer_init(void)
{
- /* Calculate cache parameters. */
- cycles_per_jiffy = (CONFIG_MIPS_TIMER_FREQ + CFG_HZ / 2) / CFG_HZ;
-
/* Report the high precision timer rate for a reference. */
printf(Using %u.%03u MHz high precision timer.\n,
((CONFIG_MIPS_TIMER_FREQ + 500) / 1000) / 1000,
@@ -48,7 +42,7 @@ int timer_init(void)
/* Set up the timer for the first expiration. */
timestamp = 0;
- expirelo = read_c0_count() + cycles_per_jiffy;
+ write_c0_compare(read_c0_count() + cycles_per_jiffy);
return 0;
}
@@ -56,12 +50,13 @@ int timer_init(void)
void reset_timer(void)
{
timestamp = 0;
- expirelo = read_c0_count() + cycles_per_jiffy;
+ write_c0_compare(read_c0_count() + cycles_per_jiffy);
}
ulong get_timer(ulong base)
{
unsigned int count;
+ unsigned int expirelo = read_c0_compare();
/* Check to see if we have missed any timestamps. */
count = read_c0_count();
@@ -73,6 +68,7 @@ ulong get_timer(ulong base)
expirelo += cycles_per_jiffy;
timestamp++;
}
+ write_c0_compare(expirelo);
return (timestamp - base);
}
@@ -80,7 +76,7 @@ ulong get_timer(ulong base)
void set_timer(ulong t)
{
timestamp = t;
- expirelo = read_c0_count() + cycles_per_jiffy;
+ write_c0_compare(read_c0_count() + cycles_per_jiffy);
}
void udelay(unsigned long usec)
_
But I have no clue about timestamp.
The timer implementation should have no such restrictions as being
available only after relocation. Timers / delays are such a basic
feature that they should be available everywhere.
I'll remember that.
Shinya
-
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Re: [U-Boot-Users] [PATCH 2/2][MIPS] Add cpu_probe and cpu_report
Wolfgang Denk wrote: In message [EMAIL PROTECTED] you wrote: Probe CPU information (core type, ISA level, core features and TLB size). These info will be utilized all over the further processing. ... cpu/mips/cpu-probe.c | 754 ++ Ummm... we're adding more than 750 lines of code - for which benefit exactly? This patch is still in development, and just probes info at the moment. We will utilize it around TLB initialization, cache unrolling, .etc. But that's not yet prepared, should have postphone submission for the review. Please ignore this patch. I'll drop this patch from my queue. Sorry for noise, Shinya How much memory footprint does this code add? Best regards, Wolfgang Denk - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [MIPS] Convert CPU type name into CONFIG_CPU_*
Wolfgang Denk wrote: In message [EMAIL PROTECTED] you wrote: Adjust to the current Linux way. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] ... -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ +#define CONFIG_CPU_MIPS32_R11 /* MIPS32 CPU core */ I have to admit that I don't like this changes. We're adding a lot of fine ganularity here First of all, current CONFIG_MIPS32 defines are useless. We can even remove them. What is fine granularity for, huh? [EMAIL PROTECTED]:~/devel/u-boot.git$ grep -r CONFIG_MIPS32 . ./include/configs/qemu-mips.h:#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ ./include/configs/dbau1x00.h:#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ ./include/configs/gth2.h:#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ ./include/configs/purple.h:#define CONFIG_MIPS321 /* MIPS 5Kc CPU core*/ ./include/configs/tb0229.h:#define CONFIG_MIPS321 /* MIPS 4Kc CPU core*/ ./include/configs/pb1x00.h:#define CONFIG_MIPS321 /* MIPS32 CPU core */ ./include/configs/incaip.h:#define CONFIG_MIPS321 /* MIPS 4Kc CPU core*/ [EMAIL PROTECTED]:~/devel/u-boot.git$ [btw tb0229 is not MIPS32 at all. it's VR4131 based machine.] What exactly is the reason for all these changes? Which problem are you trying to fix? It'll be good we could have CPU type specifier so that we can utilize as a compiler/assembler optimization. And why I use CONFIG_CPU_MIPS32_R1, instead of CONFIG_CPU_MIPS32, is due to avoiding #ifdef mess. CONFIG_CPU_MIPS32 is inadequate for this use. We need _R1 or _R2. Linux is doing well with the help of Kconfig. Probably I should have fold this patch and `[MIPS] CPU-dependent compiler/assembler options for optimization' patch into one. Thought? Shinya - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 1/3][MIPS] lib_mips/time.c: Replace CP0 access functions with existing macros
Scott Wood wrote:
On Wed, May 21, 2008 at 12:53:01PM +0900, Shinya Kuribayashi wrote:
I disagree with having this structure. Basic strategy for MIPS COUNT/
COMPARE handling is, let them overflow (os should I say wrap-around) as
they are. All we need is the Delta, not the numbers of overflows.
You *do* need the full, non-overflowing counter if you want to provide
the 32-bit millisecond clock that u-boot wants. Read the recent
discussion on CFG_HZ that led to this patch.
Ok, here's my proposal. Conceptual patches for MIPS timer routines.
There might be still room for improvement, but I'd like to see something
like thease.
Just build tested. Any comments are appriciated.
Shinya
---
[MIPS] lib_mips/time.c: Replace CP0 access functions with existing macros
We already have many pre-defined CP0 access macros in asm/mipsregs.h.
This patch replaces mips_{compare,count}_set and mips_count_get with
existing macros.
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
lib_mips/time.c | 35 ---
1 files changed, 8 insertions(+), 27 deletions(-)
diff --git a/lib_mips/time.c b/lib_mips/time.c
index cd8dc72..f03f023 100644
--- a/lib_mips/time.c
+++ b/lib_mips/time.c
@@ -22,26 +22,7 @@
*/
#include common.h
-
-
-static inline void mips_compare_set(u32 v)
-{
- asm volatile (mtc0 %0, $11 : : r (v));
-}
-
-static inline void mips_count_set(u32 v)
-{
- asm volatile (mtc0 %0, $9 : : r (v));
-}
-
-
-static inline u32 mips_count_get(void)
-{
- u32 count;
-
- asm volatile (mfc0 %0, $9 : =r (count) :);
- return count;
-}
+#include asm/mipsregs.h
/*
* timer without interrupts
@@ -49,25 +30,25 @@ static inline u32 mips_count_get(void)
int timer_init(void)
{
- mips_compare_set(0);
- mips_count_set(0);
+ write_32bit_cp0_register(CP0_COMPARE, 0);
+ write_32bit_cp0_register(CP0_COUNT, 0);
return 0;
}
void reset_timer(void)
{
- mips_count_set(0);
+ write_32bit_cp0_register(CP0_COUNT, 0);
}
ulong get_timer(ulong base)
{
- return mips_count_get() - base;
+ return read_32bit_cp0_register(CP0_COUNT) - base;
}
void set_timer(ulong t)
{
- mips_count_set(t);
+ write_32bit_cp0_register(CP0_COUNT, t);
}
void udelay (unsigned long usec)
@@ -76,7 +57,7 @@ void udelay (unsigned long usec)
ulong start = get_timer(0);
tmo = usec * (CFG_HZ / 100);
- while ((ulong)((mips_count_get() - start)) tmo)
+ while ((ulong)((read_32bit_cp0_register(CP0_COUNT) - start)) tmo)
/*NOP*/;
}
@@ -86,7 +67,7 @@ void udelay (unsigned long usec)
*/
unsigned long long get_ticks(void)
{
- return mips_count_get();
+ return read_32bit_cp0_register(CP0_COUNT);
}
/*
-
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[U-Boot-Users] [PATCH 2/3][MIPS] lib_mips/time.c: Fix udelay
What we have to do is just to wait for given micro-seconds. No need to
take into account current time, get_timer and CFG_HZ.
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
lib_mips/time.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/lib_mips/time.c b/lib_mips/time.c
index f03f023..154d792 100644
--- a/lib_mips/time.c
+++ b/lib_mips/time.c
@@ -51,13 +51,13 @@ void set_timer(ulong t)
write_32bit_cp0_register(CP0_COUNT, t);
}
-void udelay (unsigned long usec)
+void udelay(unsigned long usec)
{
ulong tmo;
- ulong start = get_timer(0);
+ unsigned int start = read_32bit_cp0_register(CP0_COUNT);
- tmo = usec * (CFG_HZ / 100);
- while ((ulong)((read_32bit_cp0_register(CP0_COUNT) - start)) tmo)
+ tmo = start + (usec * (CONFIG_MIPS_TIMER_FREQ / 100));
+ while ((ulong)(tmo - read_32bit_cp0_register(CP0_COUNT)) 0x7fff)
/*NOP*/;
}
-
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[U-Boot-Users] [PATCH 1/2][MIPS] Add asm headers
These headers are used to probe and utilize CPU informartion. - asm/cpu-features.h - asm/cpu-info.h - asm/cpu.h - asm/fpu.h - asm/hazards.h Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- include/asm-mips/cpu-features.h | 218 +++ include/asm-mips/cpu-info.h | 70 ++ include/asm-mips/cpu.h | 265 ++ include/asm-mips/fpu.h | 42 ++ include/asm-mips/hazards.h | 270 +++ include/asm-mips/mipsregs.h |1 6 files changed, 866 insertions(+), 0 deletions(-) create mode 100644 include/asm-mips/cpu-features.h create mode 100644 include/asm-mips/cpu-info.h create mode 100644 include/asm-mips/cpu.h create mode 100644 include/asm-mips/fpu.h create mode 100644 include/asm-mips/hazards.h diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h new file mode 100644 index 000..618e7a6 --- /dev/null +++ b/include/asm-mips/cpu-features.h @@ -0,0 +1,218 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + */ +#ifndef __ASM_CPU_FEATURES_H +#define __ASM_CPU_FEATURES_H + +#include asm/cpu.h +#include asm/cpu-info.h + +#ifndef current_cpu_type +#define current_cpu_type() current_cpu_data.cputype +#endif + +/* + * SMP assumption: Options of CPU 0 are a superset of all processors. + * This is true for all known MIPS systems. + */ +#ifndef cpu_has_tlb +#define cpu_has_tlb(cpu_data[0].options MIPS_CPU_TLB) +#endif +#ifndef cpu_has_4kex +#define cpu_has_4kex (cpu_data[0].options MIPS_CPU_4KEX) +#endif +#ifndef cpu_has_3k_cache +#define cpu_has_3k_cache (cpu_data[0].options MIPS_CPU_3K_CACHE) +#endif +#define cpu_has_6k_cache 0 +#define cpu_has_8k_cache 0 +#ifndef cpu_has_4k_cache +#define cpu_has_4k_cache (cpu_data[0].options MIPS_CPU_4K_CACHE) +#endif +#ifndef cpu_has_tx39_cache +#define cpu_has_tx39_cache (cpu_data[0].options MIPS_CPU_TX39_CACHE) +#endif +#ifndef cpu_has_fpu +#define cpu_has_fpu(current_cpu_data.options MIPS_CPU_FPU) +#define raw_cpu_has_fpu(raw_current_cpu_data.options MIPS_CPU_FPU) +#else +#define raw_cpu_has_fpucpu_has_fpu +#endif +#ifndef cpu_has_32fpr +#define cpu_has_32fpr (cpu_data[0].options MIPS_CPU_32FPR) +#endif +#ifndef cpu_has_counter +#define cpu_has_counter(cpu_data[0].options MIPS_CPU_COUNTER) +#endif +#ifndef cpu_has_watch +#define cpu_has_watch (cpu_data[0].options MIPS_CPU_WATCH) +#endif +#ifndef cpu_has_divec +#define cpu_has_divec (cpu_data[0].options MIPS_CPU_DIVEC) +#endif +#ifndef cpu_has_vce +#define cpu_has_vce(cpu_data[0].options MIPS_CPU_VCE) +#endif +#ifndef cpu_has_cache_cdex_p +#define cpu_has_cache_cdex_p (cpu_data[0].options MIPS_CPU_CACHE_CDEX_P) +#endif +#ifndef cpu_has_cache_cdex_s +#define cpu_has_cache_cdex_s (cpu_data[0].options MIPS_CPU_CACHE_CDEX_S) +#endif +#ifndef cpu_has_prefetch +#define cpu_has_prefetch (cpu_data[0].options MIPS_CPU_PREFETCH) +#endif +#ifndef cpu_has_mcheck +#define cpu_has_mcheck (cpu_data[0].options MIPS_CPU_MCHECK) +#endif +#ifndef cpu_has_ejtag +#define cpu_has_ejtag (cpu_data[0].options MIPS_CPU_EJTAG) +#endif +#ifndef cpu_has_llsc +#define cpu_has_llsc (cpu_data[0].options MIPS_CPU_LLSC) +#endif +#ifndef cpu_has_mips16 +#define cpu_has_mips16 (cpu_data[0].ases MIPS_ASE_MIPS16) +#endif +#ifndef cpu_has_mdmx +#define cpu_has_mdmx (cpu_data[0].ases MIPS_ASE_MDMX) +#endif +#ifndef cpu_has_mips3d +#define cpu_has_mips3d (cpu_data[0].ases MIPS_ASE_MIPS3D) +#endif +#ifndef cpu_has_smartmips +#define cpu_has_smartmips (cpu_data[0].ases MIPS_ASE_SMARTMIPS) +#endif +#ifndef cpu_has_vtag_icache +#define cpu_has_vtag_icache(cpu_data[0].icache.flags MIPS_CACHE_VTAG) +#endif +#ifndef cpu_has_dc_aliases +#define cpu_has_dc_aliases (cpu_data[0].dcache.flags MIPS_CACHE_ALIASES) +#endif +#ifndef cpu_has_ic_fills_f_dc +#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags MIPS_CACHE_IC_F_DC) +#endif +#ifndef cpu_has_pindexed_dcache +#define cpu_has_pindexed_dcache(cpu_data[0].dcache.flags MIPS_CACHE_PINDEX) +#endif + +/* + * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors + * such as the R1 have I-Caches that snoop local stores; the embedded ones + * don't. For maintaining I-cache coherency this means we need to flush the + * D-cache all the way back to whever the I-cache does refills from, so the + * I-cache has a chance to see the new data at all. Then we have to flush the + * I-cache also. + * Note we may have been rescheduled and may no longer be running
[U-Boot-Users] [PATCH 2/2][MIPS] Add cpu_probe and cpu_report
Probe CPU information (core type, ISA level, core features and TLB size).
These info will be utilized all over the further processing.
[it seems this doesn't work on qemu-mips. Need more work...]
Probed info will be appeared like below:
U-Boot 1.3.3-rc3-00018-g4cb1ca8 (May 6 2008 - 11:05:51)
DRAM: 256 MB
Flash: 64 MB
CPU revision is: 5520 (R5500)
FPU revision is: 00035520
Using default environment
In:serial
Out: serial
Err: serial
Net: No ethernet found.
#
U-Boot 1.3.3-rc3-00018-g4cb1ca8 (May 6 2008 - 11:09:28)
DRAM: 256 MB
Flash: 64 MB
CPU revision is: 00019064 (MIPS 4KEc)
Using default environment
In:serial
Out: serial
Err: serial
Net: No ethernet found.
#
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
cpu/mips/Makefile|2
cpu/mips/cpu-probe.c | 754 ++
cpu/mips/cpu.c |3
lib_mips/board.c |5
4 files changed, 763 insertions(+), 1 deletions(-)
create mode 100644 cpu/mips/cpu-probe.c
diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile
index 92dcc16..29dd941 100644
--- a/cpu/mips/Makefile
+++ b/cpu/mips/Makefile
@@ -27,7 +27,7 @@ LIB = $(obj)lib$(CPU).a
START = start.o
COBJS = asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \
- cpu.o interrupts.o incaip_clock.o
+ cpu.o cpu-probe.o interrupts.o incaip_clock.o
SOBJS = incaip_wdt.o cache.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/mips/cpu-probe.c b/cpu/mips/cpu-probe.c
new file mode 100644
index 000..a5f9b04
--- /dev/null
+++ b/cpu/mips/cpu-probe.c
@@ -0,0 +1,754 @@
+/*
+ * Processor capabilities determination functions.
+ *
+ * Copyright (C) the Anonymous
+ * Copyright (C) 1994 - 2006 Ralf Baechle
+ * Copyright (C) 2003, 2004 Maciej W. Rozycki
+ * Copyright (C) 2001, 2004 MIPS Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include common.h
+#include linux/stddef.h
+
+#include asm/cpu.h
+#include asm/fpu.h
+#include asm/mipsregs.h
+#include asm/cpu-features.h
+
+/*
+ * Probe whether cpu has config register by trying to play with
+ * alternate cache bit and see whether it matters.
+ * It's used by cpu_probe to distinguish between R3000A and R3081.
+ */
+static inline int cpu_has_confreg(void)
+{
+#ifdef CONFIG_CPU_R3000
+ extern unsigned long r3k_cache_size(unsigned long);
+ unsigned long size1, size2;
+ unsigned long cfg = read_c0_conf();
+
+ size1 = r3k_cache_size(ST0_ISC);
+ write_c0_conf(cfg ^ R30XX_CONF_AC);
+ size2 = r3k_cache_size(ST0_ISC);
+ write_c0_conf(cfg);
+ return size1 != size2;
+#else
+ return 0;
+#endif
+}
+
+/*
+ * Get the FPU Implementation/Revision.
+ */
+static inline unsigned long cpu_get_fpu_id(void)
+{
+ unsigned long tmp, fpu_id;
+
+ tmp = read_c0_status();
+ __enable_fpu();
+ fpu_id = read_32bit_cp1_register(CP1_REVISION);
+ write_c0_status(tmp);
+ return fpu_id;
+}
+
+/*
+ * Check the CPU has an FPU the official way.
+ */
+static inline int __cpu_has_fpu(void)
+{
+ return ((cpu_get_fpu_id() 0xff00) != FPIR_IMP_NONE);
+}
+
+#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
+ | MIPS_CPU_COUNTER)
+
+static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
+{
+ switch (c-processor_id 0xff00) {
+ case PRID_IMP_R2000:
+ c-cputype = CPU_R2000;
+ c-isa_level = MIPS_CPU_ISA_I;
+ c-options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
+MIPS_CPU_NOFPUEX;
+ if (__cpu_has_fpu())
+ c-options |= MIPS_CPU_FPU;
+ c-tlbsize = 64;
+ break;
+ case PRID_IMP_R3000:
+ if ((c-processor_id 0xff) == PRID_REV_R3000A)
+ if (cpu_has_confreg())
+ c-cputype = CPU_R3081E;
+ else
+ c-cputype = CPU_R3000A;
+ else
+ c-cputype = CPU_R3000;
+ c-isa_level = MIPS_CPU_ISA_I;
+ c-options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
+MIPS_CPU_NOFPUEX;
+ if (__cpu_has_fpu())
+ c-options |= MIPS_CPU_FPU;
+ c-tlbsize = 64;
+ break;
+ case PRID_IMP_R4000:
+ if (read_c0_config() CONF_SC) {
+ if ((c-processor_id 0xff) = PRID_REV_R4400)
+ c-cputype = CPU_R4400PC;
+ else
+ c-cputype = CPU_R4000PC;
+ } else {
+ if ((c
[U-Boot-Users] [MIPS] mips_config.mk: Misc fixes
- Kill redundant `-pipe' (this will be added by $(TOPDIR)/config.mk) - Modify comments Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- mips_config.mk |7 +++ 1 files changed, 3 insertions(+), 4 deletions(-) diff --git a/mips_config.mk b/mips_config.mk index 67fb67d..05eb05d 100644 --- a/mips_config.mk +++ b/mips_config.mk @@ -40,10 +40,9 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ # LDFLAGS_vmlinux += -G 0 -static -n -nostdlib # MODFLAGS += -mlong-calls # - -# -# Meanwhile, U-Boot rely on PIC. We add proper switches explicitly. +# On the other hand, we want PIC in the U-Boot code to relocate it from ROM +# to RAM. $28 is always used as gp. # -PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic -pipe +PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic PLATFORM_CPPFLAGS += -msoft-float PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [MIPS] Update asm/addrspace.h header
- Fix traditional KSEG names
- Fix PHYSADDR
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
board/gth2/gth2.c|2 -
board/incaip/incaip.c|2 -
board/purple/purple.c| 14 ++--
board/tb0229/vr4131-pci.c| 56 +++---
cpu/mips/cache.S |6 +-
include/asm-mips/addrspace.h | 167 +++---
include/asm-mips/io.h|4 +
7 files changed, 167 insertions(+), 84 deletions(-)
diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c
index 9bc4d3f..3e56678 100644
--- a/board/gth2/gth2.c
+++ b/board/gth2/gth2.c
@@ -36,7 +36,7 @@ static int wdi_status = 0;
#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
-#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096))
+#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096))
void inline log_serial_char(char c){
char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
index c624b3d..dc51373 100644
--- a/board/incaip/incaip.c
+++ b/board/incaip/incaip.c
@@ -63,7 +63,7 @@ long int initdram(int board_type)
/* Can't probe for RAM size unless we are running from Flash.
*/
- if (PHYSADDR(our_address) PHYSADDR(PHYS_FLASH_1))
+ if (CPHYSADDR(our_address) CPHYSADDR(PHYS_FLASH_1))
{
return max_sdram_size();
}
diff --git a/board/purple/purple.c b/board/purple/purple.c
index 89cb906..72d5734 100644
--- a/board/purple/purple.c
+++ b/board/purple/purple.c
@@ -85,16 +85,16 @@ static void sdram_timing_init (ulong size)
while (p4 32 done == 0) {
WRITE_MC_IOGP_1;
- for (addr = KSEG1 + 0x4000;
-addr KSEG1ADDR (size);
+ for (addr = CKSEG1 + 0x4000;
+addr CKSEG1ADDR (size);
addr = addr + 4) {
*(uint *) addr = 0xaa55aa55;
}
pass = 1;
- for (addr = KSEG1 + 0x4000;
-addr KSEG1ADDR (size) pass == 1;
+ for (addr = CKSEG1 + 0x4000;
+addr CKSEG1ADDR (size) pass == 1;
addr = addr + 4) {
if (*(uint *) addr != 0xaa55aa55)
pass = 0;
@@ -138,7 +138,7 @@ long int initdram(int board_type)
ulong size= (1 (rows + cols)) * (1 (dw - 1)) * CFG_NB;
void (* sdram_init) (ulong);
- sdram_init = (void (*)(ulong)) KSEG0ADDR(sdram_timing_init);
+ sdram_init = (void (*)(ulong)) CKSEG0ADDR(sdram_timing_init);
sdram_init(0x1);
@@ -260,14 +260,14 @@ void copy_code (ulong dest_addr)
/* flush caches
*/
- start = KSEG0;
+ start = CKSEG0;
end = start + CFG_DCACHE_SIZE;
while(start end) {
cache_unroll(start,Index_Writeback_Inv_D);
start += CFG_CACHELINE_SIZE;
}
- start = KSEG0;
+ start = CKSEG0;
end = start + CFG_ICACHE_SIZE;
while(start end) {
cache_unroll(start,Index_Invalidate_I);
diff --git a/board/tb0229/vr4131-pci.c b/board/tb0229/vr4131-pci.c
index 0ee4bf3..4c91923 100644
--- a/board/tb0229/vr4131-pci.c
+++ b/board/tb0229/vr4131-pci.c
@@ -13,34 +13,34 @@
#include pci.h
#include asm/addrspace.h
-#define VR4131_PCIMMAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c00)
-#define VR4131_PCIMMAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c04)
-#define VR4131_PCITAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c08)
-#define VR4131_PCITAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c0c)
-#define VR4131_PCIMIOAWREG (volatile unsigned int*)(KSEG1 + 0x0f000c10)
-#define VR4131_PCICONFDREG (volatile unsigned int*)(KSEG1 + 0x0f000c14)
-#define VR4131_PCICONFAREG (volatile unsigned int*)(KSEG1 + 0x0f000c18)
-#define VR4131_PCIMAILREG (volatile unsigned int*)(KSEG1 + 0x0f000c1c)
-#define VR4131_BUSERRADREG (volatile unsigned int*)(KSEG1 + 0x0f000c24)
-#define VR4131_INTCNTSTAREG(volatile unsigned int*)(KSEG1 + 0x0f000c28)
-#define VR4131_PCIEXACCREG (volatile unsigned int*)(KSEG1 + 0x0f000c2c)
-#define VR4131_PCIRECONTREG(volatile unsigned int*)(KSEG1 + 0x0f000c30)
-#define VR4131_PCIENREG(volatile unsigned int*)(KSEG1 +
0x0f000c34)
-#define VR4131_PCICLKSELREG(volatile unsigned int*)(KSEG1 + 0x0f000c38)
-#define VR4131_PCITRDYREG (volatile unsigned int*)(KSEG1 + 0x0f000c3c)
-#define VR4131_PCICLKRUNREG(volatile unsigned int*)(KSEG1 + 0x0f000c60)
-#define VR4131_PCIHOSTCONFIG (volatile unsigned int*)(KSEG1 + 0x0f000d00)
-#define VR4131_VENDORIDREG (volatile unsigned
[U-Boot-Users] [MIPS] Convert CPU type name into CONFIG_CPU_*
Adjust to the current Linux way. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- include/configs/dbau1x00.h |2 +- include/configs/gth2.h |2 +- include/configs/incaip.h|2 +- include/configs/pb1x00.h|2 +- include/configs/purple.h|2 +- include/configs/qemu-mips.h |2 +- include/configs/tb0229.h|2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index b2f606f..ddb98ac 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -28,7 +28,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ +#define CONFIG_CPU_MIPS32_R1 1 /* MIPS32 CPU core */ #define CONFIG_DBAU1X001 #define CONFIG_AU1X00 1 /* alchemy series cpu */ diff --git a/include/configs/gth2.h b/include/configs/gth2.h index c2a50c1..50487fa 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -28,7 +28,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ +#define CONFIG_CPU_MIPS32_R1 1 /* MIPS32 CPU core */ #define CONFIG_GTH21 #define CONFIG_AU1X00 1 /* alchemy series cpu */ diff --git a/include/configs/incaip.h b/include/configs/incaip.h index 5ca00b3..430626d 100644 --- a/include/configs/incaip.h +++ b/include/configs/incaip.h @@ -28,7 +28,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core*/ +#define CONFIG_CPU_MIPS32_R1 1 /* MIPS 4Kc CPU core*/ #define CONFIG_INCA_IP 1 /* on a INCA-IP Board */ #ifndefCPU_CLOCK_RATE diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 810e0f0..899959a 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -28,7 +28,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ +#define CONFIG_CPU_MIPS32_R1 1 /* MIPS32 CPU core */ #define CONFIG_PB1X00 1 #define CONFIG_AU1X00 1 /* alchemy series cpu */ diff --git a/include/configs/purple.h b/include/configs/purple.h index 1be4e05..f867efd 100644 --- a/include/configs/purple.h +++ b/include/configs/purple.h @@ -28,7 +28,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS 5Kc CPU core*/ +#define CONFIG_CPU_MIPS32_R1 1 /* MIPS 5Kc CPU core*/ #define CONFIG_PURPLE 1 /* on a PURPLE Board*/ #define CPU_CLOCK_RATE 12500 /* 125 MHz clock for the MIPS core */ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index d6bcc8e..98a07a6 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -28,7 +28,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ +#define CONFIG_CPU_MIPS32_R1 1 /* MIPS32 CPU core */ #define CONFIG_QEMU_MIPS 1 #define CONFIG_MISC_INIT_R diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h index dadf5d3..841f92d 100644 --- a/include/configs/tb0229.h +++ b/include/configs/tb0229.h @@ -25,7 +25,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core*/ +#define CONFIG_CPU_VR41XX 1 /* MIPS VR4131 CPU core */ #define CONFIG_TB0229 1 /* on a TB0229 Board*/ #ifndef CPU_CLOCK_RATE - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [MIPS] Rename Alchemy processor configs into CONFIGO_SOC_*
CONFIG_SOC_AU1X00
Common Alchemy Au1x00 stuff. All Alchemy processor based machines
need to have this config as a system type specifier.
CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200,
CONFIG_SOC_AU1500, CONFIG_SOC_AU1550
Machine type specifiers. Each port should have one of aboves.
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
cpu/mips/au1x00_eth.c| 12 ++--
cpu/mips/au1x00_serial.c |4 ++--
cpu/mips/au1x00_usb_ohci.c |2 +-
include/asm-mips/addrspace.h |6 +++---
include/asm-mips/au1x00.h|6 +++---
include/configs/dbau1x00.h | 10 +-
include/configs/gth2.h |4 ++--
include/configs/pb1x00.h |8
8 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c
index d70c5fe..aeb9662 100644
--- a/cpu/mips/au1x00_eth.c
+++ b/cpu/mips/au1x00_eth.c
@@ -23,7 +23,7 @@
*/
#include config.h
-#ifdef CONFIG_AU1X00
+#ifdef CONFIG_SOC_AU1X00
#if defined(CFG_DISCOVER_PHY)
#error PHY not supported yet
@@ -33,20 +33,20 @@
/* I assume ethernet behaves like au1000 */
-#ifdef CONFIG_AU1000
+#ifdef CONFIG_SOC_AU1000
/* Base address differ between cpu:s */
#define ETH0_BASE AU1000_ETH0_BASE
#define MAC0_ENABLE AU1000_MAC0_ENABLE
#else
-#ifdef CONFIG_AU1100
+#ifdef CONFIG_SOC_AU1100
#define ETH0_BASE AU1100_ETH0_BASE
#define MAC0_ENABLE AU1100_MAC0_ENABLE
#else
-#ifdef CONFIG_AU1500
+#ifdef CONFIG_SOC_AU1500
#define ETH0_BASE AU1500_ETH0_BASE
#define MAC0_ENABLE AU1500_MAC0_ENABLE
#else
-#ifdef CONFIG_AU1550
+#ifdef CONFIG_SOC_AU1550
#define ETH0_BASE AU1550_ETH0_BASE
#define MAC0_ENABLE AU1550_MAC0_ENABLE
#else
@@ -308,4 +308,4 @@ int au1x00_enet_initialize(bd_t *bis){
return 1;
}
-#endif /* CONFIG_AU1X00 */
+#endif /* CONFIG_SOC_AU1X00 */
diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c
index 42c668e..ec10ac0 100644
--- a/cpu/mips/au1x00_serial.c
+++ b/cpu/mips/au1x00_serial.c
@@ -27,7 +27,7 @@
#include config.h
-#ifdef CONFIG_AU1X00
+#ifdef CONFIG_SOC_AU1X00
#include common.h
#include asm/au1x00.h
@@ -132,4 +132,4 @@ int serial_tstc (void)
}
return 0;
}
-#endif /* CONFIG_SERIAL_AU1X00 */
+#endif /* CONFIG_SOC_AU1X00 */
diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c
index dbf72dc..e03b125 100644
--- a/cpu/mips/au1x00_usb_ohci.c
+++ b/cpu/mips/au1x00_usb_ohci.c
@@ -35,7 +35,7 @@
#include config.h
-#if defined(CONFIG_AU1X00) defined(CONFIG_USB_OHCI)
+#if defined(CONFIG_SOC_AU1X00) defined(CONFIG_USB_OHCI)
/* #include pci.h no PCI on the AU1x00 */
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 767804c..3a1e6d6 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -131,13 +131,13 @@
* Returns the uncached address of a sdram address
*/
#ifndef __ASSEMBLY__
-#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229)
+#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
/* We use a 36 bit physical address map here and
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x2000)
-#else /* !CONFIG_AU1X00 */
+#else /* !CONFIG_SOC_AU1X00 */
#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
-#endif /* CONFIG_AU1X00 */
+#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
/*
diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h
index 6a33197..2a948e8 100644
--- a/include/asm-mips/au1x00.h
+++ b/include/asm-mips/au1x00.h
@@ -137,7 +137,7 @@ static __inline__ int au_ffs(int x)
#define CP0_DEBUG $23
/* SDRAM Controller */
-#ifdef CONFIG_AU1550
+#ifdef CONFIG_SOC_AU1550
#define MEM_SDMODE00xB4000800
#define MEM_SDMODE10xB4000808
@@ -156,7 +156,7 @@ static __inline__ int au_ffs(int x)
#define MEM_SDWRMD10xB4000888
#define MEM_SDWRMD20xB4000890
-#else /* CONFIG_AU1550 */
+#else /* CONFIG_SOC_AU1550 */
#define MEM_SDMODE00xB400
#define MEM_SDMODE10xB404
@@ -174,7 +174,7 @@ static __inline__ int au_ffs(int x)
#define MEM_SDWRMD10xB428
#define MEM_SDWRMD20xB42C
-#endif /* CONFIG_AU1550 */
+#endif /* CONFIG_SOC_AU1550 */
#define MEM_SDSLEEP0xB430
#define MEM_SDSMCKE0xB434
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index ddb98ac..d039e7a 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -30,21 +30,21 @@
#define CONFIG_CPU_MIPS32_R1 1 /* MIPS32 CPU core */
#define CONFIG_DBAU1X001
-#define CONFIG_AU1X00 1 /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
#ifdef CONFIG_DBAU1000
/* Also known as Merlot */
-#define CONFIG_AU1000 1
+#define CONFIG_SOC_AU1000 1
#else
#ifdef CONFIG_DBAU1100
-#define
[U-Boot-Users] [MIPS] cpu/mips/Makefile: Split [CS]OBJS onto separate lines
Also get rid of some #ifdefs in *.c files.
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
cpu/mips/Makefile | 15 +--
cpu/mips/asc_serial.c |3 ---
cpu/mips/au1x00_eth.c |4
cpu/mips/au1x00_serial.c |4
cpu/mips/au1x00_usb_ohci.c |2 +-
5 files changed, 10 insertions(+), 18 deletions(-)
diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile
index 29dd941..69cc16a 100644
--- a/cpu/mips/Makefile
+++ b/cpu/mips/Makefile
@@ -25,13 +25,16 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).a
-START = start.o
-COBJS = asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \
- cpu.o cpu-probe.o interrupts.o incaip_clock.o
-SOBJS = incaip_wdt.o cache.o
+SOBJS-y= cache.o
+COBJS-y= cpu.o cpu-probe.o interrupts.o
-SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+SOBJS-$(CONFIG_INCA_IP)+= incaip_wdt.o
+COBJS-$(CONFIG_INCA_IP)+= asc_serial.o incaip_clock.o
+COBJS-$(CONFIG_PURPLE) += asc_serial.o
+COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
+
+SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
diff --git a/cpu/mips/asc_serial.c b/cpu/mips/asc_serial.c
index 3498b61..be686c2 100644
--- a/cpu/mips/asc_serial.c
+++ b/cpu/mips/asc_serial.c
@@ -4,8 +4,6 @@
#include config.h
-#if defined(CONFIG_PURPLE) || defined(CONFIG_INCA_IP)
-
#ifdef CONFIG_PURPLE
#defineserial_init asc_serial_init
#defineserial_putc asc_serial_putc
@@ -368,4 +366,3 @@ int serial_tstc (void)
return res;
}
-#endif /* CONFIG_PURPLE || CONFIG_INCA_IP */
diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c
index aeb9662..d0cf8e0 100644
--- a/cpu/mips/au1x00_eth.c
+++ b/cpu/mips/au1x00_eth.c
@@ -23,8 +23,6 @@
*/
#include config.h
-#ifdef CONFIG_SOC_AU1X00
-
#if defined(CFG_DISCOVER_PHY)
#error PHY not supported yet
/* We just assume that we are running 100FD for now */
@@ -307,5 +305,3 @@ int au1x00_enet_initialize(bd_t *bis){
return 1;
}
-
-#endif /* CONFIG_SOC_AU1X00 */
diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c
index ec10ac0..6309794 100644
--- a/cpu/mips/au1x00_serial.c
+++ b/cpu/mips/au1x00_serial.c
@@ -26,9 +26,6 @@
*/
#include config.h
-
-#ifdef CONFIG_SOC_AU1X00
-
#include common.h
#include asm/au1x00.h
@@ -132,4 +129,3 @@ int serial_tstc (void)
}
return 0;
}
-#endif /* CONFIG_SOC_AU1X00 */
diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c
index e03b125..1ca8aaf 100644
--- a/cpu/mips/au1x00_usb_ohci.c
+++ b/cpu/mips/au1x00_usb_ohci.c
@@ -35,7 +35,7 @@
#include config.h
-#if defined(CONFIG_SOC_AU1X00) defined(CONFIG_USB_OHCI)
+#ifdef CONFIG_USB_OHCI
/* #include pci.h no PCI on the AU1x00 */
-
This SF.net email is sponsored by: Microsoft
Defy all challenges. Microsoft(R) Visual Studio 2008.
http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/
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[U-Boot-Users] [MIPS] CPU-dependent compiler/assembler options for optimization
We take the same options as Linux for now. This means that an ancient -mcpu support will be lost. Users need gcc 3.0.X or later. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- cpu/mips/config.mk | 38 +++--- 1 files changed, 31 insertions(+), 7 deletions(-) diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk index a173c54..8df5e23 100644 --- a/cpu/mips/config.mk +++ b/cpu/mips/config.mk @@ -20,13 +20,6 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2) -MIPSFLAGS:=$(shell \ -if [ $v -lt 14 ]; then \ - echo -mcpu=4kc; \ -else \ - echo -march=4kc -mtune=4kc; \ -fi) ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) ENDIANNESS = -EL @@ -37,3 +30,34 @@ endif MIPSFLAGS += $(ENDIANNESS) PLATFORM_CPPFLAGS += $(MIPSFLAGS) + +# +# CPU-dependent compiler/assembler options for optimization. +# +cflags-$(CONFIG_CPU_R3000) += -march=r3000 +cflags-$(CONFIG_CPU_TX39XX)+= -march=r3900 +cflags-$(CONFIG_CPU_R6000) += -march=r6000 -Wa,--trap +cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap +cflags-$(CONFIG_CPU_VR41XX)+= -march=r4100 -Wa,--trap +cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap +cflags-$(CONFIG_CPU_TX49XX)+= -march=r4600 -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap +cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) -Wa,-mips32 -Wa,--trap +cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) -Wa,-mips32r2 -Wa,--trap +cflags-$(CONFIG_CPU_MIPS64_R1) += $(call cc-option,-march=mips64,-mips64 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) -Wa,-mips64 -Wa,--trap +cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) -Wa,-mips64r2 -Wa,--trap +cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap +cflags-$(CONFIG_CPU_R5432) += $(call cc-option,-march=r5400,-march=r5000) -Wa,--trap +cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=r5000) -Wa,--trap +cflags-$(CONFIG_CPU_NEVADA)+= $(call cc-option,-march=rm5200,-march=r5000) -Wa,--trap +cflags-$(CONFIG_CPU_RM7000)+= $(call cc-option,-march=rm7000,-march=r5000) -Wa,--trap +cflags-$(CONFIG_CPU_RM9000)+= $(call cc-option,-march=rm9000,-march=r5000) -Wa,--trap +cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) -Wa,--trap +cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap +cflags-$(CONFIG_CPU_R1)+= $(call cc-option,-march=r1,-march=r8000) -Wa,--trap + +cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) +cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) +cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) + +PLATFORM_CPPFLAGS += $(cflags-y) - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 1/2][MIPS] Add asm headers
Wolfgang Denk wrote: In message [EMAIL PROTECTED] you wrote: These headers are used to probe and utilize CPU informartion. - asm/cpu-features.h - asm/cpu-info.h - asm/cpu.h - asm/fpu.h - asm/hazards.h ... diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h new file mode 100644 index 000..58715e8 --- /dev/null +++ b/include/asm-mips/cpu.h @@ -0,0 +1,265 @@ +/* + * cpu.h: Values of the PRId register used to match up + *various MIPS cpu types. + * + * Copyright (C) 1996 David S. Miller ([EMAIL PROTECTED]) + * Copyright (C) 2004 Maciej W. Rozycki + */ Which license is this file released under? GPLv2 only, no doubt. I'll check it. Thanks for pointing this out. Shinya - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] NAND: Provide a sane default for NAND_MAX_CHIPS.
Scott Wood wrote:
This allows the header to be included regardless of whether a board's
config file provides NAND-related defininitions.
Signed-off-by: Scott Wood [EMAIL PROTECTED]
---
include/linux/mtd/nand.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 4cc4a7d..e2a25a6 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -385,6 +385,10 @@ struct nand_manufacturers {
extern struct nand_flash_dev nand_flash_ids[];
extern struct nand_manufacturers nand_manuf_ids[];
+#ifndef NAND_MAX_CHIPS
+#define NAND_MAX_CHIPS 8
+#endif
+
/**
* struct nand_bbt_descr - bad block table descriptor
* @options: options for this descriptor
Works for me, though I just checked it builds fine.
Acked-by: Shinya Kuribayashi [EMAIL PROTECTED]
-
This SF.net email is sponsored by: Microsoft
Defy all challenges. Microsoft(R) Visual Studio 2008.
http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/
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Re: [U-Boot-Users] [PATCH] mips: Call 'nand_init()' in generic board initialization when CONFIG_CMD_NAND is set
Jason McMullan wrote: --- lib_mips/board.c |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) As you submitted this patch and its description separately, I manually combined them with two CodingStyle fixes. Now you seem to be getting along with git :-) Applied, thanks. Will be pushed out soon. Shinya [MIPS] lib_mips/board.c: Add nand_init This patch adds the standard 'nand_init()' call to the mips generic 'board_init_r()' call, bringing MIPS in line with the other architectures. Signed-off-by: Jason McMullan [EMAIL PROTECTED] Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- lib_mips/board.c |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/lib_mips/board.c b/lib_mips/board.c index 1645f2c..43cfc17 100644 --- a/lib_mips/board.c +++ b/lib_mips/board.c @@ -28,6 +28,7 @@ #include version.h #include net.h #include environment.h +#include nand.h DECLARE_GLOBAL_DATA_PTR; @@ -416,6 +417,11 @@ void board_init_r (gd_t *id, ulong dest_addr) } #endif +#ifdef CONFIG_CMD_NAND + puts (NAND: ); + nand_init (); /* go init the NAND */ +#endif + #if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ misc_init_r (); - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] mips: If CONFIG_CMD_SPI is defined, call spi_init()
Jason McMullan wrote: The mips architecture currently does not call 'spi_init()' in the generic board initialization routine is CONFIG_CMD_SPI is defined. This patch rectifies that problem. Signed-off-by: Jason McMullan [EMAIL PROTECTED] Applied with two CodingStyle fixes. See below. @@ -422,6 +423,12 @@ void board_init_r (gd_t *id, ulong dest_addr) nand_init();/* go init the NAND */ #endif +#ifdef CONFIG_CMD_SPI + puts(SPI: ); ^ + spi_init(); /* go init the SPI */ ^ + puts (ready\n); +#endif + #if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ misc_init_r (); Note that I'm Linux's CodingStyle lover. But in this case, we should use the same CodingStyle in a single file. Thanks, Shinya - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [GIT PULL] MIPS updates
Dear Wolfgang, please pull MIPS updates. nand_init and spi_init will be added. --- The following changes since commit 2c8d41969b47eb0b973912830c58689b2ba0e50a: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-testing are available in the git repository at: git://git.denx.de/u-boot-mips.git master Jason McMullan (2): [MIPS] lib_mips/board.c: Add nand_init mips: If CONFIG_CMD_SPI is defined, call spi_init() lib_mips/board.c | 13 + 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/lib_mips/board.c b/lib_mips/board.c index 1645f2c..532550b 100644 --- a/lib_mips/board.c +++ b/lib_mips/board.c @@ -28,6 +28,8 @@ #include version.h #include net.h #include environment.h +#include nand.h +#include spi.h DECLARE_GLOBAL_DATA_PTR; @@ -416,6 +418,17 @@ void board_init_r (gd_t *id, ulong dest_addr) } #endif +#ifdef CONFIG_CMD_NAND + puts (NAND: ); + nand_init (); /* go init the NAND */ +#endif + +#ifdef CONFIG_CMD_SPI + puts (SPI: ); + spi_init ();/* go init the SPI */ + puts (ready\n); +#endif + #if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ misc_init_r (); - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 1/3][MIPS] asm/mipsregs.h: CodinygStyle cleanups
No functional changes. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- include/asm-mips/mipsregs.h | 283 ++- 1 files changed, 143 insertions(+), 140 deletions(-) diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 61a0dac..590af19 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -85,8 +85,8 @@ /* * Coprocessor 1 (FPU) register names */ -#define CP1_REVISION $0 -#define CP1_STATUS $31 +#define CP1_REVISION $0 +#define CP1_STATUS $31 /* * FPU Status Register Values @@ -95,223 +95,226 @@ * Status Register Values */ -#define FPU_CSR_FLUSH 0x0100 /* flush denormalised results to 0 */ -#define FPU_CSR_COND0x0080 /* $fcc0 */ -#define FPU_CSR_COND0 0x0080 /* $fcc0 */ -#define FPU_CSR_COND1 0x0200 /* $fcc1 */ -#define FPU_CSR_COND2 0x0400 /* $fcc2 */ -#define FPU_CSR_COND3 0x0800 /* $fcc3 */ -#define FPU_CSR_COND4 0x1000 /* $fcc4 */ -#define FPU_CSR_COND5 0x2000 /* $fcc5 */ -#define FPU_CSR_COND6 0x4000 /* $fcc6 */ -#define FPU_CSR_COND7 0x8000 /* $fcc7 */ +#define FPU_CSR_FLUSH 0x0100 /* flush denormalised results to 0 */ +#define FPU_CSR_COND 0x0080 /* $fcc0 */ +#define FPU_CSR_COND0 0x0080 /* $fcc0 */ +#define FPU_CSR_COND1 0x0200 /* $fcc1 */ +#define FPU_CSR_COND2 0x0400 /* $fcc2 */ +#define FPU_CSR_COND3 0x0800 /* $fcc3 */ +#define FPU_CSR_COND4 0x1000 /* $fcc4 */ +#define FPU_CSR_COND5 0x2000 /* $fcc5 */ +#define FPU_CSR_COND6 0x4000 /* $fcc6 */ +#define FPU_CSR_COND7 0x8000 /* $fcc7 */ /* * X the exception cause indicator * E the exception enable * S the sticky/flag bit -*/ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x0002 -#define FPU_CSR_INV_X 0x0001 -#define FPU_CSR_DIV_X 0x8000 -#define FPU_CSR_OVF_X 0x4000 -#define FPU_CSR_UDF_X 0x2000 -#define FPU_CSR_INE_X 0x1000 - -#define FPU_CSR_ALL_E 0x0f80 -#define FPU_CSR_INV_E 0x0800 -#define FPU_CSR_DIV_E 0x0400 -#define FPU_CSR_OVF_E 0x0200 -#define FPU_CSR_UDF_E 0x0100 -#define FPU_CSR_INE_E 0x0080 - -#define FPU_CSR_ALL_S 0x007c -#define FPU_CSR_INV_S 0x0040 -#define FPU_CSR_DIV_S 0x0020 -#define FPU_CSR_OVF_S 0x0010 -#define FPU_CSR_UDF_S 0x0008 -#define FPU_CSR_INE_S 0x0004 + */ +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x0002 +#define FPU_CSR_INV_X 0x0001 +#define FPU_CSR_DIV_X 0x8000 +#define FPU_CSR_OVF_X 0x4000 +#define FPU_CSR_UDF_X 0x2000 +#define FPU_CSR_INE_X 0x1000 + +#define FPU_CSR_ALL_E 0x0f80 +#define FPU_CSR_INV_E 0x0800 +#define FPU_CSR_DIV_E 0x0400 +#define FPU_CSR_OVF_E 0x0200 +#define FPU_CSR_UDF_E 0x0100 +#define FPU_CSR_INE_E 0x0080 + +#define FPU_CSR_ALL_S 0x007c +#define FPU_CSR_INV_S 0x0040 +#define FPU_CSR_DIV_S 0x0020 +#define FPU_CSR_OVF_S 0x0010 +#define FPU_CSR_UDF_S 0x0008 +#define FPU_CSR_INE_S 0x0004 /* rounding mode */ -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ - +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ /* * Values for PageMask register */ #include linux/config.h #ifdef CONFIG_CPU_VR41XX -#define PM_1K 0x -#define PM_4K 0x1800 -#define PM_16K 0x7800 -#define PM_64K 0x0001f800 -#define PM_256K 0x0007f800 + +#define PM_1K 0x +#define PM_4K 0x1800 +#define PM_16K 0x7800 +#define PM_64K 0x0001f800 +#define PM_256K0x0007f800 + #else -#define PM_4K 0x -#define PM_16K 0x6000 -#define PM_64K 0x0001e000 -#define PM_256K 0x0007e000 -#define PM_1M 0x001fe000 -#define PM_4M 0x007fe000 -#define PM_16M 0x01ffe000 + +#define PM_4K 0x +#define PM_16K 0x6000 +#define PM_64K 0x0001e000 +#define PM_256K0x0007e000 +#define PM_1M 0x001fe000 +#define PM_4M 0x007fe000 +#define PM_16M 0x01ffe000 + #endif /* * Values used for computation of new tlb entries */ -#define PL_4K 12 -#define PL_16K 14 -#define PL_64K 16 -#define PL_256K 18 -#define PL_1M 20 -#define PL_4M 22 -#define PL_16M 24 +#define PL_4K 12 +#define PL_16K 14 +#define PL_64K 16 +#define PL_256K18 +#define PL_1M 20 +#define PL_4M 22 +#define PL_16M 24 /* * Macros to access the system control
[U-Boot-Users] [PATCH 2/3][MIPS] asm/mipsregs.h: Update register / bit field definitions
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- include/asm-mips/mipsregs.h | 336 +-- 1 files changed, 225 insertions(+), 111 deletions(-) diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 590af19..f05f3ad 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -7,8 +7,8 @@ * Copyright (C) 2000 Silicon Graphics, Inc. * Modified for further R[236]000 support by Paul M. Antoine, 1996. * Kevin D. Kissell, [EMAIL PROTECTED] and Carsten Langgaard, [EMAIL PROTECTED] - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2003 Maciej W. Rozycki + * Copyright (C) 2000, 07 MIPS Technologies, Inc. + * Copyright (C) 2003, 2004 Maciej W. Rozycki */ #ifndef _ASM_MIPSREGS_H #define _ASM_MIPSREGS_H @@ -29,6 +29,15 @@ #endif /* + * Configure language + */ +#ifdef __ASSEMBLY__ +#define _ULCAST_ +#else +#define _ULCAST_ (unsigned long) +#endif + +/* * Coprocessor 0 register names */ #define CP0_INDEX $0 @@ -55,12 +64,15 @@ #define CP0_XCONTEXT $20 #define CP0_FRAMEMASK $21 #define CP0_DIAGNOSTIC $22 +#define CP0_DEBUG $23 +#define CP0_DEPC $24 #define CP0_PERFORMANCE $25 #define CP0_ECC $26 #define CP0_CACHEERR $27 #define CP0_TAGLO $28 #define CP0_TAGHI $29 #define CP0_ERROREPC $30 +#define CP0_DESAVE $31 /* * R4640/R4650 cp0 register names. These registers are listed @@ -82,6 +94,22 @@ #define CP0_S1_DERRADDR0 $26 #define CP0_S1_DERRADDR1 $27 #define CP0_S1_INTCONTROL $20 + +/* + * Coprocessor 0 Set 2 register names + */ +#define CP0_S2_SRSCTL $12 /* MIPSR2 */ + +/* + * Coprocessor 0 Set 3 register names + */ +#define CP0_S3_SRSMAP $12 /* MIPSR2 */ + +/* + * TX39 Series + */ +#define CP0_TX39_CACHE $7 + /* * Coprocessor 1 (FPU) register names */ @@ -142,9 +170,10 @@ /* * Values for PageMask register */ -#include linux/config.h #ifdef CONFIG_CPU_VR41XX +/* Why doesn't stupidity hurt ... */ + #define PM_1K 0x #define PM_4K 0x1800 #define PM_16K 0x7800 @@ -160,6 +189,8 @@ #define PM_1M 0x001fe000 #define PM_4M 0x007fe000 #define PM_16M 0x01ffe000 +#define PM_64M 0x07ffe000 +#define PM_256M0x1fffe000 #endif @@ -173,6 +204,8 @@ #define PL_1M 20 #define PL_4M 22 #define PL_16M 24 +#define PL_64M 26 +#define PL_256M28 /* * Macros to access the system control coprocessor @@ -252,26 +285,26 @@ /* * R4x00 interrupt enable / cause bits */ -#define IE_SW0 (1 8) -#define IE_SW1 (1 9) -#define IE_IRQ0(110) -#define IE_IRQ1(111) -#define IE_IRQ2(112) -#define IE_IRQ3(113) -#define IE_IRQ4(114) -#define IE_IRQ5(115) +#define IE_SW0 (_ULCAST_(1) 8) +#define IE_SW1 (_ULCAST_(1) 9) +#define IE_IRQ0(_ULCAST_(1) 10) +#define IE_IRQ1(_ULCAST_(1) 11) +#define IE_IRQ2(_ULCAST_(1) 12) +#define IE_IRQ3(_ULCAST_(1) 13) +#define IE_IRQ4(_ULCAST_(1) 14) +#define IE_IRQ5(_ULCAST_(1) 15) /* * R4x00 interrupt cause bits */ -#define C_SW0 (1 8) -#define C_SW1 (1 9) -#define C_IRQ0 (110) -#define C_IRQ1 (111) -#define C_IRQ2 (112) -#define C_IRQ3 (113) -#define C_IRQ4 (114) -#define C_IRQ5 (115) +#define C_SW0 (_ULCAST_(1) 8) +#define C_SW1 (_ULCAST_(1) 9) +#define C_IRQ0 (_ULCAST_(1) 10) +#define C_IRQ1 (_ULCAST_(1) 11) +#define C_IRQ2 (_ULCAST_(1) 12) +#define C_IRQ3 (_ULCAST_(1) 13) +#define C_IRQ4 (_ULCAST_(1) 14) +#define C_IRQ5 (_ULCAST_(1) 15) #ifndef _LANGUAGE_ASSEMBLY /* @@ -340,6 +373,13 @@ __BUILD_SET_CP0(config,CP0_CONFIG) #define ST0_CE 0x0002 /* + * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate + * cacheops in userspace. This bit exists only on RM7000 and RM9000 + * processors. + */ +#define ST0_CO 0x0800 + +/* * Bitfields in the R[23]000 cp0 status register. */ #define ST0_IEC0x0001 @@ -356,9 +396,14 @@ __BUILD_SET_CP0(config,CP0_CONFIG) /* * Bits specific to the R4640/R4650 */ -#define ST0_UM (1 4) -#define ST0_IL (123) -#define ST0_DL (124) +#define ST0_UM (_ULCAST_(1) 4) +#define ST0_IL (_ULCAST_(1) 23) +#define ST0_DL (_ULCAST_(1) 24) + +/* + * Enable the MIPS MDMX and DSP ASEs + */ +#define ST0_MX 0x0100 /* * Bitfields in the TX39 family CP0 Configuration Register 3 @@ -398,39 +443,40 @@ __BUILD_SET_CP0(config,CP0_CONFIG) */ #define ST0_IM
[U-Boot-Users] [PATCH 3/3][MIPS] asm/mipsregs.h: Update coprocessor register access macros
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
board/dbau1x00/dbau1x00.c |2
board/gth2/gth2.c |2
board/pb1x00/pb1x00.c |2
board/qemu-mips/qemu-mips.c |6
cpu/mips/cpu.c | 10
include/asm-mips/mipsregs.h | 950 +--
6 files changed, 836 insertions(+), 136 deletions(-)
diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c
index a13eeeb..1be72a2 100644
--- a/board/dbau1x00/dbau1x00.c
+++ b/board/dbau1x00/dbau1x00.c
@@ -52,7 +52,7 @@ int checkboard (void)
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
- proc_id = read_32bit_cp0_register(CP0_PRID);
+ proc_id = read_c0_prid();
switch (proc_id 24) {
case 0:
diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c
index 6da80dc..9bc4d3f 100644
--- a/board/gth2/gth2.c
+++ b/board/gth2/gth2.c
@@ -135,7 +135,7 @@ int checkboard (void)
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
- proc_id = read_32bit_cp0_register(CP0_PRID);
+ proc_id = read_c0_prid();
switch (proc_id 24) {
case 0:
diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c
index 536c954..82b7235 100644
--- a/board/pb1x00/pb1x00.c
+++ b/board/pb1x00/pb1x00.c
@@ -51,7 +51,7 @@ int checkboard (void)
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
- proc_id = read_32bit_cp0_register(CP0_PRID);
+ proc_id = read_c0_prid();
switch (proc_id 24) {
case 0:
diff --git a/board/qemu-mips/qemu-mips.c b/board/qemu-mips/qemu-mips.c
index 6869074..6e6eab2 100644
--- a/board/qemu-mips/qemu-mips.c
+++ b/board/qemu-mips/qemu-mips.c
@@ -38,7 +38,7 @@ int checkboard(void)
u32 proc_id;
u32 config1;
- proc_id = read_32bit_cp0_register(CP0_PRID);
+ proc_id = read_c0_prid();
printf(Board: Qemu -M mips CPU: );
switch (proc_id) {
case 0x00018000:
@@ -51,7 +51,7 @@ int checkboard(void)
printf(4KEc);
break;
case 0x00019300:
- config1 = read_mips32_cp0_config1();
+ config1 = read_c0_config1();
if (config1 1)
printf(24Kf);
else
@@ -64,7 +64,7 @@ int checkboard(void)
printf(R4000);
break;
case 0x00018100:
- config1 = read_mips32_cp0_config1();
+ config1 = read_c0_config1();
if (config1 1)
printf(5Kf);
else
diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index e267bba..0f58d25 100644
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -66,10 +66,10 @@ void flush_cache(ulong start_addr, ulong size)
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
{
- write_32bit_cp0_register(CP0_ENTRYLO0, low0);
- write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
- write_32bit_cp0_register(CP0_ENTRYLO1, low1);
- write_32bit_cp0_register(CP0_ENTRYHI, hi);
- write_32bit_cp0_register(CP0_INDEX, index);
+ write_c0_entrylo0(low0);
+ write_c0_pagemask(pagemask);
+ write_c0_entrylo1(low1);
+ write_c0_entryhi(hi);
+ write_c0_index(index);
tlb_write_indexed();
}
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index f05f3ad..be7e5c6 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -208,81 +208,6 @@
#define PL_256M28
/*
- * Macros to access the system control coprocessor
- */
-#define read_32bit_cp0_register(source)\
-({ int __res; \
- __asm__ __volatile__( \
- .set\tpush\n\t\
- .set\treorder\n\t \
- mfc0\t%0,STR(source)\n\t\
- .set\tpop \
- : =r (__res));\
- __res;})
-
-#define read_32bit_cp0_set1_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- .set\tpush\n\t\
- .set\treorder\n\t \
- cfc0\t%0,STR(source)\n\t\
- .set\tpop \
- : =r (__res));\
- __res;})
-
-/*
- * For now use this only with interrupts disabled!
- */
-#define read_64bit_cp0_register(source)\
-({ int __res; \
- __asm__ __volatile__( \
- .set
Re: [U-Boot-Users] [PATCH-v3] Big white-space cleanup.
Wolfgang Denk wrote: In message [EMAIL PROTECTED] I wrote: This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded vim: and vi: statements which hide indentation problems. Signed-off-by: Wolfgang Denk [EMAIL PROTECTED] The latest version of this patch is available for download here: ftp://ftp.denx.de/pub/tmp/big-white-space-cleanup.patch-v.3.gz I've checked all MIPS related changes: - cpu/mips/* - lib_mips/* - include/asm-mips/* - board/purple/* Unfortunately several wrong fixes or false positives still remains, but this patch definitely reduce the number of wrong indentations. Acked-by: Shinya Kuribayashi [EMAIL PROTECTED] - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH-v3] Big white-space cleanup.
Wolfgang Denk wrote: In message [EMAIL PROTECTED] you wrote: Unfortunately several wrong fixes or false positives still remains, but this patch definitely reduce the number of wrong indentations. Could you please point out the remaining problems? If I understand what's gone wrong I probably can fix my procedure and spin another patch? Please check files below: cpu/mips/au1x00_usb_ohci.h, L90, TD_PIDCHECKFAIL cpu/mips/au1x00_usb_ohci.h, L93, TD_DATAUNDERRUN cpu/mips/au1x00_usb_ohci.h, L145, You must use ... cpu/mips/au1x00_usb_ohci.h, L287, RH_NACK board/purple/purple.c, L38, board/purple/purple.c, L39, board/purple/purple.c, L50-54, Hmm. Special case? Shinya - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] Big white-space cleanup.
Wolfgang Denk wrote: plus, it looks like the patch is replacing tabs with spaces (see, e.g., pib_init() changes in board/freescale/mpc8349emds/pci.c). Hm... [snip] Argghhh No, really not. Thanks for cathing this one. It skipped both my automatic and manual verification :-( Patch version 2 available at ftp://ftp.denx.de/pub/tmp/big-white-space-cleanup.patch-v.2.gz I started to check some MIPS related file, and immediately found wrong fixes. board/purple/purple.c ... cache_unroll cpu/mips/asc_serial.c ... TOUT_LOOP, FBS_ISR, many others! cpu/mips/start.S ... All tabs removed!!! : : [stop further review at this point] Let me confirm whether above is intentional change or not, please? I'm afraid it's better to leave them as they are, even if there are silly white-space issues left. Shinya - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] [resend] mips: Support to set CFG_HZ to 1000, consistent with other architectures
Hi Jason,
I don't look closely yet, but find some comments below:
Jason McMullan wrote:
---
include/configs/dbau1x00.h |3 ++-
include/configs/gth2.h |3 ++-
include/configs/incaip.h|3 ++-
include/configs/pb1x00.h|3 ++-
include/configs/purple.h|3 ++-
include/configs/qemu-mips.h |3 ++-
include/configs/tb0229.h|3 ++-
Ok.
diff --git a/lib_mips/time.c b/lib_mips/time.c
index cd8dc72..4807f1a 100644
--- a/lib_mips/time.c
+++ b/lib_mips/time.c
@@ -23,23 +23,57 @@
#include common.h
+/* CFG_MIPS_CLOCK is the number of ticks per second of the MIPS C0 Clock
timer.
+ *
+ * For most implementations, this is the same as the CPU speed in HZ
+ * divided by 2. Some embedded MIPS implementations may use a /4
+ * or /1 divider, so see your CPU reference manual for specific details.
+ */
+#ifndef CFG_MIPS_CLOCK
+#error CFG_MIPS_CLOCK must be set in the board configuration file
+#endif
+static struct {
+ uint32_t lo;
+ uint32_t hi;
+} mips_ticks;/* Last number of ticks seen */
See below.
+/* Input is in CFG_HZ ticks */
static inline void mips_compare_set(u32 v)
{
+ v *= (CFG_MIPS_CLOCK / CFG_HZ);
asm volatile (mtc0 %0, $11 : : r (v));
}
I tend to remove these mips_{count,compare}_{get,set} functions because
they can be (and should be) replaced {read,write}_32bit_ cp0_register,
IMO.
And I want to handle (CFG_MIPS_CLOCK/CFG_HZ) stuffs or something like
that at udelay() side.
+/* Returns CFG_HZ ticks
+ *
+ * NOTE: This must be called at least once every
+ * few seconds to be reliable.
+ */
static inline u32 mips_count_get(void)
{
u32 count;
asm volatile (mfc0 %0, $9 : =r (count) :);
+
+ /* Handle 32-bit timer overflow */
+ if (count mips_ticks.lo) {
+ mips_ticks.hi++;
+ }
+ mips_ticks.lo = count;
+ count =(mips_ticks.lo / (CFG_MIPS_CLOCK / CFG_HZ)) +
+(mips_ticks.hi * (0x1ULL / (CFG_MIPS_CLOCK / CFG_HZ)));
+
return count;
}
I disagree with having this structure. Basic strategy for MIPS COUNT/
COMPARE handling is, let them overflow (os should I say wrap-around) as
they are. All we need is the Delta, not the numbers of overflows.
@@ -75,7 +109,7 @@ void udelay (unsigned long usec)
ulong tmo;
ulong start = get_timer(0);
- tmo = usec * (CFG_HZ / 100);
+ tmo = usec * CFG_HZ / 1000;
while ((ulong)((mips_count_get() - start)) tmo)
/*NOP*/;
}
Again, what is needed is `the Delta' between CP0.COUNT(Previous) and
CP0.COUNT(Current). This can be always achieved by
delta = COUNT(Curr) - COUNT(Prev)
regardless of COUNT value. Even if `(u32)0x0001 - (u32)0x',
it works.
I'll look around until this weekend. Sorry for inconvinience, and thank
you for working on this.
Shinya
-
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Re: [U-Boot-Users] [PATCH] mips: Call 'nand_init()' in generic board initialization when CONFIG_CMD_NAND is set
Hi Jason, Jason McMullan wrote: diff --git a/lib_mips/board.c b/lib_mips/board.c index 1645f2c..e33070d 100644 --- a/lib_mips/board.c +++ b/lib_mips/board.c @@ -28,6 +28,7 @@ #include version.h #include net.h #include environment.h +#include nand.h This will break build. According to the blackfin, we can't even include nand.h if it's not configured. http://git.denx.de/?p=u-boot.git;a=blob;f=lib_blackfin/board.c;h=43d8be8e21f25e37e7ade0eea86549b125775152;hb=a38dc3ea8614f8b0c41e432b445a9959b9711295#l25 # by the way, all ARCHs which need nand_init() should include nand.h in the same way as blackfin, shouldn't they? DECLARE_GLOBAL_DATA_PTR; @@ -416,6 +417,11 @@ void board_init_r (gd_t *id, ulong dest_addr) } #endif +#ifdef CONFIG_CMD_NAND + puts(NAND: ); + nand_init();/* go init the NAND */ +#endif + #if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ misc_init_r (); I'm not familiar with NAND, so don't know that above is a good timing to call nand_init(). If this works for you, I'm fine ATM. Thanks! Shinya - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] ColdFire: Get information from the correct GCC
Hi Kurt, Kurt Mahan wrote: Shinya Kuribayashi wrote: Liew Tsi Chung wrote: I am using Fedora 8. Also, the problem can be generated if using Fedora 4 and 5 except 3. If you have a Fedora 4 and above, please try it. I bet you will run into the same problem as Kurt and I did. I ran into the problem with OpenSuSE 10.2 I can't try Fedora[458] in the immediate future, sorry. But at last I'm convinced that it seems GNU make on those distros behaves in different ways; differed expansion of CFLAGS is suspicious, but I'm not going to dig into further. The version of make that I'm running is: ~ make --version GNU Make 3.81 me, too. But Debian's seems to have some extra bug fixes. As for Debian specific bugfixes, see [1]. Package: make State: installed Automatically installed: no Version: 3.81-4 Priority: optional Section: devel Maintainer: Manoj Srivastava [EMAIL PROTECTED] Uncompressed Size: 991k Depends: libc6 (= 2.7-1) Suggests: make-doc Description: The GNU version of the make utility. GNU Make is a program that determines which pieces of a large program need to be recompiled and issues the commands to recompile them, when necessary. More information about GNU Make can be found in the `make' Info page. The upstream sources for this package are available at the location ftp://ftp.gnu.org/gnu/make/. The documentation for this package does not meet the Debian Free Software Guidelines, and has been removed from this package. I reverted Debian specific patches and repackaged GNU make; this will be pure GNU make 3.81 release. Next, I reverted Wolfgang's config.mk patch and tried M54455EVB_config again. But this *still* works fine. Therefore I believe Debian's patches have no effect on our issue. At this moment, I'm interested in VPATH (or vpath) on those systems when finally generating PLATFORM_LIBS. Passing -print-data-base to make will help in that case. Otherwise, Fedora or OpenSuSE applies its specific patches on make... But anyway, it seems the problem is already verified. I'm not going to dig into further :-) thanks, Shinya [1] http://packages.debian.org/changelogs/pool/main/m/make-dfsg/make-dfsg_3.81-4/changelog - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] Allow building mips versions with ELDK 3.1.1
Wolfgang Denk wrote: In message [EMAIL PROTECTED] you wrote: .gpword works only with local symbols on certain binutils versions Signed-off-by: Vlad Lungu [EMAIL PROTECTED] --- cpu/mips/start.S |9 ++--- 1 files changed, 6 insertions(+), 3 deletions(-) Applied, thanks a lot. This fixes the start.S erros/warnings. This patch works with my two different CPUs. Thanks! So the only obvious problem remaining for MIPS are the cache.S warnings: cache.S:243: Warning: Pretending global symbol used as branch target is local. cache.S:250: Warning: Pretending global symbol used as branch target is local. Assembler might be sensitive to global symbol references under PIC code because they should be processed through GOT in principle. Therefore, we should have set up function entry point explicitly like: diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 8024a2e..7966079 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -239,14 +239,16 @@ NESTED(mips_cache_reset, 0, ra) */ movea1, t2 movea2, t4 - bal mips_init_icache + PTR_LA t7, mips_init_icache + jalrt7 /* * then initialize D-cache. */ movea1, t3 movea2, t5 - bal mips_init_dcache + PTR_LA t7, mips_init_dcache + jalrt7 jr RA END(mips_cache_reset) I'll post the patch later. thanks, Shinya - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [GIT PULL] MIPS updates
Dear Wolfgang, please pull MIPS update. Patch attached below. This will fix build warnings on cache.S. thanks, Shinya --- The following changes since commit 908261f3fdb418091d8c60bfbd7eb85e5869b579: Wolfgang Denk (1): Merge branch 'master' of git+ssh://10.10.0.7/home/wd/git/u-boot/master are available in the git repository at: git://git.denx.de/u-boot-mips.git master Shinya Kuribayashi (1): [MIPS] cpu/mips/cache.S: Fix build warning cpu/mips/cache.S |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) --- [MIPS] cpu/mips/cache.S: Fix build warning Some old GNU assemblers, such as v2.14 (ELDK 3.1.1), v2.16 (ELDK 4.1.0), warns illegal global symbol references by bal (and jal also) instruction. This does not happen with the latest binutils v2.18. Here's an example on gth2_config: mips_4KC-gcc -D__ASSEMBLY__ -g -Os -D__KERNEL__ -DTEXT_BASE=0x9000 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isy stem /opt/eldk311/usr/bin/../lib/gcc-lib/mips-linux/3.3.3/include -pipe -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -pipe -msoft-float -march=4kc -mtune=4k c -EB -c -o cache.o cache.S cache.S: Assembler messages: cache.S:243: Warning: Pretending global symbol used as branch target is local. cache.S:250: Warning: Pretending global symbol used as branch target is local. In principle, gas might be sensitive to global symbol references in PIC code because they should be processed through GOT (global offset table). But if `bal' instruction is used, it results in PC-based offset jump. This is the cause of this warning. In practice, we know it doesn't matter whether PC-based reference or GOT- based. As for this case, both will work before/after relocation. But let's fix the code. This patch explicitly sets up a target address, then jump there. Here's an example of disassembled code before/after this patch. 9668: 1485ffefbne a0,a1,9628 mips_cache_reset+0x20 966c: ac80fffcsw zero,-4(a0) 9670: 01402821movea1,t2 -9674: 0411ffbabal 9560 mips_init_icache -9678: 01803021movea2,t4 -967c: 01602821movea1,t3 -9680: 0411ffccbal 95b4 mips_init_dcache -9684: 01a03021movea2,t5 -9688: 0308jr t8 -968c: nop +9674: 01803021movea2,t4 +9678: 8f8f83eclw t7,-31764(gp) +967c: 01e0f809jalrt7 +9680: nop +9684: 01602821movea1,t3 +9688: 01a03021movea2,t5 +968c: 8f8f81e0lw t7,-32288(gp) +9690: 01e0f809jalrt7 +9694: nop +9698: 0308jr t8 +969c: nop Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- cpu/mips/cache.S |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 428d251..1b0efc3 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -240,14 +240,16 @@ NESTED(mips_cache_reset, 0, ra) */ movea1, t2 movea2, t4 - bal mips_init_icache + PTR_LA t7, mips_init_icache + jalrt7 /* * then initialize D-cache. */ movea1, t3 movea2, t5 - bal mips_init_dcache + PTR_LA t7, mips_init_dcache + jalrt7 jr RA END(mips_cache_reset) - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] ColdFire: Get information from the correct GCC
Liew Tsi Chung wrote: I am using Fedora 8. Also, the problem can be generated if using Fedora 4 and 5 except 3. If you have a Fedora 4 and above, please try it. I bet you will run into the same problem as Kurt and I did. I can't try Fedora[458] in the immediate future, sorry. But at last I'm convinced that it seems GNU make on those distros behaves in different ways; differed expansion of CFLAGS is suspicious, but I'm not going to dig into further. Could you confirm it builds with Today's config.mk patch by Wolfgang? If it works (I think it will), I'm satisfied with that. thanks for your comments, Shinya - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] commit 22069215 - [MIPS] Fix $gp usage
Wolfgang Denk wrote: start.S: Assembler messages: start.S:348: Error: relocation out of range make[1]: *** [start.o] Error 1 cache.S: Assembler messages: cache.S:243: Warning: Pretending global symbol used as branch target is local. cache.S:250: Warning: Pretending global symbol used as branch target is local. Confirmed both error and warning. I'll look into them. Jean-Christophe Plagniol-Villard reports that he sees no problems (no errors nor warnings) with binutils 2.18 Yes, it seems. I wonder if it was possible to come up with a version of the code that builds with somewhat older versions of the toolchains, too? I have no idea at the moment. Shinya - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] ColdFire: Get information from the correct GCC
Liew Tsi Chung wrote: Shinya, Which linux distro are you using? [snip] -Map u-boot.map -o u-boot m68k-uclinux-objcopy --gap-fill=0xff -O srec u-boot u-boot.srec m68k-uclinux-objcopy --gap-fill=0xff -O binary u-boot u-boot.bin [EMAIL PROTECTED]:~/devel/u-boot.git$ It's Debian lenny/testing. If any info required, please let me know. Shinya - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] ColdFire: Get information from the correct GCC
Liew Tsi Chung wrote: when gcc version is 4.2. When it comes to linking, the $(shell $(CC) --version) becomes other value and select the -m5407 option with different libgcc. I reverted this $(CC)-$(CROSS_COMPILE)gcc-conversion patch and built with M54455EVB_config and CodeSourcery's freescale-coldfire-4.2-125- m68k-uclinux-i686-pc-linux-gnu.tar.bz2. But couldn't reproduce. --- [snip] : make[1]: Entering directory `/home/skuribay/devel/u-boot.git/board/freescale/m54455evb' m68k-uclinux-gcc -g -Os -ffixed-d7 -msep-data -D__KERNEL__ -DTEXT_BASE=0x0400 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nos tdinc -isystem /opt/codesourcery/freescale-coldfire-4.2/bin/../lib/gcc/m68k-uclinux/4.2.3/include -pipe -DCONFIG_M68K -D__M68K__ -mcpu=54455 -fPIC -DTEXT_BASE =0x0400 -Wall -Wstrict-prototypes -c -o m54455evb.o m54455evb.c m68k-uclinux-gcc -g -Os -ffixed-d7 -msep-data -D__KERNEL__ -DTEXT_BASE=0x0400 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nos tdinc -isystem /opt/codesourcery/freescale-coldfire-4.2/bin/../lib/gcc/m68k-uclinux/4.2.3/include -pipe -DCONFIG_M68K -D__M68K__ -mcpu=54455 -fPIC -DTEXT_BASE =0x0400 -Wall -Wstrict-prototypes -c -o flash.o flash.c m68k-uclinux-gcc -g -Os -ffixed-d7 -msep-data -D__KERNEL__ -DTEXT_BASE=0x0400 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nos tdinc -isystem /opt/codesourcery/freescale-coldfire-4.2/bin/../lib/gcc/m68k-uclinux/4.2.3/include -pipe -DCONFIG_M68K -D__M68K__ -mcpu=54455 -fPIC -DTEXT_BASE =0x0400 -Wall -Wstrict-prototypes -c -o mii.o mii.c m68k-uclinux-ar crv libm54455evb.a m54455evb.o flash.o mii.o a - m54455evb.o a - flash.o a - mii.o make[1]: Leaving directory `/home/skuribay/devel/u-boot.git/board/freescale/m54455evb' make -C /home/skuribay/devel/u-boot.git/board/freescale/m54455evb/ u-boot.lds make[1]: Entering directory `/home/skuribay/devel/u-boot.git/board/freescale/m54455evb' make[1]: Nothing to be done for `u-boot.lds'. make[1]: Leaving directory `/home/skuribay/devel/u-boot.git/board/freescale/m54455evb' UNDEF_SYM=`m68k-uclinux-objdump -x board/freescale/m54455evb/libm54455evb.a lib_generic/libgeneric.a board/freescale/common/libfreescale.a cpu/mcf5445x/libmcf5445x.a lib_m68k/libm68k.a fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a net/libnet.a disk/libdisk.a drivers/bios_emulator/libatibiosemu.a drivers/block/libblock.a drivers/dma/libdma.a drivers/hwmon/libhwmon.a drivers/i2c/libi2c.a drivers/input/libinput.a drivers/misc/libmisc.a drivers/mtd/libmtd.a drivers/mtd/nand/libnand.a drivers/mtd/nand_legacy/libnand_legacy.a drivers/mtd/onenand/libonenand.a drivers/net/libnet.a drivers/net/sk98lin/libsk98lin.a drivers/pci/libpci.a drivers/pcmcia/libpcmcia.a drivers/spi/libspi.a drivers/rtc/librtc.a drivers/serial/libserial.a drivers/usb/libusb.a drivers/video/libvideo.a common/libcommon.a libfdt/libfdt.a api/libapi.a post/libpost.a | \ sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ cd /home/skuribay/devel/u-boot.git m68k-uclinux-ld -Bstatic -T /home/skuribay/devel/u-boot.git/board/freescale/m54455evb/u-boot.lds -n -Ttext 0x0400 $UNDEF_SYM cpu/mcf5445x/start.o \ --start-group lib_generic/libgeneric.a board/freescale/common/libfreescale.a cpu/mcf5445x/libmcf5445x.a lib_m68k/libm68k.a fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a net/libnet.a disk/libdisk.a drivers/bios_emulator/libatibiosemu.a drivers/block/libblock.a drivers/dma/libdma.a drivers/hwmon/libhwmon.a drivers/i2c/libi2c.a drivers/input/libinput.a drivers/misc/libmisc.a drivers/mtd/libmtd.a drivers/mtd/nand/libnand.a drivers/mtd/nand_legacy/libnand_legacy.a drivers/mtd/onenand/libonenand.a drivers/net/libnet.a drivers/net/sk98lin/libsk98lin.a drivers/pci/libpci.a drivers/pcmcia/libpcmcia.a drivers/spi/libspi.a drivers/rtc/librtc.a drivers/serial/libserial.a drivers/usb/libusb.a drivers/video/libvideo.a common/libcommon.a libfdt/libfdt.a api/libapi.a post/libpost.a board/freescale/m54455evb/libm54455evb.a --end-group -L /opt/codesourcery/freescale-coldfire-4.2/bin/../lib/gcc/m 68k-uclinux/4.2.3/msep-data -lgcc \ -Map u-boot.map -o u-boot m68k-uclinux-objcopy --gap-fill=0xff -O srec u-boot u-boot.srec m68k-uclinux-objcopy --gap-fill=0xff -O binary u-boot u-boot.bin [EMAIL PROTECTED]:~/devel/u-boot.git$ --- As already Wolfgang pointed out, `gcc -print-libgcc-file-name' of your toolchain seems weird. This might be buildroot problem? (1) Please show us the '-print-libgcc-file-name' part with your patch applied: $(CC) $(CFLAGS) -print-libgcc-file-name --- (without patch) /opt/freescale/usr/local/gcc-4.2.47-uclibc-0.9.47/
[U-Boot-Users] [GIT PULL] MIPS updates
Dear Wolfgang, please pull MIPS updates. 2 patches are there. One fixes a build failure caused by absence of dcache_enable(). The other is for a better handling of gas minor version (this isn't a kind of bug fix, but I'd like to push this for 1.3.3 release. Ok?). Each patch has not been posted to u-boot-users yet, so they will follow this mail. Please review (and apply). thanks, Shinya --- The following changes since commit 50f93d30dae3c5d888aa244d964ccd77be9b1c0c: Wolfgang Denk (1): Merge branch 'master' of git+ssh://10.10.0.7/home/wd/git/u-boot/master are available in the git repository at: git://git.denx.de/u-boot-mips.git master Shinya Kuribayashi (2): [MIPS] cpu/mips/cache.S: Add dcache_enable [MIPS] cpu/mips/config.mk: Fix GNU assembler minor version picker cpu/mips/cache.S | 16 cpu/mips/config.mk |2 +- 2 files changed, 17 insertions(+), 1 deletions(-) - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH][MIPS] cpu/mips/cache.S: Add dcache_enable
Recent bootelf command fixes (017e9b7925f74878d0e9475388cca9bda5ef9482, allow ports to override bootelf behavior) requires ports to have this function. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- cpu/mips/cache.S | 16 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index f593968..428d251 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -285,6 +285,22 @@ LEAF(dcache_disable) jr ra END(dcache_disable) +/*** +* +* dcache_enable - enable cache +* +* RETURNS: N/A +* +*/ +LEAF(dcache_enable) + mfc0t0, CP0_CONFIG + ori t0, CONF_CM_CMASK + xorit0, CONF_CM_CMASK + ori t0, CONF_CM_CACHABLE_NONCOHERENT + mtc0t0, CP0_CONFIG + jr ra + END(dcache_enable) + #ifdef CFG_INIT_RAM_LOCK_MIPS /*** * - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH][MIPS] cpu/mips/config.mk: Fix GNU assembler minor version picker
Current trick to pick up GNU assembler minor version uses a dot(.) as a delimiter, and take the second field to obtain minor version number. But as can be expected, this doesn't work with a version string which has dots more than needs. Here's an example: $ mips-linux-gnu-as --version | grep 'GNU assembler' GNU assembler (Sourcery G++ Lite 4.2-129) 2.18.50.20080215 $ mips-linux-gnu-as --version | grep 'GNU assembler' | cut -d. -f2 2-129) 2 $ This patch restricts the version format to 2.XX.XX... This will work in most cases. $ mips-linux-gnu-as --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' 2.18.50.20080215 $ mips-linux-gnu-as --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2 18 $ Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- cpu/mips/config.mk |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk index b505a42..a173c54 100644 --- a/cpu/mips/config.mk +++ b/cpu/mips/config.mk @@ -20,7 +20,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -v=$(shell $(AS) --version |grep GNU assembler |cut -d. -f2) +v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2) MIPSFLAGS:=$(shell \ if [ $v -lt 14 ]; then \ echo -mcpu=4kc; \ - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] ColdFire: Get information from the correct GCC
Tsi-Chung Liew wrote: cpu/mcf523x/config.mk|2 +- cpu/mcf52x2/config.mk|2 +- cpu/mcf532x/config.mk|2 +- cpu/mcf5445x/config.mk |2 +- cpu/mcf547x_8x/config.mk |2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/cpu/mcf5227x/config.mk b/cpu/mcf5227x/config.mk index 8d60fd6..2e50696 100644 --- a/cpu/mcf5227x/config.mk +++ b/cpu/mcf5227x/config.mk @@ -24,7 +24,7 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data -ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +ifeq ($(findstring 4.2,$(shell $(CROSS_COMPILE)gcc --version)),4.2) PLATFORM_CPPFLAGS += -mcpu=5208 -fPIC else PLATFORM_CPPFLAGS += -m5307 -fPIC Let me make sure the intention of this change. With or without this change, we can always evaluate $(CROSS_COMPILE)gcc --version, right? Or am I missing something? There are several $(CC)/$(AR)/$(AS)/$(CPP) users in cpu/*/Makefile cpu/*/config.mk. I'm wondering whether we need to fix all these usages or not. Thanks in advance, Shinya - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] Update .gitignore for zlib.h
Kumar Gala wrote: Signed-off-by: Kumar Gala [EMAIL PROTECTED] --- tools/.gitignore |1 + 1 files changed, 1 insertions(+), 0 deletions(-) Acked-by: Shinya Kuribayashi [EMAIL PROTECTED] - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 2/2 V2] qemu-mips: add full functionnalty and support of CONFIG_SMALLEST
Wolfgang Denk wrote: In message [EMAIL PROTECTED] you wrote: add support of : #define CONFIG_CMD_ASKENV #define CONFIG_CMD_LOADS #define CONFIG_CMD_LOADB #define CONFIG_CMD_PING #define CONFIG_CMD_CDP #define CONFIG_CMD_SAVES #define CONFIG_CMD_SETEXPR and keep only : tftp and dhcp support when CONFIG_SMALLEST is active What is the difference between the first patch and patch V2? What is CONFIG_SMALLEST ? What is full functionnalty? Although I said (I) will push in a week or two before, but I'll drop this patch from my pull-request list, since it needs to be logically sorted out a little more. Jean, I recommend to change only CFI-support addition stuff. No need to make things complicated, no commands cleanups, no CodinStyle cleanups. Best regards, Wolfgang Denk -- Shinya Kuribayashi NEC Electronics - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 2/2 V2] qemu-mips: add full functionnalty and support of CONFIG_SMALLEST
Shinya Kuribayashi wrote: Wolfgang Denk wrote: In message [EMAIL PROTECTED] you wrote: add support of : #define CONFIG_CMD_ASKENV #define CONFIG_CMD_LOADS #define CONFIG_CMD_LOADB #define CONFIG_CMD_PING #define CONFIG_CMD_CDP #define CONFIG_CMD_SAVES #define CONFIG_CMD_SETEXPR and keep only : tftp and dhcp support when CONFIG_SMALLEST is active What is the difference between the first patch and patch V2? What is CONFIG_SMALLEST ? What is full functionnalty? Although I said (I) will push in a week or two before, but I'll drop this patch from my pull-request list, since it needs to be logically sorted out a little more. Jean, I recommend to change only CFI-support addition stuff. No need to make things complicated, no commands cleanups, no CodinStyle cleanups. I'm sorry, incorrect thread... -- Shinya Kuribayashi NEC Electronics - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [MIPS] doc/README.mips: Add MIPS notes
This is for 1.3.3 release. Please review. Thanks, Shinya Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- doc/README.mips | 58 +++ 1 files changed, 58 insertions(+), 0 deletions(-) create mode 100644 doc/README.mips diff --git a/doc/README.mips b/doc/README.mips new file mode 100644 index 000..a5fcae9 --- /dev/null +++ b/doc/README.mips @@ -0,0 +1,58 @@ + +Notes for the MIPS architecture port of U-Boot + +Toolchains +-- + + http://www.denx.de/wiki/DULG/ELDK + ELDK DULG DENX + + http://www.emdebian.org/crosstools.html + Embedded Debian -- Cross-development toolchains + + http://buildroot.uclibc.org/ + Buildroot + +Known Issues + + + * Little endian build problem + +If use non-ELDK toolchains, -EB will be set to CPPFLAGS. Therefore all +objects will be generated in big-endian format. + + * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c + +Cache will be disabled before entering the loaded ELF image without +writing back and invalidating cache lines. This leads to cache +incoherency in most cases, unless the code gets loaded after U-Boot +re-initializes the cache. The more common uImage 'bootm' command does +not suffer this problem. + +[workaround] To avoid this cache incoherency, +1) insert flush_cache(all) before calling dcache_disable(), or +2) fix dcache_disable() to do both flushing and disabling cache. + + * Note that Linux users need to kill dcache_disable() in do_bootelf_exec() +or override do_bootelf_exec() not to disable I-/D-caches, because most +Linux/MIPS ports don't re-enable caches after entering kernel_entry. + +TODOs +- + + * Probe CPU types, I-/D-cache and TLB size etc. automatically + + * Secondary cache support missing + + * Centralize the link directive files + + * Initialize TLB entries redardless of their use + + * R2000/R3000 class parts are not supported + + * Limited testing across different MIPS variants + + * Due to cache initialization issues, the DRAM on board must be +initialized in board specific assembler language before the cache init +code is run -- that is, initialize the DRAM in lowlevel_init(). + - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 1/2][MIPS] qemu-mips: Cleanup whiespaces, tab indentations, etc.
No functional change.
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
include/configs/qemu-mips.h | 65 +--
1 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index e164019..be00356 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -28,25 +28,25 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
-#define CONFIG_QEMU_MIPS1
+#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
+#define CONFIG_QEMU_MIPS 1
#define CONFIG_MISC_INIT_R
/*IP address is default used by Qemu*/
-#define CONFIG_IPADDR 10.0.2.15/* Our IP address */
-#define CONFIG_SERVERIP10.0.2.2 /* Server IP
address*/
+#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
+#define CONFIG_SERVERIP10.0.2.2/* Server IP address */
-#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds*/
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
#define CONFIG_BAUDRATE115200
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#defineCONFIG_TIMESTAMP/* Print image info with
timestamp */
-#undef CONFIG_BOOTARGS
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
-#defineCONFIG_EXTRA_ENV_SETTINGS
\
+#define CONFIG_EXTRA_ENV_SETTINGS \
addmisc=setenv bootargs ${bootargs} \
console=ttyS0,${baudrate} \
panic=1\0 \
@@ -56,7 +56,6 @@
#define CONFIG_BOOTCOMMAND bootp;bootelf
-
/*
* BOOTP options
*/
@@ -65,7 +64,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
@@ -74,10 +72,10 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_DHCP
#define CONFIG_DRIVER_NE2000
@@ -86,15 +84,15 @@
#define CFG_NO_FLASH
#define CFG_NS16550
#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE1
-#define CFG_NS16550_CLK 115200
-#define CFG_NS16550_COM1(0xb40003f8)
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK115200
+#define CFG_NS16550_COM1 (0xb40003f8)
#define CONFIG_CONS_INDEX 1
#define CONFIG_CMD_IDE
#define CONFIG_DOS_PARTITION
-#define CFG_IDE_MAXBUS 2
+#define CFG_IDE_MAXBUS 2
#define CFG_ATA_IDE0_OFFSET(0x1f0)
#define CFG_ATA_IDE1_OFFSET(0x170)
#define CFG_ATA_DATA_OFFSET(0)
@@ -106,18 +104,18 @@
/*
* Miscellaneous configurable options
*/
-#defineCFG_LONGHELP/* undef to save memory
*/
+#define CFG_LONGHELP /* undef to save memory */
-#defineCFG_PROMPT qemu-mips # /* Monitor Command
Prompt*/
+#define CFG_PROMPT qemu-mips # /* Monitor Command Prompt */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2
-#defineCFG_CBSIZE 256 /* Console I/O Buffer
Size */
-#defineCFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer
Size */
-#defineCFG_MAXARGS 16 /* max number of
command args*/
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS16 /* max number of command args */
#define CFG_MALLOC_LEN 128*1024
@@ -125,11 +123,11 @@
#define CFG_MHZ132
-#define CFG_HZ (CFG_MHZ * 100)
+#define CFG_HZ (CFG_MHZ * 100)
-#define CFG_SDRAM_BASE 0x8000 /* Cached addr */
+#define CFG_SDRAM_BASE 0x8000 /* Cached addr */
-#defineCFG_LOAD_ADDR 0x8100 /* default load address
*/
+#define CFG_LOAD_ADDR 0x8100
[U-Boot-Users] [PATCH 2/2][MIPS] qemu-mips.h: Add CFI support
From: Jean-Christophe PLAGNIOL-VILLARD [EMAIL PROTECTED] CONFIG_ENV_OVERWRITE is also added. This patch is originally created by Jean-Christophe PLAGNIOL-VILLARD. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD [EMAIL PROTECTED] Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- include/configs/qemu-mips.h | 15 ++- 1 files changed, 10 insertions(+), 5 deletions(-) diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index be00356..46bfee7 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -72,8 +72,6 @@ #define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT2 -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_FLASH #undef CONFIG_CMD_LOADB #undef CONFIG_CMD_LOADS #define CONFIG_CMD_DHCP @@ -81,7 +79,6 @@ #define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_NE2000_BASE (0xb4000300) -#define CFG_NO_FLASH #define CFG_NS16550 #define CFG_NS16550_SERIAL #define CFG_NS16550_REG_SIZE 1 @@ -144,11 +141,19 @@ /* We boot from this flash, selected with dip switch */ #define CFG_FLASH_BASE 0xbfc0 +#define CFG_MAX_FLASH_BANKS1 +#define CFG_MAX_FLASH_SECT 128 +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_ENV_IS_NOWHERE 1 +#define CFG_ENV_IS_IN_FLASH1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4) /* Address and size of Primary Environment Sector */ -#define CFG_ENV_SIZE 0x1 +#define CFG_ENV_SIZE 0x8000 + +#define CONFIG_ENV_OVERWRITE 1 #undef CONFIG_NET_MULTI - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 1/2][MIPS] qemu-mips: Cleanup whiespaces, tab indentations, etc.
Wolfgang Denk wrote:
@@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Why are you changing this? It is a good old tradition of typesetters
to user wieder horizontal spacing after a full stop.
See for example the file COPYING which does this consequently.
Please leave this as is.
Didn't know that, sorry. Patch revised.
[MIPS] qemu-mips: Cleanup whiespaces, tab indentations, etc.
No functional change.
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
include/configs/qemu-mips.h | 63 +--
1 files changed, 31 insertions(+), 32 deletions(-)
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index e164019..c91525e 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -28,25 +28,25 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
-#define CONFIG_QEMU_MIPS1
+#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
+#define CONFIG_QEMU_MIPS 1
#define CONFIG_MISC_INIT_R
/*IP address is default used by Qemu*/
-#define CONFIG_IPADDR 10.0.2.15/* Our IP address */
-#define CONFIG_SERVERIP10.0.2.2 /* Server IP
address*/
+#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
+#define CONFIG_SERVERIP10.0.2.2/* Server IP address */
-#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds*/
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
#define CONFIG_BAUDRATE115200
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#defineCONFIG_TIMESTAMP/* Print image info with
timestamp */
-#undef CONFIG_BOOTARGS
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
-#defineCONFIG_EXTRA_ENV_SETTINGS
\
+#define CONFIG_EXTRA_ENV_SETTINGS \
addmisc=setenv bootargs ${bootargs} \
console=ttyS0,${baudrate} \
panic=1\0 \
@@ -56,7 +56,6 @@
#define CONFIG_BOOTCOMMAND bootp;bootelf
-
/*
* BOOTP options
*/
@@ -65,7 +64,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
@@ -74,10 +72,10 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_DHCP
#define CONFIG_DRIVER_NE2000
@@ -86,15 +84,15 @@
#define CFG_NO_FLASH
#define CFG_NS16550
#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE1
-#define CFG_NS16550_CLK 115200
-#define CFG_NS16550_COM1(0xb40003f8)
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK115200
+#define CFG_NS16550_COM1 (0xb40003f8)
#define CONFIG_CONS_INDEX 1
#define CONFIG_CMD_IDE
#define CONFIG_DOS_PARTITION
-#define CFG_IDE_MAXBUS 2
+#define CFG_IDE_MAXBUS 2
#define CFG_ATA_IDE0_OFFSET(0x1f0)
#define CFG_ATA_IDE1_OFFSET(0x170)
#define CFG_ATA_DATA_OFFSET(0)
@@ -106,18 +104,18 @@
/*
* Miscellaneous configurable options
*/
-#defineCFG_LONGHELP/* undef to save memory
*/
+#define CFG_LONGHELP /* undef to save memory */
-#defineCFG_PROMPT qemu-mips # /* Monitor Command
Prompt*/
+#define CFG_PROMPT qemu-mips # /* Monitor Command Prompt */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2
-#defineCFG_CBSIZE 256 /* Console I/O Buffer
Size */
-#defineCFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer
Size */
-#defineCFG_MAXARGS 16 /* max number of
command args*/
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS16 /* max number of command args */
#define CFG_MALLOC_LEN 128*1024
@@ -125,11 +123,11 @@
#define CFG_MHZ132
-#define CFG_HZ (CFG_MHZ * 100)
+#define CFG_HZ (CFG_MHZ * 100
Re: [U-Boot-Users] [PATCH 1/2][MIPS] qemu-mips: Cleanup whiespaces, tab indentations, etc.
Jean-Christophe PLAGNIOL-VILLARD wrote:
Please add the sof of the first author of the patch from who you
deriverd.
Sorry for that. Patch revised.
[MIPS] qemu-mips.h: Cleanup whiespaces, tab indentations, etc.
No functional change.
This patch was originally submitted by Jean-Christophe PLAGNIOL-VILLARD.
Then I re-created from scratch, and changed more lines than the original.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD [EMAIL PROTECTED]
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
include/configs/qemu-mips.h | 65 +--
1 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index e164019..931eccc 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -22,31 +22,31 @@
*/
/*
- * This file contains the configuration parameters for the dbau1x00 board.
+ * This file contains the configuration parameters for qemu-mips target.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
-#define CONFIG_QEMU_MIPS1
+#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
+#define CONFIG_QEMU_MIPS 1
#define CONFIG_MISC_INIT_R
/*IP address is default used by Qemu*/
-#define CONFIG_IPADDR 10.0.2.15/* Our IP address */
-#define CONFIG_SERVERIP10.0.2.2 /* Server IP
address*/
+#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
+#define CONFIG_SERVERIP10.0.2.2/* Server IP address */
-#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds*/
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
#define CONFIG_BAUDRATE115200
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#defineCONFIG_TIMESTAMP/* Print image info with
timestamp */
-#undef CONFIG_BOOTARGS
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
-#defineCONFIG_EXTRA_ENV_SETTINGS
\
+#define CONFIG_EXTRA_ENV_SETTINGS \
addmisc=setenv bootargs ${bootargs} \
console=ttyS0,${baudrate} \
panic=1\0 \
@@ -56,7 +56,6 @@
#define CONFIG_BOOTCOMMAND bootp;bootelf
-
/*
* BOOTP options
*/
@@ -65,7 +64,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
@@ -74,10 +72,10 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_DHCP
#define CONFIG_DRIVER_NE2000
@@ -86,15 +84,15 @@
#define CFG_NO_FLASH
#define CFG_NS16550
#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE1
-#define CFG_NS16550_CLK 115200
-#define CFG_NS16550_COM1(0xb40003f8)
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK115200
+#define CFG_NS16550_COM1 (0xb40003f8)
#define CONFIG_CONS_INDEX 1
#define CONFIG_CMD_IDE
#define CONFIG_DOS_PARTITION
-#define CFG_IDE_MAXBUS 2
+#define CFG_IDE_MAXBUS 2
#define CFG_ATA_IDE0_OFFSET(0x1f0)
#define CFG_ATA_IDE1_OFFSET(0x170)
#define CFG_ATA_DATA_OFFSET(0)
@@ -106,18 +104,18 @@
/*
* Miscellaneous configurable options
*/
-#defineCFG_LONGHELP/* undef to save memory
*/
+#define CFG_LONGHELP /* undef to save memory */
-#defineCFG_PROMPT qemu-mips # /* Monitor Command
Prompt*/
+#define CFG_PROMPT qemu-mips # /* Monitor Command Prompt */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2
-#defineCFG_CBSIZE 256 /* Console I/O Buffer
Size */
-#defineCFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer
Size */
-#defineCFG_MAXARGS 16 /* max number of
command args*/
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS16 /* max number of command args */
#define CFG_MALLOC_LEN 128*1024
@@ -125,11 +123,11 @@
#define CFG_MHZ132
-#define CFG_HZ (CFG_MHZ * 100)
+#define CFG_HZ (CFG_MHZ * 100)
-#define CFG_SDRAM_BASE 0x8000
[U-Boot-Users] [PATCH][MIPS] Use jr as register jump instruction
Current assembler codes are inconsistent in the way of register jump instruction usage; some use jr, some use j. Of course GNU as allows both usages, but as can be expected from `Jump Register' the mnemonic `jr' is more intuitive than `j'. For example, Linux doesn't have `j reg' usage at all. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- board/dbau1x00/lowlevel_init.S |2 +- board/gth2/lowlevel_init.S |2 +- board/incaip/lowlevel_init.S|8 board/pb1x00/lowlevel_init.S|2 +- board/purple/lowlevel_init.S|2 +- board/qemu-mips/lowlevel_init.S |2 +- cpu/mips/cache.S|4 ++-- cpu/mips/incaip_wdt.S |2 +- cpu/mips/start.S|6 +++--- 9 files changed, 15 insertions(+), 15 deletions(-) diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S index 14a7846..27b51f7 100644 --- a/board/dbau1x00/lowlevel_init.S +++ b/board/dbau1x00/lowlevel_init.S @@ -586,5 +586,5 @@ noCacheJump: sw t1, 0(t0) sync - j ra + jr ra nop diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S index eea378a..bf615c1 100644 --- a/board/gth2/lowlevel_init.S +++ b/board/gth2/lowlevel_init.S @@ -450,7 +450,7 @@ mtc:sw zero, 0(t0) nop nop memtestend: - j ra + jr ra nop memhang: diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S index b39f93d..08f7f21 100644 --- a/board/incaip/lowlevel_init.S +++ b/board/incaip/lowlevel_init.S @@ -105,7 +105,7 @@ __ebu_init: li t2, 0x684143FD sw t2, EBU_BUSCON1(t1) 3: - j ra + jr ra nop .endebu_init @@ -170,7 +170,7 @@ __cgu_init: li t2, 0x8001 sw t2, CGU_MUXCR(t1) 5: - j ra + jr ra nop .endcgu_init @@ -266,7 +266,7 @@ __sdram_init: li t2, 0x0001 sw t2, MC_CTRLENA(t1) - j ra + jr ra nop .endsdram_init @@ -298,7 +298,7 @@ lowlevel_init: nop movera, t0 - j ra + jr ra nop .endlowlevel_init diff --git a/board/pb1x00/lowlevel_init.S b/board/pb1x00/lowlevel_init.S index e851e2f..98bb394 100644 --- a/board/pb1x00/lowlevel_init.S +++ b/board/pb1x00/lowlevel_init.S @@ -388,5 +388,5 @@ skip_memsetup: */ sync - j ra + jr ra nop diff --git a/board/purple/lowlevel_init.S b/board/purple/lowlevel_init.S index 668124a..b9d03fc 100644 --- a/board/purple/lowlevel_init.S +++ b/board/purple/lowlevel_init.S @@ -33,5 +33,5 @@ lowlevel_init: li t0, MC_IOGP li t1, 0xf24 sw t1, 0(t0) - j ra + jr ra nop diff --git a/board/qemu-mips/lowlevel_init.S b/board/qemu-mips/lowlevel_init.S index 28166bc..836e027 100644 --- a/board/qemu-mips/lowlevel_init.S +++ b/board/qemu-mips/lowlevel_init.S @@ -37,5 +37,5 @@ lowlevel_init: mtc0zero, CP0_WIRED nop - j ra + jr ra nop diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 89ada71..f593968 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -282,7 +282,7 @@ LEAF(dcache_disable) and t0, t0, t1 ori t0, t0, CONF_CM_UNCACHED mtc0t0, CP0_CONFIG - j ra + jr ra END(dcache_disable) #ifdef CFG_INIT_RAM_LOCK_MIPS @@ -308,7 +308,7 @@ mips_cache_lock: movea1, a2 icacheop(a0,a1,a2,a3,0x1d) - j ra + jr ra .endmips_cache_lock #endif /* CFG_INIT_RAM_LOCK_MIPS */ diff --git a/cpu/mips/incaip_wdt.S b/cpu/mips/incaip_wdt.S index 71adaa1..2ebcc91 100644 --- a/cpu/mips/incaip_wdt.S +++ b/cpu/mips/incaip_wdt.S @@ -68,5 +68,5 @@ disable_incaip_wdt: li t1, WD_WRITE_ENDINIT sw t1, WD_CON0(t0) /* end command */ - j ra + jr ra nop diff --git a/cpu/mips/start.S b/cpu/mips/start.S index baac2ce..6e1a78c 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -286,7 +286,7 @@ reset: la sp, 0(t0) la t9, board_init_f - j t9 + jr t9 nop /* @@ -342,7 +342,7 @@ relocate_code: /* Jump to where we've relocated ourselves. */ addit0, a2, in_ram - _start - j t0 + jr t0 nop .gpword _GLOBAL_OFFSET_TABLE_ /* _GLOBAL_OFFSET_TABLE_ - _gp */ @@ -387,7 +387,7 @@ in_ram: movea0, a1 la t9, board_init_r - j t9 + jr t9 movea1, a2 /* delay slot */ .endrelocate_code - This SF.net email is sponsored
Re: [U-Boot-Users] [PATCH] qemu-mips: add CFI support
Hi Jean, Jean-Christophe PLAGNIOL-VILLARD wrote: Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD [EMAIL PROTECTED] diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index e164019..7ee6fd4 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -33,7 +33,7 @@ #define CONFIG_MISC_INIT_R /*IP address is default used by Qemu*/ -#define CONFIG_IPADDR10.0.2.15/* Our IP address */ +#define CONFIG_IPADDR10.0.2.15/* Our IP address */ #define CONFIG_SERVERIP 10.0.2.2 /* Server IP address*/ #define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds*/ @@ -74,16 +74,12 @@ #define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT2 -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS #define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING #define CONFIG_DRIVER_NE2000 This patch contains as many fixes as CFI related changes (above). In that case, please add some notes about them or change the subject. I applied the patch below. If something wrong, please let me know. Or will push in a week or two :-) Shinya [MIPS] qemu-mips.h: Update config header From: Jean-Christophe PLAGNIOL-VILLARD [EMAIL PROTECTED] - Add CFI support - Add CONFIG_CMD_PING since qemu-mips has NE2000 driver enabled - Cleanup whitespaces and remove #undef CMD lines Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD [EMAIL PROTECTED] Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- include/configs/qemu-mips.h | 24 +--- 1 files changed, 13 insertions(+), 11 deletions(-) diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index e164019..7ee6fd4 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -33,7 +33,7 @@ #define CONFIG_MISC_INIT_R /*IP address is default used by Qemu*/ -#define CONFIG_IPADDR 10.0.2.15/* Our IP address */ +#define CONFIG_IPADDR 10.0.2.15/* Our IP address */ #define CONFIG_SERVERIP10.0.2.2 /* Server IP address*/ #define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds*/ @@ -74,16 +74,12 @@ #define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT2 -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS #define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING #define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_NE2000_BASE (0xb4000300) -#define CFG_NO_FLASH #define CFG_NS16550 #define CFG_NS16550_SERIAL #define CFG_NS16550_REG_SIZE1 @@ -140,17 +136,23 @@ /* The following #defines are needed to get flash environment right */ #defineCFG_MONITOR_BASETEXT_BASE -#defineCFG_MONITOR_LEN (192 10) +#defineCFG_MONITOR_LEN (192 11) #define CFG_INIT_SP_OFFSET 0x40 /* We boot from this flash, selected with dip switch */ #define CFG_FLASH_BASE 0xbfc0 - -#defineCFG_ENV_IS_NOWHERE 1 - +#defineCFG_MAX_FLASH_BANKS 1 +#defineCFG_MAX_FLASH_SECT 128 +#defineCFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_USE_BUFFER_WRITE1 + +#defineCFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x6) /* Address and size of Primary Environment Sector */ -#define CFG_ENV_SIZE 0x1 +#define CFG_ENV_SIZE 0x8000 + #undef CONFIG_NET_MULTI #define MEM_SIZE 128 - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [MIPS] cpu/mips/cpu.c: Fix flush_cache bug
Cache operations have to take line address (addr), not start_addr.
I noticed this bug when debugging ping failure.
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
cpu/mips/cpu.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index 8b43d8e..e267bba 100644
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -56,8 +56,8 @@ void flush_cache(ulong start_addr, ulong size)
unsigned long aend = (start_addr + size - 1) ~(lsize - 1);
while (1) {
- cache_op(Hit_Writeback_Inv_D, start_addr);
- cache_op(Hit_Invalidate_I, start_addr);
+ cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(Hit_Invalidate_I, addr);
if (addr == aend)
break;
addr += lsize;
-
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Re: [U-Boot-Users] cache related query for MIPS
Chetan Nanda wrote: My question here is why cache is tried to flushed and disabled before jumping into start location? As described in source code, it seems be the QNX requirement. I don't know much about QNX, but archives probably help you. http://search.gmane.org/?query=bootelf+dcache_disableauthor=group=gmane.comp.boot-loaders.u-boot - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] Booting vxworks image from U-boot
Zvika Vered wrote: Is it possible to boot a vxworks ELF image using 'bootvx' ? I downloaded a vxworks 6.3 ELF image using 'tftpboot' and launched 'vxboot'. U-boot crashed. The vxworks ELF image is OK. When I download it using JTAG after reset it works. You have JTAG ICE connected, then debug it. How crash, what's the CPU status, what kind of exception happens, etc. I'm just wondering, how about changing tftp download address that cannot be bss cleared by VxWorks? Simply, near the top of RAM? - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] RFC: make new image support mandatory
Guennadi Liakhovetski wrote: HEAD. Which is almost 30% increase... Sorry, I didn't follow the new format discussion, is it also going to be useful on ARM and on other platforms not using FDT? As MIPS custodian I feel the same, too. I'm just wondering, if this feature is useful for all architectures and you say it's mandaroty, why not defining it in common.h or so? If you make it selectable, I hope we could build existing targets without CONFIG_FIT. Shinya - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB
Shinya Kuribayashi wrote: Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- cpu/mips/cache.S |9 + 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index bda9bb1..2998a3b 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -32,10 +32,11 @@ #define RA t8 - /* 16KB is the maximum size of instruction and data caches on - * MIPS 4K. - */ -#define MIPS_MAX_CACHE_SIZE 0x4000 +/* + * 16kB is the maximum size of instruction and data caches on MIPS 4K, + * 64kB is on 4KE, 24K, 5K, 34K, etc. Set bigger size for convenience. + */ +#define MIPS_MAX_CACHE_SIZE 0x1 #define INDEX_BASE KSEG0 Revised patch is attached. - add some comments on L2 cache, - and cache.S is no longer 4K specific routines now! [MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB From: Shinya Kuribayashi [EMAIL PROTECTED] Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- cpu/mips/cache.S | 14 +- 1 files changed, 9 insertions(+), 5 deletions(-) diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index e6f3175..89ada71 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -1,5 +1,5 @@ /* - * Cache-handling routined for MIPS 4K CPUs + * Cache-handling routined for MIPS CPUs * * Copyright (c) 2003 Wolfgang Denk [EMAIL PROTECTED] * @@ -32,10 +32,14 @@ #define RA t8 - /* 16KB is the maximum size of instruction and data caches on -* MIPS 4K. -*/ -#define MIPS_MAX_CACHE_SIZE0x4000 +/* + * 16kB is the maximum size of instruction and data caches on MIPS 4K, + * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. + * + * Note that the above size is the maximum size of primary cache. U-Boot + * doesn't have L2 cache support for now. + */ +#define MIPS_MAX_CACHE_SIZE0x1 #define INDEX_BASE KSEG0 - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [MIPS] asm headers' updates
Shinya Kuribayashi wrote:
Wolfgang Denk wrote:
+#if 0
+#include linux/compiler.h
+#endif
Please don't add dead code. Instead, remove these line(s).
Fixed. Thanks,
Patch revised. I updated more files, and cleaned up CodingStyle issues
all over the headers,
[MIPS] asm headers' updates
Make some asm headers adjusted to the latest Linux kernel.
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
include/asm-mips/byteorder.h | 60 +-
include/asm-mips/cachectl.h | 10 +-
include/asm-mips/cacheops.h | 78 ++---
include/asm-mips/isadep.h|5 -
include/asm-mips/processor.h | 249 +-
include/asm-mips/ptrace.h| 67 ++-
include/asm-mips/reg.h | 134 ---
include/asm-mips/regdef.h| 126 +++--
include/asm-mips/types.h | 30 -
9 files changed, 416 insertions(+), 343 deletions(-)
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
index b9604cf..b5e685f 100644
--- a/include/asm-mips/byteorder.h
+++ b/include/asm-mips/byteorder.h
@@ -1,18 +1,62 @@
-/* $Id: byteorder.h,v 1.8 1998/11/02 09:29:32 ralf Exp $
- *
+/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
- * Copyright (C) by Ralf Baechle
+ * Copyright (C) 1996, 99, 2003 by Ralf Baechle
*/
-#ifndef _MIPS_BYTEORDER_H
-#define _MIPS_BYTEORDER_H
+#ifndef _ASM_BYTEORDER_H
+#define _ASM_BYTEORDER_H
#include asm/types.h
#ifdef __GNUC__
+#ifdef CONFIG_CPU_MIPSR2
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+ __asm__(
+ wsbh%0, %1 \n
+ : =r (x)
+ : r (x));
+
+ return x;
+}
+#define __arch__swab16(x) ___arch__swab16(x)
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+ __asm__(
+ wsbh%0, %1 \n
+ rotr%0, %0, 16 \n
+ : =r (x)
+ : r (x));
+
+ return x;
+}
+#define __arch__swab32(x) ___arch__swab32(x)
+
+#ifdef CONFIG_CPU_MIPS64_R2
+
+static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
+{
+ __asm__(
+ dsbh%0, %1 \n
+ dshd%0, %0 \n
+ drotr %0, %0, 32 \n
+ : =r (x)
+ : r (x));
+
+ return x;
+}
+
+#define __arch__swab64(x) ___arch__swab64(x)
+
+#endif /* CONFIG_CPU_MIPS64_R2 */
+
+#endif /* CONFIG_CPU_MIPSR2 */
+
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__
@@ -20,12 +64,12 @@
#endif /* __GNUC__ */
-#if defined (__MIPSEB__)
+#if defined(__MIPSEB__)
# include linux/byteorder/big_endian.h
-#elif defined (__MIPSEL__)
+#elif defined(__MIPSEL__)
# include linux/byteorder/little_endian.h
#else
# error MIPS, but neither __MIPSEB__, nor __MIPSEL__???
#endif
-#endif /* _MIPS_BYTEORDER_H */
+#endif /* _ASM_BYTEORDER_H */
diff --git a/include/asm-mips/cachectl.h b/include/asm-mips/cachectl.h
index 9cc2b87..f3ce721 100644
--- a/include/asm-mips/cachectl.h
+++ b/include/asm-mips/cachectl.h
@@ -1,10 +1,12 @@
/*
- * cachectl.h -- defines for MIPS cache control system calls
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
*
* Copyright (C) 1994, 1995, 1996 by Ralf Baechle
*/
-#ifndef__ASM_MIPS_CACHECTL
-#define__ASM_MIPS_CACHECTL
+#ifndef_ASM_CACHECTL
+#define_ASM_CACHECTL
/*
* Options for cacheflush system call
@@ -21,4 +23,4 @@
#define CACHEABLE 0 /* make pages cacheable */
#define UNCACHEABLE1 /* make pages uncacheable */
-#endif /* __ASM_MIPS_CACHECTL */
+#endif /* _ASM_CACHECTL */
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
index 66b0b36..256ad2c 100644
--- a/include/asm-mips/cacheops.h
+++ b/include/asm-mips/cacheops.h
@@ -5,43 +5,81 @@
* License. See the file COPYING in the main directory of this archive
* for more details.
*
- * (C) Copyright 1996, 1997 by Ralf Baechle
+ * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
+ * (C) Copyright 1999 Silicon Graphics, Inc.
*/
-#ifndef__ASM_MIPS_CACHEOPS_H
-#define__ASM_MIPS_CACHEOPS_H
+#ifndef__ASM_CACHEOPS_H
+#define__ASM_CACHEOPS_H
/*
- * Cache Operations
+ * Cache Operations available on all MIPS processors with R4000-style caches
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
-#define Index_Invalidate_SI 0x02
-#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
-#define Index_Load_Tag_SI 0x06
-#define
[U-Boot-Users] [MIPS] cpu/mips/Makefile: Change Makefile style
Split board-related objects with one line for one file. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- cpu/mips/Makefile | 18 -- 1 files changed, 12 insertions(+), 6 deletions(-) diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile index 92dcc16..c6caf1d 100644 --- a/cpu/mips/Makefile +++ b/cpu/mips/Makefile @@ -26,12 +26,18 @@ include $(TOPDIR)/config.mk LIB= $(obj)lib$(CPU).a START = start.o -COBJS = asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \ - cpu.o interrupts.o incaip_clock.o -SOBJS = incaip_wdt.o cache.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SOBJS-y= cache.o +COBJS-y= cpu.o interrupts.o + +COBJS-y+= asc_serial.o +COBJS-y+= au1x00_serial.o +COBJS-y+= au1x00_eth.o +COBJS-y+= au1x00_usb_ohci.o +COBJS-y+= incaip_clock.o +SOBJS-y+= incaip_wdt.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) START := $(addprefix $(obj),$(START)) all: $(obj).depend $(START) $(LIB) - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [MIPS] Move gth2_config from ARM section to MIPS
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- Makefile | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index 4fde699..d68b03d 100644 --- a/Makefile +++ b/Makefile @@ -2470,11 +2470,6 @@ cm4008_config: unconfig cm41xx_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t cm41xx NULL ks8695 -gth2_config: unconfig - @mkdir -p $(obj)include - @echo #define CONFIG_GTH2 1 $(obj)include/config.h - @$(MKCONFIG) -a gth2 mips mips gth2 - # ## S3C44B0 Systems # @@ -2677,6 +2672,11 @@ pb1000_config: unconfig @echo #define CONFIG_PB1000 1 $(obj)include/config.h @$(MKCONFIG) -a pb1x00 mips mips pb1x00 +gth2_config: unconfig + @mkdir -p $(obj)include + @echo #define CONFIG_GTH2 1 $(obj)include/config.h + @$(MKCONFIG) -a gth2 mips mips gth2 + qemu_mips_config: unconfig @mkdir -p $(obj)include @echo #define CONFIG_QEMU_MIPS 1 $(obj)include/config.h - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [MIPS] cpu/mips/Makefile: Change Makefile style
Shinya Kuribayashi wrote: @@ -26,12 +26,18 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START= start.o -COBJS= asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \ - cpu.o interrupts.o incaip_clock.o -SOBJS= incaip_wdt.o cache.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SOBJS-y = cache.o +COBJS-y = cpu.o interrupts.o + +COBJS-y += asc_serial.o +COBJS-y += au1x00_serial.o +COBJS-y += au1x00_eth.o +COBJS-y += au1x00_usb_ohci.o Hm, should this be something like COBJS-y += au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o ? +COBJS-y += incaip_clock.o +SOBJS-y += incaip_wdt.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) START:= $(addprefix $(obj),$(START)) all: $(obj).depend $(START) $(LIB) - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [MIPS] Fix dcache_status()
You can't judge UNCACHED by Config.K0 LSB. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- cpu/mips/cache.S | 10 +++--- 1 files changed, 7 insertions(+), 3 deletions(-) diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index bb42616..e6f3175 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -256,9 +256,13 @@ NESTED(mips_cache_reset, 0, ra) * */ LEAF(dcache_status) - mfc0v0, CP0_CONFIG - andiv0, v0, 1 - j ra + mfc0t0, CP0_CONFIG + li t1, CONF_CM_UNCACHED + andit0, t0, CONF_CM_CMASK + movev0, zero + beq t0, t1, 2f + li v0, 1 +2: jr ra END(dcache_status) /*** - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- cpu/mips/cache.S |9 + 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index bda9bb1..2998a3b 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -32,10 +32,11 @@ #define RA t8 - /* 16KB is the maximum size of instruction and data caches on -* MIPS 4K. -*/ -#define MIPS_MAX_CACHE_SIZE0x4000 +/* + * 16kB is the maximum size of instruction and data caches on MIPS 4K, + * 64kB is on 4KE, 24K, 5K, 34K, etc. Set bigger size for convenience. + */ +#define MIPS_MAX_CACHE_SIZE0x1 #define INDEX_BASE KSEG0 - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [MIPS] Cleanup CP0 Status initialization
Add setup_c0_status from Linux. For the moment we disable interrupts, set CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for reset-time configuration and will work well across most processors. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- cpu/mips/start.S | 34 +- 1 files changed, 25 insertions(+), 9 deletions(-) diff --git a/cpu/mips/start.S b/cpu/mips/start.S index 0ecdd83..baac2ce 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -27,6 +27,30 @@ #include asm/regdef.h #include asm/mipsregs.h + /* +* For the moment disable interrupts, mark the kernel mode and +* set ST0_KX so that the CPU does not spit fire when using +* 64-bit addresses. +*/ + .macro setup_c0_status set clr + .setpush + mfc0t0, CP0_STATUS + or t0, ST0_CU0 | \set | 0x1f | \clr + xor t0, 0x1f | \clr + mtc0t0, CP0_STATUS + .setnoreorder + sll zero, 3 # ehb + .setpop + .endm + + .macro setup_c0_status_reset +#ifdef CONFIG_64BIT + setup_c0_status ST0_KX 0 +#else + setup_c0_status 0 0 +#endif + .endm + #define RVECENT(f,n) \ b f; nop #define XVECENT(f,bev) \ @@ -214,15 +238,7 @@ reset: /* WP(Watch Pending), SW0/1 should be cleared. */ mtc0zero, CP0_CAUSE - /* STATUS register */ -#ifdef CONFIG_TB0229 - li k0, ST0_CU0 -#else - mfc0k0, CP0_STATUS -#endif - li k1, ~ST0_IE - and k0, k1 - mtc0k0, CP0_STATUS + setup_c0_status_reset /* Init Timer */ mtc0zero, CP0_COUNT - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [RFC][PATCH 1/1] Add board_eth_init() function
Hi Ben,
with a quick glance, find the comments below.
Ben Warren wrote:
diff --git a/include/netdev.h b/include/netdev.h
new file mode 100644
index 000..19195fa
--- /dev/null
+++ b/include/netdev.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2008
+ * Benjamin Warren, [EMAIL PROTECTED]
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * netdev.h - definitions an prototypes for network devices
+ */
+
+#ifndef _NETDEV_H_
+#define _NETDEV_H_
+
+int tsec_initialize(bd_t * bis, int index, char *devname);
+
+#endif /* _NETDEV_H_ */
+
+
Do we need such controller dependent declarations in netdev.h?
FWIW board_eth_init() is reasonable for me.
And I know we need to go on a step-by-step basis, do you have any
plan to have register/unregister interfaces?
Ah, remove the last 2 lines :-)
diff --git a/net/eth.c b/net/eth.c
index 16a6dcb..3d02272 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -28,6 +28,13 @@
#if defined(CONFIG_CMD_NET) defined(CONFIG_NET_MULTI)
+int __board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int board_eth_init(bd_t *bis) __attribute((weak,
alias(__board_eth_init)));
+
#ifdef CFG_GT_6426x
extern int gt6426x_eth_initialize(bd_t *bis);
#endif
[This comment is not for Ben, but for everyone.]
Do we need such alias to empty function? Only __attribute((weak)) is
enough for me. If we have some default behavior which isn't empty, I
can see the weak alias. Thought?
Shinya
-
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[U-Boot-Users] [MIPS] Implement flush_cache()
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
cpu/mips/cpu.c | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index 7559ac6..71e5028 100644
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -25,6 +25,17 @@
#include command.h
#include asm/inca-ip.h
#include asm/mipsregs.h
+#include asm/cacheops.h
+
+#define cache_op(op,addr) \
+ __asm__ __volatile__( \
+ .setpush\n \
+ .setnoreorder \n \
+ .setmips3\n\t \n \
+ cache %0, %1 \n \
+ .setpop \n \
+ : \
+ : i (op), R (*(unsigned char *)(addr)))
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
@@ -41,6 +52,16 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char
*argv[])
void flush_cache(ulong start_addr, ulong size)
{
+ unsigned long lsize = CFG_DCACHE_SIZE;
+ unsigned long addr = start_addr ~(lsize - 1);
+ unsigned long aend = (start_addr + size - 1) ~(lsize - 1);
+
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, start_addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
}
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-
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[U-Boot-Users] [MIPS] INCA-IP: Move watchdog init code from start.S to lowlevel_init()
Move things to reasonable place. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- board/incaip/lowlevel_init.S |6 ++ cpu/mips/start.S |8 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S index 14d738a..b39f93d 100644 --- a/board/incaip/lowlevel_init.S +++ b/board/incaip/lowlevel_init.S @@ -276,6 +276,12 @@ __sdram_init: .entlowlevel_init lowlevel_init: + /* Disable Watchdog. +*/ + la t9, disable_incaip_wdt + jalrt9 + nop + /* EBU, CGU and SDRAM Initialization. */ li a0, CPU_CLOCK_RATE diff --git a/cpu/mips/start.S b/cpu/mips/start.S index 901e3ef..784530d 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -240,14 +240,6 @@ reset: 1: lw gp, 0(ra) -#ifdef CONFIG_INCA_IP - /* Disable INCA-IP Watchdog. -*/ - la t9, disable_incaip_wdt - jalrt9 - nop -#endif - /* Initialize any external memory. */ la t9, lowlevel_init - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [MIPS] Introduce machine_restart
Handles machine specific functions by using function pointers.
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
board/incaip/incaip.c |8
board/purple/purple.c | 10 ++
board/tb0229/tb0229.c | 11 ++-
cpu/mips/cpu.c| 17 ++---
include/asm-mips/reboot.h | 15 +++
5 files changed, 53 insertions(+), 8 deletions(-)
create mode 100644 include/asm-mips/reboot.h
diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
index dbf0ecc..c2324bc 100644
--- a/board/incaip/incaip.c
+++ b/board/incaip/incaip.c
@@ -26,9 +26,15 @@
#include asm/addrspace.h
#include asm/inca-ip.h
#include asm/io.h
+#include asm/reboot.h
extern uint incaip_get_cpuclk(void);
+static void incaip_machine_restart(char *command)
+{
+ *INCA_IP_WDT_RST_REQ = 0x3f;
+}
+
static ulong max_sdram_size(void)
{
/* The only supported SDRAM data width is 16bit.
@@ -108,5 +114,7 @@ int checkboard (void)
set_io_port_base(0);
+ _machine_restart = incaip_machine_restart;
+
return 0;
}
diff --git a/board/purple/purple.c b/board/purple/purple.c
index 74718af..2fa2e19 100644
--- a/board/purple/purple.c
+++ b/board/purple/purple.c
@@ -29,6 +29,7 @@
#include asm/io.h
#include asm/addrspace.h
#include asm/cacheops.h
+#include asm/reboot.h
#include sconsole.h
@@ -52,6 +53,13 @@ extern int asc_serial_getc (void);
extern int asc_serial_tstc (void);
extern voidasc_serial_setbrg (void);
+static void purple_machine_restart(char *command)
+{
+ void (*f)(void) = (void *) 0xbfc0;
+
+ f();
+}
+
static void sdram_timing_init (ulong size)
{
register uint pass;
@@ -148,6 +156,8 @@ int checkboard (void)
set_io_port_base(0);
+ _machine_restart = purple_machine_restart;
+
return 0;
}
diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c
index 61c2e9b..c775069 100644
--- a/board/tb0229/tb0229.c
+++ b/board/tb0229/tb0229.c
@@ -12,9 +12,16 @@
#include common.h
#include command.h
#include asm/addrspace.h
-#include asm/inca-ip.h
#include asm/io.h
#include pci.h
+#include asm/reboot.h
+
+static void tb0229_machine_restart(char *command)
+{
+ void (*f)(void) = (void *) 0xbfc0;
+
+ f();
+}
#if defined(CONFIG_PCI)
static struct pci_controller hose;
@@ -37,5 +44,7 @@ int checkboard (void)
set_io_port_base(0);
+ _machine_restart = tb0229_machine_restart;
+
return 0;
}
diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index 71e5028..4c50829 100644
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -23,9 +23,9 @@
#include common.h
#include command.h
-#include asm/inca-ip.h
#include asm/mipsregs.h
#include asm/cacheops.h
+#include asm/reboot.h
#define cache_op(op,addr) \
__asm__ __volatile__( \
@@ -37,15 +37,18 @@
: \
: i (op), R (*(unsigned char *)(addr)))
+/*
+ * Urgs ... Too many MIPS machines to handle this in a generic way.
+ * So handle all using function pointers to machine specific
+ * functions.
+ */
+void (*_machine_restart)(char *command);
+
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
-#if defined(CONFIG_INCA_IP)
- *INCA_IP_WDT_RST_REQ = 0x3f;
-#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229)
- void (*f)(void) = (void *) 0xbfc0;
+ if (_machine_restart)
+ _machine_restart(NULL);
- f();
-#endif
fprintf(stderr, *** reset failed ***\n);
return 0;
}
diff --git a/include/asm-mips/reboot.h b/include/asm-mips/reboot.h
new file mode 100644
index 000..e48c0bf
--- /dev/null
+++ b/include/asm-mips/reboot.h
@@ -0,0 +1,15 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_REBOOT_H
+#define _ASM_REBOOT_H
+
+extern void (*_machine_restart)(char *command);
+extern void (*_machine_halt)(void);
+
+#endif /* _ASM_REBOOT_H */
-
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Re: [U-Boot-Users] [MIPS] Implement flush_cache()
Andrew Dyer wrote:
looking at how cache_flush() is used (see common/cmd_load.c,
common/cmd_elf.c, etc), I believe this loop should also do a cache_op
with Hit_Invalidate_I to invalidate the icache.
seems like it would be easier to read if the condition was included in
the while() statement
Hm, then is this ok?
diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index 7559ac6..e59c9c9 100644
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -25,6 +25,17 @@
#include command.h
#include asm/inca-ip.h
#include asm/mipsregs.h
+#include asm/cacheops.h
+
+#define cache_op(op,addr) \
+ __asm__ __volatile__( \
+ .setpush\n \
+ .setnoreorder \n \
+ .setmips3\n\t \n \
+ cache %0, %1 \n \
+ .setpop \n \
+ : \
+ : i (op), R (*(unsigned char *)(addr)))
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
@@ -41,6 +52,17 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char
*argv[])
void flush_cache(ulong start_addr, ulong size)
{
+ unsigned long lsize = CFG_DCACHE_SIZE;
+ unsigned long addr = start_addr ~(lsize - 1);
+ unsigned long aend = (start_addr + size - 1) ~(lsize - 1);
+
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, start_addr);
+ cache_op(Hit_Invalidate_I, start_addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
}
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-
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[U-Boot-Users] [RFC][MIPS] Remove mips_cache_lock
I don't know the background why this lock added. So if I miss something, please let me know. Or I'll push this before merge window close(). I don't see any reason why we have to lock cache line here. Maybe some targets require this locking, but that's completely target specific re- quirement and we should not have such things in global start codes. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- cpu/mips/cache.S | 26 -- cpu/mips/start.S |5 - 2 files changed, 0 insertions(+), 31 deletions(-) diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 443240e..9d793bf 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -237,29 +237,3 @@ dcache_disable: j ra .enddcache_disable - -/*** -* -* mips_cache_lock - lock RAM area pointed to by a0 in cache. -* -* RETURNS: N/A -* -*/ -#if defined(CONFIG_PURPLE) -# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2) -#else -# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE) -#endif - .globl mips_cache_lock - .entmips_cache_lock -mips_cache_lock: - li a1, K0BASE - CACHE_LOCK_SIZE - addua0, a1 - li a2, CACHE_LOCK_SIZE - li a3, CFG_CACHELINE_SIZE - movea1, a2 - icacheop(a0,a1,a2,a3,0x1d) - - j ra - - .endmips_cache_lock diff --git a/cpu/mips/start.S b/cpu/mips/start.S index c92b162..fd44da0 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -267,11 +267,6 @@ reset: /* Set up temporary stack. */ - li a0, CFG_INIT_SP_OFFSET - la t9, mips_cache_lock - jalrt9 - nop - li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET la sp, 0(t0) - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [MIPS] asm headers' updates
Make some asm headers adjusted to the latest Linux kernel. Note: there
might be some CodingStyle issues, but let's leave thins as they are to
have a clear difference against the Linux ones.
Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED]
---
include/asm-mips/byteorder.h | 63 ++
include/asm-mips/cachectl.h | 10 +++--
include/asm-mips/cacheops.h | 78 +++---
include/asm-mips/regdef.h| 60 +---
include/asm-mips/types.h | 31 +++--
5 files changed, 200 insertions(+), 42 deletions(-)
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
index b9604cf..a10ac27 100644
--- a/include/asm-mips/byteorder.h
+++ b/include/asm-mips/byteorder.h
@@ -1,18 +1,65 @@
-/* $Id: byteorder.h,v 1.8 1998/11/02 09:29:32 ralf Exp $
- *
+/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
- * Copyright (C) by Ralf Baechle
+ * Copyright (C) 1996, 99, 2003 by Ralf Baechle
*/
-#ifndef _MIPS_BYTEORDER_H
-#define _MIPS_BYTEORDER_H
+#ifndef _ASM_BYTEORDER_H
+#define _ASM_BYTEORDER_H
+#if 0
+#include linux/compiler.h
+#endif
#include asm/types.h
#ifdef __GNUC__
+#ifdef CONFIG_CPU_MIPSR2
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+ __asm__(
+ wsbh%0, %1 \n
+ : =r (x)
+ : r (x));
+
+ return x;
+}
+#define __arch__swab16(x) ___arch__swab16(x)
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+ __asm__(
+ wsbh%0, %1 \n
+ rotr%0, %0, 16 \n
+ : =r (x)
+ : r (x));
+
+ return x;
+}
+#define __arch__swab32(x) ___arch__swab32(x)
+
+#ifdef CONFIG_CPU_MIPS64_R2
+
+static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
+{
+ __asm__(
+ dsbh%0, %1 \n
+ dshd%0, %0 \n
+ drotr %0, %0, 32 \n
+ : =r (x)
+ : r (x));
+
+ return x;
+}
+
+#define __arch__swab64(x) ___arch__swab64(x)
+
+#endif /* CONFIG_CPU_MIPS64_R2 */
+
+#endif /* CONFIG_CPU_MIPSR2 */
+
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__
@@ -20,12 +67,12 @@
#endif /* __GNUC__ */
-#if defined (__MIPSEB__)
+#if defined(__MIPSEB__)
# include linux/byteorder/big_endian.h
-#elif defined (__MIPSEL__)
+#elif defined(__MIPSEL__)
# include linux/byteorder/little_endian.h
#else
# error MIPS, but neither __MIPSEB__, nor __MIPSEL__???
#endif
-#endif /* _MIPS_BYTEORDER_H */
+#endif /* _ASM_BYTEORDER_H */
diff --git a/include/asm-mips/cachectl.h b/include/asm-mips/cachectl.h
index 9cc2b87..f3ce721 100644
--- a/include/asm-mips/cachectl.h
+++ b/include/asm-mips/cachectl.h
@@ -1,10 +1,12 @@
/*
- * cachectl.h -- defines for MIPS cache control system calls
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
*
* Copyright (C) 1994, 1995, 1996 by Ralf Baechle
*/
-#ifndef__ASM_MIPS_CACHECTL
-#define__ASM_MIPS_CACHECTL
+#ifndef_ASM_CACHECTL
+#define_ASM_CACHECTL
/*
* Options for cacheflush system call
@@ -21,4 +23,4 @@
#define CACHEABLE 0 /* make pages cacheable */
#define UNCACHEABLE1 /* make pages uncacheable */
-#endif /* __ASM_MIPS_CACHECTL */
+#endif /* _ASM_CACHECTL */
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
index 66b0b36..256ad2c 100644
--- a/include/asm-mips/cacheops.h
+++ b/include/asm-mips/cacheops.h
@@ -5,43 +5,81 @@
* License. See the file COPYING in the main directory of this archive
* for more details.
*
- * (C) Copyright 1996, 1997 by Ralf Baechle
+ * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
+ * (C) Copyright 1999 Silicon Graphics, Inc.
*/
-#ifndef__ASM_MIPS_CACHEOPS_H
-#define__ASM_MIPS_CACHEOPS_H
+#ifndef__ASM_CACHEOPS_H
+#define__ASM_CACHEOPS_H
/*
- * Cache Operations
+ * Cache Operations available on all MIPS processors with R4000-style caches
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
-#define Index_Invalidate_SI 0x02
-#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
-#define Index_Load_Tag_SI 0x06
-#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
+#if defined(CONFIG_CPU_LOONGSON2)
+#define Hit_Invalidate_I 0x00
+#else
+#define Hit_Invalidate_I 0x10
+#endif
+#define Hit_Invalidate_D 0x11
+#define Hit_Writeback_Inv_D0x15
[U-Boot-Users] [MIPS] Add asm/asm.h
This file contains some useful macros for MIPS assembler code. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- include/asm-mips/asm.h | 409 1 files changed, 409 insertions(+), 0 deletions(-) create mode 100644 include/asm-mips/asm.h diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h new file mode 100644 index 000..608cfcf --- /dev/null +++ b/include/asm-mips/asm.h @@ -0,0 +1,409 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle + * Copyright (C) 1999 by Silicon Graphics, Inc. + * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 2002 Maciej W. Rozycki + * + * Some useful macros for MIPS assembler code + * + * Some of the routines below contain useless nops that will be optimized + * away by gas in -O mode. These nops are however required to fill delay + * slots in noreorder mode. + */ +#ifndef __ASM_ASM_H +#define __ASM_ASM_H + +#include asm/sgidefs.h + +#ifndef CAT +#ifdef __STDC__ +#define __CAT(str1, str2) str1##str2 +#else +#define __CAT(str1, str2) str1/**/str2 +#endif +#define CAT(str1, str2) __CAT(str1, str2) +#endif + +/* + * PIC specific declarations + * Not used for the kernel but here seems to be the right place. + */ +#ifdef __PIC__ +#define CPRESTORE(register) \ + .cprestore register +#define CPADD(register) \ + .cpadd register +#define CPLOAD(register)\ + .cpload register +#else +#define CPRESTORE(register) +#define CPADD(register) +#define CPLOAD(register) +#endif + +/* + * LEAF - declare leaf routine + */ +#defineLEAF(symbol)\ + .globl symbol; \ + .align 2; \ + .type symbol, @function; \ + .entsymbol, 0; \ +symbol:.frame sp, 0, ra + +/* + * NESTED - declare nested routine entry point + */ +#defineNESTED(symbol, framesize, rpc) \ + .globl symbol; \ + .align 2; \ + .type symbol, @function; \ + .entsymbol, 0; \ +symbol:.frame sp, framesize, rpc + +/* + * END - mark end of function + */ +#defineEND(function) \ + .endfunction; \ + .size function, .-function + +/* + * EXPORT - export definition of symbol + */ +#define EXPORT(symbol) \ + .globl symbol; \ +symbol: + +/* + * FEXPORT - export definition of a function symbol + */ +#define FEXPORT(symbol)\ + .globl symbol; \ + .type symbol, @function; \ +symbol: + +/* + * ABS - export absolute symbol + */ +#defineABS(symbol,value) \ + .globl symbol; \ +symbol = value + +#definePANIC(msg) \ + .setpush; \ + .setreorder;\ + PTR_LA a0, 8f; \ + jal panic; \ +9: b 9b; \ + .setpop;\ + TEXT(msg) + +/* + * Print formatted string + */ +#ifdef CONFIG_PRINTK +#define PRINT(string) \ + .setpush; \ + .setreorder;\ + PTR_LA a0, 8f; \ + jal printk; \ + .setpop;\ + TEXT(string) +#else +#define PRINT(string) +#endif + +#defineTEXT(msg) \ + .pushsection .data; \ +8: .asciiz msg;\ + .popsection; + +/* + * Build text tables + */ +#define TTABLE(string) \ + .pushsection .text; \ + .word 1f; \ + .popsection \ + .pushsection .data; \ +1: .asciiz string
[U-Boot-Users] [MIPS] Fix I-/D-cache initialization loops
We currently do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I again per a loop for I-cache initialization. But according to 'See MIPS Run', we are encouraged to use three separate loops rather than combining them for both I- and D-cache. This patch tries to fix that. In accordance with fixing above, mips_init_[id]cache are now separated from mips_cache_reset() and cache loops are completely rewritten with useful macros. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- cpu/mips/cache.S | 115 -- 1 files changed, 76 insertions(+), 39 deletions(-) diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index d260e28..0842093 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -30,11 +30,23 @@ #include asm/addrspace.h #include asm/cacheops.h +#define t8 RA + /* 16KB is the maximum size of instruction and data caches on * MIPS 4K. */ #define MIPS_MAX_CACHE_SIZE0x4000 +#define INDEX_BASE CKSEG0 + + .macro cache_op op addr + .setpush + .setnoreorder + .setmips3 + cache \op, 0(\addr) + .setpop + .endm + /* * cacheop macro to automate cache operations * first some helpers... @@ -125,6 +137,56 @@ #endif .endm +/* + * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) + */ +LEAF(mips_init_icache) + bleza1, 9f + mtc0zero, CP0_TAGLO + /* clear tag to invalidate */ + PTR_LI t0, INDEX_BASE + PTR_ADDUt1, t0, a1 +1: cache_opIndex_Store_Tag_I t0 + PTR_ADDUt0, a2 + bne t0, t1, 1b + /* fill once, so data field parity is correct */ + PTR_LI t0, INDEX_BASE +2: cache_opFill t0 + PTR_ADDUt0, a2 + bne t0, t1, 2b + /* invalidate again - prudent but not strictly neccessary */ + PTR_LI t0, INDEX_BASE +1: cache_opIndex_Store_Tag_I t0 + PTR_ADDUt0, a2 + bne t0, t1, 1b +9: jr ra + END(mips_init_icache) + +/* + * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) + */ +LEAF(mips_init_dcache) + bleza1, 9f + mtc0zero, CP0_TAGLO + /* clear all tags */ + PTR_LI t0, INDEX_BASE + PTR_ADDUt1, t0, a1 +1: cache_opIndex_Store_Tag_D t0 + PTR_ADDUt0, a2 + bne t0, t1, 1b + /* load from each line (in cached space) */ + PTR_LI t0, INDEX_BASE +2: LONG_L zero, 0(t0) + PTR_ADDUt0, a2 + bne t0, t1, 2b + /* clear all tags */ + PTR_LI t0, INDEX_BASE +1: cache_opIndex_Store_Tag_D t0 + PTR_ADDUt0, a2 + bne t0, t1, 1b +9: jr ra + END(mips_init_dcache) + /*** * * mips_cache_reset - low level initialisation of the primary caches @@ -142,6 +204,7 @@ * */ NESTED(mips_cache_reset, 0, ra) + moveRA, ra li t2, CFG_ICACHE_SIZE li t3, CFG_DCACHE_SIZE li t4, CFG_CACHELINE_SIZE @@ -158,57 +221,31 @@ NESTED(mips_cache_reset, 0, ra) f_fill64a0, -64, zero bne a0, a1, 2b - /* Set invalid tag. -*/ - - mtc0zero, CP0_TAGLO - /* * The caches are probably in an indeterminate state, * so we force good parity into them by doing an * invalidate, load/fill, invalidate for each line. */ - /* Assume bottom of RAM will generate good parity for the cache. -*/ - - li a0, K0BASE - movea2, t2 # icacheSize - movea3, t4 # icacheLineSize - movea1, a2 - icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill)) - - /* To support Orion/R4600, we initialise the data cache in 3 passes. -*/ - - /* 1: initialise dcache tags. + /* +* Assume bottom of RAM will generate good parity for the cache. */ - li a0, K0BASE - movea2, t3 # dcacheSize - movea3, t5 # dcacheLineSize - movea1, a2 - icacheop(a0,a1,a2,a3,Index_Store_Tag_D) - - /* 2: fill dcache. + /* +* Initialize the I-cache first, */ + movea1, t2 + movea2, t4 + bal mips_init_icache - li a0, K0BASE - movea2, t3 # dcacheSize - movea3, t5 # dcacheLineSize - movea1, a2 - icacheopn(a0,a1,a2,a3,1lw,(dummy)) - - /* 3: clear dcache tags. + /* +* then initialize D-cache. */ + movea1, t3 + movea2, t5 + bal mips_init_dcache - li a0, K0BASE
[U-Boot-Users] [MIPS] Replace memory clearance code with f_fill64
This routine fills memory with zero by 64 bytes, and is 64-bit capable. Signed-off-by: Shinya Kuribayashi [EMAIL PROTECTED] --- cpu/mips/cache.S | 43 --- 1 files changed, 28 insertions(+), 15 deletions(-) diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 66fe47a..d260e28 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -104,6 +104,27 @@ #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) + .macro f_fill64 dst, offset, val + LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) +#if LONGSIZE == 4 + LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) +#endif + .endm + /*** * * mips_cache_reset - low level initialisation of the primary caches @@ -128,22 +149,14 @@ NESTED(mips_cache_reset, 0, ra) li v0, MIPS_MAX_CACHE_SIZE - /* Now clear that much memory starting from zero. + /* +* Now clear that much memory starting from zero. */ - - li a0, KSEG1 - addua1, a0, v0 -2: - sw zero, 0(a0) - sw zero, 4(a0) - sw zero, 8(a0) - sw zero, 12(a0) - sw zero, 16(a0) - sw zero, 20(a0) - sw zero, 24(a0) - sw zero, 28(a0) - addua0, 32 - bltua0, a1, 2b + PTR_LI a0, KSEG1 + PTR_ADDUa1, a0, v0 +2: PTR_ADDIU a0, 64 + f_fill64a0, -64, zero + bne a0, a1, 2b /* Set invalid tag. */ - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
