Re: [USRP-users] RFNoC FPGA OOT Xilinx IP Addition

[EJ Kreinar via USRP-users]

Sure, glad to help!

Most of magic variables come from the Makefile workflow in uhd-fpga
(suggest doing some greps in both uhd-fpga/usrp3/tools/make and
uhd-fpga/usrp3/top).

The OOT_DIR is a magic variable that's passed to the OOT directory, and it
lets the Makefiles resolve relative pathing issues. The
uhd_image_builder.py tools should wrap this correctly when generating FPGA
images. It's not exactly the cleanest interface, since it requires a ":="
operation in the OOT Makefile. I'm definitely open to other suggestions,
but it's worked well for me so far.

Hope to see your OOT FPGA blocks :D
EJ

On Tue, Feb 27, 2018 at 2:23 PM, Brian Padalino  wrote:

> Hey EJ,
>
> On Tue, Feb 27, 2018 at 6:27 AM, EJ Kreinar  wrote:
>
>> Hi Brian,
>>
>> There's a supported method to include OOT repos that can build and
>> include xilinx IP (or basically any other IP that you need, including HLS.
>> I've yet to try it with sysgen blocks, but that would probably work too).
>> Basically you can use uhd_image_builder.py or uhd_image_builder_gui.py to
>> include a Makefile.inc from an OOT repo, rather than copying the text from
>> the Makefile.srcs.
>>
>> See my repo here for a minimal basic example: https://github.com/ej
>> k43/rfnoc-ootexample
>>
>> There's also an open source FPGA polyphase channelizer OOT module that
>> uses this approach: https://github.com/e33b1711/rfnoc-ppchan
>>
>> Good luck! Let me know if this helps
>>
>
> This is exactly what I was looking for.  Now, is there anything that
> defines these magic variables used in the Makefile.inc?  Things like
> OOT_DIR, LIB_IP_XCI_SRCS, TOOLS_DIR, etc?  There's a lot of magic going
> on in those Makefiles and the environment in general it seems.
>
> For now, though, this looks like it will work perfectly.
>
> Thanks,
> Brian
>
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Re: [USRP-users] RFNoC FPGA OOT Xilinx IP Addition

[Brian Padalino via USRP-users]

Hey EJ,

On Tue, Feb 27, 2018 at 6:27 AM, EJ Kreinar  wrote:

> Hi Brian,
>
> There's a supported method to include OOT repos that can build and include
> xilinx IP (or basically any other IP that you need, including HLS. I've yet
> to try it with sysgen blocks, but that would probably work too). Basically
> you can use uhd_image_builder.py or uhd_image_builder_gui.py to include a
> Makefile.inc from an OOT repo, rather than copying the text from the
> Makefile.srcs.
>
> See my repo here for a minimal basic example: https://github.com/
> ejk43/rfnoc-ootexample
>
> There's also an open source FPGA polyphase channelizer OOT module that
> uses this approach: https://github.com/e33b1711/rfnoc-ppchan
>
> Good luck! Let me know if this helps
>

This is exactly what I was looking for.  Now, is there anything that
defines these magic variables used in the Makefile.inc?  Things like
OOT_DIR, LIB_IP_XCI_SRCS, TOOLS_DIR, etc?  There's a lot of magic going on
in those Makefiles and the environment in general it seems.

For now, though, this looks like it will work perfectly.

Thanks,
Brian
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Re: [USRP-users] RFNoC FPGA OOT Xilinx IP Addition

[EJ Kreinar via USRP-users]

Hi Brian,

There's a supported method to include OOT repos that can build and include
xilinx IP (or basically any other IP that you need, including HLS. I've yet
to try it with sysgen blocks, but that would probably work too). Basically
you can use uhd_image_builder.py or uhd_image_builder_gui.py to include a
Makefile.inc from an OOT repo, rather than copying the text from the
Makefile.srcs.

See my repo here for a minimal basic example:
https://github.com/ejk43/rfnoc-ootexample

There's also an open source FPGA polyphase channelizer OOT module that uses
this approach: https://github.com/e33b1711/rfnoc-ppchan

Good luck! Let me know if this helps

Best regards,
EJ

On Feb 26, 2018 2:37 PM, "Brian Padalino via USRP-users" <
usrp-users@lists.ettus.com> wrote:

> Hi,
>
> I'm trying to add a piece of Xilinx IP using an .xci file, similar to how
> the normal flow for the FPGA build goes, but I want to keep it associated
> with my OOT source, and not change the main FPGA repository.
>
> I haven't found any instructions on how to do this, so I figure I'd ask
> here.
>
> Is it as simple as adding a .xci file to the list of sources and having it
> build?  The normal FPGA build seems to go through a lot more steps to
> generate all the IP and list their simulation and synthesis sources.
>
> Guidance is appreciated on how to do this "correctly" with an OOT module.
>
> Thanks,
> Brian
>
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>
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[USRP-users] RFNoC FPGA OOT Xilinx IP Addition

[Brian Padalino via USRP-users]

Hi,

I'm trying to add a piece of Xilinx IP using an .xci file, similar to how
the normal flow for the FPGA build goes, but I want to keep it associated
with my OOT source, and not change the main FPGA repository.

I haven't found any instructions on how to do this, so I figure I'd ask
here.

Is it as simple as adding a .xci file to the list of sources and having it
build?  The normal FPGA build seems to go through a lot more steps to
generate all the IP and list their simulation and synthesis sources.

Guidance is appreciated on how to do this "correctly" with an OOT module.

Thanks,
Brian
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