Re: [USRP-users] USRP X310

2020-07-14 Thread Joe Martin via USRP-users
Marcus: 

Yes. Thanks.  As I said. 

Regards, 

Joe

> On Jul 14, 2020, at 8:29 AM, Marcus D Leech  wrote:
> 
> Joe:
> 
> The input levels that cause distortion vary quite a bit from daughtercard to 
> daughtercard, and even within a daughtercard there will be variability 
> depending on frequency. 
> 
> The performance data can be consulted for this:
> 
> https://files.ettus.com/performance_data/ 
> 
> 
> What you’re looking for is IP3 and P1dB data. 
> 
> But “damage limits” are given 
> Sent from my iPhone
> 
>> On Jul 14, 2020, at 10:17 AM, Joe Martin  wrote:
>> 
>> Arash, 
>> 
>> Marcus L.’s response has some definitive info in the links.  For example, in 
>> the TwinRX link it is stated: 
>> 
>>> Never apply more than +10 dBm of power into any RF input.
>> 
>> So there you have it.  Thanks for the details Marcus. 
>> 
>> Regards, 
>> 
>> Joe
>> 
>>> On Jul 14, 2020, at 7:55 AM, Marcus D. Leech via USRP-users 
>>> mailto:usrp-users@lists.ettus.com>> wrote:
>>> 
>>> On 07/14/2020 05:53 AM, Marcus Müller via USRP-users wrote:
 Hi Arash,
 
 The input power is not defined by the motherboard (X310) you're using,
 but by the analog frontend daughterboard (like TwinRX, UBX-160, SBX,…)
 you've plugged in to these.
 
>>> For example, see the "Care and Handling" for the SBX here:
>>> 
>>> https://kb.ettus.com/SBX_Getting_Started_Guides#Proper_Care_and_Handling 
>>> 
>>> 
>>> And for the TwinRx
>>> 
>>> https://kb.ettus.com/TwinRX_Getting_Started_Guides#Proper_Care_and_Handling
>>> 
>>> 
>>> ___
>>> USRP-users mailing list
>>> USRP-users@lists.ettus.com
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>> 

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Re: [USRP-users] USRP X310

2020-07-14 Thread Marcus D Leech via USRP-users
Joe:

The input levels that cause distortion vary quite a bit from daughtercard to 
daughtercard, and even within a daughtercard there will be variability 
depending on frequency. 

The performance data can be consulted for this:

https://files.ettus.com/performance_data/

What you’re looking for is IP3 and P1dB data. 

But “damage limits” are given 
Sent from my iPhone

> On Jul 14, 2020, at 10:17 AM, Joe Martin  wrote:
> 
> Arash, 
> 
> Marcus L.’s response has some definitive info in the links.  For example, in 
> the TwinRX link it is stated: 
> 
>> Never apply more than +10 dBm of power into any RF input.
> 
> So there you have it.  Thanks for the details Marcus. 
> 
> Regards, 
> 
> Joe
> 
>> On Jul 14, 2020, at 7:55 AM, Marcus D. Leech via USRP-users 
>>  wrote:
>> 
>>> On 07/14/2020 05:53 AM, Marcus Müller via USRP-users wrote:
>>> Hi Arash,
>>> 
>>> The input power is not defined by the motherboard (X310) you're using,
>>> but by the analog frontend daughterboard (like TwinRX, UBX-160, SBX,…)
>>> you've plugged in to these.
>>> 
>> For example, see the "Care and Handling" for the SBX here:
>> 
>> https://kb.ettus.com/SBX_Getting_Started_Guides#Proper_Care_and_Handling
>> 
>> And for the TwinRx
>> 
>> https://kb.ettus.com/TwinRX_Getting_Started_Guides#Proper_Care_and_Handling
>> 
>> 
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Re: [USRP-users] USRP X310

2020-07-14 Thread Joe Martin via USRP-users
Arash, 

Marcus L.’s response has some definitive info in the links.  For example, in 
the TwinRX link it is stated: 

> Never apply more than +10 dBm of power into any RF input.

So there you have it.  Thanks for the details Marcus. 

Regards, 

Joe

> On Jul 14, 2020, at 7:55 AM, Marcus D. Leech via USRP-users 
>  wrote:
> 
> On 07/14/2020 05:53 AM, Marcus Müller via USRP-users wrote:
>> Hi Arash,
>> 
>> The input power is not defined by the motherboard (X310) you're using,
>> but by the analog frontend daughterboard (like TwinRX, UBX-160, SBX,…)
>> you've plugged in to these.
>> 
> For example, see the "Care and Handling" for the SBX here:
> 
> https://kb.ettus.com/SBX_Getting_Started_Guides#Proper_Care_and_Handling
> 
> And for the TwinRx
> 
> https://kb.ettus.com/TwinRX_Getting_Started_Guides#Proper_Care_and_Handling
> 
> 
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Re: [USRP-users] USRP X310

2020-07-14 Thread Joe Martin via USRP-users
Arash, 

While Marcus’ response is certainly correct it does little in providing a 
practical answer to your question.  

I use an X310 with TwinRX daughterboards and have found that it is inadvisable 
to use input levels to the TwinRX daughterboard greater than -30dBm because 
higher levels than that tend to result in distortion/compression issues.  I 
don’t know what the damage threshold is for the input ports on the TwinRX 
daughterboard.  For my radio astronomy applications I use an input level of 
-60dBm and that seems to work quite well for me.  I don’t know if other 
daughterboards for the X310 have different input-level behavior.  Perhaps this 
response will give you ball park answers that you can use.

Regards, 

Joe


> On Jul 14, 2020, at 3:53 AM, Marcus Müller via USRP-users 
>  wrote:
> 
> Hi Arash,
> 
> The input power is not defined by the motherboard (X310) you're using,
> but by the analog frontend daughterboard (like TwinRX, UBX-160, SBX,…)
> you've plugged in to these.
> 
> On 14.07.20 11:38, Arash Jafari via USRP-users wrote:
>> National Instrument congratulation!! very bad documentation.
> 
> …
> 
> Best regards,
> Marcus Müller
> 
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Re: [USRP-users] USRP X310

2020-07-14 Thread Marcus D. Leech via USRP-users

On 07/14/2020 05:53 AM, Marcus Müller via USRP-users wrote:

Hi Arash,

The input power is not defined by the motherboard (X310) you're using,
but by the analog frontend daughterboard (like TwinRX, UBX-160, SBX,…)
you've plugged in to these.


For example, see the "Care and Handling" for the SBX here:

https://kb.ettus.com/SBX_Getting_Started_Guides#Proper_Care_and_Handling

And for the TwinRx

https://kb.ettus.com/TwinRX_Getting_Started_Guides#Proper_Care_and_Handling


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Re: [USRP-users] USRP X310

2020-07-14 Thread Marcus Müller via USRP-users
Hi Arash,

The input power is not defined by the motherboard (X310) you're using,
but by the analog frontend daughterboard (like TwinRX, UBX-160, SBX,…)
you've plugged in to these.

On 14.07.20 11:38, Arash Jafari via USRP-users wrote:
> National Instrument congratulation!! very bad documentation.

…

Best regards,
Marcus Müller

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Re: [USRP-users] USRP X310 sample rate of 184.32 MHz

2020-05-11 Thread Carlos Alberto Ruiz Naranjo via USRP-users
Thank you Brian! It runs fine :)

El lun., 11 may. 2020 a las 17:08, Brian Padalino ()
escribió:

> On Mon, May 11, 2020 at 6:20 AM Carlos Alberto Ruiz Naranjo via USRP-users
>  wrote:
>
>> Hello,
>>
>> I'm using the USRP X310 with CBX-120. I set the radio sample rate to
>> 184.32 MHz but I have the following message:
>>
>> [WARNING] [X300 RADIO] Requesting invalid sampling rate from device:
>> 184.32 MHz. Actual rate is: 200 MHz.
>>
>> Isn't it possible to set it to that sample rate?
>>
>
> You need to set the master_clock_rate in the arguments of the USRP to be
> 184.32MHz.
>
>   https://files.ettus.com/manual/page_configuration.html
>
> Brian
>
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Re: [USRP-users] USRP X310 sample rate of 184.32 MHz

2020-05-11 Thread Brian Padalino via USRP-users
On Mon, May 11, 2020 at 6:20 AM Carlos Alberto Ruiz Naranjo via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hello,
>
> I'm using the USRP X310 with CBX-120. I set the radio sample rate to
> 184.32 MHz but I have the following message:
>
> [WARNING] [X300 RADIO] Requesting invalid sampling rate from device:
> 184.32 MHz. Actual rate is: 200 MHz.
>
> Isn't it possible to set it to that sample rate?
>

You need to set the master_clock_rate in the arguments of the USRP to be
184.32MHz.

  https://files.ettus.com/manual/page_configuration.html

Brian
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Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-23 Thread Marcus D. Leech via USRP-users

On 03/24/2020 12:24 AM, Lukas Haase wrote:

Hi Marcus,

I would have two possible solutions but both of them are non-trivial:

1. As you say, parallelism. For each of N supported timed commands, the 
decoding of the timed commands is cloned
2. If the timed commands are enough clock cycles in the future, they can be 
decoded immideately once they come in. For each type of register they set, they 
set the following: value of the register. Clock cycle at which it should occur. 
Then we would have something like:
   reg [31:0] cycle_number; //  how to handle overflow? commands can be a max 
of 1/200e6 * 2^32 seconds in advance
   always @(posedge clk) begin
 cycle_number <= cycle_number + 1;
 if cycle_number == when_to_set_phase_accumulator_register
   phase_accumulator <= data_for_phase_accumulator;
 if cycle_number == when_to_set_phase_increment_register
   phase_increment <= data_for_phase_increment;
   end
Right, but the timed-command FIFO handler doesn't really *KNOW* anything 
about the semantics of the registers its setting, and indeed, given
  the large variety of daughter-cards, and other "things" it probably 
shouldn't *KNOW* too much about anything, because that, among other things,
  makes the code MUCH harder to maintain, and occupies more room in the 
limited-space FPGA.







Absolute phase coherence (with predictable/zero phase-offset) is, in
practice, incredibly hard to achieve--PARTICULARLY PHASE OFFSET.
Which is why most fielded RF systems work just fine with "wobbly"
phase-offset, with mechanisms to factor it out "at startup" (for whatever
definition of "start up" is appropriate).

I know it is hard to achieve and I know normal *comm* systems do not care.
BUT: There is a large class of practically relevent applications that require 
TX/RX phase coherence: Ranging and radar.
Everything that that needs to deduce time of flight (=range) via carrier phase 
shift.
If it's just one frequency we can again calibrate.
But to make systems robust, they use multiple frequencies and obtain phase 
shifts from diverse (hopped) frequencies.
Yes, it's hard to implement but these systems do exist, have been built and 
work.
Yup, those systems have hardware that "understands" all of the subtle 
semantics of the application at hand.




(I am also aware that there are other options to implement these systems 
outside of USRP/SDR context: a single PLL for both TX/RX with potential freq 
dividers/multipliers, coupling transmitted signal harmonics back, bandpass 
filter and use as RX LO etc).
The problem with the "marvelous generality" of an SDR solution (whether 
it's USRP or something else) is that there are *specific* applications
  that don't necessarily slide easily into the model of "marvelous 
generality".


Your application seems to have two things that are sometimes hard to 
achieve in a generic SDR:


 o Rapid frequency hopping  (RF synthesizers for rapid 
frequency-hopping systems are often designed very differently than for

more-general systems).

 o Predictable and reliable phase-offset across hops.  [That is, 
hop to X, hop to Y, come back to X, and have an expectation of the same 
systemic

phase offset].




In other words: How would you implement such a ranging system with USRP?

Currently I only see two options that work but none of them are acceptable:
Option 1: Use analog only tuning. But this is not flexible because it only 
works with integer-N tuning (poor resolution) and has huge settling timed
Option 2: Do everything (=hopping) in software on the host computer, e.g. 
within gnuradio. But this requires unnecessary huge data rates (200MSsps)
Option 2 leaves you in a situation where the hardware isn't changing 
across hops.  I agree that it carries a heavy implementation burden on

  the software side.

There's a 3rd option you didn't mention:

Implement application-specific "stuff" in the FPGA, using either the 
RFNoC framework or "raw".  RFNoC and the whole open-source FPGA code
  were designed to allow that, and many Ettus customers do custom 
things in the FPGA specifically because the as-shipped architecture doesn't
  quite fit their application model.  That is, as I'll re-iterate, an 
attribute of highly-generalized systems--they have this natural tendency to

  not deal well speciic "edge cases".





I hope that someone with better understanding of the timed-command FIFO
can chime in and tell me that I'm completely wrong.

Indeed much appreciated.


Thanks,
Lukas




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Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-23 Thread Lukas Haase via USRP-users
Hi Marcus,

> Von: "Marcus D. Leech" 
> On 03/23/2020 11:53 PM, Lukas Haase wrote:
> >> Von: "Marcus D. Leech" 
> >> On 03/23/2020 11:08 PM, Lukas Haase wrote:
> >>> Hi Marcus,
>  Von: "Marcus D. Leech" 
>  On 03/13/2020 10:52 AM, Lukas Haase wrote:
> > Hi again Rob,
> >
> > Yes, I confirm:
> >
> > 1.) Finally I get the commands to execute at the same time (TX and RX 
> > individually and both at the same time)
> > 2.) Yes, the phase is random after each retune, even when I retune back 
> > to the same frequency
> > 3.) (2) is only true if it includes *DSP* retuning. With naalog 
> > retuning (+integer-N retuning) I get phase coherence, as expected.
> >
> > I actually expected the PLL retuning much more challenging than the DSP 
> > retuning but for some reason it seems to be the opposite...
>  It depends on whether the phase-accumulator in the DSP is reset to zero,
>  or whether just the increment register is updated with the
>   new phase increment.   There are good arguments for both approaches.
> >>> I just wanted to check in again if you know how this is implemented and 
> >>> how your thoughts are regarding tuning in both cases. My take:
> >>>
> >>> Case #1: Phase accumulator and increment register is reset.
> >>>  - This results in transients when re-tuning frequency because the 
> >>> mixer LO always (re-)starts at zero phase.
> >>>  - Since this completely defines the state of the DDC/DUC, I imagine 
> >>> phase coherence must be preserved assuming the resets in TX and RX happen 
> >>> exactly at the same time (which is still not certain to me)
> >
> >
> >
> > I have actually always wondered HOW these magic timed commands actually 
> > work.
> >
> > The FPGA has a clock which to my knowledge is the system clock which is 200 
> > MHz. Call this clock "clk".
> > But this is also the sample rate.
> > So everything that operates on a sample level accuracy must execute within 
> > one clock cycle which seems hard to me.
> >
> > If I queue 16 timed commands how can they really be executed at the same 
> > clock cycle?
> Well, you have to remember that FPGAs are inherently massively-parallel
> nano-computers.  But in THIS case, it looks to me like there's
>a FIFO, and elements on it are processed one at a time.  In an FPGA,
> all kinds of "stuff" can happen at the same time, because it's
>a whack of somewhat-independent logic cells (or, actually, LUTs, but
> that's an implementation issue).

I would have two possible solutions but both of them are non-trivial:

1. As you say, parallelism. For each of N supported timed commands, the 
decoding of the timed commands is cloned
2. If the timed commands are enough clock cycles in the future, they can be 
decoded immideately once they come in. For each type of register they set, they 
set the following: value of the register. Clock cycle at which it should occur. 
Then we would have something like:
  reg [31:0] cycle_number; //  how to handle overflow? commands can be a max of 
1/200e6 * 2^32 seconds in advance
  always @(posedge clk) begin
cycle_number <= cycle_number + 1;
if cycle_number == when_to_set_phase_accumulator_register
  phase_accumulator <= data_for_phase_accumulator;
if cycle_number == when_to_set_phase_increment_register
  phase_increment <= data_for_phase_increment;
  end


> >> According to my study of the FPGA code, the register sets are serialized
> >> within the timed-command FIFO, which is an AXI FIFO, which means
> >> that said commands may be spread over several 10s of nanoseconds in
> > Is this an alternative way of saying "timed commands actually do NOT 
> > execute at the same time on the x310" or alternatively "The x310 does 
> > actually NOT support phase coherent operation"?
> I won't go that far, because I'm not an FPGA expert.  But the whole
> "synchronize the things" via timed commands was originally intended to
>allow synchronizaton *across* multiple USRP units.  Which will work,
> according to my analysis, because those FIFOs will all be executed
>in lock-step *across* the USRPs involved.  But within a USRP, I think
> things are a bit murkier.
> >
> > That would come pretty much to a shock.
> >
> > It would explain why phase coherence works with analog-only tuning 
> > (assuming one single register set is sufficient for analog tuning).
> >
> > On the other hand, it would not explain why RX-RX phase coherence (or 
> > TX-TX) works. In that case, only the two DDCs are used. But there are still 
> > several register sets which would equally break stuff.
> Like I said, I'm not an expert at FPGA stuff, and I'm hoping someone
> more priestly than me can comment.

That'd be amazing.

> Absolute phase coherence (with predictable/zero phase-offset) is, in
> practice, incredibly hard to achieve--PARTICULARLY PHASE OFFSET.
>Which is why most fielded RF systems work just fine with "wobbly"
> phase-offset, with mec

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-23 Thread Marcus D. Leech via USRP-users

On 03/23/2020 11:53 PM, Lukas Haase wrote:

Hi Marcus,


Gesendet: Montag, 23. März 2020 um 23:35 Uhr
Von: "Marcus D. Leech" 
An: "Lukas Haase" 
Cc: "Rob Kossler" , "USRP-users@lists.ettus.com" 

Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
timed command

On 03/23/2020 11:08 PM, Lukas Haase wrote:

Hi Marcus,


Gesendet: Freitag, 13. März 2020 um 13:29 Uhr
Von: "Marcus D. Leech" 
An: "Lukas Haase" , "Rob Kossler" 
Cc: "USRP-users@lists.ettus.com" 
Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
timed command

On 03/13/2020 10:52 AM, Lukas Haase wrote:

Hi again Rob,

Yes, I confirm:

1.) Finally I get the commands to execute at the same time (TX and RX 
individually and both at the same time)
2.) Yes, the phase is random after each retune, even when I retune back to the 
same frequency
3.) (2) is only true if it includes *DSP* retuning. With naalog retuning 
(+integer-N retuning) I get phase coherence, as expected.

I actually expected the PLL retuning much more challenging than the DSP 
retuning but for some reason it seems to be the opposite...

It depends on whether the phase-accumulator in the DSP is reset to zero,
or whether just the increment register is updated with the
 new phase increment.   There are good arguments for both approaches.

I just wanted to check in again if you know how this is implemented and how 
your thoughts are regarding tuning in both cases. My take:

Case #1: Phase accumulator and increment register is reset.
 - This results in transients when re-tuning frequency because the mixer LO 
always (re-)starts at zero phase.
 - Since this completely defines the state of the DDC/DUC, I imagine phase 
coherence must be preserved assuming the resets in TX and RX happen exactly at 
the same time (which is still not certain to me)




I have actually always wondered HOW these magic timed commands actually work.

The FPGA has a clock which to my knowledge is the system clock which is 200 MHz. Call 
this clock "clk".
But this is also the sample rate.
So everything that operates on a sample level accuracy must execute within one 
clock cycle which seems hard to me.

If I queue 16 timed commands how can they really be executed at the same clock 
cycle?
Well, you have to remember that FPGAs are inherently massively-parallel 
nano-computers.  But in THIS case, it looks to me like there's
  a FIFO, and elements on it are processed one at a time.  In an FPGA, 
all kinds of "stuff" can happen at the same time, because it's
  a whack of somewhat-independent logic cells (or, actually, LUTs, but 
that's an implementation issue).






According to my study of the FPGA code, the register sets are serialized
within the timed-command FIFO, which is an AXI FIFO, which means
that said commands may be spread over several 10s of nanoseconds in

Is this an alternative way of saying "timed commands actually do NOT execute at the same time 
on the x310" or alternatively "The x310 does actually NOT support phase coherent 
operation"?
I won't go that far, because I'm not an FPGA expert.  But the whole 
"synchronize the things" via timed commands was originally intended to
  allow synchronizaton *across* multiple USRP units.  Which will work, 
according to my analysis, because those FIFOs will all be executed
  in lock-step *across* the USRPs involved.  But within a USRP, I think 
things are a bit murkier.


That would come pretty much to a shock.

It would explain why phase coherence works with analog-only tuning (assuming 
one single register set is sufficient for analog tuning).

On the other hand, it would not explain why RX-RX phase coherence (or TX-TX) 
works. In that case, only the two DDCs are used. But there are still several 
register sets which would equally break stuff.
Like I said, I'm not an expert at FPGA stuff, and I'm hoping someone 
more priestly than me can comment.


Absolute phase coherence (with predictable/zero phase-offset) is, in 
practice, incredibly hard to achieve--PARTICULARLY PHASE OFFSET.
  Which is why most fielded RF systems work just fine with "wobbly" 
phase-offset, with mechanisms to factor it out "at startup" (for whatever

  definition of "start up" is appropriate).

I hope that someone with better understanding of the timed-command FIFO 
can chime in and tell me that I'm completely wrong.







Lukas





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Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-23 Thread Lukas Haase via USRP-users
Hi Marcus,

> Gesendet: Montag, 23. März 2020 um 23:35 Uhr
> Von: "Marcus D. Leech" 
> An: "Lukas Haase" 
> Cc: "Rob Kossler" , "USRP-users@lists.ettus.com" 
> 
> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
> timed command
>
> On 03/23/2020 11:08 PM, Lukas Haase wrote:
> > Hi Marcus,
> >
> >> Gesendet: Freitag, 13. März 2020 um 13:29 Uhr
> >> Von: "Marcus D. Leech" 
> >> An: "Lukas Haase" , "Rob Kossler" 
> >> Cc: "USRP-users@lists.ettus.com" 
> >> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using 
> >> a timed command
> >>
> >> On 03/13/2020 10:52 AM, Lukas Haase wrote:
> >>> Hi again Rob,
> >>>
> >>> Yes, I confirm:
> >>>
> >>> 1.) Finally I get the commands to execute at the same time (TX and RX 
> >>> individually and both at the same time)
> >>> 2.) Yes, the phase is random after each retune, even when I retune back 
> >>> to the same frequency
> >>> 3.) (2) is only true if it includes *DSP* retuning. With naalog retuning 
> >>> (+integer-N retuning) I get phase coherence, as expected.
> >>>
> >>> I actually expected the PLL retuning much more challenging than the DSP 
> >>> retuning but for some reason it seems to be the opposite...
> >> It depends on whether the phase-accumulator in the DSP is reset to zero,
> >> or whether just the increment register is updated with the
> >> new phase increment.   There are good arguments for both approaches.
> > I just wanted to check in again if you know how this is implemented and how 
> > your thoughts are regarding tuning in both cases. My take:
> >
> > Case #1: Phase accumulator and increment register is reset.
> > - This results in transients when re-tuning frequency because the mixer 
> > LO always (re-)starts at zero phase.
> > - Since this completely defines the state of the DDC/DUC, I imagine 
> > phase coherence must be preserved assuming the resets in TX and RX happen 
> > exactly at the same time (which is still not certain to me)




I have actually always wondered HOW these magic timed commands actually work.

The FPGA has a clock which to my knowledge is the system clock which is 200 
MHz. Call this clock "clk".
But this is also the sample rate.
So everything that operates on a sample level accuracy must execute within one 
clock cycle which seems hard to me.

If I queue 16 timed commands how can they really be executed at the same clock 
cycle?

> According to my study of the FPGA code, the register sets are serialized 
> within the timed-command FIFO, which is an AXI FIFO, which means
>that said commands may be spread over several 10s of nanoseconds in 

Is this an alternative way of saying "timed commands actually do NOT execute at 
the same time on the x310" or alternatively "The x310 does actually NOT support 
phase coherent operation"?

That would come pretty much to a shock.

It would explain why phase coherence works with analog-only tuning (assuming 
one single register set is sufficient for analog tuning).

On the other hand, it would not explain why RX-RX phase coherence (or TX-TX) 
works. In that case, only the two DDCs are used. But there are still several 
register sets which would equally break stuff.

Lukas



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Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-23 Thread Marcus D. Leech via USRP-users

On 03/23/2020 11:08 PM, Lukas Haase wrote:

Hi Marcus,


Gesendet: Freitag, 13. März 2020 um 13:29 Uhr
Von: "Marcus D. Leech" 
An: "Lukas Haase" , "Rob Kossler" 
Cc: "USRP-users@lists.ettus.com" 
Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
timed command

On 03/13/2020 10:52 AM, Lukas Haase wrote:

Hi again Rob,

Yes, I confirm:

1.) Finally I get the commands to execute at the same time (TX and RX 
individually and both at the same time)
2.) Yes, the phase is random after each retune, even when I retune back to the 
same frequency
3.) (2) is only true if it includes *DSP* retuning. With naalog retuning 
(+integer-N retuning) I get phase coherence, as expected.

I actually expected the PLL retuning much more challenging than the DSP 
retuning but for some reason it seems to be the opposite...

It depends on whether the phase-accumulator in the DSP is reset to zero,
or whether just the increment register is updated with the
new phase increment.   There are good arguments for both approaches.

I just wanted to check in again if you know how this is implemented and how 
your thoughts are regarding tuning in both cases. My take:

Case #1: Phase accumulator and increment register is reset.
- This results in transients when re-tuning frequency because the mixer LO 
always (re-)starts at zero phase.
- Since this completely defines the state of the DDC/DUC, I imagine phase 
coherence must be preserved assuming the resets in TX and RX happen exactly at 
the same time (which is still not certain to me)
According to my study of the FPGA code, the register sets are serialized 
within the timed-command FIFO, which is an AXI FIFO, which means
  that said commands may be spread over several 10s of nanoseconds in 
the X310 (based on a 200MHz system clock).


Case #2: Only increment register is updated
- This results in a smooth transition
- I would guess that this is what USRP implements
- Since not the whole state of DUC/DDC is reset I can imagine there is a 
potential for phase coherence problems.
- if I update the phase increment register for DUC to fdsp=500e3 and the 
phase increment register for DDC to fdsp=-500e3 can there be any way of 
breaking phase coherence? I just can't think of a away (because while the 
frequency is different, it's exactly the mirror frequency and results in the 
same absolut value)

Thanks,
Lukas




Well, updating the increment register only is "smoother", but not 
perfectly smooth, really.  Because you're bound to abruptly change the 
phase.





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Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-23 Thread Lukas Haase via USRP-users
Hi Marcus,

> Gesendet: Freitag, 13. März 2020 um 13:29 Uhr
> Von: "Marcus D. Leech" 
> An: "Lukas Haase" , "Rob Kossler" 
> Cc: "USRP-users@lists.ettus.com" 
> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
> timed command
>
> On 03/13/2020 10:52 AM, Lukas Haase wrote:
> > Hi again Rob,
> >
> > Yes, I confirm:
> >
> > 1.) Finally I get the commands to execute at the same time (TX and RX 
> > individually and both at the same time)
> > 2.) Yes, the phase is random after each retune, even when I retune back to 
> > the same frequency
> > 3.) (2) is only true if it includes *DSP* retuning. With naalog retuning 
> > (+integer-N retuning) I get phase coherence, as expected.
> >
> > I actually expected the PLL retuning much more challenging than the DSP 
> > retuning but for some reason it seems to be the opposite...
> It depends on whether the phase-accumulator in the DSP is reset to zero, 
> or whether just the increment register is updated with the
>new phase increment.   There are good arguments for both approaches.

I just wanted to check in again if you know how this is implemented and how 
your thoughts are regarding tuning in both cases. My take:

Case #1: Phase accumulator and increment register is reset.
   - This results in transients when re-tuning frequency because the mixer LO 
always (re-)starts at zero phase.
   - Since this completely defines the state of the DDC/DUC, I imagine phase 
coherence must be preserved assuming the resets in TX and RX happen exactly at 
the same time (which is still not certain to me)

Case #2: Only increment register is updated
   - This results in a smooth transition
   - I would guess that this is what USRP implements
   - Since not the whole state of DUC/DDC is reset I can imagine there is a 
potential for phase coherence problems.
   - if I update the phase increment register for DUC to fdsp=500e3 and the 
phase increment register for DDC to fdsp=-500e3 can there be any way of 
breaking phase coherence? I just can't think of a away (because while the 
frequency is different, it's exactly the mirror frequency and results in the 
same absolut value)

Thanks,
Lukas





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Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-20 Thread Rob Kossler via USRP-users
Hi Lukas,
Taking this off the list for a bit...

   - On the LO sync, all I mean is the you will need to use a tune request
   with the RF policy not NONE and use timed commands - just like for the DSP
   freq.  Does that make sense?
   - The reason that I think that my original methodology for measuring
   rx-to-tx phase is not valid is that one of the channels, let's say
   Tx1->Rx1, runs continuously (no tuning commands) while the other, Tx0->Rx0,
   has an abrupt phase change at an arbitrary time when the user clicks the
   button (I'm assuming the phase change is caused by the phase accumulators
   being actually reset to zero). On the other hand, the Tx0->Rx0 path
   actually has two abrupt phase changes (because both accumulators are set to
   zero at the same time) so perhaps it should cancel out. I'm really not
   clear on this.
   - Regarding the phase walk which occurs when I wired the Tx signal
   source to the multiply_conjugate (in place of Rx1), I really don't
   understand what is causing this walk. I realize that the hardware is not
   actually operating at the frequency you specify because of hardware
   limitations (such as 10 MHz ref) and quantizations of both the LO and the
   DSP freq.  But, if the quantization errors are the same in the Rx and Tx
   paths and if they are both disciplined to the 10 MHz ref, I don't
   understand why the errors don't cancel out such that there is no phase walk.

So, even though I'm greatly confused, I still do believe that it is likely
that it is working for you the way you need it to.  I believe the problem
is related to our methodology for measuring the Tx-to-Rx phase.  But can't
be sure.  Is there another way you can know if it's working for you the way
it needs to be?

Rob

On Fri, Mar 20, 2020 at 2:21 PM Lukas Haase  wrote:

> Hi Rob,
>
> That's a good point and I thought about this very early on but figures it
> would not matter because the phase of the "Tx signal source" is just
> constant.
>
> In terms of phase we could think of it as "phase_we_want_to_measure +
> phase_of_tx_source". But since phase_of_tx_source does not change over
> runs, it shouldn't cause any differences. However, it was 2 months ago when
> I did this. I will have another look at it with your code.
>
> Thanks for pointing out the LO synchronization. When you say "from run to
> run", you mean when I quit/execute again the python script for example,
> right? I was sure that I had to take this as a fact for now. I am not
> familiar with the option of synchronizing the LO settings. In all the docs
> (e.g.
> https://kb.ettus.com/Synchronization_and_MIMO_Capability_with_USRP_Devices,
> https://kb.ettus.com/Synchronizing_USRP_Events_Using_Timed_Commands_in_UHD)
> I have not read about it. Can you elaborate on this?
>
> Thanks again,
> Lukas
>
>
>
> *Gesendet:* Freitag, 20. März 2020 um 13:44 Uhr
> *Von:* "Rob Kossler" 
> *An:* "Lukas Haase" , usrp-users <
> usrp-users@lists.ettus.com>
> *Betreff:* Re: [USRP-users] USRP X310 ignored DSP retuning on TX when
> using a timed command
> OK.  Thinking about it a little more, I think that perhaps the tx-to-rx
> phase measurement methodology was flawed.  So, maybe this is not any
> issue.  I changed the Python (new version attached) to send the gnuradio Tx
> signal source (which also drives Tx0 and Tx1) to one input of the
> multiply_conjugate (replacing Rx1 which previously was the other input).
> When I run, now the phase "walks", but always over the same range of
> values.  When I retune Tx0 and Rx0, the "walk" resets but still walks over
> the same range.  As to why the phase walks, I don't know the answer right
> off.
>
> On a separate topic, I noticed that your code does not synchronize the LO
> setting.  This means that the RF phase between the channels could vary from
> run to run.
>
> On Fri, Mar 20, 2020 at 12:04 PM Rob Kossler  wrote:
>
>> Lukas,
>> After looking at this a bit, I think that there is indeed an issue.  I
>> think that it is possible to get consistent tx-to-tx phase results and
>> consistent rx-to-rx phase results, but NOT consistent rx-to-tx phase
>> results.  A few remarks:
>>
>>- Setup
>>   - 2-channel X310/UBX-160 with two external loopback RF cables
>>   (with attenuation) such that Tx0=>Rx0 and Tx1=>Rx1 (I likely don't even
>>   need the loopback cables because I could operate on just the leakage 
>> signal
>>   from each channel, but I decided to use external cables).
>>   - UHD 3.15.LTS and gnuradio 3.7.13.5.
>>
>>
>>- Methodology
>>   - Transmit an identical waveform (1 MHz to

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-20 Thread Lukas Haase via USRP-users
Hi Rob,

 

That's a good point and I thought about this very early on but figures it would not matter because the phase of the "Tx signal source" is just constant.

 

In terms of phase we could think of it as "phase_we_want_to_measure + phase_of_tx_source". But since phase_of_tx_source does not change over runs, it shouldn't cause any differences. However, it was 2 months ago when I did this. I will have another look at it with your code.

 

Thanks for pointing out the LO synchronization. When you say "from run to run", you mean when I quit/execute again the python script for example, right? I was sure that I had to take this as a fact for now. I am not familiar with the option of synchronizing the LO settings. In all the docs (e.g. https://kb.ettus.com/Synchronization_and_MIMO_Capability_with_USRP_Devices, https://kb.ettus.com/Synchronizing_USRP_Events_Using_Timed_Commands_in_UHD) I have not read about it. Can you elaborate on this?

 

Thanks again,

Lukas

 

 
 

Gesendet: Freitag, 20. März 2020 um 13:44 Uhr
Von: "Rob Kossler" 
An: "Lukas Haase" , usrp-users 
Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command



OK.  Thinking about it a little more, I think that perhaps the tx-to-rx phase measurement methodology was flawed.  So, maybe this is not any issue.  I changed the Python (new version attached) to send the gnuradio Tx signal source (which also drives Tx0 and Tx1) to one input of the multiply_conjugate (replacing Rx1 which previously was the other input).  When I run, now the phase "walks", but always over the same range of values.  When I retune Tx0 and Rx0, the "walk" resets but still walks over the same range.  As to why the phase walks, I don't know the answer right off.

 

On a separate topic, I noticed that your code does not synchronize the LO setting.  This means that the RF phase between the channels could vary from run to run.

 


On Fri, Mar 20, 2020 at 12:04 PM Rob Kossler <rkoss...@nd.edu> wrote:



Lukas,

After looking at this a bit, I think that there is indeed an issue.  I think that it is possible to get consistent tx-to-tx phase results and consistent rx-to-rx phase results, but NOT consistent rx-to-tx phase results.  A few remarks:



	Setup
	
		2-channel X310/UBX-160 with two external loopback RF cables (with attenuation) such that Tx0=>Rx0 and Tx1=>Rx1 (I likely don't even need the loopback cables because I could operate on just the leakage signal from each channel, but I decided to use external cables). 
		UHD 3.15.LTS and gnuradio 3.7.13.5.
	
	





	Methodology
	
		Transmit an identical waveform (1 MHz tone) out of both Tx ports
		Measure relative Rx phase by using a multiply_conjugate block for the 2 Rx channels (see below for description of why I changed what you sent me) with output connected to a complex_to_mag_phase block and subsequent moving_average
		Use digital tuning (with timed commands) to toggle between 2 dsp frequencies while noting the relative phase results
	
	
	Test cases
	
		Case 1: Verify rx-to-rx phase results by sending tune requests to the 2 Rx channels (but sending nothing to the Tx channels)
		Case 2: Verify tx-to-tx phase results by sending tune requests to the 2 Tx channels (but sending nothing to the Rx channels)
		Case 3: Verify rx-to-tx phase results by sending tune requests to channel 0 Rx and Tx (but sending nothing to channel 1 Rx and Tx)
		Case 4: Verify rx-to-tx phase results by sending tune requests to channel 1 Rx and Tx (but sending nothing to channel 0 Rx and Tx)
	
	


Cases 1 and 2 show consistent results, but cases 3 and 4 do not. I cannot conceive of what the problem is. It is so perplexing that I hesitate to send this email because it seems I must be doing something wrong.  Perhaps there is a problem in the methodology above along with the test cases.  But, it seems sound to me.

 


The Rx block diagram you sent me does not match the Python code you sent.  This threw me off for a while.  In your block diagram, the phase measurement is made from the division of the two low pass filter outputs.  In the Python code you sent, the phase measurement uses only the first low pass filter output.  The reason this is important is that I suspected early on that the problem might be related to your gnuradio signal_source used for IF downconversion.  This signal source is not synchronous with the USRP as you change USRP freqs. However, I figured that it wasn't a problem because it was "divided out".  But, since it is actually not divided out,I believe that this was providing misleading results.

 

In the end, I just changed your code to add a "multiply_conjugate_cc" block with the two Rx channels as the two inputs.  This effectively uses one channel to downconvert the other and thus eliminates the need for the signal source in the Rx block diagram.  I then connected this m

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-20 Thread Lukas Haase via USRP-users
Hi Rob,

 

Thanks again so much for reproducing the setup.

Based on Cases 1-4 this is consistent which what I get and it really feels good that you are able to reproduce it.


 

I have been wrapping my head around WHY can happen for TX/RX but not for TX/TX or RX/RX. It's really hard to imagine to me why if everything clearly happens at the same time. One thought that I had:


	At time X, when the frequency is tuned, the phase accumulator is actually NOT reset to zero, to my knowledge. All that happens is that the phase increment is updated, such that at the next run, the LO signal is "current_value+1/freq_new/resolution" instead of "current_value+1/old_freq/resolution".
	The one thing that's different between TX and RX is the sign ... can it be that phase coherence is somehow lost because of the different sign?


Next, really sorry for confusing you with the block diagram. I use gnuradio-companion where it's really easy to connect/disconnect lines. And I used them for transparently switching between the cases "absolute phase RX1", "absolute phase RX2" and "relative phase RX1-RX2" ... by just rewiring and recreating the block diagram. Hence I added the annotations in https://snipboard.io/i9jLJg.jpg : "Take this for RX1", "Take this for RX2", "Take this for rel. phase". Again, sorry that this was inconsistent between the screenshot and the code. I had rewired it to absolute phase at that point.

 

Great idea with the multiply_conjugate_cc block, I haven't thought of this yet. Thank for for sending your updated code ... I will continue with that now ...

 

 

Best,

Lukas

 

 

Gesendet: Freitag, 20. März 2020 um 12:04 Uhr
Von: "Rob Kossler" 
An: "Lukas Haase" , usrp-users 
Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command



Lukas,

After looking at this a bit, I think that there is indeed an issue.  I think that it is possible to get consistent tx-to-tx phase results and consistent rx-to-rx phase results, but NOT consistent rx-to-tx phase results.  A few remarks:



	Setup
	
		2-channel X310/UBX-160 with two external loopback RF cables (with attenuation) such that Tx0=>Rx0 and Tx1=>Rx1 (I likely don't even need the loopback cables because I could operate on just the leakage signal from each channel, but I decided to use external cables). 
		UHD 3.15.LTS and gnuradio 3.7.13.5.
	
	





	Methodology
	
		Transmit an identical waveform (1 MHz tone) out of both Tx ports
		Measure relative Rx phase by using a multiply_conjugate block for the 2 Rx channels (see below for description of why I changed what you sent me) with output connected to a complex_to_mag_phase block and subsequent moving_average
		Use digital tuning (with timed commands) to toggle between 2 dsp frequencies while noting the relative phase results
	
	
	Test cases
	
		Case 1: Verify rx-to-rx phase results by sending tune requests to the 2 Rx channels (but sending nothing to the Tx channels)
		Case 2: Verify tx-to-tx phase results by sending tune requests to the 2 Tx channels (but sending nothing to the Rx channels)
		Case 3: Verify rx-to-tx phase results by sending tune requests to channel 0 Rx and Tx (but sending nothing to channel 1 Rx and Tx)
		Case 4: Verify rx-to-tx phase results by sending tune requests to channel 1 Rx and Tx (but sending nothing to channel 0 Rx and Tx)
	
	


Cases 1 and 2 show consistent results, but cases 3 and 4 do not. I cannot conceive of what the problem is. It is so perplexing that I hesitate to send this email because it seems I must be doing something wrong.  Perhaps there is a problem in the methodology above along with the test cases.  But, it seems sound to me.

 


The Rx block diagram you sent me does not match the Python code you sent.  This threw me off for a while.  In your block diagram, the phase measurement is made from the division of the two low pass filter outputs.  In the Python code you sent, the phase measurement uses only the first low pass filter output.  The reason this is important is that I suspected early on that the problem might be related to your gnuradio signal_source used for IF downconversion.  This signal source is not synchronous with the USRP as you change USRP freqs. However, I figured that it wasn't a problem because it was "divided out".  But, since it is actually not divided out,I believe that this was providing misleading results.

 

In the end, I just changed your code to add a "multiply_conjugate_cc" block with the two Rx channels as the two inputs.  This effectively uses one channel to downconvert the other and thus eliminates the need for the signal source in the Rx block diagram.  I then connected this multiply_conjugate directly to the complex_to_mag_phase.  You could simplify the code by removing the other multiply blocks, low pass filters, and divide since these are no

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-20 Thread Rob Kossler via USRP-users
 continuous streaming but perhaps there is still something in the gnuradio
>>config that is not quite right.  But, I don't know what that is right now.
>>I need to think about this a bit
>>
>> Rob
>>
>> On Thu, Mar 19, 2020 at 8:17 PM Lukas Haase  wrote:
>>
>>> Hi Rob,
>>>
>>> Sorry I really should have ran the python file before uploading. The
>>> issue was that I combined to files into one and forgot to remove the
>>> imported file.
>>> Here is a new one (tested): http://paste.ubuntu.com/p/VsGRmsbZQ5/
>>>
>>>
>>> Thanks for reporting your results  very interesting!
>>>
>>> Why do you think second mode makes sense to you? (assuming you are using
>>> timed commands to to retune TX+RX at the same time)
>>>
>>> In general, it seems to me that things are related to streaming
>>> start/stop. Maybe things are reset when streaming starts/ends but not when
>>> re-tuning?
>>>
>>> Maybe this is what Marcus was mentioning: resetting phase accumulator
>>> vs. "increment register is updated with the new phase increment"?
>>>
>>> MAYBE stopping/starting resets the phase accumulator to zero and just
>>> timed retuning doesn't reset anything. But still, my question is left why
>>> this would result in a random phase offset between DUC and DDC.
>>>
>>> Thanks again!!
>>> Lukas
>>>
>>>
>>> *Gesendet:* Donnerstag, 19. März 2020 um 19:16 Uhr
>>> *Von:* "Rob Kossler" 
>>> *An:* "Lukas Haase" 
>>> *Cc:* "USRP-users@lists.ettus.com" 
>>> *Betreff:* Re: [USRP-users] USRP X310 ignored DSP retuning on TX when
>>> using a timed command
>>> Lukas,
>>> I installed gnuradio and tried to run but encounter the following.  I'm
>>> guessing this is your block.
>>> Traceback (most recent call last):
>>>   File "test.py", line 25, in 
>>> import epy_block_1
>>> ImportError: No module named epy_block_1
>>> Rob
>>>
>>> On Thu, Mar 19, 2020 at 6:28 PM Rob Kossler  wrote:
>>>
>>>> Ok.  False alarm.  I forgot about the dboard clock needing set to 20MHz
>>>> for RF freq below 1 GHz.  When I made this change, now I get consistent
>>>> Rx-Tx phase for the first mode where both Tx and Rx start/stop at each 
>>>> test.
>>>> Rob
>>>>
>>>> On Thu, Mar 19, 2020 at 6:10 PM Rob Kossler  wrote:
>>>>
>>>>> Ok. I modified my code to be more like yours...
>>>>>
>>>>>- toggling dsp freq rather than LO freq
>>>>>- LO at 900 MHz
>>>>>- external connections Tx0 => Splitter_1x2 => both Rx0 and Rx1
>>>>>- Previously, I was starting / stopping both Rx & Tx in between
>>>>>each test.  Now, I added a mode where the Tx is on continuously, and 
>>>>> the Rx
>>>>>starts & stops for each test after the dsp freq change
>>>>>
>>>>> The results are the following:
>>>>>
>>>>>- In the first mode where both Tx and Rx start/stop at each test,
>>>>>I get consistent group delay (as measured by the correlation peak 
>>>>> index)
>>>>>for both Rx-Rx and Rx-Tx.  But for phase, the Rx-Rx phase is 
>>>>> consistent,
>>>>>but the Rx-Tx phase seems random
>>>>>- In the second mode where Tx is on continuously and I start/stop
>>>>>Rx after each dsp freq change, the group delay is constant for Rx-Rx 
>>>>> but
>>>>>random for Rx-Tx.  The phase results are constant for Rx-Rx but random 
>>>>> for
>>>>>Rx-Tx.
>>>>>
>>>>> Regarding the 2nd mode, this makes sense to me.  But, for the 1st
>>>>> mode, I don't understand why the Rx-Tx phase seems random. Still thinking
>>>>> about it
>>>>> Rob
>>>>>
>>>>> On Thu, Mar 19, 2020 at 4:35 PM Rob Kossler  wrote:
>>>>>
>>>>>> Lukas,
>>>>>> Just before receiving your email, I ran the following with my custom
>>>>>> c++ & matlab software using X310/UBX-160 with the connections I 
>>>>>> described.
>>>>>> The following shows the output which is very consistent.  I used a 100 
>>>>

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-20 Thread Rob Kossler via USRP-users
BE stopping/starting resets the phase accumulator to zero and just
>> timed retuning doesn't reset anything. But still, my question is left why
>> this would result in a random phase offset between DUC and DDC.
>>
>> Thanks again!!
>> Lukas
>>
>>
>> *Gesendet:* Donnerstag, 19. März 2020 um 19:16 Uhr
>> *Von:* "Rob Kossler" 
>> *An:* "Lukas Haase" 
>> *Cc:* "USRP-users@lists.ettus.com" 
>> *Betreff:* Re: [USRP-users] USRP X310 ignored DSP retuning on TX when
>> using a timed command
>> Lukas,
>> I installed gnuradio and tried to run but encounter the following.  I'm
>> guessing this is your block.
>> Traceback (most recent call last):
>>   File "test.py", line 25, in 
>> import epy_block_1
>> ImportError: No module named epy_block_1
>> Rob
>>
>> On Thu, Mar 19, 2020 at 6:28 PM Rob Kossler  wrote:
>>
>>> Ok.  False alarm.  I forgot about the dboard clock needing set to 20MHz
>>> for RF freq below 1 GHz.  When I made this change, now I get consistent
>>> Rx-Tx phase for the first mode where both Tx and Rx start/stop at each test.
>>> Rob
>>>
>>> On Thu, Mar 19, 2020 at 6:10 PM Rob Kossler  wrote:
>>>
>>>> Ok. I modified my code to be more like yours...
>>>>
>>>>- toggling dsp freq rather than LO freq
>>>>- LO at 900 MHz
>>>>- external connections Tx0 => Splitter_1x2 => both Rx0 and Rx1
>>>>- Previously, I was starting / stopping both Rx & Tx in between
>>>>each test.  Now, I added a mode where the Tx is on continuously, and 
>>>> the Rx
>>>>starts & stops for each test after the dsp freq change
>>>>
>>>> The results are the following:
>>>>
>>>>- In the first mode where both Tx and Rx start/stop at each test, I
>>>>get consistent group delay (as measured by the correlation peak index) 
>>>> for
>>>>both Rx-Rx and Rx-Tx.  But for phase, the Rx-Rx phase is consistent, but
>>>>the Rx-Tx phase seems random
>>>>- In the second mode where Tx is on continuously and I start/stop
>>>>Rx after each dsp freq change, the group delay is constant for Rx-Rx but
>>>>random for Rx-Tx.  The phase results are constant for Rx-Rx but random 
>>>> for
>>>>Rx-Tx.
>>>>
>>>> Regarding the 2nd mode, this makes sense to me.  But, for the 1st mode,
>>>> I don't understand why the Rx-Tx phase seems random. Still thinking about
>>>> it
>>>> Rob
>>>>
>>>> On Thu, Mar 19, 2020 at 4:35 PM Rob Kossler  wrote:
>>>>
>>>>> Lukas,
>>>>> Just before receiving your email, I ran the following with my custom
>>>>> c++ & matlab software using X310/UBX-160 with the connections I described.
>>>>> The following shows the output which is very consistent.  I used a 100 
>>>>> tone
>>>>> multi-tone waveform spread over 4 MHz bandwidth (using 5 MS/s sample rate
>>>>> on Tx and Rx).  Note the consistency of results as I toggled between 2
>>>>> frequencies: 2450 and 2460 MHz.
>>>>>
>>>>> My method was the following:
>>>>>
>>>>>- Tx waveform was 500 points long
>>>>>- Rx capture was 5000 points long
>>>>>- Compute cross-correlation (using Matlab xcorr) as follows:
>>>>>xcorr(rx0, conj(tx)) AND xcorr(rx0,conj(rx1))
>>>>>- Find the correlation peak (which was very pronounced) which
>>>>>shows the sample delay between the two signals.  Extract the phase at 
>>>>> the
>>>>>peak
>>>>>
>>>>> Oops, I just realized that I used a constant DSP freq (10 MHz) and I
>>>>> changed the LO freq in my test.  I will try again with moving the DSP freq
>>>>> instead.
>>>>> Rob
>>>>>
>>>>> Test 1: freq = 2450.0 MHz
>>>>>   Rx0/Tx0 xcorr peak at index 108 with phase -121.8
>>>>>   Rx0/Rx1 xcorr peak at index 115 with phase -95.7
>>>>> Test 2: freq = 2460.0 MHz
>>>>>   Rx0/Tx0 xcorr peak at index 108 with phase -58.7
>>>>>   Rx0/Rx1 xcorr peak at index 115 with phase 13.1
>>>>> Test 3: freq = 2450.0 MHz
>>>>>   Rx0/Tx0 xcorr peak at index 108 with phase -121.7
>>>>

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-19 Thread Rob Kossler via USRP-users
Hi Lukas,
A few remarks:

   - The 2nd code you sent works fine.  Thanks.
   - I'm not sure that starting/stopping as I do in my program is causing
   the issue.  The only reason I didn't continuously stream both Rx and Tx
   like you do in gnuradio is because my software is not setup to do that.
   - So, I still think it's possible that UHD can do the job with
   continuous streaming but perhaps there is still something in the gnuradio
   config that is not quite right.  But, I don't know what that is right now.
   I need to think about this a bit

Rob

On Thu, Mar 19, 2020 at 8:17 PM Lukas Haase  wrote:

> Hi Rob,
>
> Sorry I really should have ran the python file before uploading. The issue
> was that I combined to files into one and forgot to remove the imported
> file.
> Here is a new one (tested): http://paste.ubuntu.com/p/VsGRmsbZQ5/
>
>
> Thanks for reporting your results  very interesting!
>
> Why do you think second mode makes sense to you? (assuming you are using
> timed commands to to retune TX+RX at the same time)
>
> In general, it seems to me that things are related to streaming
> start/stop. Maybe things are reset when streaming starts/ends but not when
> re-tuning?
>
> Maybe this is what Marcus was mentioning: resetting phase accumulator vs.
> "increment register is updated with the new phase increment"?
>
> MAYBE stopping/starting resets the phase accumulator to zero and just
> timed retuning doesn't reset anything. But still, my question is left why
> this would result in a random phase offset between DUC and DDC.
>
> Thanks again!!
> Lukas
>
>
> *Gesendet:* Donnerstag, 19. März 2020 um 19:16 Uhr
> *Von:* "Rob Kossler" 
> *An:* "Lukas Haase" 
> *Cc:* "USRP-users@lists.ettus.com" 
> *Betreff:* Re: [USRP-users] USRP X310 ignored DSP retuning on TX when
> using a timed command
> Lukas,
> I installed gnuradio and tried to run but encounter the following.  I'm
> guessing this is your block.
> Traceback (most recent call last):
>   File "test.py", line 25, in 
> import epy_block_1
> ImportError: No module named epy_block_1
> Rob
>
> On Thu, Mar 19, 2020 at 6:28 PM Rob Kossler  wrote:
>
>> Ok.  False alarm.  I forgot about the dboard clock needing set to 20MHz
>> for RF freq below 1 GHz.  When I made this change, now I get consistent
>> Rx-Tx phase for the first mode where both Tx and Rx start/stop at each test.
>> Rob
>>
>> On Thu, Mar 19, 2020 at 6:10 PM Rob Kossler  wrote:
>>
>>> Ok. I modified my code to be more like yours...
>>>
>>>- toggling dsp freq rather than LO freq
>>>- LO at 900 MHz
>>>- external connections Tx0 => Splitter_1x2 => both Rx0 and Rx1
>>>- Previously, I was starting / stopping both Rx & Tx in between each
>>>test.  Now, I added a mode where the Tx is on continuously, and the Rx
>>>starts & stops for each test after the dsp freq change
>>>
>>> The results are the following:
>>>
>>>- In the first mode where both Tx and Rx start/stop at each test, I
>>>get consistent group delay (as measured by the correlation peak index) 
>>> for
>>>both Rx-Rx and Rx-Tx.  But for phase, the Rx-Rx phase is consistent, but
>>>the Rx-Tx phase seems random
>>>- In the second mode where Tx is on continuously and I start/stop Rx
>>>after each dsp freq change, the group delay is constant for Rx-Rx but
>>>random for Rx-Tx.  The phase results are constant for Rx-Rx but random 
>>> for
>>>Rx-Tx.
>>>
>>> Regarding the 2nd mode, this makes sense to me.  But, for the 1st mode,
>>> I don't understand why the Rx-Tx phase seems random. Still thinking about
>>> it
>>> Rob
>>>
>>> On Thu, Mar 19, 2020 at 4:35 PM Rob Kossler  wrote:
>>>
>>>> Lukas,
>>>> Just before receiving your email, I ran the following with my custom
>>>> c++ & matlab software using X310/UBX-160 with the connections I described.
>>>> The following shows the output which is very consistent.  I used a 100 tone
>>>> multi-tone waveform spread over 4 MHz bandwidth (using 5 MS/s sample rate
>>>> on Tx and Rx).  Note the consistency of results as I toggled between 2
>>>> frequencies: 2450 and 2460 MHz.
>>>>
>>>> My method was the following:
>>>>
>>>>- Tx waveform was 500 points long
>>>>- Rx capture was 5000 points long
>>>>- Compute cross-correlation (using Matlab xcorr

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-19 Thread Marcus D. Leech via USRP-users

On 03/19/2020 08:16 PM, Lukas Haase via USRP-users wrote:

Hi Rob,
Sorry I really should have ran the python file before uploading. The 
issue was that I combined to files into one and forgot to remove the 
imported file.

Here is a new one (tested): http://paste.ubuntu.com/p/VsGRmsbZQ5/
Thanks for reporting your results  very interesting!
Why do you think second mode makes sense to you? (assuming you are 
using timed commands to to retune TX+RX at the same time)
In general, it seems to me that things are related to streaming 
start/stop. Maybe things are reset when streaming starts/ends but not 
when re-tuning?
Maybe this is what Marcus was mentioning: resetting phase accumulator 
vs. "increment register is updated with the new phase increment"?
MAYBE stopping/starting resets the phase accumulator to zero and just 
timed retuning doesn't reset anything. But still, my question is left 
why this would result in a random phase offset between DUC and DDC.

Thanks again!!
Lukas

So, having spent a couple of hours snooping around the X3xx FPGA code, 
where Verilog is not one of my native languages, I have come to
  a bit of a conclusion about the ways things work.  Now, keep in mind, 
this is like me reading War and Peace in the original Russian, and as
  an English speaker, coming the vague conclusion that "It was about 
Russia".


There's a "settings bus" within the FPGA that is implemented with AXI 
FIFO modules.  If your command (which results, most often in
  having to "set" one or more registers via the settings bus) is not a 
timed command, it enters the FIFO, and then is "executed" one
  clock later.  If it has a time associated with it, then it is 
withdrawn when that time has been reached in "vita_time".  Note that 
since this
  is a FIFO, commands that are to be executed "at the same time" will 
be serialized by the inherent FIFO nature of execution.


So, with two DDC settings and two DUC settings all sitting in the FIFO, 
their actual execution times will be 'spread' over (as far as I can tell)
  4 clocks cycles of the FIFO, or about 20nsec.  Now in the case where 
multiple X3xx are involved, the FIFO will look identical across all
  the units, and will execute at the same time, but still be 
serialized.  But if you have two DDC settings across a pair of X3xx, the 
settings
  will execute at exactly the same time, since they will in effect be 
executing in parallel.   Put another way, with shared clocks, and a common
  "view" of system time, parallel FIFOs will get drained in the same 
order and at the same rate.


Someone with a better understanding of the FPGA really should 
comment.But this is my (albeit incomplete) understanding of the

  settings-bus logic the FPGA.

Now, even having said THIS, since you'd expect the FIFO to be 
deterministic.  So, you'd not expect there to be large random

  phase offsets that differ from run to run, I think.



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Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-19 Thread Lukas Haase via USRP-users
Hi Rob,

 

Sorry I really should have ran the python file before uploading. The issue was that I combined to files into one and forgot to remove the imported file.

Here is a new one (tested): http://paste.ubuntu.com/p/VsGRmsbZQ5/

 

 

Thanks for reporting your results  very interesting!

 

Why do you think second mode makes sense to you? (assuming you are using timed commands to to retune TX+RX at the same time)

 

In general, it seems to me that things are related to streaming start/stop. Maybe things are reset when streaming starts/ends but not when re-tuning?

 

Maybe this is what Marcus was mentioning: resetting phase accumulator vs. "increment register is updated with the new phase increment"?

 

MAYBE stopping/starting resets the phase accumulator to zero and just timed retuning doesn't reset anything. But still, my question is left why this would result in a random phase offset between DUC and DDC.

 

Thanks again!!

Lukas

 
 

Gesendet: Donnerstag, 19. März 2020 um 19:16 Uhr
Von: "Rob Kossler" 
An: "Lukas Haase" 
Cc: "USRP-users@lists.ettus.com" 
Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command



Lukas,

I installed gnuradio and tried to run but encounter the following.  I'm guessing this is your block.

Traceback (most recent call last):
  File "test.py", line 25, in 
    import epy_block_1
ImportError: No module named epy_block_1

Rob

 


On Thu, Mar 19, 2020 at 6:28 PM Rob Kossler <rkoss...@nd.edu> wrote:



Ok.  False alarm.  I forgot about the dboard clock needing set to 20MHz for RF freq below 1 GHz.  When I made this change, now I get consistent Rx-Tx phase for the first mode where both Tx and Rx start/stop at each test.

Rob

 


On Thu, Mar 19, 2020 at 6:10 PM Rob Kossler <rkoss...@nd.edu> wrote:




Ok. I modified my code to be more like yours...



	toggling dsp freq rather than LO freq
	LO at 900 MHz
	external connections Tx0 => Splitter_1x2 => both Rx0 and Rx1
	Previously, I was starting / stopping both Rx & Tx in between each test.  Now, I added a mode where the Tx is on continuously, and the Rx starts & stops for each test after the dsp freq change


The results are the following:


	In the first mode where both Tx and Rx start/stop at each test, I get consistent group delay (as measured by the correlation peak index) for both Rx-Rx and Rx-Tx.  But for phase, the Rx-Rx phase is consistent, but the Rx-Tx phase seems random
	In the second mode where Tx is on continuously and I start/stop Rx after each dsp freq change, the group delay is constant for Rx-Rx but random for Rx-Tx.  The phase results are constant for Rx-Rx but random for Rx-Tx.


Regarding the 2nd mode, this makes sense to me.  But, for the 1st mode, I don't understand why the Rx-Tx phase seems random. Still thinking about it

Rob


 


On Thu, Mar 19, 2020 at 4:35 PM Rob Kossler <rkoss...@nd.edu> wrote:



Lukas,

Just before receiving your email, I ran the following with my custom c++ & matlab software using X310/UBX-160 with the connections I described.  The following shows the output which is very consistent.  I used a 100 tone multi-tone waveform spread over 4 MHz bandwidth (using 5 MS/s sample rate on Tx and Rx).  Note the consistency of results as I toggled between 2 frequencies: 2450 and 2460 MHz.

 

My method was the following:



	Tx waveform was 500 points long
	Rx capture was 5000 points long
	Compute cross-correlation (using Matlab xcorr) as follows: xcorr(rx0, conj(tx)) AND xcorr(rx0,conj(rx1))
	Find the correlation peak (which was very pronounced) which shows the sample delay between the two signals.  Extract the phase at the peak


Oops, I just realized that I used a constant DSP freq (10 MHz) and I changed the LO freq in my test.  I will try again with moving the DSP freq instead.

Rob


 

Test 1: freq = 2450.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -121.8
  Rx0/Rx1 xcorr peak at index 115 with phase -95.7
Test 2: freq = 2460.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -58.7
  Rx0/Rx1 xcorr peak at index 115 with phase 13.1
Test 3: freq = 2450.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -121.7
  Rx0/Rx1 xcorr peak at index 115 with phase -95.8
Test 4: freq = 2460.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -58.6
  Rx0/Rx1 xcorr peak at index 115 with phase 13.0
Test 5: freq = 2450.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -121.7
  Rx0/Rx1 xcorr peak at index 115 with phase -95.8
Test 6: freq = 2460.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -58.8
  Rx0/Rx1 xcorr peak at index 115 with phase 12.7
Test 7: freq = 2450.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -121.8
  Rx0/Rx1 xcorr peak at index 115 with phase -95.9
Test 8: freq = 2460.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -58.7
  Rx0/Rx1 xcorr peak at index 115 with phase 12.9
Test 9: freq = 2450.0 MHz
  Rx0/Tx0 xcorr peak at 

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-19 Thread Rob Kossler via USRP-users
ote:
>>>
>>>> Hi Rob,
>>>>
>>>> Yes, I confirm your conclusion.
>>>>
>>>>
>>>>- I calculate the relative phase by dividing the outputs of both
>>>>receivers. To understand better, note that I have an additional "IF 
>>>> stage"
>>>>in my own signal flow such that I exclude DC offset correction etc. the
>>>>USRP may perform. This is the block diagram of the transmitter part:
>>>>https://snipboard.io/YFgIKs.jpg . I send "exp(1j*1MHz*t) . This
>>>>shows the receiver part: https://snipboard.io/i9jLJg.jpg . I
>>>>multiply the received signal with exp(-1j*1MHz*t) and filter them. Then 
>>>> I
>>>>divide both streams and take the phase part. I take a moving average 
>>>> (for
>>>>flucatuations), add pi and display the number.
>>>>- https://snipboard.io/YFgIKs.jpg https://snipboard.io/YFgIKs.jpg
>>>>https://snipboard.io/YFgIKs.jpg That's so nice, thank you!! My code
>>>>is here: http://paste.ubuntu.com/p/MbCJfPGzYW/ . I'm not sure if
>>>>you have gnuradio(and QT) installed but if yes, simply "python2
>>>>switch_on_click.py" should do. Let me quickly elaborate how it works:
>>>>   - Class "switch_on_click" implements a normal gnuradio flow with
>>>>   USRP transmitter and receiver.
>>>>   - It also uses a custom module together with buttons and a probe
>>>>   block to call functions upon clicking on a button
>>>>   - The callback functions are defined in class "blk"
>>>>   - The most important is "def button_rtx_handler" on line 106
>>>>   which is executed when user clicks on button "Switch RTX (together)"
>>>>- Again, thank you for trying this out!! If it works, would you
>>>>mind sharing this code then? I may be able to check then where it 
>>>> breaks on
>>>>my system
>>>>- I use 900 MHz as default center frequency (and "rf_freq"). When
>>>>clicking, I jump between dsp_freq=0 and dsp_freq=500e3. As to my 
>>>> waveform,
>>>>you can infer from my screenshots and code above: I am transmitting and
>>>>receiving a 1MHz waveform (which acts as an additional "IF stage"). The
>>>>received signal is then downconcerted from 1MHz to DC. I use 5 MSsps
>>>>sampling rate.
>>>>
>>>>
>>>> Again, thank you SO much.
>>>>
>>>> Best,
>>>> Lukas
>>>>
>>>>
>>>> *Gesendet:* Donnerstag, 19. März 2020 um 10:43 Uhr
>>>> *Von:* "Rob Kossler" 
>>>> *An:* "Lukas Haase" 
>>>> *Cc:* "USRP-users@lists.ettus.com" 
>>>> *Betreff:* Re: [USRP-users] USRP X310 ignored DSP retuning on TX when
>>>> using a timed command
>>>> Hi Lukas,
>>>> So, the conclusion is that your Rx0-to-Rx1 relative phase is nearly
>>>> constant such that it seems that both Rx0/Rx1 are phase coherent and
>>>> Tx0/Tx1 are phase coherent.  But, phase from Tx-to-Rx is random.  Please
>>>> correct me if that is wrong.
>>>>
>>>> I have a few comments:
>>>>
>>>>- How do you measure/calculate the relative phase?
>>>>- Can you send me the full Python code to look at?  As I mentioned
>>>>previously, I am not too good at gnuradio/Python, but I might be able to
>>>>spot something.
>>>>- As to your question, I always use synchronous measurements.  And,
>>>>I'm confident that my Rx-to-Rx phase is coherent.  But, I haven't really
>>>>looked at Tx-to-Rx in a while so I will do so later today.  Here are the
>>>>steps I plan to take:
>>>>   1. Connect Tx0 to Rx1.  Note that there is a pretty strong
>>>>   leakage signal from Tx0 to Rx0 so I don't really need to provide a 
>>>> physical
>>>>   connection in order to get a signal on Rx0.  The signal attenuation 
>>>> in this
>>>>   leakage path is approx 40 dB so it is not too much different than the
>>>>   signal level I will receive on Rx1 if I use an external 30 dB 
>>>> attenuator.
>>>>   2. Set Rx and Tx frequency to freq 1
>>>>   3. Measure and note the relativ

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-19 Thread Rob Kossler via USRP-users
y the received signal with exp(-1j*1MHz*t) and filter them. Then I
>>>divide both streams and take the phase part. I take a moving average (for
>>>flucatuations), add pi and display the number.
>>>- https://snipboard.io/YFgIKs.jpg https://snipboard.io/YFgIKs.jpg
>>>https://snipboard.io/YFgIKs.jpg That's so nice, thank you!! My code
>>>is here: http://paste.ubuntu.com/p/MbCJfPGzYW/ . I'm not sure if you
>>>have gnuradio(and QT) installed but if yes, simply "python2
>>>switch_on_click.py" should do. Let me quickly elaborate how it works:
>>>   - Class "switch_on_click" implements a normal gnuradio flow with
>>>   USRP transmitter and receiver.
>>>   - It also uses a custom module together with buttons and a probe
>>>   block to call functions upon clicking on a button
>>>   - The callback functions are defined in class "blk"
>>>   - The most important is "def button_rtx_handler" on line 106
>>>   which is executed when user clicks on button "Switch RTX (together)"
>>>- Again, thank you for trying this out!! If it works, would you mind
>>>sharing this code then? I may be able to check then where it breaks on my
>>>system
>>>- I use 900 MHz as default center frequency (and "rf_freq"). When
>>>clicking, I jump between dsp_freq=0 and dsp_freq=500e3. As to my 
>>> waveform,
>>>you can infer from my screenshots and code above: I am transmitting and
>>>receiving a 1MHz waveform (which acts as an additional "IF stage"). The
>>>received signal is then downconcerted from 1MHz to DC. I use 5 MSsps
>>>sampling rate.
>>>
>>>
>>> Again, thank you SO much.
>>>
>>> Best,
>>> Lukas
>>>
>>>
>>> *Gesendet:* Donnerstag, 19. März 2020 um 10:43 Uhr
>>> *Von:* "Rob Kossler" 
>>> *An:* "Lukas Haase" 
>>> *Cc:* "USRP-users@lists.ettus.com" 
>>> *Betreff:* Re: [USRP-users] USRP X310 ignored DSP retuning on TX when
>>> using a timed command
>>> Hi Lukas,
>>> So, the conclusion is that your Rx0-to-Rx1 relative phase is nearly
>>> constant such that it seems that both Rx0/Rx1 are phase coherent and
>>> Tx0/Tx1 are phase coherent.  But, phase from Tx-to-Rx is random.  Please
>>> correct me if that is wrong.
>>>
>>> I have a few comments:
>>>
>>>- How do you measure/calculate the relative phase?
>>>- Can you send me the full Python code to look at?  As I mentioned
>>>previously, I am not too good at gnuradio/Python, but I might be able to
>>>spot something.
>>>- As to your question, I always use synchronous measurements.  And,
>>>I'm confident that my Rx-to-Rx phase is coherent.  But, I haven't really
>>>looked at Tx-to-Rx in a while so I will do so later today.  Here are the
>>>steps I plan to take:
>>>   1. Connect Tx0 to Rx1.  Note that there is a pretty strong
>>>   leakage signal from Tx0 to Rx0 so I don't really need to provide a 
>>> physical
>>>   connection in order to get a signal on Rx0.  The signal attenuation 
>>> in this
>>>   leakage path is approx 40 dB so it is not too much different than the
>>>   signal level I will receive on Rx1 if I use an external 30 dB 
>>> attenuator.
>>>   2. Set Rx and Tx frequency to freq 1
>>>   3. Measure and note the relative phase for Rx0/Tx0 and Rx1/Tx0
>>>   for freq 1
>>>   4. Set Rx and Tx frequency to freq 2
>>>   5. Measure and note the relative phase for Rx0/Tx0 and Rx1/Tx0
>>>   for freq 2
>>>   6. Repeat steps 2-5 a few times to ensure that the measurements
>>>   are repeatable
>>>- Questions: what should I use for freq 1 and freq 2?  What waveform
>>>are you transmitting?  What sample rates for Tx and Rx?
>>>
>>> Rob
>>>
>>>
>>>
>>> On Wed, Mar 18, 2020 at 7:47 PM Lukas Haase via USRP-users <
>>> usrp-users@lists.ettus.com> wrote:
>>>
>>>> Hi Rob,
>>>>
>>>> I think the issue is really having two usrp_multi devices with timed
>>>> commands and same timestmap or similar. From your tests below:
>>>>
>>>> 1.) I can *confirm *that the relative phase between two RX in your
>>>> suggested test 

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-19 Thread Rob Kossler via USRP-users
ow with
>>   USRP transmitter and receiver.
>>   - It also uses a custom module together with buttons and a probe
>>   block to call functions upon clicking on a button
>>   - The callback functions are defined in class "blk"
>>   - The most important is "def button_rtx_handler" on line 106 which
>>   is executed when user clicks on button "Switch RTX (together)"
>>- Again, thank you for trying this out!! If it works, would you mind
>>sharing this code then? I may be able to check then where it breaks on my
>>system
>>- I use 900 MHz as default center frequency (and "rf_freq"). When
>>clicking, I jump between dsp_freq=0 and dsp_freq=500e3. As to my waveform,
>>    you can infer from my screenshots and code above: I am transmitting and
>>receiving a 1MHz waveform (which acts as an additional "IF stage"). The
>>received signal is then downconcerted from 1MHz to DC. I use 5 MSsps
>>sampling rate.
>>
>>
>> Again, thank you SO much.
>>
>> Best,
>> Lukas
>>
>>
>> *Gesendet:* Donnerstag, 19. März 2020 um 10:43 Uhr
>> *Von:* "Rob Kossler" 
>> *An:* "Lukas Haase" 
>> *Cc:* "USRP-users@lists.ettus.com" 
>> *Betreff:* Re: [USRP-users] USRP X310 ignored DSP retuning on TX when
>> using a timed command
>> Hi Lukas,
>> So, the conclusion is that your Rx0-to-Rx1 relative phase is nearly
>> constant such that it seems that both Rx0/Rx1 are phase coherent and
>> Tx0/Tx1 are phase coherent.  But, phase from Tx-to-Rx is random.  Please
>> correct me if that is wrong.
>>
>> I have a few comments:
>>
>>- How do you measure/calculate the relative phase?
>>- Can you send me the full Python code to look at?  As I mentioned
>>previously, I am not too good at gnuradio/Python, but I might be able to
>>spot something.
>>- As to your question, I always use synchronous measurements.  And,
>>I'm confident that my Rx-to-Rx phase is coherent.  But, I haven't really
>>looked at Tx-to-Rx in a while so I will do so later today.  Here are the
>>steps I plan to take:
>>   1. Connect Tx0 to Rx1.  Note that there is a pretty strong leakage
>>   signal from Tx0 to Rx0 so I don't really need to provide a physical
>>   connection in order to get a signal on Rx0.  The signal attenuation in 
>> this
>>   leakage path is approx 40 dB so it is not too much different than the
>>   signal level I will receive on Rx1 if I use an external 30 dB 
>> attenuator.
>>   2. Set Rx and Tx frequency to freq 1
>>   3. Measure and note the relative phase for Rx0/Tx0 and Rx1/Tx0 for
>>   freq 1
>>   4. Set Rx and Tx frequency to freq 2
>>   5. Measure and note the relative phase for Rx0/Tx0 and Rx1/Tx0 for
>>   freq 2
>>   6. Repeat steps 2-5 a few times to ensure that the measurements
>>   are repeatable
>>- Questions: what should I use for freq 1 and freq 2?  What waveform
>>are you transmitting?  What sample rates for Tx and Rx?
>>
>> Rob
>>
>>
>>
>> On Wed, Mar 18, 2020 at 7:47 PM Lukas Haase via USRP-users <
>> usrp-users@lists.ettus.com> wrote:
>>
>>> Hi Rob,
>>>
>>> I think the issue is really having two usrp_multi devices with timed
>>> commands and same timestmap or similar. From your tests below:
>>>
>>> 1.) I can *confirm *that the relative phase between two RX in your
>>> suggested test is always the same! In fact, it is always 4.56 rad, even
>>> across restarts and for different frequencies! That somewhat makes sense
>>> because the phase offset is now only dependent on the difference between
>>> the two channels (fixed) and cable lengths from the splitter (fixed). I
>>> verified by removing the timed command on usrp source, the phase offset
>>> becomes random after each retune. Of course, this is independent of TX
>>> tuning (timed vs. not). For reference, this is the code used:
>>>
>>> tune_req_rx = uhd.tune_request()
>>> tune_req_rx.rf_freq_policy = uhd.tune_request.POLICY_NONE
>>> tune_req_rx.dsp_freq_policy = uhd.tune_request.POLICY_MANUAL
>>> tune_req_rx.dsp_freq = -dsp_freq
>>> tune_req_tx = uhd.tune_request()
>>> tune_req_tx.rf_freq_policy = uhd.tune_request.POLICY_NONE
>>> tune_req_tx.dsp_freq_policy = uhd.tune_request.POLICY

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-19 Thread Rob Kossler via USRP-users
Lukas,
Just before receiving your email, I ran the following with my custom c++ &
matlab software using X310/UBX-160 with the connections I described.  The
following shows the output which is very consistent.  I used a 100 tone
multi-tone waveform spread over 4 MHz bandwidth (using 5 MS/s sample rate
on Tx and Rx).  Note the consistency of results as I toggled between 2
frequencies: 2450 and 2460 MHz.

My method was the following:

   - Tx waveform was 500 points long
   - Rx capture was 5000 points long
   - Compute cross-correlation (using Matlab xcorr) as follows: xcorr(rx0,
   conj(tx)) AND xcorr(rx0,conj(rx1))
   - Find the correlation peak (which was very pronounced) which shows the
   sample delay between the two signals.  Extract the phase at the peak

Oops, I just realized that I used a constant DSP freq (10 MHz) and I
changed the LO freq in my test.  I will try again with moving the DSP freq
instead.
Rob

Test 1: freq = 2450.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -121.8
  Rx0/Rx1 xcorr peak at index 115 with phase -95.7
Test 2: freq = 2460.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -58.7
  Rx0/Rx1 xcorr peak at index 115 with phase 13.1
Test 3: freq = 2450.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -121.7
  Rx0/Rx1 xcorr peak at index 115 with phase -95.8
Test 4: freq = 2460.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -58.6
  Rx0/Rx1 xcorr peak at index 115 with phase 13.0
Test 5: freq = 2450.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -121.7
  Rx0/Rx1 xcorr peak at index 115 with phase -95.8
Test 6: freq = 2460.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -58.8
  Rx0/Rx1 xcorr peak at index 115 with phase 12.7
Test 7: freq = 2450.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -121.8
  Rx0/Rx1 xcorr peak at index 115 with phase -95.9
Test 8: freq = 2460.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -58.7
  Rx0/Rx1 xcorr peak at index 115 with phase 12.9
Test 9: freq = 2450.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -121.8
  Rx0/Rx1 xcorr peak at index 115 with phase -95.8
Test 10: freq = 2460.0 MHz
  Rx0/Tx0 xcorr peak at index 108 with phase -58.7
  Rx0/Rx1 xcorr peak at index 115 with phase 12.9
>>


On Thu, Mar 19, 2020 at 4:21 PM Lukas Haase  wrote:

> Hi Rob,
>
> Yes, I confirm your conclusion.
>
>
>- I calculate the relative phase by dividing the outputs of both
>receivers. To understand better, note that I have an additional "IF stage"
>in my own signal flow such that I exclude DC offset correction etc. the
>USRP may perform. This is the block diagram of the transmitter part:
>https://snipboard.io/YFgIKs.jpg . I send "exp(1j*1MHz*t) . This shows
>the receiver part: https://snipboard.io/i9jLJg.jpg . I multiply the
>received signal with exp(-1j*1MHz*t) and filter them. Then I divide both
>streams and take the phase part. I take a moving average (for
>flucatuations), add pi and display the number.
>- https://snipboard.io/YFgIKs.jpg https://snipboard.io/YFgIKs.jpg
>https://snipboard.io/YFgIKs.jpg That's so nice, thank you!! My code is
>here: http://paste.ubuntu.com/p/MbCJfPGzYW/ . I'm not sure if you have
>gnuradio(and QT) installed but if yes, simply "python2 switch_on_click.py"
>should do. Let me quickly elaborate how it works:
>   - Class "switch_on_click" implements a normal gnuradio flow with
>   USRP transmitter and receiver.
>   - It also uses a custom module together with buttons and a probe
>   block to call functions upon clicking on a button
>   - The callback functions are defined in class "blk"
>   - The most important is "def button_rtx_handler" on line 106 which
>   is executed when user clicks on button "Switch RTX (together)"
>- Again, thank you for trying this out!! If it works, would you mind
>sharing this code then? I may be able to check then where it breaks on my
>system
>- I use 900 MHz as default center frequency (and "rf_freq"). When
>clicking, I jump between dsp_freq=0 and dsp_freq=500e3. As to my waveform,
>you can infer from my screenshots and code above: I am transmitting and
>receiving a 1MHz waveform (which acts as an additional "IF stage"). The
>received signal is then downconcerted from 1MHz to DC. I use 5 MSsps
>sampling rate.
>
>
> Again, thank you SO much.
>
> Best,
> Lukas
>
>
> *Gesendet:* Donnerstag, 19. März 2020 um 10:43 Uhr
> *Von:* "Rob Kossler" 
> *An:* "Lukas Haase" 
> *Cc:* "USRP-users@lists.ettus.com" 
> *Betreff:* Re: [USRP-users] USRP X310 ignored DSP retuning on TX when
> using a timed command
> Hi Lukas,
> So, the conclusion is that your Rx0-to-Rx1 relative phase is nearly
> 

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-19 Thread Lukas Haase via USRP-users
Hi Rob,

 

Yes, I confirm your conclusion.

 


	I calculate the relative phase by dividing the outputs of both receivers. To understand better, note that I have an additional "IF stage" in my own signal flow such that I exclude DC offset correction etc. the USRP may perform. This is the block diagram of the transmitter part: https://snipboard.io/YFgIKs.jpg . I send "exp(1j*1MHz*t) . This shows the receiver part: https://snipboard.io/i9jLJg.jpg . I multiply the received signal with exp(-1j*1MHz*t) and filter them. Then I divide both streams and take the phase part. I take a moving average (for flucatuations), add pi and display the number.
	https://snipboard.io/YFgIKs.jpg https://snipboard.io/YFgIKs.jpg https://snipboard.io/YFgIKs.jpg That's so nice, thank you!! My code is here: http://paste.ubuntu.com/p/MbCJfPGzYW/ . I'm not sure if you have gnuradio(and QT) installed but if yes, simply "python2 switch_on_click.py" should do. Let me quickly elaborate how it works:
	
		Class "switch_on_click" implements a normal gnuradio flow with USRP transmitter and receiver.
		It also uses a custom module together with buttons and a probe block to call functions upon clicking on a button
		The callback functions are defined in class "blk"
		The most important is "def button_rtx_handler" on line 106 which is executed when user clicks on button "Switch RTX (together)"
	
	
	Again, thank you for trying this out!! If it works, would you mind sharing this code then? I may be able to check then where it breaks on my system
	I use 900 MHz as default center frequency (and "rf_freq"). When clicking, I jump between dsp_freq=0 and dsp_freq=500e3. As to my waveform, you can infer from my screenshots and code above: I am transmitting and receiving a 1MHz waveform (which acts as an additional "IF stage"). The received signal is then downconcerted from 1MHz to DC. I use 5 MSsps sampling rate.



 

Again, thank you SO much.

 

Best,

Lukas

 

 

Gesendet: Donnerstag, 19. März 2020 um 10:43 Uhr
Von: "Rob Kossler" 
An: "Lukas Haase" 
Cc: "USRP-users@lists.ettus.com" 
Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command



Hi Lukas,
So, the conclusion is that your Rx0-to-Rx1 relative phase is nearly constant such that it seems that both Rx0/Rx1 are phase coherent and Tx0/Tx1 are phase coherent.  But, phase from Tx-to-Rx is random.  Please correct me if that is wrong.  

 

I have a few comments:



	How do you measure/calculate the relative phase?
	Can you send me the full Python code to look at?  As I mentioned previously, I am not too good at gnuradio/Python, but I might be able to spot something.
	As to your question, I always use synchronous measurements.  And, I'm confident that my Rx-to-Rx phase is coherent.  But, I haven't really looked at Tx-to-Rx in a while so I will do so later today.  Here are the steps I plan to take:
	
		Connect Tx0 to Rx1.  Note that there is a pretty strong leakage signal from Tx0 to Rx0 so I don't really need to provide a physical connection in order to get a signal on Rx0.  The signal attenuation in this leakage path is approx 40 dB so it is not too much different than the signal level I will receive on Rx1 if I use an external 30 dB attenuator.
		Set Rx and Tx frequency to freq 1
		Measure and note the relative phase for Rx0/Tx0 and Rx1/Tx0 for freq 1
		Set Rx and Tx frequency to freq 2
		Measure and note the relative phase for Rx0/Tx0 and Rx1/Tx0 for freq 2
		Repeat steps 2-5 a few times to ensure that the measurements are repeatable
	
	
	Questions: what should I use for freq 1 and freq 2?  What waveform are you transmitting?  What sample rates for Tx and Rx?


Rob


 



 
 


On Wed, Mar 18, 2020 at 7:47 PM Lukas Haase via USRP-users <usrp-users@lists.ettus.com> wrote:




Hi Rob,

 

I think the issue is really having two usrp_multi devices with timed commands and same timestmap or similar. From your tests below:

 

1.) I can confirm that the relative phase between two RX in your suggested test is always the same! In fact, it is always 4.56 rad, even across restarts and for different frequencies! That somewhat makes sense because the phase offset is now only dependent on the difference between the two channels (fixed) and cable lengths from the splitter (fixed). I verified by removing the timed command on usrp source, the phase offset becomes random after each retune. Of course, this is independent of TX tuning (timed vs. not). For reference, this is the code used:

 


    tune_req_rx = uhd.tune_request()
    tune_req_rx.rf_freq_policy = uhd.tune_request.POLICY_NONE
    tune_req_rx.dsp_freq_policy = uhd.tune_request.POLICY_MANUAL
    tune_req_rx.dsp_freq = -dsp_freq

    tune_req_tx = uhd.tune_request()
    tune_req_tx.rf_freq_policy = uhd.tune_request.POLICY_NONE
    tune_req_tx.dsp_

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-19 Thread Rob Kossler via USRP-users
ng
> the two) and guess what: Also now the relative phase stays constant! (This
> time it actually slightly varies from 3.0 rad to 3.7 rad between two
> different frequencies).
> What does that mean? I think it means that TX must be tuned coherently and
> RX must be tuned coherently, i.e., timed commands generally work for
> multiple TX's and multiple RX's *individually*. Do I get that right?
>
> What doesn't seem to work is RX+TX *together*.
>
> I am very desperately asking if you had coherent TX+RX setup working at
> any point or know somebody who did. It would be so much worth to know if
> this is something that never worked to begin with or if I'm just doing
> something wrong. On the other hand I don't want to believe being the only
> person on the planet having tried TX+RX phase coherent operation :-/
>
> Any other further suggestions on how to continue debugging with the above
> in mind would be helpful too.
>
> In my opinion there are two options left:
> 1.) There is still a nondeterministic delay between the TX and RX timed
> commands (to my understanding, even a constant delay would result in
> coherent phase)
> 2.) While the phase accumulators in RX are set to the same values (and in
> TX as well), they may be set to a different, random value.
>
> However, I don't really know how to test these.
>
> Thanks,
> Lukas
>
>
> *Gesendet:* Freitag, 13. März 2020 um 12:27 Uhr
> *Von:* "Rob Kossler" 
> *An:* "Lukas Haase" 
> *Cc:* "Marcus D Leech" , "
> USRP-users@lists.ettus.com" 
> *Betreff:* Re: [USRP-users] USRP X310 ignored DSP retuning on TX when
> using a timed command
> Ok, great.  I am trying to think of ways to now add the phase
> measurement.  Ideas...
>
>- In order to get consistent phase, you would need to tune Rx and Tx
>DSP at the same time (rather than below where you are only tuning one of
>them).  So, assuming that this will not produce consistent phase results,
>then maybe try the following idea...
>- If you want to check just Rx DSP tuning (with fixed Tx DSP tuning),
>you could try a 2 channel Rx measurement where the Tx is split externally
>with 1:2 splitter in order to drive both Rx0 and Rx1.  Then, measure the
>relative phase Rx0/Rx1 and then tune back and forth between two Rx DSP
>freqs to see if the relative phase on Rx remains constant.  If so, this
>would give you good confidence that Rx DSP tuning is indeed happening
>synchronously
>- Assuming that the Rx IS synchronous in the step above (perhaps a bad
>assumption, but here goes), you could then check TX DSP tuning (with fixed
>Rx DSP tuning) by using two Tx and two Rx channels with Tx0 connected to
>Rx0 and Tx1 connected to Rx1.  At this point we are confident that Rx DSP
>tuning is synchronous so any synchronous misbehavior would imply a Tx sync
>problem.
>
> Sorry I can't think of better ideas.
> Rob
>
> On Fri, Mar 13, 2020 at 12:12 PM Lukas Haase  wrote:
>
>> Hi Rob,
>>
>> 1.) yes, works(*)
>> 2.) yes, works(*)
>>
>> (*): qualitatively. I set the timed command to "get_current_time() +
>> uhd.time_spec(2.0)" and I see the chance 2 seconds after my click on the
>> screen. I cannot (do not know how) check if it actually happens at
>> sample-precicse location.
>>
>> Great, any ideas to simplify the setup would nice. I just don't know how
>> I could continue to debugging the phase.
>>
>> Best,
>> Luke
>>
>>
>> Gesendet: Freitag, 13. März 2020 um 11:08 Uhr
>> Von: "Rob Kossler" 
>> An: "Lukas Haase" 
>> Cc: "Marcus D Leech" , "
>> USRP-users@lists.ettus.com" 
>> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using
>> a timed command
>>
>> Thanks Lukas,
>> I wanted to confirm that you did not have an older version of FPGA
>> firmware because there was a DDC/DUC bug fix[
>> https://github.com/EttusResearch/fpga/commit/0b2364653405612a6d5dfaa0e69b1c6798771e6d]
>> related to phase.  However, the version you provided with uhd_usrp_probe
>> confirms that you have the bug fix included.  So, this is not the problem.
>>
>> From what you said, I assume that you can successfully do the following:
>> 1) with Rx tuning fixed (no re-tuning at all), tune Tx DSP only (do not
>> change TX RF) and you can see the frequency change at the specified command
>> time (i.e., if you specify the command time 1 sec in the future, the change
>> does not occur until 1 sec in the future).
>> 2) opposite of #1: with Tx tuning fixed, tu

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-18 Thread Lukas Haase via USRP-users
Hi Marcus,

> Gesendet: Freitag, 13. März 2020 um 13:29 Uhr
> On 03/13/2020 10:52 AM, Lukas Haase wrote:
> > Hi again Rob,
> >
> > Yes, I confirm:
> >
> > 1.) Finally I get the commands to execute at the same time (TX and RX 
> > individually and both at the same time)
> > 2.) Yes, the phase is random after each retune, even when I retune back to 
> > the same frequency
> > 3.) (2) is only true if it includes *DSP* retuning. With naalog retuning 
> > (+integer-N retuning) I get phase coherence, as expected.
> >
> > I actually expected the PLL retuning much more challenging than the DSP 
> > retuning but for some reason it seems to be the opposite...
> It depends on whether the phase-accumulator in the DSP is reset to zero, 
> or whether just the increment register is updated with the
> new phase increment.   There are good arguments for both approaches.

As far as I learned the phase accumulator is reset to zero in the x310. Is this 
not the case?

Lukas



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Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-18 Thread Lukas Haase via USRP-users
Hi Rob,

 

I think the issue is really having two usrp_multi devices with timed commands and same timestmap or similar. From your tests below:

 

1.) I can confirm that the relative phase between two RX in your suggested test is always the same! In fact, it is always 4.56 rad, even across restarts and for different frequencies! That somewhat makes sense because the phase offset is now only dependent on the difference between the two channels (fixed) and cable lengths from the splitter (fixed). I verified by removing the timed command on usrp source, the phase offset becomes random after each retune. Of course, this is independent of TX tuning (timed vs. not). For reference, this is the code used:

 


    tune_req_rx = uhd.tune_request()
    tune_req_rx.rf_freq_policy = uhd.tune_request.POLICY_NONE
    tune_req_rx.dsp_freq_policy = uhd.tune_request.POLICY_MANUAL
    tune_req_rx.dsp_freq = -dsp_freq

    tune_req_tx = uhd.tune_request()
    tune_req_tx.rf_freq_policy = uhd.tune_request.POLICY_NONE
    tune_req_tx.dsp_freq_policy = uhd.tune_request.POLICY_MANUAL
    tune_req_tx.dsp_freq = dsp_freq

 

    now = usrp_sink.get_time_now()
    when = now + uhd.time_spec(1.0)
 

    usrp_sink.set_command_time(when)
    usrp_source.set_command_time(when)

    res1 = usrp_sink.set_center_freq(tune_req_tx)  # TX
    res2 = usrp_source.set_center_freq(tune_req_rx, 0)  #RX1
    res3 = usrp_source.set_center_freq(tune_req_rx, 1)  #RX2

    usrp_sink.clear_command_time()
    usrp_source.clear_command_time()


 

2.) I also tried your second suggestion. Before reading on, you wanna guess what the outcome is?

I connected "TX/RX" to "RX2" on UBX #1 (TX1 --> RX1) and "TX/RX" to "RX2" on UBX #2 (TX2 --> RX2). In absence of a second 30dB attenuator I used two antennas closely spaced together. For reference, my code looks now like:

 


    tune_req_rx = uhd.tune_request()
    tune_req_rx.rf_freq_policy = uhd.tune_request.POLICY_NONE
    tune_req_rx.dsp_freq_policy = uhd.tune_request.POLICY_MANUAL
    tune_req_rx.dsp_freq = -dsp_freq

    tune_req_tx = uhd.tune_request()
    tune_req_tx.rf_freq_policy = uhd.tune_request.POLICY_NONE
    tune_req_tx.dsp_freq_policy = uhd.tune_request.POLICY_MANUAL
    tune_req_tx.dsp_freq = dsp_freq

 

    now = usrp_sink.get_time_now()
    when = now + uhd.time_spec(1.0)
 

    usrp_sink.set_command_time(when)
    usrp_source.set_command_time(when)

    res1 = usrp_sink.set_center_freq(tune_req_tx, 0)     # TX1
    res2 = usrp_sink.set_center_freq(tune_req_tx, 1) # TX2
    res3 = usrp_source.set_center_freq(tune_req_rx, 0) # RX1
    res4 = usrp_source.set_center_freq(tune_req_rx, 1) # RX2

    usrp_sink.clear_command_time()
    usrp_source.clear_command_time()


 

I again look at the relative phase of RX1 and RX2 (obtained by dividing the two) and guess what: Also now the relative phase stays constant! (This time it actually slightly varies from 3.0 rad to 3.7 rad between two different frequencies).

What does that mean? I think it means that TX must be tuned coherently and RX must be tuned coherently, i.e., timed commands generally work for multiple TX's and multiple RX's individually. Do I get that right?

 

What doesn't seem to work is RX+TX together.

 

I am very desperately asking if you had coherent TX+RX setup working at any point or know somebody who did. It would be so much worth to know if this is something that never worked to begin with or if I'm just doing something wrong. On the other hand I don't want to believe being the only person on the planet having tried TX+RX phase coherent operation :-/

 
Any other further suggestions on how to continue debugging with the above in mind would be helpful too.

 

In my opinion there are two options left:

1.) There is still a nondeterministic delay between the TX and RX timed commands (to my understanding, even a constant delay would result in coherent phase)

2.) While the phase accumulators in RX are set to the same values (and in TX as well), they may be set to a different, random value.

 

However, I don't really know how to test these.

 

Thanks,

Lukas

 

 


Gesendet: Freitag, 13. März 2020 um 12:27 Uhr
Von: "Rob Kossler" 
An: "Lukas Haase" 
Cc: "Marcus D Leech" , "USRP-users@lists.ettus.com" 
Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command



Ok, great.  I am trying to think of ways to now add the phase measurement.  Ideas...



	In order to get consistent phase, you would need to tune Rx and Tx DSP at the same time (rather than below where you are only tuning one of them).  So, assuming that this will not produce consistent phase results, then maybe try the following idea...
	If you want to check just Rx DSP t

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-13 Thread Marcus D. Leech via USRP-users

On 03/13/2020 10:52 AM, Lukas Haase wrote:

Hi again Rob,

Yes, I confirm:

1.) Finally I get the commands to execute at the same time (TX and RX 
individually and both at the same time)
2.) Yes, the phase is random after each retune, even when I retune back to the 
same frequency
3.) (2) is only true if it includes *DSP* retuning. With naalog retuning 
(+integer-N retuning) I get phase coherence, as expected.

I actually expected the PLL retuning much more challenging than the DSP 
retuning but for some reason it seems to be the opposite...
It depends on whether the phase-accumulator in the DSP is reset to zero, 
or whether just the increment register is updated with the

  new phase increment.   There are good arguments for both approaches.




Thanks,
Lukas
  
  
  


Gesendet: Freitag, 13. März 2020 um 10:07 Uhr
Von: "Rob Kossler" 
An: "Lukas Haase" 
Cc: "Marcus D Leech" , "USRP-users@lists.ettus.com" 

Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
timed command

Also, is it true that now you can successfully tune both RF and DSP at the 
desired command time (but the remaining problem is that the Rx phase is not 
consistent when after you tune to a new frequency and then tune back to the 
original)? If this is not correct, please explain again.
Rob

On Fri, Mar 13, 2020 at 9:53 AM Rob Kossler 
mailto:rkoss...@nd.edu]> wrote:
Lukas,
Can you confirm the exact git hash for both UHD and the FPGA image you are 
using? Perhaps the easiest way is to run uhd_usrp_probe.
Rob

On Fri, Mar 13, 2020 at 1:00 AM Lukas Haase 
mailto:lukasha...@gmx.at]> wrote:Dear Marcus, Dear Rob,

Thank you very much for these tips with "Unknown PPS", stream 2 streams and the 
explanation of set_start_time. That makes sense.

Since then I spent hours and hours every day on TX+RX but STILL no synchronized 
phase for dspfreq!
Timed commands seem to work.
Also, in general, synchronization.
With this code, I get my long desired cohrent phase between TX+RX but ONLY if I 
do not touch dsp tuning (and only use the PLL in integer-N mode):

 tune_req_rx = uhd.tune_request()
 tune_req_rx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
 tune_req_rx.dsp_freq_policy = uhd.tune_request.POLICY_NONE # IMPORTANT!
 tune_req_rx.rf_freq = rf_freq
 tune_req_tx.dsp_freq = -dsp_freq
 tune_req_rx.args=uhd.device_addr(','.join(["mode_n=integer", 
"int_n_step=1000e3",]))

 tune_req_tx = uhd.tune_request()
 tune_req_tx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
 tune_req_tx.dsp_freq_policy = uhd.tune_request.POLICY_NONE # IMPORTANT!
 tune_req_tx.rf_freq = rf_freq
 tune_req_tx.dsp_freq = dsp_freq
 tune_req_tx.args=uhd.device_addr(','.join(["mode_n=integer", 
"int_n_step=1000e3",]))

 now = usrp_sink.get_time_now()
 when = now + uhd.time_spec(1.0)
 print("Clicked to switch R-T-X frf=" + str(rf_freq) + ", fdsp=" + str(dsp_freq) + " at " + 
str(now.get_full_secs()) + ":" + str(now.get_frac_secs()) + " for " + str(when.get_full_secs()) + ":" + 
str(when.get_frac_secs()))

 usrp_sink.set_command_time(when)
 usrp_source.set_command_time(when)
 res2 = usrp_sink.set_center_freq(tune_req_tx)   # "TX/RX" of first 
UBX160 is transmitter
 res1 = usrp_source.set_center_freq(tune_req_rx, 1)  # "RX2" of second 
UBX160 is receiver
 usrp_sink.clear_command_time()
 usrp_source.clear_command_time()

With phase coherence I mean if I read out the received phase and I switch 
between f1 and f2, I always get the same phase for f1 and f2, respectively.

But if I set dsp_freq_policy to MANUAL (or I add an LO offset which also 
required dsp retuning) I just don't get any coherent phase.

I used the tricks you mentioned:

- I use unknown PPS in both which makes USRP time start at zero (tested)
- Both "USRP Source" and "USRP Sink" have 2 channels (and one of each connects 
to Null Source/Sink). This should ensure that stream start time is set! (tested)
- Even if not, I also used explicitely
tb.uhd_usrp_source_0.set_start_time(uhd.time_spec(10))
tb.uhd_usrp_sink_0.set_start_time(uhd.time_spec(10))
   at the beginning of my flow graph. I see no signal until 10s, as expected
- I experimented with "tx_time" and stream tags but for some reason many timed 
I get flooded with L's


Can it be that there is another bug lurking somewhere deep in the USRP firmware?

Thanks,
Lukas



Gesendet: Mittwoch, 04. März 2020 um 19:27 Uhr
Von: "Marcus D Leech" mailto:patchvonbr...@gmail.com]>
An: "Rob Kossler" mailto:rkoss...@nd.edu]>
Cc: "Lukas Haase" mailto:lukasha...@gmx.at]>, 
"USRP-users@lists.ettus.com[mailto:USR

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-13 Thread Rob Kossler via USRP-users
Ok, great.  I am trying to think of ways to now add the phase measurement.
Ideas...

   - In order to get consistent phase, you would need to tune Rx and Tx DSP
   at the same time (rather than below where you are only tuning one of
   them).  So, assuming that this will not produce consistent phase results,
   then maybe try the following idea...
   - If you want to check just Rx DSP tuning (with fixed Tx DSP tuning),
   you could try a 2 channel Rx measurement where the Tx is split externally
   with 1:2 splitter in order to drive both Rx0 and Rx1.  Then, measure the
   relative phase Rx0/Rx1 and then tune back and forth between two Rx DSP
   freqs to see if the relative phase on Rx remains constant.  If so, this
   would give you good confidence that Rx DSP tuning is indeed happening
   synchronously
   - Assuming that the Rx IS synchronous in the step above (perhaps a bad
   assumption, but here goes), you could then check TX DSP tuning (with fixed
   Rx DSP tuning) by using two Tx and two Rx channels with Tx0 connected to
   Rx0 and Tx1 connected to Rx1.  At this point we are confident that Rx DSP
   tuning is synchronous so any synchronous misbehavior would imply a Tx sync
   problem.

Sorry I can't think of better ideas.
Rob

On Fri, Mar 13, 2020 at 12:12 PM Lukas Haase  wrote:

> Hi Rob,
>
> 1.) yes, works(*)
> 2.) yes, works(*)
>
> (*): qualitatively. I set the timed command to "get_current_time() +
> uhd.time_spec(2.0)" and I see the chance 2 seconds after my click on the
> screen. I cannot (do not know how) check if it actually happens at
> sample-precicse location.
>
> Great, any ideas to simplify the setup would nice. I just don't know how I
> could continue to debugging the phase.
>
> Best,
> Luke
>
>
> Gesendet: Freitag, 13. März 2020 um 11:08 Uhr
> Von: "Rob Kossler" 
> An: "Lukas Haase" 
> Cc: "Marcus D Leech" , "
> USRP-users@lists.ettus.com" 
> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using
> a timed command
>
> Thanks Lukas,
> I wanted to confirm that you did not have an older version of FPGA
> firmware because there was a DDC/DUC bug fix[
> https://github.com/EttusResearch/fpga/commit/0b2364653405612a6d5dfaa0e69b1c6798771e6d]
> related to phase.  However, the version you provided with uhd_usrp_probe
> confirms that you have the bug fix included.  So, this is not the problem.
>
> From what you said, I assume that you can successfully do the following:
> 1) with Rx tuning fixed (no re-tuning at all), tune Tx DSP only (do not
> change TX RF) and you can see the frequency change at the specified command
> time (i.e., if you specify the command time 1 sec in the future, the change
> does not occur until 1 sec in the future).
> 2) opposite of #1: with Tx tuning fixed, tune Rx DSP only and you can see
> the frequency change at the specified command time.
>
> I am trying to simplify the issue by removing RF tuning completely and by
> tuning only 1 of Rx/Tx at a time.  Perhaps this will help lead to the
> answer.
> Rob
>
>
>
> On Fri, Mar 13, 2020 at 10:53 AM Lukas Haase  lukasha...@gmx.at]> wrote:Hi again Rob,
>
> Yes, I confirm:
>
> 1.) Finally I get the commands to execute at the same time (TX and RX
> individually and both at the same time)
> 2.) Yes, the phase is random after each retune, even when I retune back to
> the same frequency
> 3.) (2) is only true if it includes *DSP* retuning. With naalog retuning
> (+integer-N retuning) I get phase coherence, as expected.
>
> I actually expected the PLL retuning much more challenging than the DSP
> retuning but for some reason it seems to be the opposite...
>
> Thanks,
> Lukas
>
>
>
>
___
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com


Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-13 Thread Lukas Haase via USRP-users
Hi Rob,

1.) yes, works(*)
2.) yes, works(*)

(*): qualitatively. I set the timed command to "get_current_time() + 
uhd.time_spec(2.0)" and I see the chance 2 seconds after my click on the 
screen. I cannot (do not know how) check if it actually happens at 
sample-precicse location.

Great, any ideas to simplify the setup would nice. I just don't know how I 
could continue to debugging the phase.

Best,
Luke


Gesendet: Freitag, 13. März 2020 um 11:08 Uhr
Von: "Rob Kossler" 
An: "Lukas Haase" 
Cc: "Marcus D Leech" , "USRP-users@lists.ettus.com" 

Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
timed command

Thanks Lukas,
I wanted to confirm that you did not have an older version of FPGA firmware 
because there was a DDC/DUC bug 
fix[https://github.com/EttusResearch/fpga/commit/0b2364653405612a6d5dfaa0e69b1c6798771e6d]
 related to phase.  However, the version you provided with uhd_usrp_probe 
confirms that you have the bug fix included.  So, this is not the problem. 
 
From what you said, I assume that you can successfully do the following:
1) with Rx tuning fixed (no re-tuning at all), tune Tx DSP only (do not change 
TX RF) and you can see the frequency change at the specified command time 
(i.e., if you specify the command time 1 sec in the future, the change does not 
occur until 1 sec in the future).
2) opposite of #1: with Tx tuning fixed, tune Rx DSP only and you can see the 
frequency change at the specified command time.
 
I am trying to simplify the issue by removing RF tuning completely and by 
tuning only 1 of Rx/Tx at a time.  Perhaps this will help lead to the answer.
Rob
 
  

On Fri, Mar 13, 2020 at 10:53 AM Lukas Haase 
mailto:lukasha...@gmx.at]> wrote:Hi again Rob,

Yes, I confirm:

1.) Finally I get the commands to execute at the same time (TX and RX 
individually and both at the same time)
2.) Yes, the phase is random after each retune, even when I retune back to the 
same frequency
3.) (2) is only true if it includes *DSP* retuning. With naalog retuning 
(+integer-N retuning) I get phase coherence, as expected.

I actually expected the PLL retuning much more challenging than the DSP 
retuning but for some reason it seems to be the opposite...

Thanks,
Lukas
 
 
 

Gesendet: Freitag, 13. März 2020 um 10:07 Uhr
Von: "Rob Kossler" mailto:rkoss...@nd.edu]>
An: "Lukas Haase" mailto:lukasha...@gmx.at]>
Cc: "Marcus D Leech" mailto:patchvonbr...@gmail.com]>, 
"USRP-users@lists.ettus.com[mailto:USRP-users@lists.ettus.com]"; 
mailto:usrp-users@lists.ettus.com]>
Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
timed command

Also, is it true that now you can successfully tune both RF and DSP at the 
desired command time (but the remaining problem is that the Rx phase is not 
consistent when after you tune to a new frequency and then tune back to the 
original)? If this is not correct, please explain again.
Rob 

On Fri, Mar 13, 2020 at 9:53 AM Rob Kossler 
mailto:rkoss...@nd.edu][mailto:rkoss...@nd.edu[mailto:rkoss...@nd.edu]]>
 wrote:
Lukas,
Can you confirm the exact git hash for both UHD and the FPGA image you are 
using? Perhaps the easiest way is to run uhd_usrp_probe.
Rob 

On Fri, Mar 13, 2020 at 1:00 AM Lukas Haase 
mailto:lukasha...@gmx.at][mailto:lukasha...@gmx.at[mailto:lukasha...@gmx.at]]>
 wrote:Dear Marcus, Dear Rob,

Thank you very much for these tips with "Unknown PPS", stream 2 streams and the 
explanation of set_start_time. That makes sense.

Since then I spent hours and hours every day on TX+RX but STILL no synchronized 
phase for dspfreq!
Timed commands seem to work.
Also, in general, synchronization.
With this code, I get my long desired cohrent phase between TX+RX but ONLY if I 
do not touch dsp tuning (and only use the PLL in integer-N mode):

        tune_req_rx = uhd.tune_request()
        tune_req_rx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
        tune_req_rx.dsp_freq_policy = uhd.tune_request.POLICY_NONE # IMPORTANT!
        tune_req_rx.rf_freq = rf_freq
        tune_req_tx.dsp_freq = -dsp_freq
        tune_req_rx.args=uhd.device_addr(','.join(["mode_n=integer", 
"int_n_step=1000e3",]))

        tune_req_tx = uhd.tune_request()
        tune_req_tx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
        tune_req_tx.dsp_freq_policy = uhd.tune_request.POLICY_NONE # IMPORTANT!
        tune_req_tx.rf_freq = rf_freq
        tune_req_tx.dsp_freq = dsp_freq
        tune_req_tx.args=uhd.device_addr(','.join(["mode_n=integer", 
"int_n_step=1000e3",]))

        now = usrp_sink.get_time_now()
        when = now + uhd.time_spec(1.0)
        print("Clicked to switch R-T-X frf=" + str(rf_freq) + ", fdsp=" + 
str(dsp_freq) + " at " + str(now.get_full_secs()) + ":" + 
str(now.get_frac_secs()) + &qu

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-13 Thread Rob Kossler via USRP-users
Thanks Lukas,
I wanted to confirm that you did not have an older version of FPGA firmware
because there was a DDC/DUC bug fix
<https://github.com/EttusResearch/fpga/commit/0b2364653405612a6d5dfaa0e69b1c6798771e6d>
related to phase.  However, the version you provided with uhd_usrp_probe
confirms that you have the bug fix included.  So, this is not the problem.

>From what you said, I assume that you can successfully do the following:
1) with Rx tuning fixed (no re-tuning at all), tune Tx DSP only (do not
change TX RF) and you can see the frequency change at the specified command
time (i.e., if you specify the command time 1 sec in the future, the change
does not occur until 1 sec in the future).
2) opposite of #1: with Tx tuning fixed, tune Rx DSP only and you can see
the frequency change at the specified command time.

I am trying to simplify the issue by removing RF tuning completely and by
tuning only 1 of Rx/Tx at a time.  Perhaps this will help lead to the
answer.
Rob



On Fri, Mar 13, 2020 at 10:53 AM Lukas Haase  wrote:

> Hi again Rob,
>
> Yes, I confirm:
>
> 1.) Finally I get the commands to execute at the same time (TX and RX
> individually and both at the same time)
> 2.) Yes, the phase is random after each retune, even when I retune back to
> the same frequency
> 3.) (2) is only true if it includes *DSP* retuning. With naalog retuning
> (+integer-N retuning) I get phase coherence, as expected.
>
> I actually expected the PLL retuning much more challenging than the DSP
> retuning but for some reason it seems to be the opposite...
>
> Thanks,
> Lukas
>
>
>
>
> Gesendet: Freitag, 13. März 2020 um 10:07 Uhr
> Von: "Rob Kossler" 
> An: "Lukas Haase" 
> Cc: "Marcus D Leech" , "
> USRP-users@lists.ettus.com" 
> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using
> a timed command
>
> Also, is it true that now you can successfully tune both RF and DSP at the
> desired command time (but the remaining problem is that the Rx phase is not
> consistent when after you tune to a new frequency and then tune back to the
> original)? If this is not correct, please explain again.
> Rob
>
> On Fri, Mar 13, 2020 at 9:53 AM Rob Kossler  rkoss...@nd.edu]> wrote:
> Lukas,
> Can you confirm the exact git hash for both UHD and the FPGA image you are
> using? Perhaps the easiest way is to run uhd_usrp_probe.
> Rob
>
> On Fri, Mar 13, 2020 at 1:00 AM Lukas Haase  lukasha...@gmx.at]> wrote:Dear Marcus, Dear Rob,
>
> Thank you very much for these tips with "Unknown PPS", stream 2 streams
> and the explanation of set_start_time. That makes sense.
>
> Since then I spent hours and hours every day on TX+RX but STILL no
> synchronized phase for dspfreq!
> Timed commands seem to work.
> Also, in general, synchronization.
> With this code, I get my long desired cohrent phase between TX+RX but ONLY
> if I do not touch dsp tuning (and only use the PLL in integer-N mode):
>
> tune_req_rx = uhd.tune_request()
> tune_req_rx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
> tune_req_rx.dsp_freq_policy = uhd.tune_request.POLICY_NONE #
> IMPORTANT!
> tune_req_rx.rf_freq = rf_freq
> tune_req_tx.dsp_freq = -dsp_freq
> tune_req_rx.args=uhd.device_addr(','.join(["mode_n=integer",
> "int_n_step=1000e3",]))
>
> tune_req_tx = uhd.tune_request()
> tune_req_tx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
> tune_req_tx.dsp_freq_policy = uhd.tune_request.POLICY_NONE #
> IMPORTANT!
> tune_req_tx.rf_freq = rf_freq
> tune_req_tx.dsp_freq = dsp_freq
> tune_req_tx.args=uhd.device_addr(','.join(["mode_n=integer",
> "int_n_step=1000e3",]))
>
> now = usrp_sink.get_time_now()
> when = now + uhd.time_spec(1.0)
> print("Clicked to switch R-T-X frf=" + str(rf_freq) + ", fdsp=" +
> str(dsp_freq) + " at " + str(now.get_full_secs()) + ":" +
> str(now.get_frac_secs()) + " for " + str(when.get_full_secs()) + ":" +
> str(when.get_frac_secs()))
>
> usrp_sink.set_command_time(when)
> usrp_source.set_command_time(when)
> res2 = usrp_sink.set_center_freq(tune_req_tx)   # "TX/RX" of
> first UBX160 is transmitter
> res1 = usrp_source.set_center_freq(tune_req_rx, 1)  # "RX2" of
> second UBX160 is receiver
> usrp_sink.clear_command_time()
> usrp_source.clear_command_time()
>
> With phase coherence I mean if I read out the received phase and I switch
> between f1 and f2, I always get the same phase for f1 and f2, resp

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-13 Thread Lukas Haase via USRP-users
Hi again Rob,

Yes, I confirm:

1.) Finally I get the commands to execute at the same time (TX and RX 
individually and both at the same time)
2.) Yes, the phase is random after each retune, even when I retune back to the 
same frequency
3.) (2) is only true if it includes *DSP* retuning. With naalog retuning 
(+integer-N retuning) I get phase coherence, as expected.

I actually expected the PLL retuning much more challenging than the DSP 
retuning but for some reason it seems to be the opposite...

Thanks,
Lukas
 
 
 

Gesendet: Freitag, 13. März 2020 um 10:07 Uhr
Von: "Rob Kossler" 
An: "Lukas Haase" 
Cc: "Marcus D Leech" , "USRP-users@lists.ettus.com" 

Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
timed command

Also, is it true that now you can successfully tune both RF and DSP at the 
desired command time (but the remaining problem is that the Rx phase is not 
consistent when after you tune to a new frequency and then tune back to the 
original)? If this is not correct, please explain again.
Rob 

On Fri, Mar 13, 2020 at 9:53 AM Rob Kossler 
mailto:rkoss...@nd.edu]> wrote:
Lukas,
Can you confirm the exact git hash for both UHD and the FPGA image you are 
using? Perhaps the easiest way is to run uhd_usrp_probe.
Rob 

On Fri, Mar 13, 2020 at 1:00 AM Lukas Haase 
mailto:lukasha...@gmx.at]> wrote:Dear Marcus, Dear Rob,

Thank you very much for these tips with "Unknown PPS", stream 2 streams and the 
explanation of set_start_time. That makes sense.

Since then I spent hours and hours every day on TX+RX but STILL no synchronized 
phase for dspfreq!
Timed commands seem to work.
Also, in general, synchronization.
With this code, I get my long desired cohrent phase between TX+RX but ONLY if I 
do not touch dsp tuning (and only use the PLL in integer-N mode):

        tune_req_rx = uhd.tune_request()
        tune_req_rx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
        tune_req_rx.dsp_freq_policy = uhd.tune_request.POLICY_NONE # IMPORTANT!
        tune_req_rx.rf_freq = rf_freq
        tune_req_tx.dsp_freq = -dsp_freq
        tune_req_rx.args=uhd.device_addr(','.join(["mode_n=integer", 
"int_n_step=1000e3",]))

        tune_req_tx = uhd.tune_request()
        tune_req_tx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
        tune_req_tx.dsp_freq_policy = uhd.tune_request.POLICY_NONE # IMPORTANT!
        tune_req_tx.rf_freq = rf_freq
        tune_req_tx.dsp_freq = dsp_freq
        tune_req_tx.args=uhd.device_addr(','.join(["mode_n=integer", 
"int_n_step=1000e3",]))

        now = usrp_sink.get_time_now()
        when = now + uhd.time_spec(1.0)
        print("Clicked to switch R-T-X frf=" + str(rf_freq) + ", fdsp=" + 
str(dsp_freq) + " at " + str(now.get_full_secs()) + ":" + 
str(now.get_frac_secs()) + " for " + str(when.get_full_secs()) + ":" + 
str(when.get_frac_secs()))

        usrp_sink.set_command_time(when)
        usrp_source.set_command_time(when)
        res2 = usrp_sink.set_center_freq(tune_req_tx)       # "TX/RX" of first 
UBX160 is transmitter
        res1 = usrp_source.set_center_freq(tune_req_rx, 1)  # "RX2" of second 
UBX160 is receiver
        usrp_sink.clear_command_time()
        usrp_source.clear_command_time()

With phase coherence I mean if I read out the received phase and I switch 
between f1 and f2, I always get the same phase for f1 and f2, respectively.

But if I set dsp_freq_policy to MANUAL (or I add an LO offset which also 
required dsp retuning) I just don't get any coherent phase.

I used the tricks you mentioned:

- I use unknown PPS in both which makes USRP time start at zero (tested)
- Both "USRP Source" and "USRP Sink" have 2 channels (and one of each connects 
to Null Source/Sink). This should ensure that stream start time is set! (tested)
- Even if not, I also used explicitely
   tb.uhd_usrp_source_0.set_start_time(uhd.time_spec(10))
   tb.uhd_usrp_sink_0.set_start_time(uhd.time_spec(10))
  at the beginning of my flow graph. I see no signal until 10s, as expected
- I experimented with "tx_time" and stream tags but for some reason many timed 
I get flooded with L's


Can it be that there is another bug lurking somewhere deep in the USRP firmware?

Thanks,
Lukas



Gesendet: Mittwoch, 04. März 2020 um 19:27 Uhr
Von: "Marcus D Leech" mailto:patchvonbr...@gmail.com]>
An: "Rob Kossler" mailto:rkoss...@nd.edu]>
Cc: "Lukas Haase" mailto:lukasha...@gmx.at]>, 
"USRP-users@lists.ettus.com[mailto:USRP-users@lists.ettus.com]"; 
mailto:usrp-users@lists.ettus.com]>
Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
timed command

When you select one of the PPS synch options in a GRC USRP block it will set 
the time to zero. 
 
Easy enough to

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-13 Thread Lukas Haase via USRP-users
|   |   | _
|   |   |/
|   |   |   |   TX Frontend: 0
|   |   |   |   Name: UBX TX
|   |   |   |   Antennas: TX/RX, CAL
|   |   |   |   Sensors: lo_locked
|   |   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
|   |   |   |   Bandwidth range: 16000.0 to 16000.0 step 0.0 Hz
|   |   |   |   Connection Type: QI
|   |   |   |   Uses LO offset: No
|   |   | _
|   |   |/
|   |   |   |   TX Codec: B
|   |   |   |   Name: ad9146
|   |   |   |   Gain Elements: None
|   | _
|   |/
|   |   |   RFNoC blocks on this device:
|   |   |
|   |   |   * DmaFIFO_0
|   |   |   * Radio_0
|   |   |   * Radio_1
|   |   |   * DDC_0
|   |   |   * DDC_1
|   |   |   * DUC_0
|   |   |   * DUC_1


Thanks!
Lukas
 
 

Gesendet: Freitag, 13. März 2020 um 09:53 Uhr
Von: "Rob Kossler" 
An: "Lukas Haase" 
Cc: "Marcus D Leech" , "USRP-users@lists.ettus.com" 

Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
timed command

Lukas,
Can you confirm the exact git hash for both UHD and the FPGA image you are 
using? Perhaps the easiest way is to run uhd_usrp_probe.
Rob 

On Fri, Mar 13, 2020 at 1:00 AM Lukas Haase 
mailto:lukasha...@gmx.at]> wrote:Dear Marcus, Dear Rob,

Thank you very much for these tips with "Unknown PPS", stream 2 streams and the 
explanation of set_start_time. That makes sense.

Since then I spent hours and hours every day on TX+RX but STILL no synchronized 
phase for dspfreq!
Timed commands seem to work.
Also, in general, synchronization.
With this code, I get my long desired cohrent phase between TX+RX but ONLY if I 
do not touch dsp tuning (and only use the PLL in integer-N mode):

        tune_req_rx = uhd.tune_request()
        tune_req_rx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
        tune_req_rx.dsp_freq_policy = uhd.tune_request.POLICY_NONE # IMPORTANT!
        tune_req_rx.rf_freq = rf_freq
        tune_req_tx.dsp_freq = -dsp_freq
        tune_req_rx.args=uhd.device_addr(','.join(["mode_n=integer", 
"int_n_step=1000e3",]))

        tune_req_tx = uhd.tune_request()
        tune_req_tx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
        tune_req_tx.dsp_freq_policy = uhd.tune_request.POLICY_NONE # IMPORTANT!
        tune_req_tx.rf_freq = rf_freq
        tune_req_tx.dsp_freq = dsp_freq
        tune_req_tx.args=uhd.device_addr(','.join(["mode_n=integer", 
"int_n_step=1000e3",]))

        now = usrp_sink.get_time_now()
        when = now + uhd.time_spec(1.0)
        print("Clicked to switch R-T-X frf=" + str(rf_freq) + ", fdsp=" + 
str(dsp_freq) + " at " + str(now.get_full_secs()) + ":" + 
str(now.get_frac_secs()) + " for " + str(when.get_full_secs()) + ":" + 
str(when.get_frac_secs()))

        usrp_sink.set_command_time(when)
        usrp_source.set_command_time(when)
        res2 = usrp_sink.set_center_freq(tune_req_tx)       # "TX/RX" of first 
UBX160 is transmitter
        res1 = usrp_source.set_center_freq(tune_req_rx, 1)  # "RX2" of second 
UBX160 is receiver
        usrp_sink.clear_command_time()
        usrp_source.clear_command_time()

With phase coherence I mean if I read out the received phase and I switch 
between f1 and f2, I always get the same phase for f1 and f2, respectively.

But if I set dsp_freq_policy to MANUAL (or I add an LO offset which also 
required dsp retuning) I just don't get any coherent phase.

I used the tricks you mentioned:

- I use unknown PPS in both which makes USRP time start at zero (tested)
- Both "USRP Source" and "USRP Sink" have 2 channels (and one of each connects 
to Null Source/Sink). This should ensure that stream start time is set! (tested)
- Even if not, I also used explicitely
   tb.uhd_usrp_source_0.set_start_time(uhd.time_spec(10))
   tb.uhd_usrp_sink_0.set_start_time(uhd.time_spec(10))
  at the beginning of my flow graph. I see no signal until 10s, as expected
- I experimented with "tx_time" and stream tags but for some reason many timed 
I get flooded with L's


Can it be that there is another bug lurking somewhere deep in the USRP firmware?

Thanks,
Lukas



Gesendet: Mittwoch, 04. März 2020 um 19:27 Uhr
Von: "Marcus D Leech" mailto:patchvonbr...@gmail.com]>
An: "Rob Kossler" mailto:rkoss...@nd.edu]>
Cc: "Lukas Haase" mailto:lukasha...@gmx.at]>, 
"USRP-users@lists.ettus.com[mailto:USRP-users@lists.ettus.com]"; 
mailto:usrp-users@lists.ettus.com]>
Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
timed command

When you select one of the PPS synch options in a GRC USRP block it will set 
the time to zero. 
 
Easy e

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-13 Thread Rob Kossler via USRP-users
Also, is it true that now you can successfully tune both RF and DSP at the
desired command time (but the remaining problem is that the Rx phase is not
consistent when after you tune to a new frequency and then tune back to the
original)? If this is not correct, please explain again.
Rob

On Fri, Mar 13, 2020 at 9:53 AM Rob Kossler  wrote:

> Lukas,
> Can you confirm the exact git hash for both UHD and the FPGA image you are
> using? Perhaps the easiest way is to run uhd_usrp_probe.
> Rob
>
> On Fri, Mar 13, 2020 at 1:00 AM Lukas Haase  wrote:
>
>> Dear Marcus, Dear Rob,
>>
>> Thank you very much for these tips with "Unknown PPS", stream 2 streams
>> and the explanation of set_start_time. That makes sense.
>>
>> Since then I spent hours and hours every day on TX+RX but STILL no
>> synchronized phase for dspfreq!
>> Timed commands seem to work.
>> Also, in general, synchronization.
>> With this code, I get my long desired cohrent phase between TX+RX but
>> ONLY if I do not touch dsp tuning (and only use the PLL in integer-N mode):
>>
>> tune_req_rx = uhd.tune_request()
>> tune_req_rx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
>> tune_req_rx.dsp_freq_policy = uhd.tune_request.POLICY_NONE #
>> IMPORTANT!
>> tune_req_rx.rf_freq = rf_freq
>> tune_req_tx.dsp_freq = -dsp_freq
>> tune_req_rx.args=uhd.device_addr(','.join(["mode_n=integer",
>> "int_n_step=1000e3",]))
>>
>> tune_req_tx = uhd.tune_request()
>> tune_req_tx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
>> tune_req_tx.dsp_freq_policy = uhd.tune_request.POLICY_NONE #
>> IMPORTANT!
>> tune_req_tx.rf_freq = rf_freq
>> tune_req_tx.dsp_freq = dsp_freq
>> tune_req_tx.args=uhd.device_addr(','.join(["mode_n=integer",
>> "int_n_step=1000e3",]))
>>
>> now = usrp_sink.get_time_now()
>> when = now + uhd.time_spec(1.0)
>> print("Clicked to switch R-T-X frf=" + str(rf_freq) + ", fdsp=" +
>> str(dsp_freq) + " at " + str(now.get_full_secs()) + ":" +
>> str(now.get_frac_secs()) + " for " + str(when.get_full_secs()) + ":" +
>> str(when.get_frac_secs()))
>>
>> usrp_sink.set_command_time(when)
>> usrp_source.set_command_time(when)
>> res2 = usrp_sink.set_center_freq(tune_req_tx)   # "TX/RX" of
>> first UBX160 is transmitter
>> res1 = usrp_source.set_center_freq(tune_req_rx, 1)  # "RX2" of
>> second UBX160 is receiver
>> usrp_sink.clear_command_time()
>> usrp_source.clear_command_time()
>>
>> With phase coherence I mean if I read out the received phase and I switch
>> between f1 and f2, I always get the same phase for f1 and f2, respectively.
>>
>> But if I set dsp_freq_policy to MANUAL (or I add an LO offset which also
>> required dsp retuning) I just don't get any coherent phase.
>>
>> I used the tricks you mentioned:
>>
>> - I use unknown PPS in both which makes USRP time start at zero (tested)
>> - Both "USRP Source" and "USRP Sink" have 2 channels (and one of each
>> connects to Null Source/Sink). This should ensure that stream start time is
>> set! (tested)
>> - Even if not, I also used explicitely
>>tb.uhd_usrp_source_0.set_start_time(uhd.time_spec(10))
>>tb.uhd_usrp_sink_0.set_start_time(uhd.time_spec(10))
>>   at the beginning of my flow graph. I see no signal until 10s, as
>> expected
>> - I experimented with "tx_time" and stream tags but for some reason many
>> timed I get flooded with L's
>>
>>
>> Can it be that there is another bug lurking somewhere deep in the USRP
>> firmware?
>>
>> Thanks,
>> Lukas
>>
>>
>>
>> Gesendet: Mittwoch, 04. März 2020 um 19:27 Uhr
>> Von: "Marcus D Leech" 
>> An: "Rob Kossler" 
>> Cc: "Lukas Haase" , "USRP-users@lists.ettus.com" <
>> usrp-users@lists.ettus.com>
>> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using
>> a timed command
>>
>> When you select one of the PPS synch options in a GRC USRP block it will
>> set the time to zero.
>>
>> Easy enough to modify the code to do something more sophisticated, but
>> knowing that it will be set to zero helps you know how to proceed.
>>
>>
>> Sent from my iPhone
>>  On Mar 4, 2020,

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-13 Thread Rob Kossler via USRP-users
Lukas,
Can you confirm the exact git hash for both UHD and the FPGA image you are
using? Perhaps the easiest way is to run uhd_usrp_probe.
Rob

On Fri, Mar 13, 2020 at 1:00 AM Lukas Haase  wrote:

> Dear Marcus, Dear Rob,
>
> Thank you very much for these tips with "Unknown PPS", stream 2 streams
> and the explanation of set_start_time. That makes sense.
>
> Since then I spent hours and hours every day on TX+RX but STILL no
> synchronized phase for dspfreq!
> Timed commands seem to work.
> Also, in general, synchronization.
> With this code, I get my long desired cohrent phase between TX+RX but ONLY
> if I do not touch dsp tuning (and only use the PLL in integer-N mode):
>
> tune_req_rx = uhd.tune_request()
> tune_req_rx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
> tune_req_rx.dsp_freq_policy = uhd.tune_request.POLICY_NONE #
> IMPORTANT!
> tune_req_rx.rf_freq = rf_freq
> tune_req_tx.dsp_freq = -dsp_freq
> tune_req_rx.args=uhd.device_addr(','.join(["mode_n=integer",
> "int_n_step=1000e3",]))
>
> tune_req_tx = uhd.tune_request()
> tune_req_tx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
> tune_req_tx.dsp_freq_policy = uhd.tune_request.POLICY_NONE #
> IMPORTANT!
> tune_req_tx.rf_freq = rf_freq
> tune_req_tx.dsp_freq = dsp_freq
> tune_req_tx.args=uhd.device_addr(','.join(["mode_n=integer",
> "int_n_step=1000e3",]))
>
> now = usrp_sink.get_time_now()
> when = now + uhd.time_spec(1.0)
> print("Clicked to switch R-T-X frf=" + str(rf_freq) + ", fdsp=" +
> str(dsp_freq) + " at " + str(now.get_full_secs()) + ":" +
> str(now.get_frac_secs()) + " for " + str(when.get_full_secs()) + ":" +
> str(when.get_frac_secs()))
>
> usrp_sink.set_command_time(when)
> usrp_source.set_command_time(when)
> res2 = usrp_sink.set_center_freq(tune_req_tx)   # "TX/RX" of
> first UBX160 is transmitter
> res1 = usrp_source.set_center_freq(tune_req_rx, 1)  # "RX2" of
> second UBX160 is receiver
> usrp_sink.clear_command_time()
> usrp_source.clear_command_time()
>
> With phase coherence I mean if I read out the received phase and I switch
> between f1 and f2, I always get the same phase for f1 and f2, respectively.
>
> But if I set dsp_freq_policy to MANUAL (or I add an LO offset which also
> required dsp retuning) I just don't get any coherent phase.
>
> I used the tricks you mentioned:
>
> - I use unknown PPS in both which makes USRP time start at zero (tested)
> - Both "USRP Source" and "USRP Sink" have 2 channels (and one of each
> connects to Null Source/Sink). This should ensure that stream start time is
> set! (tested)
> - Even if not, I also used explicitely
>tb.uhd_usrp_source_0.set_start_time(uhd.time_spec(10))
>tb.uhd_usrp_sink_0.set_start_time(uhd.time_spec(10))
>   at the beginning of my flow graph. I see no signal until 10s, as expected
> - I experimented with "tx_time" and stream tags but for some reason many
> timed I get flooded with L's
>
>
> Can it be that there is another bug lurking somewhere deep in the USRP
> firmware?
>
> Thanks,
> Lukas
>
>
>
> Gesendet: Mittwoch, 04. März 2020 um 19:27 Uhr
> Von: "Marcus D Leech" 
> An: "Rob Kossler" 
> Cc: "Lukas Haase" , "USRP-users@lists.ettus.com" <
> usrp-users@lists.ettus.com>
> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using
> a timed command
>
> When you select one of the PPS synch options in a GRC USRP block it will
> set the time to zero.
>
> Easy enough to modify the code to do something more sophisticated, but
> knowing that it will be set to zero helps you know how to proceed.
>
>
> Sent from my iPhone
>  On Mar 4, 2020, at 12:43 PM, Rob Kossler via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
> 
>
> Regarding #2)
> I don't think that what you want is a "command" tag, but rather a "time
> stamp tag" which I believe is "tx_time" based on the link you provided to
> the documentation.  The documentation says, "The timestamp tag value is a
> PMT tuple of the following: (uint64 seconds, double fractional seconds)".
> If I am correct, perhaps the code snipped you provided will not come into
> play.
>
> Just to be clear, I don't think you should need to do both #1 and #2.
> But, I "believe" that either method should be possible to accomplish the
> goa

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-12 Thread Lukas Haase via USRP-users
Dear Marcus, Dear Rob,

Thank you very much for these tips with "Unknown PPS", stream 2 streams and the 
explanation of set_start_time. That makes sense.

Since then I spent hours and hours every day on TX+RX but STILL no synchronized 
phase for dspfreq!
Timed commands seem to work.
Also, in general, synchronization.
With this code, I get my long desired cohrent phase between TX+RX but ONLY if I 
do not touch dsp tuning (and only use the PLL in integer-N mode):

tune_req_rx = uhd.tune_request()
tune_req_rx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
tune_req_rx.dsp_freq_policy = uhd.tune_request.POLICY_NONE # IMPORTANT!
tune_req_rx.rf_freq = rf_freq
tune_req_tx.dsp_freq = -dsp_freq
tune_req_rx.args=uhd.device_addr(','.join(["mode_n=integer", 
"int_n_step=1000e3",]))

tune_req_tx = uhd.tune_request()
tune_req_tx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
tune_req_tx.dsp_freq_policy = uhd.tune_request.POLICY_NONE # IMPORTANT!
tune_req_tx.rf_freq = rf_freq
tune_req_tx.dsp_freq = dsp_freq
tune_req_tx.args=uhd.device_addr(','.join(["mode_n=integer", 
"int_n_step=1000e3",]))

now = usrp_sink.get_time_now()
when = now + uhd.time_spec(1.0)
print("Clicked to switch R-T-X frf=" + str(rf_freq) + ", fdsp=" + 
str(dsp_freq) + " at " + str(now.get_full_secs()) + ":" + 
str(now.get_frac_secs()) + " for " + str(when.get_full_secs()) + ":" + 
str(when.get_frac_secs()))

usrp_sink.set_command_time(when)
usrp_source.set_command_time(when)
res2 = usrp_sink.set_center_freq(tune_req_tx)   # "TX/RX" of first 
UBX160 is transmitter
res1 = usrp_source.set_center_freq(tune_req_rx, 1)  # "RX2" of second 
UBX160 is receiver
usrp_sink.clear_command_time()
usrp_source.clear_command_time()

With phase coherence I mean if I read out the received phase and I switch 
between f1 and f2, I always get the same phase for f1 and f2, respectively.

But if I set dsp_freq_policy to MANUAL (or I add an LO offset which also 
required dsp retuning) I just don't get any coherent phase.

I used the tricks you mentioned:

- I use unknown PPS in both which makes USRP time start at zero (tested)
- Both "USRP Source" and "USRP Sink" have 2 channels (and one of each connects 
to Null Source/Sink). This should ensure that stream start time is set! (tested)
- Even if not, I also used explicitely
   tb.uhd_usrp_source_0.set_start_time(uhd.time_spec(10))
   tb.uhd_usrp_sink_0.set_start_time(uhd.time_spec(10))
  at the beginning of my flow graph. I see no signal until 10s, as expected
- I experimented with "tx_time" and stream tags but for some reason many timed 
I get flooded with L's


Can it be that there is another bug lurking somewhere deep in the USRP firmware?

Thanks,
Lukas



Gesendet: Mittwoch, 04. März 2020 um 19:27 Uhr
Von: "Marcus D Leech" 
An: "Rob Kossler" 
Cc: "Lukas Haase" , "USRP-users@lists.ettus.com" 

Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
timed command

When you select one of the PPS synch options in a GRC USRP block it will set 
the time to zero. 
 
Easy enough to modify the code to do something more sophisticated, but knowing 
that it will be set to zero helps you know how to proceed. 
 
 
Sent from my iPhone
 On Mar 4, 2020, at 12:43 PM, Rob Kossler via USRP-users 
 wrote:
 


Regarding #2)
I don't think that what you want is a "command" tag, but rather a "time stamp 
tag" which I believe is "tx_time" based on the link you provided to the 
documentation.  The documentation says, "The timestamp tag value is a PMT tuple 
of the following: (uint64 seconds, double fractional seconds)".  If I am 
correct, perhaps the code snipped you provided will not come into play.
 
Just to be clear, I don't think you should need to do both #1 and #2.  But, I 
"believe" that either method should be possible to accomplish the goal of 
attaching a time stamp to the streaming.  
 
Also, keep in mind that the time stamp that you provide to the DUC block for 
the freq change is related to the time stamp you attach to the streaming 
samples.  Let me explain with a few remarks:

If you apply the time stamp of 0.5 to the streaming samples, then the first 
sample will have time 0.5 and then UHD will keep track of all subsequent 
samples to know the absolute time of any given sample.  I am assuming that once 
you start transmitting you will keep transmitting continuously until the flow 
graph ends.If you then start hopping your DUC with time stamps such as 0.6, 
0.7, 0.8, etc, then UHD should apply the hop at the correct part of the stream 
since it knows the tim

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-04 Thread Marcus D Leech via USRP-users
annoying is 
>>> that I have two objects for the same device (*one* USRP and "USRP 
>>> Source"+"USRP Sink", both with their independent uhd::usrp::multi_usrp 
>>> objects. My question is, is it possible to just use "USRP Source" (this is 
>>> where timed commands work) to execute the retuning for *both* RX+TX?
>>> 
>>> 3.a.) Given: X310 with 2xUBX-160. What is the subdev spec if I wanted to 
>>> receive on all FOUR inputs??
>>> The problem is that both RX and TX frontends have the same name "0" 
>>> (according to uhd_usrp_probe).
>>> 
>>> Two receivers, receiving both from "TX/RX" input of each UBX-160 would be 
>>> trivial: "A:0 B:0". However, how do I address "RX2"? Intuitively "A:0 A:1 
>>> B:0 B:1" but as said, both "TX/RX" and "RX2" are named "0".
>>> What would I do if I wanted to transmit from "TX/RX" of the second UBX and 
>>> receive on all other boards?
>>> 
>>> On the USRP Sink: "B:0"
>>> On the USP Source intuitively: "A:0 A:1 B:1" but that's wrong.
>>> 
>>> 3.b.) In gr, there will be two multi_usrp objects: One for the receiver 
>>> (member variable of USRP Source) and one for the transmitter (member 
>>> variable of USRP Sink).
>>> Can I set up a USRP Source that has two channels where the second one is 
>>> actually a TX channel? (only used for retuning via timed commands)?
>>> 
>>> 
>>> Thanks,
>>> Lukas
>>> 
>>> 
>>>  
>>>  
>>> 
>>> Gesendet: Dienstag, 03. März 2020 um 15:22 Uhr
>>> Von: "Rob Kossler" 
>>> An: "Lukas Haase" 
>>> Cc: "Sam Reiter" , "USRP-users@lists.ettus.com" 
>>> 
>>> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
>>> timed command
>>> 
>>> I did a quick google search using "gnuradio uhd timed tx streaming". I 
>>> found that the GR 
>>> usrp_sink[https://www.gnuradio.org/doc/sphinx-3.7.7/uhd.html] has the 
>>> function "set_start_time" which seems to be what you need.  The question 
>>> is: what time do you set?  Probably just something like "get_time_now() + 
>>> 0.1". It may be a bit tricky since this value is to be set before starting 
>>> the flow graph.  Maybe you could set it to some fixed constant like 0.5 and 
>>> then when the flow graph starts you could execute a command to 
>>> set_time_now() to 0.0.  Anyway, if this advice doesn't pan out, perhaps 
>>> just search around a bit in GR archives.  I'm sure others have successfully 
>>> streamed with timed Tx commands.
>>> Rob 
>>> 
>>> On Tue, Mar 3, 2020 at 3:00 PM Lukas Haase 
>>> mailto:lukasha...@gmx.at]> wrote:
>>> 
>>> Hi Sam, Hi Rob,
>>> 
>>> This makes so much sense!
>>> I think you are right.
>>> And indeed, the issue I found only with TX, not RX.
>>> 
>>> 
>>> Could you think of a possible hack sending a "dummy command" to the RF 
>>> board along with the timed tuning request?
>>> 
>>> 
>>> Regarding the sending of time stamps in the TX in gr-uhd, I am confused 
>>> though. I do think this IS happening. I reproduce the work function of 
>>> "USRP Sink" here:
>>> 
>>> int usrp_sink_impl::work(int noutput_items,
>>>  gr_vector_const_void_star& input_items,
>>>  gr_vector_void_star& output_items)
>>> {
>>> int ninput_items = noutput_items; // cuz it's a sync block
>>> 
>>> // default to send a mid-burst packet
>>> _metadata.start_of_burst = false;
>>> _metadata.end_of_burst = false;
>>> 
>>> // collect tags in this work()
>>> const uint64_t samp0_count = nitems_read(0);
>>> get_tags_in_range(_tags, 0, samp0_count, samp0_count + ninput_items);
>>> if (not _tags.empty())
>>> this->tag_work(ninput_items);
>>> 
>>> if (not pmt::is_null(_length_tag_key)) {
>>> // check if there is data left to send from a burst tagged with 
>>> length_tag
>>> // If a burst is started during this call to work(), tag_work() 
>>> should have
>>> // been called and we should have _nitems_to_se

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-04 Thread Rob Kossler via USRP-users
e from the sample time
>>> msg_handler_command(value);
>>> }
>>>
>>> 3.) So I am really back to the start. What is generally a bit annoying
>>> is that I have two objects for the same device (*one* USRP and "USRP
>>> Source"+"USRP Sink", both with their independent uhd::usrp::multi_usrp
>>> objects. My question is, is it possible to just use "USRP Source" (this is
>>> where timed commands work) to execute the retuning for *both* RX+TX?
>>>
>>> 3.a.) Given: X310 with 2xUBX-160. What is the subdev spec if I wanted to
>>> receive on all FOUR inputs??
>>> The problem is that both RX and TX frontends have the same name "0"
>>> (according to uhd_usrp_probe).
>>>
>>> Two receivers, receiving both from "TX/RX" input of each UBX-160 would
>>> be trivial: "A:0 B:0". However, how do I address "RX2"? Intuitively "A:0
>>> A:1 B:0 B:1" but as said, both "TX/RX" and "RX2" are named "0".
>>> What would I do if I wanted to transmit from "TX/RX" of the second UBX
>>> and receive on all other boards?
>>>
>>> On the USRP Sink: "B:0"
>>> On the USP Source intuitively: "A:0 A:1 B:1" but that's wrong.
>>>
>>> 3.b.) In gr, there will be two multi_usrp objects: One for the receiver
>>> (member variable of USRP Source) and one for the transmitter (member
>>> variable of USRP Sink).
>>> Can I set up a USRP Source that has two channels where the second one is
>>> actually a TX channel? (only used for retuning via timed commands)?
>>>
>>>
>>> Thanks,
>>> Lukas
>>>
>>>
>>>
>>>
>>>
>>> Gesendet: Dienstag, 03. März 2020 um 15:22 Uhr
>>> Von: "Rob Kossler" 
>>> An: "Lukas Haase" 
>>> Cc: "Sam Reiter" , "USRP-users@lists.ettus.com" <
>>> usrp-users@lists.ettus.com>
>>> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when
>>> using a timed command
>>>
>>> I did a quick google search using "gnuradio uhd timed tx streaming". I
>>> found that the GR usrp_sink[
>>> https://www.gnuradio.org/doc/sphinx-3.7.7/uhd.html] has the function
>>> "set_start_time" which seems to be what you need.  The question is: what
>>> time do you set?  Probably just something like "get_time_now() + 0.1". It
>>> may be a bit tricky since this value is to be set before starting the flow
>>> graph.  Maybe you could set it to some fixed constant like 0.5 and then
>>> when the flow graph starts you could execute a command to set_time_now() to
>>> 0.0.  Anyway, if this advice doesn't pan out, perhaps just search around a
>>> bit in GR archives.  I'm sure others have successfully streamed with timed
>>> Tx commands.
>>> Rob
>>>
>>> On Tue, Mar 3, 2020 at 3:00 PM Lukas Haase >> lukasha...@gmx.at]> wrote:
>>>
>>> Hi Sam, Hi Rob,
>>>
>>> This makes so much sense!
>>> I think you are right.
>>> And indeed, the issue I found only with TX, not RX.
>>>
>>>
>>> Could you think of a possible hack sending a "dummy command" to the RF
>>> board along with the timed tuning request?
>>>
>>>
>>> Regarding the sending of time stamps in the TX in gr-uhd, I am confused
>>> though. I do think this IS happening. I reproduce the work function of
>>> "USRP Sink" here:
>>>
>>> int usrp_sink_impl::work(int noutput_items,
>>>  gr_vector_const_void_star& input_items,
>>>  gr_vector_void_star& output_items)
>>> {
>>> int ninput_items = noutput_items; // cuz it's a sync block
>>>
>>> // default to send a mid-burst packet
>>> _metadata.start_of_burst = false;
>>> _metadata.end_of_burst = false;
>>>
>>> // collect tags in this work()
>>> const uint64_t samp0_count = nitems_read(0);
>>> get_tags_in_range(_tags, 0, samp0_count, samp0_count + ninput_items);
>>> if (not _tags.empty())
>>> this->tag_work(ninput_items);
>>>
>>> if (not pmt::is_null(_length_tag_key)) {
>>> // check if there is data left to send from a burst tagged with
>>> length_tag
>>>

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-04 Thread Rob Kossler via USRP-users
uot; input of each UBX-160 would be
>> trivial: "A:0 B:0". However, how do I address "RX2"? Intuitively "A:0 A:1
>> B:0 B:1" but as said, both "TX/RX" and "RX2" are named "0".
>> What would I do if I wanted to transmit from "TX/RX" of the second UBX
>> and receive on all other boards?
>>
>> On the USRP Sink: "B:0"
>> On the USP Source intuitively: "A:0 A:1 B:1" but that's wrong.
>>
>> 3.b.) In gr, there will be two multi_usrp objects: One for the receiver
>> (member variable of USRP Source) and one for the transmitter (member
>> variable of USRP Sink).
>> Can I set up a USRP Source that has two channels where the second one is
>> actually a TX channel? (only used for retuning via timed commands)?
>>
>>
>> Thanks,
>> Lukas
>>
>>
>>
>>
>>
>> Gesendet: Dienstag, 03. März 2020 um 15:22 Uhr
>> Von: "Rob Kossler" 
>> An: "Lukas Haase" 
>> Cc: "Sam Reiter" , "USRP-users@lists.ettus.com" <
>> usrp-users@lists.ettus.com>
>> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using
>> a timed command
>>
>> I did a quick google search using "gnuradio uhd timed tx streaming". I
>> found that the GR usrp_sink[
>> https://www.gnuradio.org/doc/sphinx-3.7.7/uhd.html] has the function
>> "set_start_time" which seems to be what you need.  The question is: what
>> time do you set?  Probably just something like "get_time_now() + 0.1". It
>> may be a bit tricky since this value is to be set before starting the flow
>> graph.  Maybe you could set it to some fixed constant like 0.5 and then
>> when the flow graph starts you could execute a command to set_time_now() to
>> 0.0.  Anyway, if this advice doesn't pan out, perhaps just search around a
>> bit in GR archives.  I'm sure others have successfully streamed with timed
>> Tx commands.
>> Rob
>>
>> On Tue, Mar 3, 2020 at 3:00 PM Lukas Haase > lukasha...@gmx.at]> wrote:
>>
>> Hi Sam, Hi Rob,
>>
>> This makes so much sense!
>> I think you are right.
>> And indeed, the issue I found only with TX, not RX.
>>
>>
>> Could you think of a possible hack sending a "dummy command" to the RF
>> board along with the timed tuning request?
>>
>>
>> Regarding the sending of time stamps in the TX in gr-uhd, I am confused
>> though. I do think this IS happening. I reproduce the work function of
>> "USRP Sink" here:
>>
>> int usrp_sink_impl::work(int noutput_items,
>>  gr_vector_const_void_star& input_items,
>>  gr_vector_void_star& output_items)
>> {
>> int ninput_items = noutput_items; // cuz it's a sync block
>>
>> // default to send a mid-burst packet
>> _metadata.start_of_burst = false;
>> _metadata.end_of_burst = false;
>>
>> // collect tags in this work()
>> const uint64_t samp0_count = nitems_read(0);
>> get_tags_in_range(_tags, 0, samp0_count, samp0_count + ninput_items);
>> if (not _tags.empty())
>> this->tag_work(ninput_items);
>>
>> if (not pmt::is_null(_length_tag_key)) {
>> // check if there is data left to send from a burst tagged with
>> length_tag
>> // If a burst is started during this call to work(), tag_work()
>> should have
>> // been called and we should have _nitems_to_send > 0.
>> if (_nitems_to_send > 0) {
>> ninput_items = std::min(_nitems_to_send, ninput_items);
>> // if we run out of items to send, it's the end of the burst
>> if (_nitems_to_send - long(ninput_items) == 0)
>> _metadata.end_of_burst = true;
>> } else {
>> // There is a tag gap since no length_tag was found
>> immediately following
>> // the last sample of the previous burst. Drop samples until
>> the next
>> // length_tag is found. Notify the user of the tag gap.
>> std::cerr << "tG" << std::flush;
>> // increment the timespec by the number of samples dropped
>> _metadata.time_spec += ::uhd::time_spec_t(0, ninput_items,
>> _sample_rate);
>> return ninput_items;
>> }
>> }
>>
>> boost::this_thread::disable_interruption disable_interrupt;
>>

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-04 Thread Rob Kossler via USRP-users
Hi Lukas,
Let me respond to #1 right away.  The "set_start_time" function sets the
time of the tx stream.  It does not set the "clock time" on the usrp.  If
you are indeed correct that the "clock time" on the usrp is initialized to
0.0 at the start of the GR run, then you are lucky and all you should need
to do is use the "set_start_time" function with a time spec of something
like 0.2 or 0.5 (any time after 0.0 with perhaps a little delay built in).
To see if it is working, you could set the time spec to something very
large like 5.0 or 10.0 and then you should see the GR run start up but no
Tx for the next 5 or 10 seconds.  Then the Tx should start.  Does that make
sense?
Rob


On Wed, Mar 4, 2020 at 12:06 PM Lukas Haase  wrote:

> Hi Rob,
>
> 1.) I do not really understand how "set_start_time" is related to my
> problem and why this is what I need. Based on my experiments, the time is
> automatically set to 0 when the flow diagram starts.
>
> I am also sure others must have used timed TX+RX but it does not seem so.
> No kidding, I am working on this since Dec and I still do not have it
> working. I left my traces various times on this and the gnuradio mailing
> list but I did not get help.
>
> 2.) I have played around using stream tags and was very happy that it
> worked but I found now that this is because gr-uhd does NOT attach a
> command time although the documentation says so.
>
> https://www.gnuradio.org/doc/doxygen/classgr_1_1uhd_1_1usrp__sink.html:
> tx_command tag. The command is attached to a sample, and will executed
> before the sample is transmitted, and after the previous sample.
>
> However, in the code (usrp_sink_impl.cc:433, usrp_sink_impl::tag_work):
>
> else if (pmt::equal(key, COMMAND_KEY)) {
> if (my_tag_count != samp0_count) {
> max_count = my_tag_count;
> break;
> }
> // TODO set the command time from the sample time
> msg_handler_command(value);
> }
>
> 3.) So I am really back to the start. What is generally a bit annoying is
> that I have two objects for the same device (*one* USRP and "USRP
> Source"+"USRP Sink", both with their independent uhd::usrp::multi_usrp
> objects. My question is, is it possible to just use "USRP Source" (this is
> where timed commands work) to execute the retuning for *both* RX+TX?
>
> 3.a.) Given: X310 with 2xUBX-160. What is the subdev spec if I wanted to
> receive on all FOUR inputs??
> The problem is that both RX and TX frontends have the same name "0"
> (according to uhd_usrp_probe).
>
> Two receivers, receiving both from "TX/RX" input of each UBX-160 would be
> trivial: "A:0 B:0". However, how do I address "RX2"? Intuitively "A:0 A:1
> B:0 B:1" but as said, both "TX/RX" and "RX2" are named "0".
> What would I do if I wanted to transmit from "TX/RX" of the second UBX and
> receive on all other boards?
>
> On the USRP Sink: "B:0"
> On the USP Source intuitively: "A:0 A:1 B:1" but that's wrong.
>
> 3.b.) In gr, there will be two multi_usrp objects: One for the receiver
> (member variable of USRP Source) and one for the transmitter (member
> variable of USRP Sink).
> Can I set up a USRP Source that has two channels where the second one is
> actually a TX channel? (only used for retuning via timed commands)?
>
>
> Thanks,
> Lukas
>
>
>
>
>
> Gesendet: Dienstag, 03. März 2020 um 15:22 Uhr
> Von: "Rob Kossler" 
> An: "Lukas Haase" 
> Cc: "Sam Reiter" , "USRP-users@lists.ettus.com" <
> usrp-users@lists.ettus.com>
> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using
> a timed command
>
> I did a quick google search using "gnuradio uhd timed tx streaming". I
> found that the GR usrp_sink[
> https://www.gnuradio.org/doc/sphinx-3.7.7/uhd.html] has the function
> "set_start_time" which seems to be what you need.  The question is: what
> time do you set?  Probably just something like "get_time_now() + 0.1". It
> may be a bit tricky since this value is to be set before starting the flow
> graph.  Maybe you could set it to some fixed constant like 0.5 and then
> when the flow graph starts you could execute a command to set_time_now() to
> 0.0.  Anyway, if this advice doesn't pan out, perhaps just search around a
> bit in GR archives.  I'm sure others have successfully streamed with timed
> Tx commands.
> Rob
>
> On Tue, Mar 3, 2020 at 3:00 PM Lukas Haase  lukasha...@gmx.at]> 

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-04 Thread Lukas Haase via USRP-users
Hi Rob,

1.) I do not really understand how "set_start_time" is related to my problem 
and why this is what I need. Based on my experiments, the time is automatically 
set to 0 when the flow diagram starts.

I am also sure others must have used timed TX+RX but it does not seem so. No 
kidding, I am working on this since Dec and I still do not have it working. I 
left my traces various times on this and the gnuradio mailing list but I did 
not get help.

2.) I have played around using stream tags and was very happy that it worked 
but I found now that this is because gr-uhd does NOT attach a command time 
although the documentation says so.

https://www.gnuradio.org/doc/doxygen/classgr_1_1uhd_1_1usrp__sink.html:
tx_command tag. The command is attached to a sample, and will executed before 
the sample is transmitted, and after the previous sample.

However, in the code (usrp_sink_impl.cc:433, usrp_sink_impl::tag_work):

else if (pmt::equal(key, COMMAND_KEY)) {
if (my_tag_count != samp0_count) {
max_count = my_tag_count;
break;
}
// TODO set the command time from the sample time
msg_handler_command(value);
}

3.) So I am really back to the start. What is generally a bit annoying is that 
I have two objects for the same device (*one* USRP and "USRP Source"+"USRP 
Sink", both with their independent uhd::usrp::multi_usrp objects. My question 
is, is it possible to just use "USRP Source" (this is where timed commands 
work) to execute the retuning for *both* RX+TX?

3.a.) Given: X310 with 2xUBX-160. What is the subdev spec if I wanted to 
receive on all FOUR inputs??
The problem is that both RX and TX frontends have the same name "0" (according 
to uhd_usrp_probe).

Two receivers, receiving both from "TX/RX" input of each UBX-160 would be 
trivial: "A:0 B:0". However, how do I address "RX2"? Intuitively "A:0 A:1 B:0 
B:1" but as said, both "TX/RX" and "RX2" are named "0".
What would I do if I wanted to transmit from "TX/RX" of the second UBX and 
receive on all other boards?

On the USRP Sink: "B:0"
On the USP Source intuitively: "A:0 A:1 B:1" but that's wrong.

3.b.) In gr, there will be two multi_usrp objects: One for the receiver (member 
variable of USRP Source) and one for the transmitter (member variable of USRP 
Sink).
Can I set up a USRP Source that has two channels where the second one is 
actually a TX channel? (only used for retuning via timed commands)?


Thanks,
Lukas


 
 

Gesendet: Dienstag, 03. März 2020 um 15:22 Uhr
Von: "Rob Kossler" 
An: "Lukas Haase" 
Cc: "Sam Reiter" , "USRP-users@lists.ettus.com" 

Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
timed command

I did a quick google search using "gnuradio uhd timed tx streaming". I found 
that the GR usrp_sink[https://www.gnuradio.org/doc/sphinx-3.7.7/uhd.html] has 
the function "set_start_time" which seems to be what you need.  The question 
is: what time do you set?  Probably just something like "get_time_now() + 0.1". 
It may be a bit tricky since this value is to be set before starting the flow 
graph.  Maybe you could set it to some fixed constant like 0.5 and then when 
the flow graph starts you could execute a command to set_time_now() to 0.0.  
Anyway, if this advice doesn't pan out, perhaps just search around a bit in GR 
archives.  I'm sure others have successfully streamed with timed Tx commands.
Rob 

On Tue, Mar 3, 2020 at 3:00 PM Lukas Haase 
mailto:lukasha...@gmx.at]> wrote:

Hi Sam, Hi Rob,

This makes so much sense!
I think you are right.
And indeed, the issue I found only with TX, not RX.


Could you think of a possible hack sending a "dummy command" to the RF board 
along with the timed tuning request?


Regarding the sending of time stamps in the TX in gr-uhd, I am confused though. 
I do think this IS happening. I reproduce the work function of "USRP Sink" here:

int usrp_sink_impl::work(int noutput_items,
                         gr_vector_const_void_star& input_items,
                         gr_vector_void_star& output_items)
{
    int ninput_items = noutput_items; // cuz it's a sync block

    // default to send a mid-burst packet
    _metadata.start_of_burst = false;
    _metadata.end_of_burst = false;

    // collect tags in this work()
    const uint64_t samp0_count = nitems_read(0);
    get_tags_in_range(_tags, 0, samp0_count, samp0_count + ninput_items);
    if (not _tags.empty())
        this->tag_work(ninput_items);

    if (not pmt::is_null(_length_tag_key)) {
        // check if there is data left to send from a burst tagged with 
length_tag
        // If a burst is started during this call to work(), tag

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-03 Thread Rob Kossler via USRP-users
cluding
> _metadata:
>
> const size_t num_sent = _tx_stream->send(input_items, ninput_items,
> _metadata, 1.0);
>
> The "time_spec" is updated for each block that is sent out:
>
> _metadata.time_spec += ::uhd::time_spec_t(0, num_sent, _sample_rate);
>
> Now you mentioned "has_time_spec" below. I extended to code in the
> following way:
>
> // increment the timespec by the number of samples sent
> _metadata.time_spec += ::uhd::time_spec_t(0, num_sent, _sample_rate);
> GR_LOG_DEBUG(d_debug_logger, boost::format("Setting metadata
> time_spec: %d:%f") % _metadata.time_spec.get_full_secs() %
> _metadata.time_spec.get_frac_secs());
> _metadata.has_time_spec = true;
>
>
> To my understanding, gr-uhd now passes the correct timestamps on to UHD.
> However, the timed command is still ignored.
>
>
> Thanks,
> Lukas
>
>
> PS: I will attempt to use the tagged stream ... but then I will have the
> issue that I need to tune TX *plus* RX at the same time! Furthermore, the
> streaming tags API is super rudimentary. Also, skimming the source code for
> the tag processing, I am not sure if this would change anything.
>
>
>
>
>
>
>
>
> Gesendet: Dienstag, 03. März 2020 um 13:25 Uhr
> Von: "Sam Reiter" 
> An: "Rob Kossler" 
> Cc: "Lukas Haase" , "USRP-users@lists.ettus.com" <
> usrp-users@lists.ettus.com>
> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using
> a timed command
>
> Everything Rob is saying is dead on - the "sense of time" for the radio is
> a 64-bit counter within the radio core that other blocks (like the DDC and
> DUC) don't have access to. Those blocks need to derive a sense of time from
> the timestamps of CHDR packets passing through them. I just wrapped up a
> new app note that covers this (among other synchronization-related topics):
>
>
> https://kb.ettus.com/Synchronizing_USRP_Events_Using_Timed_Commands_in_UHD#Clocking_and_Timekeeping_in_the_USRP
>
> Lukas, I would doubt that this is an undiscovered bug as much as it is an
> issue with implementation. If this were in C++, you'd want to set the
> 'has_time_spec' and 'time_spec' fields of your TX metadata for at least 1
> packet to impart a sense of time on the DUC:
>
>
> https://files.ettus.com/manual/structuhd_1_1tx__metadata__t.html[https://files.ettus.com/manual/structuhd_1_1tx__metadata__t.html]
>
> I just spoke with someone on my end who said you need to use stream tags
> to do this, but again, I don't currently have much direction for how that
> would be implemented in your code.
>
>
> Sam Reiter
>
> On Tue, Mar 3, 2020 at 11:48 AM Rob Kossler  rkoss...@nd.edu]> wrote:
> Also, note that there is no corresponding issue on receive because the Rx
> radio always inserts the time stamp in the sample stream. So, I guess you
> would not see this with the DDC.
> Rob
>
> On Tue, Mar 3, 2020 at 12:43 PM Rob Kossler  rkoss...@nd.edu]> wrote:
>
> Hi Lukas,
> The FPGA image on the USRP is divided into blocks such as the DUC block
> and the Radio block.  The latter controls the RF daughterboard and has
> access to the device clock.  So, when you provide a timed command to the
> Radio block (such as for tuning the RF) it can implement the command at the
> specified time by comparing to the device clock.  The DUC block does not
> have access to the MB clock and so when you give it a timed command, it
> monitors the incoming sample stream to extract the time. If the sample
> stream does not include a time stamp, the command never executes.  Don't
> think of this as a bug, but rather as a design limitation.
>
> When I work directly with UHD from C++, I use the function
> rx_streamer::issue_stream_command() which has options to stream data with
> no time stamp or with a time stamp.  When using timed commands with DUC or
> DDC, I must include the time stamp or else the command will never be
> executed.  But, with GR, I don't know how to specify the corresponding
> options.
> Rob
>
> On Tue, Mar 3, 2020 at 12:29 PM Lukas Haase  lukasha...@gmx.at]> wrote:Hi Sam, Hi Rob,
>
> Thanks for following up on this!
> I am very happy you were able to reproduce this ... which means that at
> least an issue exists :)
>
> What Sam suggests makes sense even though hard to believe for me:
>
> 1. How could something like that go unnoticed for so long? (I am sure I am
> not the first performing digital tuning)
> 2. In the past I got successful phase coherence using automatic tuning
> (passing center frequency + offset to tune_request_t and using integer-N
> tuning) using timed com

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-03 Thread Lukas Haase via USRP-users
Hi Sam, Hi Rob,

This makes so much sense!
I think you are right.
And indeed, the issue I found only with TX, not RX.


Could you think of a possible hack sending a "dummy command" to the RF board 
along with the timed tuning request?


Regarding the sending of time stamps in the TX in gr-uhd, I am confused though. 
I do think this IS happening. I reproduce the work function of "USRP Sink" here:

int usrp_sink_impl::work(int noutput_items,
 gr_vector_const_void_star& input_items,
 gr_vector_void_star& output_items)
{
int ninput_items = noutput_items; // cuz it's a sync block

// default to send a mid-burst packet
_metadata.start_of_burst = false;
_metadata.end_of_burst = false;

// collect tags in this work()
const uint64_t samp0_count = nitems_read(0);
get_tags_in_range(_tags, 0, samp0_count, samp0_count + ninput_items);
if (not _tags.empty())
this->tag_work(ninput_items);

if (not pmt::is_null(_length_tag_key)) {
// check if there is data left to send from a burst tagged with 
length_tag
// If a burst is started during this call to work(), tag_work() should 
have
// been called and we should have _nitems_to_send > 0.
if (_nitems_to_send > 0) {
ninput_items = std::min(_nitems_to_send, ninput_items);
// if we run out of items to send, it's the end of the burst
if (_nitems_to_send - long(ninput_items) == 0)
_metadata.end_of_burst = true;
} else {
// There is a tag gap since no length_tag was found immediately 
following
// the last sample of the previous burst. Drop samples until the 
next
// length_tag is found. Notify the user of the tag gap.
std::cerr << "tG" << std::flush;
// increment the timespec by the number of samples dropped
_metadata.time_spec += ::uhd::time_spec_t(0, ninput_items, 
_sample_rate);
return ninput_items;
}
}

boost::this_thread::disable_interruption disable_interrupt;
#ifdef GR_UHD_USE_STREAM_API
// send all ninput_items with metadata
const size_t num_sent = _tx_stream->send(input_items, ninput_items, 
_metadata, 1.0);
#else
const size_t num_sent = _dev->get_device()->send(input_items,
 ninput_items,
 _metadata,
 *_type,
 
::uhd::device::SEND_MODE_FULL_BUFF,
 1.0);
#endif
boost::this_thread::restore_interruption 
restore_interrupt(disable_interrupt);

// if using length_tags, decrement items left to send by the number of 
samples sent
if (not pmt::is_null(_length_tag_key) && _nitems_to_send > 0) {
_nitems_to_send -= long(num_sent);
}

// increment the timespec by the number of samples sent
_metadata.time_spec += ::uhd::time_spec_t(0, num_sent, _sample_rate);

// Some post-processing tasks if we actually transmitted the entire burst
if (not _pending_cmds.empty() && num_sent == size_t(ninput_items)) {
GR_LOG_DEBUG(d_debug_logger,
 boost::format("Executing %d pending commands.") %
 _pending_cmds.size());
BOOST_FOREACH (const pmt::pmt_t& cmd_pmt, _pending_cmds) {
msg_handler_command(cmd_pmt);
}
_pending_cmds.clear();
}

return num_sent;
}

From this code, it can be seen that the data is transmitted including _metadata:

const size_t num_sent = _tx_stream->send(input_items, ninput_items, _metadata, 
1.0);

The "time_spec" is updated for each block that is sent out:

_metadata.time_spec += ::uhd::time_spec_t(0, num_sent, _sample_rate);

Now you mentioned "has_time_spec" below. I extended to code in the following 
way:

// increment the timespec by the number of samples sent
_metadata.time_spec += ::uhd::time_spec_t(0, num_sent, _sample_rate);
GR_LOG_DEBUG(d_debug_logger, boost::format("Setting metadata time_spec: 
%d:%f") % _metadata.time_spec.get_full_secs() % 
_metadata.time_spec.get_frac_secs());
_metadata.has_time_spec = true;


To my understanding, gr-uhd now passes the correct timestamps on to UHD.
However, the timed command is still ignored.


Thanks,
Lukas


PS: I will attempt to use the tagged stream ... but then I will have the issue 
that I need to tune TX *plus* RX at the same time! Furthermore, the streaming 
tags API is super rudimentary. Also, skimming the source code for the tag 
processing, I am not sure if this would change anything.




 
 
 

Gesendet: Dienstag, 03. März 2020 um 13:25 Uhr
Von: "Sam Reiter" 
An: &q

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-03 Thread Sam Reiter via USRP-users
Everything Rob is saying is dead on - the "sense of time" for the radio is
a 64-bit counter within the radio core that other blocks (like the DDC and
DUC) don't have access to. Those blocks need to derive a sense of time from
the timestamps of CHDR packets passing through them. I just wrapped up a
new app note that covers this (among other synchronization-related topics):

https://kb.ettus.com/Synchronizing_USRP_Events_Using_Timed_Commands_in_UHD#Clocking_and_Timekeeping_in_the_USRP

Lukas, I would doubt that this is an undiscovered bug as much as it is an
issue with implementation. If this were in C++, you'd want to set the
'has_time_spec' and 'time_spec' fields of your TX metadata for at least 1
packet to impart a sense of time on the DUC:

https://files.ettus.com/manual/structuhd_1_1tx__metadata__t.html

I just spoke with someone on my end who said you need to use stream tags to
do this, but again, I don't currently have much direction for how that
would be implemented in your code.

Sam Reiter

On Tue, Mar 3, 2020 at 11:48 AM Rob Kossler  wrote:

> Also, note that there is no corresponding issue on receive because the Rx
> radio always inserts the time stamp in the sample stream. So, I guess you
> would not see this with the DDC.
> Rob
>
> On Tue, Mar 3, 2020 at 12:43 PM Rob Kossler  wrote:
>
>> Hi Lukas,
>> The FPGA image on the USRP is divided into blocks such as the DUC block
>> and the Radio block.  The latter controls the RF daughterboard and has
>> access to the device clock.  So, when you provide a timed command to the
>> Radio block (such as for tuning the RF) it can implement the command at the
>> specified time by comparing to the device clock.  The DUC block does not
>> have access to the MB clock and so when you give it a timed command, it
>> monitors the incoming sample stream to extract the time. If the sample
>> stream does not include a time stamp, the command never executes.  Don't
>> think of this as a bug, but rather as a design limitation.
>>
>> When I work directly with UHD from C++, I use the function
>> rx_streamer::issue_stream_command() which has options to stream data with
>> no time stamp or with a time stamp.  When using timed commands with DUC or
>> DDC, I must include the time stamp or else the command will never be
>> executed.  But, with GR, I don't know how to specify the corresponding
>> options.
>> Rob
>>
>> On Tue, Mar 3, 2020 at 12:29 PM Lukas Haase  wrote:
>>
>>> Hi Sam, Hi Rob,
>>>
>>> Thanks for following up on this!
>>> I am very happy you were able to reproduce this ... which means that at
>>> least an issue exists :)
>>>
>>> What Sam suggests makes sense even though hard to believe for me:
>>>
>>> 1. How could something like that go unnoticed for so long? (I am sure I
>>> am not the first performing digital tuning)
>>> 2. In the past I got successful phase coherence using automatic tuning
>>> (passing center frequency + offset to tune_request_t and using integer-N
>>> tuning) using timed commands. This did not work reliably and only for
>>> certain frequencies but in my opinion this should have INCLUDED the DUC
>>> tuning. If the DUC retune wouldn't have been executed as part of this
>>> automatic tuning, I could not have gotten phase coherence (and actually,
>>> not even the desired frequency).
>>>
>>> The reason why I am only doing DUC tuning now is to avoid all the hassle
>>> with integer-N tuning, PLL retuning and settling time.
>>>
>>> Sam, what is the "radio block" you were talking about?
>>>
>>> Anyway, would it be worthwile to attempt debugging this is absence of gr?
>>> The only reason this prevented me from doing is that I would need to
>>> manually create the baseband samples and continuously stream them out while
>>> in parallel do the retuning.
>>> I am not too familiar with UHD on its own but I assume this would be
>>> very complicated, require multithreading etc.
>>> Do you have any demo code that could be easily modified for this
>>> scenario?
>>>
>>> Best,
>>> Lukas
>>>
>>>
>>> Gesendet: Dienstag, 03. März 2020 um 12:08 Uhr
>>> Von: "Sam Reiter" 
>>> An: "Rob Kossler" 
>>> Cc: "Lukas Haase" , "USRP-users@lists.ettus.com" <
>>> usrp-users@lists.ettus.com>
>>> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when
>>> using a timed command
>>>
>>> For what it's worth, 

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-03 Thread Rob Kossler via USRP-users
Also, note that there is no corresponding issue on receive because the Rx
radio always inserts the time stamp in the sample stream. So, I guess you
would not see this with the DDC.
Rob

On Tue, Mar 3, 2020 at 12:43 PM Rob Kossler  wrote:

> Hi Lukas,
> The FPGA image on the USRP is divided into blocks such as the DUC block
> and the Radio block.  The latter controls the RF daughterboard and has
> access to the device clock.  So, when you provide a timed command to the
> Radio block (such as for tuning the RF) it can implement the command at the
> specified time by comparing to the device clock.  The DUC block does not
> have access to the MB clock and so when you give it a timed command, it
> monitors the incoming sample stream to extract the time. If the sample
> stream does not include a time stamp, the command never executes.  Don't
> think of this as a bug, but rather as a design limitation.
>
> When I work directly with UHD from C++, I use the function
> rx_streamer::issue_stream_command() which has options to stream data with
> no time stamp or with a time stamp.  When using timed commands with DUC or
> DDC, I must include the time stamp or else the command will never be
> executed.  But, with GR, I don't know how to specify the corresponding
> options.
> Rob
>
> On Tue, Mar 3, 2020 at 12:29 PM Lukas Haase  wrote:
>
>> Hi Sam, Hi Rob,
>>
>> Thanks for following up on this!
>> I am very happy you were able to reproduce this ... which means that at
>> least an issue exists :)
>>
>> What Sam suggests makes sense even though hard to believe for me:
>>
>> 1. How could something like that go unnoticed for so long? (I am sure I
>> am not the first performing digital tuning)
>> 2. In the past I got successful phase coherence using automatic tuning
>> (passing center frequency + offset to tune_request_t and using integer-N
>> tuning) using timed commands. This did not work reliably and only for
>> certain frequencies but in my opinion this should have INCLUDED the DUC
>> tuning. If the DUC retune wouldn't have been executed as part of this
>> automatic tuning, I could not have gotten phase coherence (and actually,
>> not even the desired frequency).
>>
>> The reason why I am only doing DUC tuning now is to avoid all the hassle
>> with integer-N tuning, PLL retuning and settling time.
>>
>> Sam, what is the "radio block" you were talking about?
>>
>> Anyway, would it be worthwile to attempt debugging this is absence of gr?
>> The only reason this prevented me from doing is that I would need to
>> manually create the baseband samples and continuously stream them out while
>> in parallel do the retuning.
>> I am not too familiar with UHD on its own but I assume this would be very
>> complicated, require multithreading etc.
>> Do you have any demo code that could be easily modified for this scenario?
>>
>> Best,
>> Lukas
>>
>>
>> Gesendet: Dienstag, 03. März 2020 um 12:08 Uhr
>> Von: "Sam Reiter" 
>> An: "Rob Kossler" 
>> Cc: "Lukas Haase" , "USRP-users@lists.ettus.com" <
>> usrp-users@lists.ettus.com>
>> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using
>> a timed command
>>
>> For what it's worth, I was able to reproduce the behavior described here,
>> but didn't get to dig into it much. My leading suspicion would be what Rob
>> mentioned about timestamping. Lukas' code sets a command time, but I'm not
>> clear on how timestamp metadata for packets being sent to the radio are
>> handled. Might be a good question to loop the discuss-gnuradio mailing list
>> in on?
>>
>>
>>
>> Sam Reiter
>>
>> On Tue, Mar 3, 2020 at 10:59 AM Rob Kossler via USRP-users <
>> usrp-users@lists.ettus.com[mailto:usrp-users@lists.ettus.com]> wrote:
>> I wonder if the issue is related to a missing time stamp on the baseband
>> samples going from GR to UHD.  If the stream does not have a time stamp,
>> the DUC is unable to apply the timed command because the DUC does not
>> really know the time - it must pull the time from the streaming samples.
>> This is in contrast to the radio block which does have access to time and
>> can apply timed commands by referring to the motherboard clock.
>>
>> I am not too familiar with GR so I'm not sure how to know if GR is
>> putting a time stamp on the streaming samples.
>> Rob
>>
>> On Mon, Mar 2, 2020 at 10:04 AM Lukas Haase via USRP-users <
>> usrp-users@lists.ettus.com[mailto:usrp-users@lists.ettus.co

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-03 Thread Rob Kossler via USRP-users
Hi Marcus,
I'm pretty sure that the DDC and DUC don't have access to the MB clock and
thus have no option but to executed timed commands using the time stamp in
the sample stream.
Rob

On Tue, Mar 3, 2020 at 12:41 PM Marcus D. Leech via USRP-users <
usrp-users@lists.ettus.com> wrote:

> On 03/03/2020 12:08 PM, Sam Reiter via USRP-users wrote:
>
> For what it's worth, I was able to reproduce the behavior described here,
> but didn't get to dig into it much. My leading suspicion would be what Rob
> mentioned about timestamping. Lukas' code sets a command time, but I'm not
> clear on how timestamp metadata for packets being sent to the radio are
> handled. Might be a good question to loop the discuss-gnuradio mailing list
> in on?
>
> Sam Reiter
>
> Timed commands, I thought, were ALWAYS referred to the motherboard clock,
> without regard to timestamps in the stream?
>
>
>
> On Tue, Mar 3, 2020 at 10:59 AM Rob Kossler via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> I wonder if the issue is related to a missing time stamp on the baseband
>> samples going from GR to UHD.  If the stream does not have a time stamp,
>> the DUC is unable to apply the timed command because the DUC does not
>> really know the time - it must pull the time from the streaming samples.
>> This is in contrast to the radio block which does have access to time and
>> can apply timed commands by referring to the motherboard clock.
>>
>> I am not too familiar with GR so I'm not sure how to know if GR is
>> putting a time stamp on the streaming samples.
>> Rob
>>
>> On Mon, Mar 2, 2020 at 10:04 AM Lukas Haase via USRP-users <
>> usrp-users@lists.ettus.com> wrote:
>>
>>> Hi Marcus,
>>>
>>> Thank you that would be amazing!
>>>
>>> I followed the tutorial and built everything from source:
>>>
>>> $ lsb_release -a
>>> No LSB modules are available.
>>> Distributor ID: Ubuntu
>>> Description:Ubuntu 18.04.4 LTS
>>> Release:18.04
>>> Codename:   bionic
>>> $ uname -a
>>> Linux sdr 5.3.0-40-generic #32~18.04.1-Ubuntu SMP Mon Feb 3 14:05:59 UTC
>>> 2020 x86_64 x86_64 x86_64 GNU/Linux
>>> $ cd uhd
>>> $ git status
>>> HEAD detached at v3.15.0.0
>>> $ cd ../gnuradio
>>> $ git status
>>> HEAD detached at v3.7.14.0
>>>
>>>
>>> Thank you!
>>>
>>> Lukas
>>>
>>>
>>>
>>> PS: For some reason I sometimes do not get responses from this list. I
>>> just saw it looking at the mailman archives. Hence I cannot respond (to
>>> keep headers intact) but need to create a new message and manually "quote".
>>> I hope that still preserves the context somehow.
>>>
>>>
>>>
>>> Marcus Leech wrote:
>>> > On 02/28/2020 01:01 PM, Lukas Haase via USRP-users wrote:
>>> >> Hi again,
>>> >>
>>> >> I created a minimum example (gnuradio) that shows the issue described
>>> below.
>>> >> To summarize: Retuning to a different dsp frequency on an USRP X310
>>> (+UBX160) does not work (command ignored) ONLY if a timed command (in
>>> future is used).
>>> >> The code shows it in a simple manner. Commenting out the single line
>>> with set_command_time makes the example work.
>>> >>
>>> >> I am absolutely out of ideas and would appreciate any input!
>>> >>
>>> >> Best,
>>> >> Lukas
>>> > Lukas.
>>> >
>>> > Thanks for sticking with this.  I'll have a discussion with Ettus R&D
>>> to
>>> > see if this is a known issue and/or if there's a workaround.
>>> >
>>> > Remind me which version of UHD you're using?
>>>
>>>
>>>
>>> ___
>>> USRP-users mailing list
>>> USRP-users@lists.ettus.com
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>> ___
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>>
>
>
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Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-03 Thread Rob Kossler via USRP-users
Hi Lukas,
The FPGA image on the USRP is divided into blocks such as the DUC block and
the Radio block.  The latter controls the RF daughterboard and has access
to the device clock.  So, when you provide a timed command to the Radio
block (such as for tuning the RF) it can implement the command at the
specified time by comparing to the device clock.  The DUC block does not
have access to the MB clock and so when you give it a timed command, it
monitors the incoming sample stream to extract the time. If the sample
stream does not include a time stamp, the command never executes.  Don't
think of this as a bug, but rather as a design limitation.

When I work directly with UHD from C++, I use the function
rx_streamer::issue_stream_command() which has options to stream data with
no time stamp or with a time stamp.  When using timed commands with DUC or
DDC, I must include the time stamp or else the command will never be
executed.  But, with GR, I don't know how to specify the corresponding
options.
Rob

On Tue, Mar 3, 2020 at 12:29 PM Lukas Haase  wrote:

> Hi Sam, Hi Rob,
>
> Thanks for following up on this!
> I am very happy you were able to reproduce this ... which means that at
> least an issue exists :)
>
> What Sam suggests makes sense even though hard to believe for me:
>
> 1. How could something like that go unnoticed for so long? (I am sure I am
> not the first performing digital tuning)
> 2. In the past I got successful phase coherence using automatic tuning
> (passing center frequency + offset to tune_request_t and using integer-N
> tuning) using timed commands. This did not work reliably and only for
> certain frequencies but in my opinion this should have INCLUDED the DUC
> tuning. If the DUC retune wouldn't have been executed as part of this
> automatic tuning, I could not have gotten phase coherence (and actually,
> not even the desired frequency).
>
> The reason why I am only doing DUC tuning now is to avoid all the hassle
> with integer-N tuning, PLL retuning and settling time.
>
> Sam, what is the "radio block" you were talking about?
>
> Anyway, would it be worthwile to attempt debugging this is absence of gr?
> The only reason this prevented me from doing is that I would need to
> manually create the baseband samples and continuously stream them out while
> in parallel do the retuning.
> I am not too familiar with UHD on its own but I assume this would be very
> complicated, require multithreading etc.
> Do you have any demo code that could be easily modified for this scenario?
>
> Best,
> Lukas
>
>
> Gesendet: Dienstag, 03. März 2020 um 12:08 Uhr
> Von: "Sam Reiter" 
> An: "Rob Kossler" 
> Cc: "Lukas Haase" , "USRP-users@lists.ettus.com" <
> usrp-users@lists.ettus.com>
> Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using
> a timed command
>
> For what it's worth, I was able to reproduce the behavior described here,
> but didn't get to dig into it much. My leading suspicion would be what Rob
> mentioned about timestamping. Lukas' code sets a command time, but I'm not
> clear on how timestamp metadata for packets being sent to the radio are
> handled. Might be a good question to loop the discuss-gnuradio mailing list
> in on?
>
>
>
> Sam Reiter
>
> On Tue, Mar 3, 2020 at 10:59 AM Rob Kossler via USRP-users <
> usrp-users@lists.ettus.com[mailto:usrp-users@lists.ettus.com]> wrote:
> I wonder if the issue is related to a missing time stamp on the baseband
> samples going from GR to UHD.  If the stream does not have a time stamp,
> the DUC is unable to apply the timed command because the DUC does not
> really know the time - it must pull the time from the streaming samples.
> This is in contrast to the radio block which does have access to time and
> can apply timed commands by referring to the motherboard clock.
>
> I am not too familiar with GR so I'm not sure how to know if GR is putting
> a time stamp on the streaming samples.
> Rob
>
> On Mon, Mar 2, 2020 at 10:04 AM Lukas Haase via USRP-users <
> usrp-users@lists.ettus.com[mailto:usrp-users@lists.ettus.com]> wrote:Hi
> Marcus,
>
> Thank you that would be amazing!
>
> I followed the tutorial and built everything from source:
>
> $ lsb_release -a
> No LSB modules are available.
> Distributor ID: Ubuntu
> Description:Ubuntu 18.04.4 LTS
> Release:18.04
> Codename:   bionic
> $ uname -a
> Linux sdr 5.3.0-40-generic #32~18.04.1-Ubuntu SMP Mon Feb 3 14:05:59 UTC
> 2020 x86_64 x86_64 x86_64 GNU/Linux
> $ cd uhd
> $ git status
> HEAD detached at v3.15.0.0
> $ cd ../gnuradio
> $ git status
> HEAD detached at v3.7.14.0
>
>
> Than

Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-03 Thread Marcus D. Leech via USRP-users

On 03/03/2020 12:08 PM, Sam Reiter via USRP-users wrote:
For what it's worth, I was able to reproduce the behavior described 
here, but didn't get to dig into it much. My leading suspicion would 
be what Rob mentioned about timestamping. Lukas' code sets a command 
time, but I'm not clear on how timestamp metadata for packets being 
sent to the radio are handled. Might be a good question to loop the 
discuss-gnuradio mailing list in on?


Sam Reiter
Timed commands, I thought, were ALWAYS referred to the motherboard 
clock, without regard to timestamps in the stream?





On Tue, Mar 3, 2020 at 10:59 AM Rob Kossler via USRP-users 
mailto:usrp-users@lists.ettus.com>> wrote:


I wonder if the issue is related to a missing time stamp on the
baseband samples going from GR to UHD.  If the stream does not
have a time stamp, the DUC is unable to apply the timed command
because the DUC does not really know the time - it must pull the
time from the streaming samples. This is in contrast to the radio
block which does have access to time and can apply timed commands
by referring to the motherboard clock.

I am not too familiar with GR so I'm not sure how to know if GR is
putting a time stamp on the streaming samples.
Rob

On Mon, Mar 2, 2020 at 10:04 AM Lukas Haase via USRP-users
mailto:usrp-users@lists.ettus.com>>
wrote:

Hi Marcus,

Thank you that would be amazing!

I followed the tutorial and built everything from source:

$ lsb_release -a
No LSB modules are available.
Distributor ID: Ubuntu
Description:Ubuntu 18.04.4 LTS
Release:18.04
Codename:   bionic
$ uname -a
Linux sdr 5.3.0-40-generic #32~18.04.1-Ubuntu SMP Mon Feb 3
14:05:59 UTC 2020 x86_64 x86_64 x86_64 GNU/Linux
$ cd uhd
$ git status
HEAD detached at v3.15.0.0
$ cd ../gnuradio
$ git status
HEAD detached at v3.7.14.0


Thank you!

Lukas



PS: For some reason I sometimes do not get responses from this
list. I just saw it looking at the mailman archives. Hence I
cannot respond (to keep headers intact) but need to create a
new message and manually "quote". I hope that still preserves
the context somehow.



Marcus Leech wrote:
> On 02/28/2020 01:01 PM, Lukas Haase via USRP-users wrote:
>> Hi again,
>>
>> I created a minimum example (gnuradio) that shows the issue
described below.
>> To summarize: Retuning to a different dsp frequency on an
USRP X310 (+UBX160) does not work (command ignored) ONLY if a
timed command (in future is used).
>> The code shows it in a simple manner. Commenting out the
single line with set_command_time makes the example work.
>>
>> I am absolutely out of ideas and would appreciate any input!
>>
>> Best,
>> Lukas
> Lukas.
>
> Thanks for sticking with this.  I'll have a discussion with
Ettus R&D to
> see if this is a known issue and/or if there's a workaround.
>
> Remind me which version of UHD you're using?



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Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-03 Thread Lukas Haase via USRP-users
Hi Sam, Hi Rob, 

Thanks for following up on this!
I am very happy you were able to reproduce this ... which means that at least 
an issue exists :)

What Sam suggests makes sense even though hard to believe for me:

1. How could something like that go unnoticed for so long? (I am sure I am not 
the first performing digital tuning)
2. In the past I got successful phase coherence using automatic tuning (passing 
center frequency + offset to tune_request_t and using integer-N tuning) using 
timed commands. This did not work reliably and only for certain frequencies but 
in my opinion this should have INCLUDED the DUC tuning. If the DUC retune 
wouldn't have been executed as part of this automatic tuning, I could not have 
gotten phase coherence (and actually, not even the desired frequency).

The reason why I am only doing DUC tuning now is to avoid all the hassle with 
integer-N tuning, PLL retuning and settling time.

Sam, what is the "radio block" you were talking about?

Anyway, would it be worthwile to attempt debugging this is absence of gr?
The only reason this prevented me from doing is that I would need to manually 
create the baseband samples and continuously stream them out while in parallel 
do the retuning.
I am not too familiar with UHD on its own but I assume this would be very 
complicated, require multithreading etc.
Do you have any demo code that could be easily modified for this scenario?

Best,
Lukas


Gesendet: Dienstag, 03. März 2020 um 12:08 Uhr
Von: "Sam Reiter" 
An: "Rob Kossler" 
Cc: "Lukas Haase" , "USRP-users@lists.ettus.com" 

Betreff: Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a 
timed command

For what it's worth, I was able to reproduce the behavior described here, but 
didn't get to dig into it much. My leading suspicion would be what Rob 
mentioned about timestamping. Lukas' code sets a command time, but I'm not 
clear on how timestamp metadata for packets being sent to the radio are 
handled. Might be a good question to loop the discuss-gnuradio mailing list in 
on?

 

Sam Reiter  

On Tue, Mar 3, 2020 at 10:59 AM Rob Kossler via USRP-users 
mailto:usrp-users@lists.ettus.com]> wrote:
I wonder if the issue is related to a missing time stamp on the baseband 
samples going from GR to UHD.  If the stream does not have a time stamp, the 
DUC is unable to apply the timed command because the DUC does not really know 
the time - it must pull the time from the streaming samples. This is in 
contrast to the radio block which does have access to time and can apply timed 
commands by referring to the motherboard clock.
 
I am not too familiar with GR so I'm not sure how to know if GR is putting a 
time stamp on the streaming samples.
Rob 

On Mon, Mar 2, 2020 at 10:04 AM Lukas Haase via USRP-users 
mailto:usrp-users@lists.ettus.com]> wrote:Hi Marcus,

Thank you that would be amazing!

I followed the tutorial and built everything from source:

$ lsb_release -a
No LSB modules are available.
Distributor ID: Ubuntu
Description:    Ubuntu 18.04.4 LTS
Release:        18.04
Codename:       bionic
$ uname -a
Linux sdr 5.3.0-40-generic #32~18.04.1-Ubuntu SMP Mon Feb 3 14:05:59 UTC 2020 
x86_64 x86_64 x86_64 GNU/Linux
$ cd uhd
$ git status
HEAD detached at v3.15.0.0
$ cd ../gnuradio
$ git status
HEAD detached at v3.7.14.0


Thank you!

Lukas



PS: For some reason I sometimes do not get responses from this list. I just saw 
it looking at the mailman archives. Hence I cannot respond (to keep headers 
intact) but need to create a new message and manually "quote". I hope that 
still preserves the context somehow.



Marcus Leech wrote:
> On 02/28/2020 01:01 PM, Lukas Haase via USRP-users wrote:
>> Hi again,
>>
>> I created a minimum example (gnuradio) that shows the issue described below.
>> To summarize: Retuning to a different dsp frequency on an USRP X310 
>> (+UBX160) does not work (command ignored) ONLY if a timed command (in future 
>> is used).
>> The code shows it in a simple manner. Commenting out the single line with 
>> set_command_time makes the example work.
>>
>> I am absolutely out of ideas and would appreciate any input!
>>
>> Best,
>> Lukas
> Lukas.
>
> Thanks for sticking with this.  I'll have a discussion with Ettus R&D to
> see if this is a known issue and/or if there's a workaround.
>
> Remind me which version of UHD you're using?



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Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-03 Thread Sam Reiter via USRP-users
For what it's worth, I was able to reproduce the behavior described here,
but didn't get to dig into it much. My leading suspicion would be what Rob
mentioned about timestamping. Lukas' code sets a command time, but I'm not
clear on how timestamp metadata for packets being sent to the radio are
handled. Might be a good question to loop the discuss-gnuradio mailing list
in on?

Sam Reiter

On Tue, Mar 3, 2020 at 10:59 AM Rob Kossler via USRP-users <
usrp-users@lists.ettus.com> wrote:

> I wonder if the issue is related to a missing time stamp on the baseband
> samples going from GR to UHD.  If the stream does not have a time stamp,
> the DUC is unable to apply the timed command because the DUC does not
> really know the time - it must pull the time from the streaming samples.
> This is in contrast to the radio block which does have access to time and
> can apply timed commands by referring to the motherboard clock.
>
> I am not too familiar with GR so I'm not sure how to know if GR is putting
> a time stamp on the streaming samples.
> Rob
>
> On Mon, Mar 2, 2020 at 10:04 AM Lukas Haase via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hi Marcus,
>>
>> Thank you that would be amazing!
>>
>> I followed the tutorial and built everything from source:
>>
>> $ lsb_release -a
>> No LSB modules are available.
>> Distributor ID: Ubuntu
>> Description:Ubuntu 18.04.4 LTS
>> Release:18.04
>> Codename:   bionic
>> $ uname -a
>> Linux sdr 5.3.0-40-generic #32~18.04.1-Ubuntu SMP Mon Feb 3 14:05:59 UTC
>> 2020 x86_64 x86_64 x86_64 GNU/Linux
>> $ cd uhd
>> $ git status
>> HEAD detached at v3.15.0.0
>> $ cd ../gnuradio
>> $ git status
>> HEAD detached at v3.7.14.0
>>
>>
>> Thank you!
>>
>> Lukas
>>
>>
>>
>> PS: For some reason I sometimes do not get responses from this list. I
>> just saw it looking at the mailman archives. Hence I cannot respond (to
>> keep headers intact) but need to create a new message and manually "quote".
>> I hope that still preserves the context somehow.
>>
>>
>>
>> Marcus Leech wrote:
>> > On 02/28/2020 01:01 PM, Lukas Haase via USRP-users wrote:
>> >> Hi again,
>> >>
>> >> I created a minimum example (gnuradio) that shows the issue described
>> below.
>> >> To summarize: Retuning to a different dsp frequency on an USRP X310
>> (+UBX160) does not work (command ignored) ONLY if a timed command (in
>> future is used).
>> >> The code shows it in a simple manner. Commenting out the single line
>> with set_command_time makes the example work.
>> >>
>> >> I am absolutely out of ideas and would appreciate any input!
>> >>
>> >> Best,
>> >> Lukas
>> > Lukas.
>> >
>> > Thanks for sticking with this.  I'll have a discussion with Ettus R&D to
>> > see if this is a known issue and/or if there's a workaround.
>> >
>> > Remind me which version of UHD you're using?
>>
>>
>>
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>>
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Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-03 Thread Rob Kossler via USRP-users
I wonder if the issue is related to a missing time stamp on the baseband
samples going from GR to UHD.  If the stream does not have a time stamp,
the DUC is unable to apply the timed command because the DUC does not
really know the time - it must pull the time from the streaming samples.
This is in contrast to the radio block which does have access to time and
can apply timed commands by referring to the motherboard clock.

I am not too familiar with GR so I'm not sure how to know if GR is putting
a time stamp on the streaming samples.
Rob

On Mon, Mar 2, 2020 at 10:04 AM Lukas Haase via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hi Marcus,
>
> Thank you that would be amazing!
>
> I followed the tutorial and built everything from source:
>
> $ lsb_release -a
> No LSB modules are available.
> Distributor ID: Ubuntu
> Description:Ubuntu 18.04.4 LTS
> Release:18.04
> Codename:   bionic
> $ uname -a
> Linux sdr 5.3.0-40-generic #32~18.04.1-Ubuntu SMP Mon Feb 3 14:05:59 UTC
> 2020 x86_64 x86_64 x86_64 GNU/Linux
> $ cd uhd
> $ git status
> HEAD detached at v3.15.0.0
> $ cd ../gnuradio
> $ git status
> HEAD detached at v3.7.14.0
>
>
> Thank you!
>
> Lukas
>
>
>
> PS: For some reason I sometimes do not get responses from this list. I
> just saw it looking at the mailman archives. Hence I cannot respond (to
> keep headers intact) but need to create a new message and manually "quote".
> I hope that still preserves the context somehow.
>
>
>
> Marcus Leech wrote:
> > On 02/28/2020 01:01 PM, Lukas Haase via USRP-users wrote:
> >> Hi again,
> >>
> >> I created a minimum example (gnuradio) that shows the issue described
> below.
> >> To summarize: Retuning to a different dsp frequency on an USRP X310
> (+UBX160) does not work (command ignored) ONLY if a timed command (in
> future is used).
> >> The code shows it in a simple manner. Commenting out the single line
> with set_command_time makes the example work.
> >>
> >> I am absolutely out of ideas and would appreciate any input!
> >>
> >> Best,
> >> Lukas
> > Lukas.
> >
> > Thanks for sticking with this.  I'll have a discussion with Ettus R&D to
> > see if this is a known issue and/or if there's a workaround.
> >
> > Remind me which version of UHD you're using?
>
>
>
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Re: [USRP-users] USRP X310 over PCIe: Recommended setup? (Windows, Linux, which one?)

2020-03-02 Thread Neel Pandeya via USRP-users
Hello Lukas:

Yes, I would recommend using the Intel X710-DA2.  It should work solidly
out-of-the-box with Ubuntu 18.04.4 and 19.10.

You will need SFP+ modules, and the 10Gtek module in your Amazon.com link
should work, although we have never tested that specific module before.  We
have successfully used other 10Gtek modules before, but I do not recall
which specific model.  I can dig up this information later, if you need it.

I would suggest using a cable that already has SFP terminations [1,2,3].

Please let me know if you have any further questions.

[1] https://www.ettus.com/all-products/10gige-dc/

[2] https://www.ettus.com/all-products/10gige-1m/

[3] https://www.ettus.com/all-products/10gige-3m/

--Neel Pandeya



On Mon, 2 Mar 2020 at 10:24, Lukas Haase  wrote:

> Hi Neel,
>
> Thank you!
>
> I think moving forward this might be a better solution. Since I have no
> experience with it:
>
> 1. I'll just go with your Intel X710-DA2 recommendation (
> https://www.amazon.com/Intel-Ethernet-Converged-X710-DA2-X710DA2/dp/B00NJ3ZC26)
> but I think I need some SFP+ module, right?
>
> 2. Does it matter which SFP+ module I use? Any recommendation? What about
> this one?
> https://www.amazon.com/10Gtek-SFP-10G-T-S-Compatible-10GBase-T-Transceiver/dp/B01KFBFL16
>
> 3. Would you even recommend using glass fibre instead of copper?
>
> Thanks,
> Luke
>
>
> PS: As a first step I am trying Wheberth's auggestion right now but my
> experience with NI RIO on Windows was very poor so I want to opt for 10Gbe
> in the long run
>
>
>
>
>
> Gesendet: Montag, 24. Februar 2020 um 13:47 Uhr
> Von: "Neel Pandeya" 
> An: "Lukas Haase" 
> Cc: "Ettus Mail List" 
> Betreff: Re: [USRP-users] USRP X310 over PCIe: Recommended setup?
> (Windows, Linux, which one?)
>
> Hello Lukas:
>
> Do you have the option of using 10 Gbps Ethernet?
>
> It will provide you the equivalent performance on the X300/X310 as the
> PCIe interface.
>
> The Intel X710-DA2 network card works very well out-of-the-box with Ubuntu
> 18.04 and 19.10.
>
> Most people using Linux and GNU Radio with the X300/X310 use Ethernet,
> instead of PCIe.
>
> --Neel Pandeya
>
>
>
> On Mon, 24 Feb 2020 at 12:38, Robin Coxe via USRP-users <
> usrp-users@lists.ettus.com[mailto:usrp-users@lists.ettus.com]> wrote:
> Hi Lukas.   Most USRP X310 Linux users employ 10gigE to connect to the
> host PC.  PCIe on the USRP X310 uses a proprietary ASIC and the driver is,
> as you discovered, built on an obsolete kernel.  You could attempt to
> appeal directly to NI for support if switching to 10 gigE isn't an option
> for you.
>
> -Robin
>
>
> On Mon, Feb 24, 2020 at 10:23 AM Lukas Haase via USRP-users <
> usrp-users@lists.ettus.com[mailto:usrp-users@lists.ettus.com]> wrote:Hi,
>
> I have used USRP X310 over PCIe and gnuradio on Windows for quite a bit. I
> suffered from large connectivity issues so I wanted to switch to Linux for
> quite some time. Also, I need to start modifying gnuradio/uhd source which
> is even more painful in Windows.
>
> I set up an Ubuntu 18.04 system (which is not exactly new) and in the last
> step Linux NI RIO Installation fails. And
> https://files.ettus.com/manual/page_ni_rio_kernel.html[https://files.ettus.com/manual/page_ni_rio_kernel.html]
> states: "Currently, the latest supported kernel version is 4.2.x.". What a
> bummer!
>
> Is there any way to get USRP X310 + PCIe working on Ubuntu 18.04?
> If not, what is the recommended setup when someone needs PCIe, gnuradio,
> source code?
> I would really prefer a Debian-like Linux system that's not completely
> outdated (such as pre-bionic).
>
> Best,
> Lukas
>
>
> PS:
>
> $ lsb_release -a
> No LSB modules are available.
> Distributor ID: Ubuntu
> Description:Ubuntu 18.04.4 LTS
> Release:18.04
> Codename:   bionic
> $ uname -a
> Linux station 5.3.0-40-generic #32~18.04.1-Ubuntu SMP Mon Feb 3 14:05:59
> UTC 2020 x86_64 x86_64 x86_64 GNU/Linux
>
>
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Re: [USRP-users] USRP X310 over PCIe: Recommended setup? (Windows, Linux, which one?)

2020-03-02 Thread Lukas Haase via USRP-users
Hi Neel,

Thank you!

I think moving forward this might be a better solution. Since I have no 
experience with it:

1. I'll just go with your Intel X710-DA2 recommendation 
(https://www.amazon.com/Intel-Ethernet-Converged-X710-DA2-X710DA2/dp/B00NJ3ZC26)
 but I think I need some SFP+ module, right?

2. Does it matter which SFP+ module I use? Any recommendation? What about this 
one? 
https://www.amazon.com/10Gtek-SFP-10G-T-S-Compatible-10GBase-T-Transceiver/dp/B01KFBFL16

3. Would you even recommend using glass fibre instead of copper?

Thanks,
Luke


PS: As a first step I am trying Wheberth's auggestion right now but my 
experience with NI RIO on Windows was very poor so I want to opt for 10Gbe in 
the long run

 
 
 

Gesendet: Montag, 24. Februar 2020 um 13:47 Uhr
Von: "Neel Pandeya" 
An: "Lukas Haase" 
Cc: "Ettus Mail List" 
Betreff: Re: [USRP-users] USRP X310 over PCIe: Recommended setup? (Windows, 
Linux, which one?)

Hello Lukas:
 
Do you have the option of using 10 Gbps Ethernet?
 
It will provide you the equivalent performance on the X300/X310 as the PCIe 
interface.
 
The Intel X710-DA2 network card works very well out-of-the-box with Ubuntu 
18.04 and 19.10.
 
Most people using Linux and GNU Radio with the X300/X310 use Ethernet, instead 
of PCIe.
 
--Neel Pandeya
 
  

On Mon, 24 Feb 2020 at 12:38, Robin Coxe via USRP-users 
mailto:usrp-users@lists.ettus.com]> wrote:
Hi Lukas.   Most USRP X310 Linux users employ 10gigE to connect to the host PC. 
 PCIe on the USRP X310 uses a proprietary ASIC and the driver is, as you 
discovered, built on an obsolete kernel.  You could attempt to appeal directly 
to NI for support if switching to 10 gigE isn't an option for you.
 
-Robin
  

On Mon, Feb 24, 2020 at 10:23 AM Lukas Haase via USRP-users 
mailto:usrp-users@lists.ettus.com]> wrote:Hi,

I have used USRP X310 over PCIe and gnuradio on Windows for quite a bit. I 
suffered from large connectivity issues so I wanted to switch to Linux for 
quite some time. Also, I need to start modifying gnuradio/uhd source which is 
even more painful in Windows.

I set up an Ubuntu 18.04 system (which is not exactly new) and in the last step 
Linux NI RIO Installation fails. And 
https://files.ettus.com/manual/page_ni_rio_kernel.html[https://files.ettus.com/manual/page_ni_rio_kernel.html]
 states: "Currently, the latest supported kernel version is 4.2.x.". What a 
bummer!

Is there any way to get USRP X310 + PCIe working on Ubuntu 18.04?
If not, what is the recommended setup when someone needs PCIe, gnuradio, source 
code?
I would really prefer a Debian-like Linux system that's not completely outdated 
(such as pre-bionic).

Best,
Lukas


PS:

$ lsb_release -a
No LSB modules are available.
Distributor ID: Ubuntu
Description:    Ubuntu 18.04.4 LTS
Release:        18.04
Codename:       bionic
$ uname -a
Linux station 5.3.0-40-generic #32~18.04.1-Ubuntu SMP Mon Feb 3 14:05:59 UTC 
2020 x86_64 x86_64 x86_64 GNU/Linux


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Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-03-02 Thread Lukas Haase via USRP-users
Hi Marcus,

Thank you that would be amazing!

I followed the tutorial and built everything from source:

$ lsb_release -a
No LSB modules are available.
Distributor ID: Ubuntu
Description:Ubuntu 18.04.4 LTS
Release:18.04
Codename:   bionic
$ uname -a
Linux sdr 5.3.0-40-generic #32~18.04.1-Ubuntu SMP Mon Feb 3 14:05:59 UTC 2020 
x86_64 x86_64 x86_64 GNU/Linux
$ cd uhd
$ git status
HEAD detached at v3.15.0.0
$ cd ../gnuradio
$ git status
HEAD detached at v3.7.14.0


Thank you!

Lukas



PS: For some reason I sometimes do not get responses from this list. I just saw 
it looking at the mailman archives. Hence I cannot respond (to keep headers 
intact) but need to create a new message and manually "quote". I hope that 
still preserves the context somehow.



Marcus Leech wrote:
> On 02/28/2020 01:01 PM, Lukas Haase via USRP-users wrote:
>> Hi again,
>>
>> I created a minimum example (gnuradio) that shows the issue described below.
>> To summarize: Retuning to a different dsp frequency on an USRP X310 
>> (+UBX160) does not work (command ignored) ONLY if a timed command (in future 
>> is used).
>> The code shows it in a simple manner. Commenting out the single line with 
>> set_command_time makes the example work.
>>
>> I am absolutely out of ideas and would appreciate any input!
>>
>> Best,
>> Lukas
> Lukas.
>
> Thanks for sticking with this.  I'll have a discussion with Ettus R&D to
> see if this is a known issue and/or if there's a workaround.
>
> Remind me which version of UHD you're using?



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Re: [USRP-users] USRP X310 ignored DSP retuning on TX when using a timed command

2020-02-28 Thread Marcus D. Leech via USRP-users

On 02/28/2020 01:01 PM, Lukas Haase via USRP-users wrote:

Hi again,

I created a minimum example (gnuradio) that shows the issue described below.
To summarize: Retuning to a different dsp frequency on an USRP X310 (+UBX160) 
does not work (command ignored) ONLY if a timed command (in future is used).
The code shows it in a simple manner. Commenting out the single line with 
set_command_time makes the example work.

I am absolutely out of ideas and would appreciate any input!

Best,
Lukas

Lukas.

Thanks for sticking with this.  I'll have a discussion with Ettus R&D to 
see if this is a known issue and/or if there's a workaround.


Remind me which version of UHD you're using?




#!/usr/bin/env python2
# -*- coding: utf-8 -*-

from gnuradio import analog
from gnuradio import gr
from gnuradio import uhd
import threading
import time

class switch_on_click_debug_tx_retune(gr.top_block):

 def __init__(self):
 gr.top_block.__init__(self, "Switch On Click Debug Tx Retune")
 self.variable_function_probe_0 = variable_function_probe_0 = 0
 self.samp_rate = samp_rate = 5e6
 self.uhd_usrp_sink_0 = uhd.usrp_sink(",".join(("", "dboard_clock_rate=20e6")), 
uhd.stream_args(cpu_format="fc32", channels=range(1)))
 self.uhd_usrp_sink_0.set_clock_rate(200e6, uhd.ALL_MBOARDS)
 self.uhd_usrp_sink_0.set_clock_source('internal', 0)
 self.uhd_usrp_sink_0.set_samp_rate(samp_rate)
 self.uhd_usrp_sink_0.set_center_freq(900e6, 0)
 self.uhd_usrp_sink_0.set_gain(0, 0)

 def _hopper():
 i = 0
 while True:
 if i % 2 == 0:
fdsp = 0
 else:
fdsp = -2e6
 print("Change TX dsp_freq=" + str(fdsp))
 tune_req_tx = uhd.tune_request()
 tune_req_tx.rf_freq_policy = uhd.tune_request.POLICY_NONE
 tune_req_tx.dsp_freq_policy = uhd.tune_request.POLICY_MANUAL
 tune_req_tx.rf_freq = 900e6
 tune_req_tx.dsp_freq = fdsp

 now = self.uhd_usrp_sink_0.get_time_now()
 # *** HOPPING WORKS IF THE NEXT LINE IS COMMENTED *** !!!
 self.uhd_usrp_sink_0.set_command_time(now + uhd.time_spec(0.1))
 res1 = self.uhd_usrp_sink_0.set_center_freq(  tune_req_tx, 0)
 self.uhd_usrp_sink_0.clear_command_time()

 i = i + 1
 time.sleep(4.0)
 _hopper_thread = threading.Thread(target=_hopper)
 _hopper_thread.daemon = True
 _hopper_thread.start()

 self.analog_sig_source_x_1 = analog.sig_source_c(samp_rate, 
analog.GR_COS_WAVE, 1e6, 1, 0)
 self.connect((self.analog_sig_source_x_1, 0), (self.uhd_usrp_sink_0, 
0))

 def get_samp_rate(self):
 return self.samp_rate

 def set_samp_rate(self, samp_rate):
 self.samp_rate = samp_rate
 self.uhd_usrp_sink_0.set_samp_rate(self.samp_rate)
 self.analog_sig_source_x_1.set_sampling_freq(self.samp_rate)

def main(top_block_cls=switch_on_click_debug_tx_retune, options=None):

 tb = top_block_cls()
 tb.start()
 try:
 raw_input('Press Enter to quit: ')
 except EOFError:
 pass
 tb.stop()
 tb.wait()


if __name__ == '__main__':
 main()




PS: I look at the output on a spectrum analyzer and observe how the frequency 
changes.



















Gesendet: Donnerstag, 27. Februar 2020 um 19:30 Uhr
Von: "Lukas Haase" 
An: "USRP-users@lists.ettus.com" 
Betreff: Re: How do timed commands work for two blocks (USRP Sink+USRP Source)?

A quick update which may make things easier to debug: I am observing TX/RX on a 
spectrum analyzer and see if the frequency changes.
As soon as I enable timed command, the tune command is ignored!

For simplicity, I am completely removing the RX parts (uhd_usrp_source_0).

Now this works:

tune_req_tx = uhd.tune_request()
tune_req_tx.rf_freq_policy = uhd.tune_request.POLICY_MANUAL
tune_req_tx.dsp_freq_policy = uhd.tune_request.POLICY_MANUAL
tune_req_tx.rf_freq = 900e6
tune_req_tx.dsp_freq = -2e6

now = usrp_sink.get_time_now()
#usrp_sink.set_command_time(now + uhd.time_spec(1))
res1 = usrp_sink.set_center_freq(  tune_req_tx, 0)
usrp_sink.clear_command_time()

When this code is executed, the signal jumps by 2 MHz at the spectrum analyzer.

Now I only uncomment set_timed_command above:

usrp_sink.set_command_time(now + uhd.time_spec(1))

and repeat. NO frequency change any more!

That means as soon as I use timed command (set_command_time) for changing the 
DSP frequency on a TX it is just IGNORED!

This must be a bug ... or do I really do something fundamentally wrong?


USRP X310 with 2xUBX-160. TX/RX from dautherboard 1 is connected to spectrum 
analyzer.


Thank you!
Lukas



Lukas Haase wrote:

How do these timed commands work exactly when using USRP Source together with 
USRP Sink? (I need to phase-align RX and TX hence use

Re: [USRP-users] USRP X310 over PCIe: Recommended setup? (Windows, Linux, which one?)

2020-02-25 Thread Wheberth Damascena Dias via USRP-users
Hi Lukas, I use pretty much this setup (Ubuntu 18 + X310 over PCIe).

You can install kernel 4.15.0 from ubuntu repository and reinstall the
driver. It work just fine. You may also need to download some RFNoC XML
files that are missing on Ubuntu repositories (see:
https://bugs.launchpad.net/ubuntu/+source/uhd/+bug/1780805).

Make sure to configure the PCIe slot to PCIe Gen 1 on the bios.

Regards,
Wheberth

Em seg, 24 de fev de 2020 15:23, Lukas Haase via USRP-users <
usrp-users@lists.ettus.com> escreveu:

> Hi,
>
> I have used USRP X310 over PCIe and gnuradio on Windows for quite a bit. I
> suffered from large connectivity issues so I wanted to switch to Linux for
> quite some time. Also, I need to start modifying gnuradio/uhd source which
> is even more painful in Windows.
>
> I set up an Ubuntu 18.04 system (which is not exactly new) and in the last
> step Linux NI RIO Installation fails. And
> https://files.ettus.com/manual/page_ni_rio_kernel.html states:
> "Currently, the latest supported kernel version is 4.2.x.". What a bummer!
>
> Is there any way to get USRP X310 + PCIe working on Ubuntu 18.04?
> If not, what is the recommended setup when someone needs PCIe, gnuradio,
> source code?
> I would really prefer a Debian-like Linux system that's not completely
> outdated (such as pre-bionic).
>
> Best,
> Lukas
>
>
> PS:
>
> $ lsb_release -a
> No LSB modules are available.
> Distributor ID: Ubuntu
> Description:Ubuntu 18.04.4 LTS
> Release:18.04
> Codename:   bionic
> $ uname -a
> Linux station 5.3.0-40-generic #32~18.04.1-Ubuntu SMP Mon Feb 3 14:05:59
> UTC 2020 x86_64 x86_64 x86_64 GNU/Linux
>
>
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Re: [USRP-users] USRP X310 over PCIe: Recommended setup? (Windows, Linux, which one?)

2020-02-24 Thread Neel Pandeya via USRP-users
Hello Lukas:

Do you have the option of using 10 Gbps Ethernet?

It will provide you the equivalent performance on the X300/X310 as the PCIe
interface.

The Intel X710-DA2 network card works very well out-of-the-box with Ubuntu
18.04 and 19.10.

Most people using Linux and GNU Radio with the X300/X310 use Ethernet,
instead of PCIe.

--Neel Pandeya



On Mon, 24 Feb 2020 at 12:38, Robin Coxe via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hi Lukas.   Most USRP X310 Linux users employ 10gigE to connect to the
> host PC.  PCIe on the USRP X310 uses a proprietary ASIC and the driver is,
> as you discovered, built on an obsolete kernel.  You could attempt to
> appeal directly to NI for support if switching to 10 gigE isn't an option
> for you.
>
> -Robin
>
>
> On Mon, Feb 24, 2020 at 10:23 AM Lukas Haase via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hi,
>>
>> I have used USRP X310 over PCIe and gnuradio on Windows for quite a bit.
>> I suffered from large connectivity issues so I wanted to switch to Linux
>> for quite some time. Also, I need to start modifying gnuradio/uhd source
>> which is even more painful in Windows.
>>
>> I set up an Ubuntu 18.04 system (which is not exactly new) and in the
>> last step Linux NI RIO Installation fails. And
>> https://files.ettus.com/manual/page_ni_rio_kernel.html states:
>> "Currently, the latest supported kernel version is 4.2.x.". What a bummer!
>>
>> Is there any way to get USRP X310 + PCIe working on Ubuntu 18.04?
>> If not, what is the recommended setup when someone needs PCIe, gnuradio,
>> source code?
>> I would really prefer a Debian-like Linux system that's not completely
>> outdated (such as pre-bionic).
>>
>> Best,
>> Lukas
>>
>>
>> PS:
>>
>> $ lsb_release -a
>> No LSB modules are available.
>> Distributor ID: Ubuntu
>> Description:Ubuntu 18.04.4 LTS
>> Release:18.04
>> Codename:   bionic
>> $ uname -a
>> Linux station 5.3.0-40-generic #32~18.04.1-Ubuntu SMP Mon Feb 3 14:05:59
>> UTC 2020 x86_64 x86_64 x86_64 GNU/Linux
>>
>>
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>>
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Re: [USRP-users] USRP X310 over PCIe: Recommended setup? (Windows, Linux, which one?)

2020-02-24 Thread Robin Coxe via USRP-users
Hi Lukas.   Most USRP X310 Linux users employ 10gigE to connect to the host
PC.  PCIe on the USRP X310 uses a proprietary ASIC and the driver is, as
you discovered, built on an obsolete kernel.  You could attempt to appeal
directly to NI for support if switching to 10 gigE isn't an option for you.

-Robin


On Mon, Feb 24, 2020 at 10:23 AM Lukas Haase via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hi,
>
> I have used USRP X310 over PCIe and gnuradio on Windows for quite a bit. I
> suffered from large connectivity issues so I wanted to switch to Linux for
> quite some time. Also, I need to start modifying gnuradio/uhd source which
> is even more painful in Windows.
>
> I set up an Ubuntu 18.04 system (which is not exactly new) and in the last
> step Linux NI RIO Installation fails. And
> https://files.ettus.com/manual/page_ni_rio_kernel.html states:
> "Currently, the latest supported kernel version is 4.2.x.". What a bummer!
>
> Is there any way to get USRP X310 + PCIe working on Ubuntu 18.04?
> If not, what is the recommended setup when someone needs PCIe, gnuradio,
> source code?
> I would really prefer a Debian-like Linux system that's not completely
> outdated (such as pre-bionic).
>
> Best,
> Lukas
>
>
> PS:
>
> $ lsb_release -a
> No LSB modules are available.
> Distributor ID: Ubuntu
> Description:Ubuntu 18.04.4 LTS
> Release:18.04
> Codename:   bionic
> $ uname -a
> Linux station 5.3.0-40-generic #32~18.04.1-Ubuntu SMP Mon Feb 3 14:05:59
> UTC 2020 x86_64 x86_64 x86_64 GNU/Linux
>
>
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>
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Re: [USRP-users] USRP X310 problem

2019-10-01 Thread Paolo Palana via USRP-users
Try the command.

dd if=.bit of=.bit count= count=1

and then try to configure the fpga .bit


On 27/09/19 16:12, Aaron Montilla via USRP-users wrote:
> Hi,
> I am trying to set the connection between my PC and my USRP X310.
> I ran the command uhd_find_devices, and successfully it found the
> USRP. Then I use the uhd_usrp_probe command and I had the next error:
> aaron@leonard:~$ uhd_usrp_probe
> [INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501;
> UHD_3.15.0.git-71-g18bc320d
> [INFO] [X300] X300 initialization sequence...
> [INFO] [X300] Maximum frame size: 1472 bytes.
> [INFO] [X300] Radio 1x clock: 200 MHz
> [INFO] [GPS] Found an internal GPSDO: LC_XO, Firmware Rev 0.929a
> [INFO] [0/DmaFIFO_0] Initializing block control (NOC ID:
> 0xF1F0D000)
> [ERROR] [0/DmaFIFO_0] Major compat number mismatch for noc_shell:
> Expecting 6, got 5.
> Error: RuntimeError: FPGA component `noc_shell' is revision 5 and UHD
> supports revision 6. Please either upgrade the FPGA image
> (recommended) or downgrade UHD.
>
> I thought that upgrade the USRP was the best option, but when I try, I
> have another error saying that the size of the image is too large (
> only for 1 byte). I also read that I had to use the .bin file but I
> didn't have any.
> So, could you please tell me what I could do?
>
> Thank you very much in advance.
> Kind regards,
> Aaron
>
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Re: [USRP-users] USRP X310 send period

2019-07-18 Thread Nate Temple via USRP-users
The RFNoC Replay block would be a good starting point, if you want to do
this all in the FPGA.

On Thu, Jul 18, 2019 at 2:04 PM Marcus Müller via USRP-users <
usrp-users@lists.ettus.com> wrote:

> At the very benign 20 MS/s, I'd really say your first option is the way
> to go. The rest probably won't work very well du to turn on/off
> behaviour requiring you to zero pad a bit to flush your TX data chains.
>
> You can of course also write an RFNoC block to store and generate data
> in-FPGA, but really: at 20MS/s just continously stream. Even a bog-
> normal Gigabit Ethernet card has plenty enough bandwidth to do that. I
> doubt sending a sequence from RAM will occupy much CPU on your host PC.
>
> Best regards,
> Marcus
>
> On Thu, 2019-07-18 at 22:58 +0200, Cédric Hannotier via USRP-users
> wrote:
> > Dear all,
> >
> > I would like to periodically send a frame with an USRP X310 (frame
> > length: 320 samples, rate: 20 MS/s, period: 1-500 ms). However, I
> > struggle to find the best way to implement it. What I have tried so
> > far:
> >
> >   1. Append zeros to the frame to reach the expected period.
> > However,
> > this consumes too much bandwidth due to the zeros.
> >
> >   2. Use tx_streamer->send() with a tx_metadata_t.time_spec and
> > tx_streamer->recv_async_msg(). Using that, only the frame is sent,
> > saving most of the bandwidth. However, with small periods, it tends
> > to
> > print some 'L'.
> >
> >   3. Buffer a batch of send request on the USRP, then wait a
> > specific
> > time (using eg. recv_async_msg() until the returned metadata
> > contains
> > the penultimate time_spec (I expect that the time_spec returned is
> > the
> > one specified in the send metadata)) and redo. The issue is that I
> > was
> > not able to find the buffer size (is it related to the
> > tx_streamer->get_max_num_samps()?). I would like to fill the buffer
> > without overflow.
> >
> > I was hoping that I could save the frame in an USRP's memory, and
> > then
> > ask it to periodically send the frame with a specific period. Is it
> > possible?
> >
> > Here is an example of (2):
> >
> > template 
> > void send_from_file(const uhd::usrp::multi_usrp::sptr &usrp,
> >  uhd::tx_streamer::sptr tx_stream, const
> > std::string&
> > file,
> >  const double period)
> > {
> > size_t data_size = get_file_size(file);
> > std::ifstream infile(file, std::ifstream::binary);
> > std::vector buff(data_size);
> > infile.read(reinterpret_cast(buff.data()),
> > (std::streamsize)(buff.size()*sizeof(samp_type)));
> > infile.close();
> > size_t num_tx_samps = buff.size();
> > std::cout << file << " " << buff[0] << " " << num_tx_samps <<
> > std::endl;
> >
> > uhd::tx_metadata_t md;
> > md.start_of_burst = true;
> > md.end_of_burst   = true;
> > md.has_time_spec  = true;
> > md.time_spec= usrp->get_time_last_pps()+5.;
> > double timeout = md.time_spec.get_real_secs();
> > uhd::async_metadata_t md_status;
> >
> > while (not stop_signal_called) {
> >   tx_stream->send(&buff.front(), num_tx_samps, md);
> >   if (tx_stream->recv_async_msg(md_status, timeout)) {
> >   if (md_status.event_code !=
> > uhd::async_metadata_t::event_code_t::EVENT_CODE_BURST_ACK) {
> >   std::cerr << "Error: " << md_status.event_code
> > << std::endl;
> >   exit(EXIT_FAILURE);
> >   }
> >   } else {
> >   std::cerr << "timeout before sent" << std::endl;
> >   exit(EXIT_FAILURE);
> >   }
> >
> >   timeout = 0.1;
> >   md.time_spec += period;
> > }
> > }
> >
> >
> >
> > Best Regards,
> > Cédric
> >
> > ___
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> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Re: [USRP-users] USRP X310 send period

2019-07-18 Thread Marcus Müller via USRP-users
At the very benign 20 MS/s, I'd really say your first option is the way
to go. The rest probably won't work very well du to turn on/off
behaviour requiring you to zero pad a bit to flush your TX data chains.

You can of course also write an RFNoC block to store and generate data
in-FPGA, but really: at 20MS/s just continously stream. Even a bog-
normal Gigabit Ethernet card has plenty enough bandwidth to do that. I
doubt sending a sequence from RAM will occupy much CPU on your host PC.

Best regards,
Marcus

On Thu, 2019-07-18 at 22:58 +0200, Cédric Hannotier via USRP-users
wrote:
> Dear all,
> 
> I would like to periodically send a frame with an USRP X310 (frame 
> length: 320 samples, rate: 20 MS/s, period: 1-500 ms). However, I 
> struggle to find the best way to implement it. What I have tried so
> far:
> 
>   1. Append zeros to the frame to reach the expected period.
> However, 
> this consumes too much bandwidth due to the zeros.
> 
>   2. Use tx_streamer->send() with a tx_metadata_t.time_spec and 
> tx_streamer->recv_async_msg(). Using that, only the frame is sent, 
> saving most of the bandwidth. However, with small periods, it tends
> to 
> print some 'L'.
> 
>   3. Buffer a batch of send request on the USRP, then wait a
> specific 
> time (using eg. recv_async_msg() until the returned metadata
> contains 
> the penultimate time_spec (I expect that the time_spec returned is
> the 
> one specified in the send metadata)) and redo. The issue is that I
> was 
> not able to find the buffer size (is it related to the 
> tx_streamer->get_max_num_samps()?). I would like to fill the buffer 
> without overflow.
> 
> I was hoping that I could save the frame in an USRP's memory, and
> then 
> ask it to periodically send the frame with a specific period. Is it 
> possible?
> 
> Here is an example of (2):
> 
> template 
> void send_from_file(const uhd::usrp::multi_usrp::sptr &usrp,
>  uhd::tx_streamer::sptr tx_stream, const
> std::string& 
> file,
>  const double period)
> {
> size_t data_size = get_file_size(file);
> std::ifstream infile(file, std::ifstream::binary);
> std::vector buff(data_size);
> infile.read(reinterpret_cast(buff.data()), 
> (std::streamsize)(buff.size()*sizeof(samp_type)));
> infile.close();
> size_t num_tx_samps = buff.size();
> std::cout << file << " " << buff[0] << " " << num_tx_samps <<
> std::endl;
> 
> uhd::tx_metadata_t md;
> md.start_of_burst = true;
> md.end_of_burst   = true;
> md.has_time_spec  = true;
> md.time_spec= usrp->get_time_last_pps()+5.;
> double timeout = md.time_spec.get_real_secs();
> uhd::async_metadata_t md_status;
> 
> while (not stop_signal_called) {
>   tx_stream->send(&buff.front(), num_tx_samps, md);
>   if (tx_stream->recv_async_msg(md_status, timeout)) {
>   if (md_status.event_code != 
> uhd::async_metadata_t::event_code_t::EVENT_CODE_BURST_ACK) {
>   std::cerr << "Error: " << md_status.event_code
> << std::endl;
>   exit(EXIT_FAILURE);
>   }
>   } else {
>   std::cerr << "timeout before sent" << std::endl;
>   exit(EXIT_FAILURE);
>   }
> 
>   timeout = 0.1;
>   md.time_spec += period;
> }
> }
> 
> 
> 
> Best Regards,
> Cédric
> 
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Re: [USRP-users] USRP X310 PCIe connection Driver Problem

2019-06-04 Thread akin soysal via USRP-users
Hi,

Thanks Nicole. We solved the problem by installing centos 7.0. It performs
a lot better with real time constraints.

Akın

4 Haz 2019 Sal 01:40 tarihinde Nicole Bienert  şunu yazdı:

> Hi,
>
> I was having the same problem, but I figured it out. Shut everything down,
> then turn on the SDR first and the computer second. Next type sudo
> /usr/local/bin/niusrprio_pcie *stop*. Do not type start before using the
> stop command. If you type start then later type stop, it still won't work.
> I'm guessing that the computer attempts to connect to the device over PCIe
> upon start up, but doesn't do so correctly, so you have to stop that
> process before doing anything else. Don't forget use the stop command when
> you are done with the USRP, before turning your computer off. Below are the
> commands, and after that is an instruction set for getting everything
> working from scratch.
>
> Here are the commands for what works:
> radioglaciology@radioglaciology-Precision-7730:~$ *sudo
> /usr/local/bin/niusrprio_pcie stop*
> [sudo] password for radioglaciology:
> Stopping: niusrpriorpc
> Unloading: niusrpriok NiRioSrv
>
> radioglaciology@radioglaciology-Precision-7730:~$ *sudo
> /usr/local/bin/niusrprio_pcie start*
> Making sure drivers are up to date...
> Module nikal is up-to-date
> Module nibds is up-to-date
> Module nistreamk is up-to-date
> Module NiRioSrv is up-to-date
> Module niusrpriok is up-to-date
> Loading: NiRioSrv niusrpriok
> Starting: niusrpriorpc
>
> radioglaciology@radioglaciology-Precision-7730:~$ *sudo
> /usr/local/bin/niusrprio_pcie status*
> Modules Loaded: nikal nibds nistreamk NiRioSrv niusrpriok
> Server: niusrpriorpc
>
> radioglaciology@radioglaciology-Precision-7730:~$ *uhd_find_devices*
> [INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501;
> UHD_3.14.1.HEAD-0-g5491b80e
> --
> -- UHD Device 0
> --
> Device Address:
> serial: 318EFCA
> fpga: HG
> name:
> product: X310
> resource: RIO0
> type: x300
>
>
> radioglaciology@radioglaciology-Precision-7730:~$ *uhd_usrp_probe*
> [INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501;
> UHD_3.14.1.HEAD-0-g5491b80e
> [INFO] [X300] X300 initialization sequence...
> [INFO] [X300] Connecting to niusrpriorpc at localhost:5444...
> [INFO] [X300] Using LVBITX bitfile /usr/local/share/uhd/images/
> usrp_x310_fpga_HG.lvbitx...
> [INFO] [X300] Radio 1x clock: 200 MHz
> [INFO] [GPS] Found an internal GPSDO: LC_XO, Firmware Rev 0.929b
> [INFO] [0/DmaFIFO_0] Initializing block control (NOC ID:
> 0xF1F0D000)
> [INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1296 MB/s)
> [INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1304 MB/s)
> [INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD1001)
> [INFO] [0/Radio_1] Initializing block control (NOC ID: 0x12AD1001)
> [INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0)
> [INFO] [0/DDC_1] Initializing block control (NOC ID: 0xDDC0)
> [INFO] [0/DUC_0] Initializing block control (NOC ID: 0xD0C0)
> [INFO] [0/DUC_1] Initializing block control (NOC ID: 0xD0C0)
>   _
>  /
> |   Device: X-Series Device
> | _
> |/
> |   |   Mboard: X310
> ** truncated output***
>
> Here's what was happening before when things weren't working:
> radioglaciology@radioglaciology-Precision-7730:~$ *uhd_find_devices*
> [INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501;
> UHD_3.14.1.HEAD-0-g5491b80e
> No UHD Devices Found
>
> radioglaciology@radioglaciology-Precision-7730:~$ *sudo
> /usr/local/bin/niusrprio_pcie start*
> Making sure drivers are up to date...
> Module nikal is up-to-date
> Module nibds is up-to-date
> Module nistreamk is up-to-date
> Module NiRioSrv is up-to-date
> Module niusrpriok is up-to-date
> Loading: NiRioSrv niusrpriok
> Starting: niusrpriorpc
>
> radioglaciology@radioglaciology-Precision-7730:~$* sudo
> /usr/local/bin/niusrprio_pcie status*
> Modules Loaded: nikal nibds nistreamk NiRioSrv niusrpriok
> Server: niusrpriorpc
>
> radioglaciology@radioglaciology-Precision-7730:~$ *uhd_find_devices*
> [INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501;
> UHD_3.14.1.HEAD-0-g5491b80e
> --
> -- UHD Device 0
> --
> Device Address:
> serial:
> fpga: HG
> name:
> product: X310
> resource: RIO0
> type: x300
>
> radioglaciology@radioglaciology-Precision-7730:~$ *uhd_usrp_probe
> --args="resource=RIO0"*
> [INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501;
> UHD_3.14.1.HEAD-0-g5491b80e
> [INFO] [X300] X300 initialization sequence...
> [INFO] [X300] Connecting to niusrpriorpc at localhost:5444...
> [INFO] [X300] Using LVBITX bitfile /usr/local/share/uhd/images/
> usrp_x310_fpga_

Re: [USRP-users] USRP X310 PCIe connection Driver Problem

2019-06-03 Thread Nicole Bienert via USRP-users
Hi,

I was having the same problem, but I figured it out. Shut everything down,
then turn on the SDR first and the computer second. Next type sudo
/usr/local/bin/niusrprio_pcie *stop*. Do not type start before using the
stop command. If you type start then later type stop, it still won't work.
I'm guessing that the computer attempts to connect to the device over PCIe
upon start up, but doesn't do so correctly, so you have to stop that
process before doing anything else. Don't forget use the stop command when
you are done with the USRP, before turning your computer off. Below are the
commands, and after that is an instruction set for getting everything
working from scratch.

Here are the commands for what works:
radioglaciology@radioglaciology-Precision-7730:~$ *sudo
/usr/local/bin/niusrprio_pcie stop*
[sudo] password for radioglaciology:
Stopping: niusrpriorpc
Unloading: niusrpriok NiRioSrv

radioglaciology@radioglaciology-Precision-7730:~$ *sudo
/usr/local/bin/niusrprio_pcie start*
Making sure drivers are up to date...
Module nikal is up-to-date
Module nibds is up-to-date
Module nistreamk is up-to-date
Module NiRioSrv is up-to-date
Module niusrpriok is up-to-date
Loading: NiRioSrv niusrpriok
Starting: niusrpriorpc

radioglaciology@radioglaciology-Precision-7730:~$ *sudo
/usr/local/bin/niusrprio_pcie status*
Modules Loaded: nikal nibds nistreamk NiRioSrv niusrpriok
Server: niusrpriorpc

radioglaciology@radioglaciology-Precision-7730:~$ *uhd_find_devices*
[INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501;
UHD_3.14.1.HEAD-0-g5491b80e
--
-- UHD Device 0
--
Device Address:
serial: 318EFCA
fpga: HG
name:
product: X310
resource: RIO0
type: x300


radioglaciology@radioglaciology-Precision-7730:~$ *uhd_usrp_probe*
[INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501;
UHD_3.14.1.HEAD-0-g5491b80e
[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Connecting to niusrpriorpc at localhost:5444...
[INFO] [X300] Using LVBITX bitfile /usr/local/share/uhd/images/
usrp_x310_fpga_HG.lvbitx...
[INFO] [X300] Radio 1x clock: 200 MHz
[INFO] [GPS] Found an internal GPSDO: LC_XO, Firmware Rev 0.929b
[INFO] [0/DmaFIFO_0] Initializing block control (NOC ID: 0xF1F0D000)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1296 MB/s)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1304 MB/s)
[INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD1001)
[INFO] [0/Radio_1] Initializing block control (NOC ID: 0x12AD1001)
[INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0)
[INFO] [0/DDC_1] Initializing block control (NOC ID: 0xDDC0)
[INFO] [0/DUC_0] Initializing block control (NOC ID: 0xD0C0)
[INFO] [0/DUC_1] Initializing block control (NOC ID: 0xD0C0)
  _
 /
|   Device: X-Series Device
| _
|/
|   |   Mboard: X310
** truncated output***

Here's what was happening before when things weren't working:
radioglaciology@radioglaciology-Precision-7730:~$ *uhd_find_devices*
[INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501;
UHD_3.14.1.HEAD-0-g5491b80e
No UHD Devices Found

radioglaciology@radioglaciology-Precision-7730:~$ *sudo
/usr/local/bin/niusrprio_pcie start*
Making sure drivers are up to date...
Module nikal is up-to-date
Module nibds is up-to-date
Module nistreamk is up-to-date
Module NiRioSrv is up-to-date
Module niusrpriok is up-to-date
Loading: NiRioSrv niusrpriok
Starting: niusrpriorpc

radioglaciology@radioglaciology-Precision-7730:~$* sudo
/usr/local/bin/niusrprio_pcie status*
Modules Loaded: nikal nibds nistreamk NiRioSrv niusrpriok
Server: niusrpriorpc

radioglaciology@radioglaciology-Precision-7730:~$ *uhd_find_devices*
[INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501;
UHD_3.14.1.HEAD-0-g5491b80e
--
-- UHD Device 0
--
Device Address:
serial:
fpga: HG
name:
product: X310
resource: RIO0
type: x300

radioglaciology@radioglaciology-Precision-7730:~$ *uhd_usrp_probe
--args="resource=RIO0"*
[INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501;
UHD_3.14.1.HEAD-0-g5491b80e
[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Connecting to niusrpriorpc at localhost:5444...
[INFO] [X300] Using LVBITX bitfile /usr/local/share/uhd/images/
usrp_x310_fpga_HG.lvbitx...
Error: RuntimeError: x300_impl: Could not initialize RIO session. Unknown
error. (Error code -63150)


For anyone who navigates to this thread, here are full instructions for
setting up your computer and connecting to the USRP X310 from scratch on
Ubuntu:


   1.

   Follow the instructions here to download uhd, fpga images, and gnuradio.
   Follow all the instructions, and install everything.
   


Re: [USRP-users] USRP X310 PCIe connection Driver Problem

2019-03-05 Thread akin soysal via USRP-users
OK, so I did manage to debug it further by setting the
ENABLE_EXTENDED_ERROR_INFO flag to true. It seems like the
nirio_driver_iface::rio_ioctl function is returning 52003 error.

uhd_usrp_probe --args "type=x300,resource=RIO0,fpga=HG"
[INFO] [UHD] linux; GNU C++ version 5.4.0 20160609; Boost_105800;
UHD_3.13.1.HEAD-0-gbbce3e45
[INFO] [NIRIO] rpc_client stopping...
[INFO] [NIRIO] rpc_client stopped.
ERROR: The following function call returned status code -52003
nirio_driver_iface::rio_ioctl(_device_handle, NIRIO_IOCTL_POST_OPEN, NULL,
0, NULL, 0)
/home/ulak/uhd/uhd/host/lib/transport/nirio/niriok_proxy_impl_v1.cpp:438
[INFO] [NIRIO] rpc_client stopping...
[INFO] [NIRIO] rpc_client stopped.
ERROR: The following function call returned status code -52003
nirio_driver_iface::rio_ioctl(_device_handle, NIRIO_IOCTL_POST_OPEN, NULL,
0, NULL, 0)
/home/ulak/uhd/uhd/host/lib/transport/nirio/niriok_proxy_impl_v1.cpp:438
[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Connecting to niusrpriorpc at localhost:5444...
ERROR: The following function call returned status code -52003
nirio_driver_iface::rio_ioctl(_device_handle, NIRIO_IOCTL_POST_OPEN, NULL,
0, NULL, 0)
/home/ulak/uhd/uhd/host/lib/transport/nirio/niriok_proxy_impl_v1.cpp:438
[INFO] [NIRIO] rpc_client stopping...
[INFO] [NIRIO] rpc_client stopped.
[INFO] [X300] Using LVBITX bitfile /home/ulak/usrp_x310_fpga_HG.lvbitx...
ERROR: The following function call returned status code -52003
nirio_driver_iface::rio_ioctl(_device_handle, NIRIO_IOCTL_POST_OPEN, NULL,
0, NULL, 0)
/home/ulak/uhd/uhd/host/lib/transport/nirio/niriok_proxy_impl_v1.cpp:438
[INFO] [NIRIO] rpc_client stopping...
[INFO] [NIRIO] rpc_client stopped.
ERROR: The following function call returned status code -63150
_rpc_client.niusrprio_open_session( _resource_name, bitfile_path,
signature, download_fpga)
/home/ulak/uhd/uhd/host/lib/transport/nirio/niusrprio_session.cpp:80
ERROR: The following function call returned status code -63150
mb.rio_fpga_interface->open(lvbitx, dev_addr.has_key("download-fpga"))
/home/ulak/uhd/uhd/host/lib/usrp/x300/x300_impl.cpp:609
[INFO] [NIRIO] rpc_client stopping...
[INFO] [NIRIO] rpc_client stopped.
Error: RuntimeError: x300_impl: Could not initialize RIO session. Unknown
error. (Error code -63150)





On Tue, Mar 5, 2019 at 1:32 PM akin soysal  wrote:

> Dear all,
>
> I am trying to connect over PCIe to my USRP X310. I have installed the
> latest drivers niusrprio-installer-18.0.0.tar.gz and I am starting the PCIe
> connection with the following command:
>
> sudo /usr/local/bin/niusrprio_pcie start
> Making sure drivers are up to date...
> Module nikal is up-to-date
> Module nibds is up-to-date
> Module nistreamk is up-to-date
> Module NiRioSrv is up-to-date
> Module niusrpriok is up-to-date
> Loading: NiRioSrv niusrpriok
> Starting: niusrpriorpc
>
> Then I try the uhd_usrp_probe:
>
> uhd_usrp_probe --args "type=x300,resource=RIO0"
> [INFO] [UHD] linux; GNU C++ version 5.4.0 20160609; Boost_105800;
> UHD_3.13.1.HEAD-0-gbbce3e45
> [INFO] [NIRIO] rpc_client stopping...
> [INFO] [NIRIO] rpc_client stopped.
> [INFO] [NIRIO] rpc_client stopping...
> [INFO] [NIRIO] rpc_client stopped.
> [INFO] [X300] X300 initialization sequence...
> [INFO] [X300] Connecting to niusrpriorpc at localhost:5444...
> [INFO] [NIRIO] rpc_client stopping...
> [INFO] [NIRIO] rpc_client stopped.
> [INFO] [X300] Using LVBITX bitfile
> /usr/local/share/uhd/images/usrp_x310_fpga_HG.lvbitx...
> [INFO] [NIRIO] rpc_client stopping...
> [INFO] [NIRIO] rpc_client stopped.
> [INFO] [NIRIO] rpc_client stopping...
> [INFO] [NIRIO] rpc_client stopped.
> Error: RuntimeError: x300_impl: Could not initialize RIO session. Unknown
> error. (Error code -63150)
>
> I have another PC and USRP x310 and this is working fine. I have followed
> the exact same steps and there isn't any issue. What could be the problem
> and how can I debug this further?
>
> Regards,
> Akın
>
>
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Re: [USRP-users] USRP X310 GPS or IEEE 1588 Synchronization

2019-02-28 Thread akin soysal via USRP-users
Hello,

I know that the 10GbE ethernet interface is adding an extra 500us round
trip time delay with fiber DAC. I tested it myself. 1 GbE would probably
give a similar delay as well. So do you think it would stay below our delay
budget of 250us?

Regards,
Akın

On Fri, 1 Mar 2019 00:24 Nate Temple  Hi Rob,
>
> Yes, that's correct, you can use the WR-LEN with the X310.
>
> Regards,
> Nate Temple
>
>
>
>
>
>
> On Wed, Feb 27, 2019 at 12:40 PM Rob Kossler  wrote:
>
>> Nate,
>> Although the X3xx series to not natively support White Rabbit, I believe
>> that they can get all of the benefits by using a WR-LEN in close proximity
>> to the X310.  Is that correct?
>>
>> Rob
>>
>> On Wed, Feb 27, 2019 at 11:45 AM Nate Temple via USRP-users <
>> usrp-users@lists.ettus.com> wrote:
>>
>>> Hi Akin,
>>>
>>> The Octoclock-G would be suitable for this purpose, and yes, it does
>>> contain a GPSDO (OCXO). https://kb.ettus.com/GPSDO#GPSDO_.28OCXO.29
>>>
>>> The Octoclock-G does not contain an antenna, you must provide one to the
>>> GPS Antenna input (SMA).
>>>
>>> The X3xx series do not support IEEE 1588, however, the N3xx series USRPs
>>> do support White Rabbit, which is an extension of the IEEE-1588-2008
>>> standard. More info can be found here on it
>>> https://kb.ettus.com/Using_Ethernet-Based_Synchronization_on_the_USRP%E2%84%A2_N3xx_Devices
>>>
>>>
>>> Regards,
>>> Nate Temple
>>>
>>> On Wed, Feb 27, 2019 at 8:31 AM akin soysal via USRP-users <
>>> usrp-users@lists.ettus.com> wrote:
>>>
 Hello All,


 I have a question. We want to synchronize the clock of the two USRP
 X310s with a GPS or IEEE 1588 standard. I would like to synchronize the two
 USRPs with each other so that the base station and user terminal would not
 experience any synchronization issue. I also would like to synchronize one
 of the USRP X310s with an external base station, which supports IEEE 1588
 and GPS clocks, and we have a synchronization budget of about *250us*.


 I learned that the setup that worked in France is using the following
 Ettus product:


 https://www.ettus.com/product/details/OctoClock-G


 Do you think that this would suffice for our needs? It has its own GPS
 clock and antenna inside, right? It is compatible with USRP X310?


 I know that the product specification does not include IEEE 1588, so I
 am concluding that it would not be possible to use this standard for our
 scenario, do you agree?

 Thanks and regards,

 Akın
 ___
 USRP-users mailing list
 USRP-users@lists.ettus.com
 http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

>>> ___
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>>>
>>
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Re: [USRP-users] USRP X310 GPS or IEEE 1588 Synchronization

2019-02-28 Thread Nate Temple via USRP-users
Hi Rob,

Yes, that's correct, you can use the WR-LEN with the X310.

Regards,
Nate Temple






On Wed, Feb 27, 2019 at 12:40 PM Rob Kossler  wrote:

> Nate,
> Although the X3xx series to not natively support White Rabbit, I believe
> that they can get all of the benefits by using a WR-LEN in close proximity
> to the X310.  Is that correct?
>
> Rob
>
> On Wed, Feb 27, 2019 at 11:45 AM Nate Temple via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hi Akin,
>>
>> The Octoclock-G would be suitable for this purpose, and yes, it does
>> contain a GPSDO (OCXO). https://kb.ettus.com/GPSDO#GPSDO_.28OCXO.29
>>
>> The Octoclock-G does not contain an antenna, you must provide one to the
>> GPS Antenna input (SMA).
>>
>> The X3xx series do not support IEEE 1588, however, the N3xx series USRPs
>> do support White Rabbit, which is an extension of the IEEE-1588-2008
>> standard. More info can be found here on it
>> https://kb.ettus.com/Using_Ethernet-Based_Synchronization_on_the_USRP%E2%84%A2_N3xx_Devices
>>
>>
>> Regards,
>> Nate Temple
>>
>> On Wed, Feb 27, 2019 at 8:31 AM akin soysal via USRP-users <
>> usrp-users@lists.ettus.com> wrote:
>>
>>> Hello All,
>>>
>>>
>>> I have a question. We want to synchronize the clock of the two USRP
>>> X310s with a GPS or IEEE 1588 standard. I would like to synchronize the two
>>> USRPs with each other so that the base station and user terminal would not
>>> experience any synchronization issue. I also would like to synchronize one
>>> of the USRP X310s with an external base station, which supports IEEE 1588
>>> and GPS clocks, and we have a synchronization budget of about *250us*.
>>>
>>>
>>> I learned that the setup that worked in France is using the following
>>> Ettus product:
>>>
>>>
>>> https://www.ettus.com/product/details/OctoClock-G
>>>
>>>
>>> Do you think that this would suffice for our needs? It has its own GPS
>>> clock and antenna inside, right? It is compatible with USRP X310?
>>>
>>>
>>> I know that the product specification does not include IEEE 1588, so I
>>> am concluding that it would not be possible to use this standard for our
>>> scenario, do you agree?
>>>
>>> Thanks and regards,
>>>
>>> Akın
>>> ___
>>> USRP-users mailing list
>>> USRP-users@lists.ettus.com
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>> ___
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>>
>
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Re: [USRP-users] USRP X310 GPS or IEEE 1588 Synchronization

2019-02-27 Thread Rob Kossler via USRP-users
Nate,
Although the X3xx series to not natively support White Rabbit, I believe
that they can get all of the benefits by using a WR-LEN in close proximity
to the X310.  Is that correct?

Rob

On Wed, Feb 27, 2019 at 11:45 AM Nate Temple via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hi Akin,
>
> The Octoclock-G would be suitable for this purpose, and yes, it does
> contain a GPSDO (OCXO). https://kb.ettus.com/GPSDO#GPSDO_.28OCXO.29
>
> The Octoclock-G does not contain an antenna, you must provide one to the
> GPS Antenna input (SMA).
>
> The X3xx series do not support IEEE 1588, however, the N3xx series USRPs
> do support White Rabbit, which is an extension of the IEEE-1588-2008
> standard. More info can be found here on it
> https://kb.ettus.com/Using_Ethernet-Based_Synchronization_on_the_USRP%E2%84%A2_N3xx_Devices
>
>
> Regards,
> Nate Temple
>
> On Wed, Feb 27, 2019 at 8:31 AM akin soysal via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hello All,
>>
>>
>> I have a question. We want to synchronize the clock of the two USRP X310s
>> with a GPS or IEEE 1588 standard. I would like to synchronize the two USRPs
>> with each other so that the base station and user terminal would not
>> experience any synchronization issue. I also would like to synchronize one
>> of the USRP X310s with an external base station, which supports IEEE 1588
>> and GPS clocks, and we have a synchronization budget of about *250us*.
>>
>>
>> I learned that the setup that worked in France is using the following
>> Ettus product:
>>
>>
>> https://www.ettus.com/product/details/OctoClock-G
>>
>>
>> Do you think that this would suffice for our needs? It has its own GPS
>> clock and antenna inside, right? It is compatible with USRP X310?
>>
>>
>> I know that the product specification does not include IEEE 1588, so I am
>> concluding that it would not be possible to use this standard for our
>> scenario, do you agree?
>>
>> Thanks and regards,
>>
>> Akın
>> ___
>> USRP-users mailing list
>> USRP-users@lists.ettus.com
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
> ___
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>
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Re: [USRP-users] USRP X310 GPS or IEEE 1588 Synchronization

2019-02-27 Thread Nate Temple via USRP-users
Hi Akin,

The Octoclock-G would be suitable for this purpose, and yes, it does
contain a GPSDO (OCXO). https://kb.ettus.com/GPSDO#GPSDO_.28OCXO.29

The Octoclock-G does not contain an antenna, you must provide one to the
GPS Antenna input (SMA).

The X3xx series do not support IEEE 1588, however, the N3xx series USRPs do
support White Rabbit, which is an extension of the IEEE-1588-2008 standard.
More info can be found here on it
https://kb.ettus.com/Using_Ethernet-Based_Synchronization_on_the_USRP%E2%84%A2_N3xx_Devices


Regards,
Nate Temple

On Wed, Feb 27, 2019 at 8:31 AM akin soysal via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hello All,
>
>
> I have a question. We want to synchronize the clock of the two USRP X310s
> with a GPS or IEEE 1588 standard. I would like to synchronize the two USRPs
> with each other so that the base station and user terminal would not
> experience any synchronization issue. I also would like to synchronize one
> of the USRP X310s with an external base station, which supports IEEE 1588
> and GPS clocks, and we have a synchronization budget of about *250us*.
>
>
> I learned that the setup that worked in France is using the following
> Ettus product:
>
>
> https://www.ettus.com/product/details/OctoClock-G
>
>
> Do you think that this would suffice for our needs? It has its own GPS
> clock and antenna inside, right? It is compatible with USRP X310?
>
>
> I know that the product specification does not include IEEE 1588, so I am
> concluding that it would not be possible to use this standard for our
> scenario, do you agree?
>
> Thanks and regards,
>
> Akın
> ___
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
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Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

2019-02-23 Thread Armin Schmidt via USRP-users
Hallo Martin,

Concerning the vanilla UHD-example: I'm just remember, that I've
couldn't find an example on your repository, where you used multi_usrp
in combination with RFNoC. Before we used our FPGA-Image in our
CPP-Application we tested it with GNU-Radio. But there we tested just
one channel (I think it's not possible to use in GNU-Radio something
like multi_usrp, right?) So I think, in GNU-Radio behind the scene is
directly a device3 initialized, right? So, and there we hadn't the
problem. The problem was only in our CPP-Application using the
multi_usrp. But I haven't tested to initialize just a single device3. I
could do this, if it helps!

Many thanks,

Armin Schmidt

Am 23.02.19 um 00:26 schrieb Martin Braun:
> Armin,
>
> I'd like to learn a little more about this failure. Here's a couple of
> questions:
> - How many USRPs are you running at once? Does this also happen with a
> single USRP?
> - Does this also happen when using a vanilla UHD example? Since you're
> running a custom RFNOC block, it would be good to eliminate as many
> variables as possible. benchmark_rate will exercise the Radio and DDC.
>
> -- M
>
> On Tue, Feb 19, 2019 at 2:42 AM Armin Schmidt via USRP-users
> mailto:usrp-users@lists.ettus.com>> wrote:
>
> Hallo,
> We're about to migrate from multi-usrp-application with UHD 3.9
> and custome FPGA to UHD 3.14 with RFNoC. We are using the USRP
> x310 with daughterboards ubx-160. Everything seems to work fine
> except that when we stop our application in the terminal with
> ctrl-c, a new startup is only possible after a powercycle of all
> USRP's.
> The problem is, that we can connect our RFNoC-blocks and start
> streaming, but without a powercycle the recv() function starts
> after several successfully received packets to produce
> continuously the following error and hangs in this state:
> [ERROR] [STREAMER] The receive packet handler failed to time-align
> packets.
> 1002 received packets were processed by the handler.
> However, a timestamp match could not be determined.
>
> For me it is not clear, where to search for the problem. We set
> sudo sysctl net.core.rmem_max=33554432.
>
> Following our code for initializing the USRPS and RFNoC:
>
> //===
>     //Setup a RX usrp device:
>     //===
>     multiUSRP =
> uhd::usrp::multi_usrp::make(parser.value("args").toStdString());   
> //create multi-USRP
>
>     QThread::sleep(1);  //allow for some setup-time
>
>     if(parser.value("args") == "")  //show default values
>     {
>     uhd::device_addr_t hint("");
>     std::vector addresses =
> ((multiUSRP->get_device())->find(hint));
>     QString address =
> QString::fromUtf8((addresses[0].to_string()).c_str());
>     QStringList addressList = address.split(",");
>     QString args = addressList[0] + ",";
>
>     for(int i = 0; i < addresses.size(); i++)
>     {
>     address =
> QString::fromUtf8((addresses[i].to_string()).c_str());
>     addressList = address.split(",");
>     args += "addr" + QString::number(i) + "=" +
> (addressList[1].split("="))[1] + ",";
>     }
>
>     args += "master_clock_rate=" +
> QString::number(multiUSRP->get_master_clock_rate());
>
>     qInfo() << endl << "Creating the RX usrp device with: " <<
> args;
>     }
>
>     else
>     {
>     qInfo() << endl << "Creating the RX usrp device with: " <<
> parser.value("args");
>     }
>
>     usrpDevice = multiUSRP->get_device3();
>     usrpDevice->clear();    //reset device streaming state (resets
> blocks after a stream)
>
>     //==
>     //Create block controls:
>     //==
>     std::vector blocks;
>     std::string agc0_id, ddc0_id, psd0_id, agc1_id, ddc1_id,
> psd1_id, radio_args, agc_args, ddc_args, streamargs;
>     ddc0_id = "DDC_0";
>
>     //Initialize Radio-blocks:
>     //
>     QStringList rx_channel_strings =
> (parser.value("channels")).split(",");
>     numChannels = rx_channel_strings.size();
>     QVector radio_ctrls;
>
>     qInfo() << endl;
>
>     //initializes all m radio controls:
>     for(int i = 0; i < numChannels; i++)
>     {
>     uhd::rfnoc::block_id_t radio_ctrl_id(qFloor(i/2), "Radio",
> (i % 2)); //create on USRP x the radio object for channel 0 or 1
>    
> 
> radio_ctrls.append(usrpDevice->get_block_ctrl(radio_ctrl_id));
>  
> //this line will faile, if radio is not available
>
>     qInfo() << "Using USRP: " << qFloor(i/2) << ", channel: "
> << (i % 2) << endl;
>     }
>
>     //radio_ctrl->set_args(radio_args);
>
>     //Set clock-source:
>     /*for(int i = 0; i < nu

Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

2019-02-23 Thread Armin Schmidt via USRP-users
Hallo Martin,

So at the moment for testing the new RFNocC-designe I've used two USRP's
x310 synchronized with a octocklock from ettus.

In our real application we operate 5 or 6 USRP's in parallel, all
connected over the 1 gigabit-ethernet to our host-machine.

The problem described happens also with one USRP (two channels). But
I've recognised once, that with only one USRP in use, it managed after
several outputs of the Error-message to recuperate and afterwards it
seemed to work (I have to test this behaviour with one USRP again, I'm
not shure, if it is always reproducible).

We haven't used a vanilla UHD example. I will try this next week!

Many thanks,

Armin

Am 23.02.19 um 00:26 schrieb Martin Braun:
> Armin,
>
> I'd like to learn a little more about this failure. Here's a couple of
> questions:
> - How many USRPs are you running at once? Does this also happen with a
> single USRP?
> - Does this also happen when using a vanilla UHD example? Since you're
> running a custom RFNOC block, it would be good to eliminate as many
> variables as possible. benchmark_rate will exercise the Radio and DDC.
>
> -- M
>
> On Tue, Feb 19, 2019 at 2:42 AM Armin Schmidt via USRP-users
> mailto:usrp-users@lists.ettus.com>> wrote:
>
> Hallo,
> We're about to migrate from multi-usrp-application with UHD 3.9
> and custome FPGA to UHD 3.14 with RFNoC. We are using the USRP
> x310 with daughterboards ubx-160. Everything seems to work fine
> except that when we stop our application in the terminal with
> ctrl-c, a new startup is only possible after a powercycle of all
> USRP's.
> The problem is, that we can connect our RFNoC-blocks and start
> streaming, but without a powercycle the recv() function starts
> after several successfully received packets to produce
> continuously the following error and hangs in this state:
> [ERROR] [STREAMER] The receive packet handler failed to time-align
> packets.
> 1002 received packets were processed by the handler.
> However, a timestamp match could not be determined.
>
> For me it is not clear, where to search for the problem. We set
> sudo sysctl net.core.rmem_max=33554432.
>
> Following our code for initializing the USRPS and RFNoC:
>
> //===
>     //Setup a RX usrp device:
>     //===
>     multiUSRP =
> uhd::usrp::multi_usrp::make(parser.value("args").toStdString());   
> //create multi-USRP
>
>     QThread::sleep(1);  //allow for some setup-time
>
>     if(parser.value("args") == "")  //show default values
>     {
>     uhd::device_addr_t hint("");
>     std::vector addresses =
> ((multiUSRP->get_device())->find(hint));
>     QString address =
> QString::fromUtf8((addresses[0].to_string()).c_str());
>     QStringList addressList = address.split(",");
>     QString args = addressList[0] + ",";
>
>     for(int i = 0; i < addresses.size(); i++)
>     {
>     address =
> QString::fromUtf8((addresses[i].to_string()).c_str());
>     addressList = address.split(",");
>     args += "addr" + QString::number(i) + "=" +
> (addressList[1].split("="))[1] + ",";
>     }
>
>     args += "master_clock_rate=" +
> QString::number(multiUSRP->get_master_clock_rate());
>
>     qInfo() << endl << "Creating the RX usrp device with: " <<
> args;
>     }
>
>     else
>     {
>     qInfo() << endl << "Creating the RX usrp device with: " <<
> parser.value("args");
>     }
>
>     usrpDevice = multiUSRP->get_device3();
>     usrpDevice->clear();    //reset device streaming state (resets
> blocks after a stream)
>
>     //==
>     //Create block controls:
>     //==
>     std::vector blocks;
>     std::string agc0_id, ddc0_id, psd0_id, agc1_id, ddc1_id,
> psd1_id, radio_args, agc_args, ddc_args, streamargs;
>     ddc0_id = "DDC_0";
>
>     //Initialize Radio-blocks:
>     //
>     QStringList rx_channel_strings =
> (parser.value("channels")).split(",");
>     numChannels = rx_channel_strings.size();
>     QVector radio_ctrls;
>
>     qInfo() << endl;
>
>     //initializes all m radio controls:
>     for(int i = 0; i < numChannels; i++)
>     {
>     uhd::rfnoc::block_id_t radio_ctrl_id(qFloor(i/2), "Radio",
> (i % 2)); //create on USRP x the radio object for channel 0 or 1
>    
> 
> radio_ctrls.append(usrpDevice->get_block_ctrl(radio_ctrl_id));
>  
> //this line will faile, if radio is not available
>
>     qInfo() << "Using USRP: " << qFloor(i/2) << ", channel: "
> << (i % 2) << endl;
>     }
>
>     //radio_ctrl->set_args(radio_args);
>
>     //Set clock-source:
>     /*for(int i = 0; i < numChannels;

Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

2019-02-22 Thread Martin Braun via USRP-users
Armin,

I'd like to learn a little more about this failure. Here's a couple of
questions:
- How many USRPs are you running at once? Does this also happen with a
single USRP?
- Does this also happen when using a vanilla UHD example? Since you're
running a custom RFNOC block, it would be good to eliminate as many
variables as possible. benchmark_rate will exercise the Radio and DDC.

-- M

On Tue, Feb 19, 2019 at 2:42 AM Armin Schmidt via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hallo,
> We're about to migrate from multi-usrp-application with UHD 3.9 and
> custome FPGA to UHD 3.14 with RFNoC. We are using the USRP x310 with
> daughterboards ubx-160. Everything seems to work fine except that when we
> stop our application in the terminal with ctrl-c, a new startup is only
> possible after a powercycle of all USRP's.
> The problem is, that we can connect our RFNoC-blocks and start streaming,
> but without a powercycle the recv() function starts after several
> successfully received packets to produce continuously the following error
> and hangs in this state:
> [ERROR] [STREAMER] The receive packet handler failed to time-align packets.
> 1002 received packets were processed by the handler.
> However, a timestamp match could not be determined.
>
> For me it is not clear, where to search for the problem. We set sudo
> sysctl net.core.rmem_max=33554432.
>
> Following our code for initializing the USRPS and RFNoC:
>
> //===
> //Setup a RX usrp device:
> //===
> multiUSRP =
> uhd::usrp::multi_usrp::make(parser.value("args").toStdString());
> //create multi-USRP
>
> QThread::sleep(1);  //allow for some setup-time
>
> if(parser.value("args") == "")  //show default values
> {
> uhd::device_addr_t hint("");
> std::vector addresses =
> ((multiUSRP->get_device())->find(hint));
> QString address =
> QString::fromUtf8((addresses[0].to_string()).c_str());
> QStringList addressList = address.split(",");
> QString args = addressList[0] + ",";
>
> for(int i = 0; i < addresses.size(); i++)
> {
> address =
> QString::fromUtf8((addresses[i].to_string()).c_str());
> addressList = address.split(",");
> args += "addr" + QString::number(i) + "=" +
> (addressList[1].split("="))[1] + ",";
> }
>
> args += "master_clock_rate=" +
> QString::number(multiUSRP->get_master_clock_rate());
>
> qInfo() << endl << "Creating the RX usrp device with: " << args;
> }
>
> else
> {
> qInfo() << endl << "Creating the RX usrp device with: " <<
> parser.value("args");
> }
>
> usrpDevice = multiUSRP->get_device3();
> usrpDevice->clear();//reset device streaming state (resets blocks
> after a stream)
>
> //==
> //Create block controls:
> //==
> std::vector blocks;
> std::string agc0_id, ddc0_id, psd0_id, agc1_id, ddc1_id, psd1_id,
> radio_args, agc_args, ddc_args, streamargs;
> ddc0_id = "DDC_0";
>
> //Initialize Radio-blocks:
> //
> QStringList rx_channel_strings = (parser.value("channels")).split(",");
> numChannels = rx_channel_strings.size();
> QVector radio_ctrls;
>
> qInfo() << endl;
>
> //initializes all m radio controls:
> for(int i = 0; i < numChannels; i++)
> {
> uhd::rfnoc::block_id_t radio_ctrl_id(qFloor(i/2), "Radio", (i %
> 2)); //create on USRP x the radio object for channel 0 or 1
>
> radio_ctrls.append(usrpDevice->get_block_ctrl(radio_ctrl_id));
> //this line will faile, if radio is not available
>
> qInfo() << "Using USRP: " << qFloor(i/2) << ", channel: " << (i %
> 2) << endl;
> }
>
> //radio_ctrl->set_args(radio_args);
>
> //Set clock-source:
> /*for(int i = 0; i < numChannels; i++)
> {
> radio_ctrls[i]->set_time_source("external");
> radio_ctrls[i]->set_clock_source("external");
> }*/
> //radio_ctrls[0]->set_time_next_pps()
>
> multiUSRP->set_time_source("external");
> multiUSRP->set_clock_source("external");
> multiUSRP->set_time_unknown_pps(uhd::time_spec_t(0.0));
> QThread::sleep(1); //wait for pps sync pulse
>
> //check time synchronization across all motherboards
> if (multiUSRP->get_time_synchronized())
> {
> qInfo() << endl << "Time Synchronization across all Motherboards
> done";
> }
>
> else
> {
> qInfo() << endl << "Time Synchronization across all Motherboards
> failed";
> throw "Time Synchronization across all Motherboards failed";
> }
>
> //set the RX-antenna:
> for(int i = 0; i < numChannels; i++)
> {
> radio_ctrls[i]->set_rx_antenna("RX2", 0);
> }
>
> QThread::sleep(1);  //allow for some setup-time
>
> //this->set_rx_gain((parser.value("gain")).toDouble());
> //this->set_rx_freq((parser.value("freq")).toDouble());
>
>

Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

2019-02-22 Thread Brian Padalino via USRP-users
On Fri, Feb 22, 2019 at 6:19 PM Martin Braun  wrote:

> This pokes a register in the STC3. It'll pull the FPGA into reset. You
> then need to wait a bit before the FPGA is back up.
>

So it's a forced reload of the FPGA from the onboard image.  To use this in
software, I'd issue the command, then try to ping the device until it
responds.  Then I would re-load my application from there?

Thanks,
Brian
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Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

2019-02-22 Thread Martin Braun via USRP-users
This pokes a register in the STC3. It'll pull the FPGA into reset. You then
need to wait a bit before the FPGA is back up.

-- M

On Fri, Feb 22, 2019 at 10:21 AM Brian Padalino via USRP-users <
usrp-users@lists.ettus.com> wrote:

> On Wed, Feb 20, 2019 at 7:45 PM Jonathon Pendlum <
> jonathon.pend...@ettus.com> wrote:
>
>> Hi Armin,
>>
>> You can reset X3x0 series devices via a register write with the following
>> command (this is in to your UHD src directory):
>> firmware/usrp3/x300/x300_debug.py --addr 192.168.40.2 --poke=0x00100058
>> --data=1.
>>
>
> Can you elaborate a little bit on what this register does, and why the UHD
> software might not always poke it to reset it?
>
> Thanks,
> Brian
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>
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Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

2019-02-22 Thread Brian Padalino via USRP-users
On Wed, Feb 20, 2019 at 7:45 PM Jonathon Pendlum 
wrote:

> Hi Armin,
>
> You can reset X3x0 series devices via a register write with the following
> command (this is in to your UHD src directory):
> firmware/usrp3/x300/x300_debug.py --addr 192.168.40.2 --poke=0x00100058
> --data=1.
>

Can you elaborate a little bit on what this register does, and why the UHD
software might not always poke it to reset it?

Thanks,
Brian
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Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

2019-02-20 Thread Jonathon Pendlum via USRP-users
Hi Armin,

You can reset X3x0 series devices via a register write with the following
command (this is in to your UHD src directory):
firmware/usrp3/x300/x300_debug.py --addr 192.168.40.2 --poke=0x00100058
--data=1.

When you kill your app and resume, how long do you wait before restarting?
Can you try waiting a minute or two and see if that fixes the issue? If
that works, then it points to some internal buffering in the USRP not being
cleared before restarting streaming.

Jonathon

On Wed, Feb 20, 2019 at 6:27 PM Armin Schmidt via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hm, does someone know if it is possible somehow to reset the FPGA over a
> register? We see, that there exists a registers for resets of different
> modules (SR_SW_RST), but don't know, if we could use this over the API.
> Does somewhere exist a register-map? I think that should be the basis of
> every documentation.
>
> Would be quite sad, if Ettus don't prioritize the possible to use the
> hardware for real operation and not only for tinker-projects. We are
> operating at the moment three systems, each with five x310 and
> ubx-160-doughterboards and in the next several months/years it will be a
> lot more. So I hope Ettus will see this conversation and respond, otherwise
> we will be forced to move on to other vendors! The Ettus-support is quite
> painful and slow from my experiences and the documentation even worse!
>
> Am Di., 19. Feb. 2019 um 20:45 Uhr schrieb Brian Padalino <
> bpadal...@gmail.com>:
>
>> On Tue, Feb 19, 2019 at 12:07 PM Armin Schmidt  wrote:
>>
>>> Thanks for your replay! Hm, yes I've thought also about to use
>>> STREAM_MODE_STOP_CONTINUOUS, but I would like to be able to restart my app
>>> also after a crash. Ok, it should never happen, but one can never guarantee
>>> that case. Do you have an idea, how to deal with such cases? I think it's a
>>> bug in UHD, because in the version 3.9 was that never a problem.
>>>
>>
>> From my conversations with Ettus, getting the radios to a known good
>> state after a crash is not something they are prioritizing.
>>
>> My recommendation to you is that you reload the FPGA over JTAG every time
>> before starting your application such that it is always in a known
>> good/initial state.
>>
>> Brian
>>
>>> ___
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>
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Re: [USRP-users] USRP X310 Maximum frame size: 7972 bytes.

2019-02-20 Thread Marcus D. Leech via USRP-users

On 02/20/2019 07:50 AM, akin soysal via USRP-users wrote:

Hello,

In order to decrease the latency, I was playing around with the MTU 
size setting it to 4000, 7000, 9000 and now a permanent error happens 
in my server connected to USRP. I tried it with two different USRP 
X310s and the problem happens in both. Where does the 7972 bytes come 
from? Thanks. Regards, Akın


/uhd/uhd/host/build$ uhd_usrp_probe
[INFO] [UHD] linux; GNU C++ version 5.4.0 20160609; Boost_105800; 
UHD_3.13.1.HEAD-0-gbbce3e45

[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Maximum frame size: 7972 bytes.
[INFO] [X300] Radio 1x clock: 200 MHz
[WARNING] [X300] For this connection, UHD recommends a send frame size 
of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.
[WARNING] [X300] For this connection, UHD recommends a receive frame 
size of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.
[WARNING] [X300] For this connection, UHD recommends a send frame size 
of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.
[WARNING] [X300] For this connection, UHD recommends a receive frame 
size of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.
[INFO] [0/DmaFIFO_0] Initializing block control (NOC ID: 
0xF1F0D000)

[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1306 MB/s)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1311 MB/s)
[WARNING] [X300] For this connection, UHD recommends a send frame size 
of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.
[WARNING] [X300] For this connection, UHD recommends a receive frame 
size of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.
[WARNING] [X300] For this connection, UHD recommends a send frame size 
of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.
[WARNING] [X300] For this connection, UHD recommends a receive frame 
size of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.

[INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD1001)
[WARNING] [X300] For this connection, UHD recommends a send frame size 
of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.
[WARNING] [X300] For this connection, UHD recommends a receive frame 
size of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.
[WARNING] [X300] For this connection, UHD recommends a send frame size 
of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.
[WARNING] [X300] For this connection, UHD recommends a receive frame 
size of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.

[INFO] [0/Radio_1] Initializing block control (NOC ID: 0x12AD1001)
[WARNING] [X300] For this connection, UHD recommends a send frame size 
of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.
[WARNING] [X300] For this connection, UHD recommends a receive frame 
size of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.
[WARNING] [X300] For this connection, UHD recommends a send frame size 
of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.
[WARNING] [X300] For this connection, UHD recommends a receive frame 
size of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.

[INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0)
[WARNING] [X300] For this connection, UHD recommends a send frame size 
of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negatively impact your maximum achievable sample rate.
[WARNING] [X300] For this connection, UHD recommends a receive frame 
size of at least 8000 for best
performance, but your system's MTU will only allow 7972.This will 
negativel

Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

2019-02-20 Thread Armin Schmidt via USRP-users
Hm, does someone know if it is possible somehow to reset the FPGA over a
register? We see, that there exists a registers for resets of different
modules (SR_SW_RST), but don't know, if we could use this over the API.
Does somewhere exist a register-map? I think that should be the basis of
every documentation.

Would be quite sad, if Ettus don't prioritize the possible to use the
hardware for real operation and not only for tinker-projects. We are
operating at the moment three systems, each with five x310 and
ubx-160-doughterboards and in the next several months/years it will be a
lot more. So I hope Ettus will see this conversation and respond, otherwise
we will be forced to move on to other vendors! The Ettus-support is quite
painful and slow from my experiences and the documentation even worse!

Am Di., 19. Feb. 2019 um 20:45 Uhr schrieb Brian Padalino <
bpadal...@gmail.com>:

> On Tue, Feb 19, 2019 at 12:07 PM Armin Schmidt  wrote:
>
>> Thanks for your replay! Hm, yes I've thought also about to use
>> STREAM_MODE_STOP_CONTINUOUS, but I would like to be able to restart my app
>> also after a crash. Ok, it should never happen, but one can never guarantee
>> that case. Do you have an idea, how to deal with such cases? I think it's a
>> bug in UHD, because in the version 3.9 was that never a problem.
>>
>
> From my conversations with Ettus, getting the radios to a known good state
> after a crash is not something they are prioritizing.
>
> My recommendation to you is that you reload the FPGA over JTAG every time
> before starting your application such that it is always in a known
> good/initial state.
>
> Brian
>
>>
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Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

2019-02-19 Thread Brian Padalino via USRP-users
On Tue, Feb 19, 2019 at 12:07 PM Armin Schmidt  wrote:

> Thanks for your replay! Hm, yes I've thought also about to use
> STREAM_MODE_STOP_CONTINUOUS, but I would like to be able to restart my app
> also after a crash. Ok, it should never happen, but one can never guarantee
> that case. Do you have an idea, how to deal with such cases? I think it's a
> bug in UHD, because in the version 3.9 was that never a problem.
>

>From my conversations with Ettus, getting the radios to a known good state
after a crash is not something they are prioritizing.

My recommendation to you is that you reload the FPGA over JTAG every time
before starting your application such that it is always in a known
good/initial state.

Brian

>
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Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

2019-02-19 Thread Armin Schmidt via USRP-users
Thanks for your replay! Hm, yes I've thought also about to use
STREAM_MODE_STOP_CONTINUOUS, but I would like to be able to restart my app
also after a crash. Ok, it should never happen, but one can never guarantee
that case. Do you have an idea, how to deal with such cases? I think it's a
bug in UHD, because in the version 3.9 was that never a problem.



Am Di., 19. Feb. 2019 um 14:47 Uhr schrieb Brian Padalino <
bpadal...@gmail.com>:

> On Tue, Feb 19, 2019 at 5:42 AM Armin Schmidt via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hallo,
>> We're about to migrate from multi-usrp-application with UHD 3.9 and
>> custome FPGA to UHD 3.14 with RFNoC. We are using the USRP x310 with
>> daughterboards ubx-160. Everything seems to work fine except that when we
>> stop our application in the terminal with ctrl-c, a new startup is only
>> possible after a powercycle of all USRP's.
>> The problem is, that we can connect our RFNoC-blocks and start streaming,
>> but without a powercycle the recv() function starts after several
>> successfully received packets to produce continuously the following error
>> and hangs in this state:
>> [ERROR] [STREAMER] The receive packet handler failed to time-align
>> packets.
>> 1002 received packets were processed by the handler.
>> However, a timestamp match could not be determined.
>>
>> For me it is not clear, where to search for the problem. We set sudo
>> sysctl net.core.rmem_max=33554432.
>>
>> Following our code for initializing the USRPS and RFNoC:
>>
>> //===
>> //Setup a RX usrp device:
>> //===
>> multiUSRP =
>> uhd::usrp::multi_usrp::make(parser.value("args").toStdString());
>> //create multi-USRP
>>
>> QThread::sleep(1);  //allow for some setup-time
>>
>> if(parser.value("args") == "")  //show default values
>> {
>> uhd::device_addr_t hint("");
>> std::vector addresses =
>> ((multiUSRP->get_device())->find(hint));
>> QString address =
>> QString::fromUtf8((addresses[0].to_string()).c_str());
>> QStringList addressList = address.split(",");
>> QString args = addressList[0] + ",";
>>
>> for(int i = 0; i < addresses.size(); i++)
>> {
>> address =
>> QString::fromUtf8((addresses[i].to_string()).c_str());
>> addressList = address.split(",");
>> args += "addr" + QString::number(i) + "=" +
>> (addressList[1].split("="))[1] + ",";
>> }
>>
>> args += "master_clock_rate=" +
>> QString::number(multiUSRP->get_master_clock_rate());
>>
>> qInfo() << endl << "Creating the RX usrp device with: " << args;
>> }
>>
>> else
>> {
>> qInfo() << endl << "Creating the RX usrp device with: " <<
>> parser.value("args");
>> }
>>
>> usrpDevice = multiUSRP->get_device3();
>> usrpDevice->clear();//reset device streaming state (resets blocks
>> after a stream)
>>
>> //==
>> //Create block controls:
>> //==
>> std::vector blocks;
>> std::string agc0_id, ddc0_id, psd0_id, agc1_id, ddc1_id, psd1_id,
>> radio_args, agc_args, ddc_args, streamargs;
>> ddc0_id = "DDC_0";
>>
>> //Initialize Radio-blocks:
>> //
>> QStringList rx_channel_strings =
>> (parser.value("channels")).split(",");
>> numChannels = rx_channel_strings.size();
>> QVector radio_ctrls;
>>
>> qInfo() << endl;
>>
>> //initializes all m radio controls:
>> for(int i = 0; i < numChannels; i++)
>> {
>> uhd::rfnoc::block_id_t radio_ctrl_id(qFloor(i/2), "Radio", (i %
>> 2)); //create on USRP x the radio object for channel 0 or 1
>>
>> radio_ctrls.append(usrpDevice->get_block_ctrl(radio_ctrl_id));
>> //this line will faile, if radio is not available
>>
>> qInfo() << "Using USRP: " << qFloor(i/2) << ", channel: " << (i %
>> 2) << endl;
>> }
>>
>> //radio_ctrl->set_args(radio_args);
>>
>> //Set clock-source:
>> /*for(int i = 0; i < numChannels; i++)
>> {
>> radio_ctrls[i]->set_time_source("external");
>> radio_ctrls[i]->set_clock_source("external");
>> }*/
>> //radio_ctrls[0]->set_time_next_pps()
>>
>> multiUSRP->set_time_source("external");
>> multiUSRP->set_clock_source("external");
>> multiUSRP->set_time_unknown_pps(uhd::time_spec_t(0.0));
>> QThread::sleep(1); //wait for pps sync pulse
>>
>> //check time synchronization across all motherboards
>> if (multiUSRP->get_time_synchronized())
>> {
>> qInfo() << endl << "Time Synchronization across all Motherboards
>> done";
>> }
>>
>> else
>> {
>> qInfo() << endl << "Time Synchronization across all Motherboards
>> failed";
>> throw "Time Synchronization across all Motherboards failed";
>> }
>>
>> //set the RX-antenna:
>> for(int i = 0; i < numChannels; i++)
>> {
>> radio_ctrls[i]->set_rx_antenna("RX2", 0);
>> }

Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

2019-02-19 Thread Brian Padalino via USRP-users
On Tue, Feb 19, 2019 at 5:42 AM Armin Schmidt via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hallo,
> We're about to migrate from multi-usrp-application with UHD 3.9 and
> custome FPGA to UHD 3.14 with RFNoC. We are using the USRP x310 with
> daughterboards ubx-160. Everything seems to work fine except that when we
> stop our application in the terminal with ctrl-c, a new startup is only
> possible after a powercycle of all USRP's.
> The problem is, that we can connect our RFNoC-blocks and start streaming,
> but without a powercycle the recv() function starts after several
> successfully received packets to produce continuously the following error
> and hangs in this state:
> [ERROR] [STREAMER] The receive packet handler failed to time-align packets.
> 1002 received packets were processed by the handler.
> However, a timestamp match could not be determined.
>
> For me it is not clear, where to search for the problem. We set sudo
> sysctl net.core.rmem_max=33554432.
>
> Following our code for initializing the USRPS and RFNoC:
>
> //===
> //Setup a RX usrp device:
> //===
> multiUSRP =
> uhd::usrp::multi_usrp::make(parser.value("args").toStdString());
> //create multi-USRP
>
> QThread::sleep(1);  //allow for some setup-time
>
> if(parser.value("args") == "")  //show default values
> {
> uhd::device_addr_t hint("");
> std::vector addresses =
> ((multiUSRP->get_device())->find(hint));
> QString address =
> QString::fromUtf8((addresses[0].to_string()).c_str());
> QStringList addressList = address.split(",");
> QString args = addressList[0] + ",";
>
> for(int i = 0; i < addresses.size(); i++)
> {
> address =
> QString::fromUtf8((addresses[i].to_string()).c_str());
> addressList = address.split(",");
> args += "addr" + QString::number(i) + "=" +
> (addressList[1].split("="))[1] + ",";
> }
>
> args += "master_clock_rate=" +
> QString::number(multiUSRP->get_master_clock_rate());
>
> qInfo() << endl << "Creating the RX usrp device with: " << args;
> }
>
> else
> {
> qInfo() << endl << "Creating the RX usrp device with: " <<
> parser.value("args");
> }
>
> usrpDevice = multiUSRP->get_device3();
> usrpDevice->clear();//reset device streaming state (resets blocks
> after a stream)
>
> //==
> //Create block controls:
> //==
> std::vector blocks;
> std::string agc0_id, ddc0_id, psd0_id, agc1_id, ddc1_id, psd1_id,
> radio_args, agc_args, ddc_args, streamargs;
> ddc0_id = "DDC_0";
>
> //Initialize Radio-blocks:
> //
> QStringList rx_channel_strings = (parser.value("channels")).split(",");
> numChannels = rx_channel_strings.size();
> QVector radio_ctrls;
>
> qInfo() << endl;
>
> //initializes all m radio controls:
> for(int i = 0; i < numChannels; i++)
> {
> uhd::rfnoc::block_id_t radio_ctrl_id(qFloor(i/2), "Radio", (i %
> 2)); //create on USRP x the radio object for channel 0 or 1
>
> radio_ctrls.append(usrpDevice->get_block_ctrl(radio_ctrl_id));
> //this line will faile, if radio is not available
>
> qInfo() << "Using USRP: " << qFloor(i/2) << ", channel: " << (i %
> 2) << endl;
> }
>
> //radio_ctrl->set_args(radio_args);
>
> //Set clock-source:
> /*for(int i = 0; i < numChannels; i++)
> {
> radio_ctrls[i]->set_time_source("external");
> radio_ctrls[i]->set_clock_source("external");
> }*/
> //radio_ctrls[0]->set_time_next_pps()
>
> multiUSRP->set_time_source("external");
> multiUSRP->set_clock_source("external");
> multiUSRP->set_time_unknown_pps(uhd::time_spec_t(0.0));
> QThread::sleep(1); //wait for pps sync pulse
>
> //check time synchronization across all motherboards
> if (multiUSRP->get_time_synchronized())
> {
> qInfo() << endl << "Time Synchronization across all Motherboards
> done";
> }
>
> else
> {
> qInfo() << endl << "Time Synchronization across all Motherboards
> failed";
> throw "Time Synchronization across all Motherboards failed";
> }
>
> //set the RX-antenna:
> for(int i = 0; i < numChannels; i++)
> {
> radio_ctrls[i]->set_rx_antenna("RX2", 0);
> }
>
> QThread::sleep(1);  //allow for some setup-time
>
> //this->set_rx_gain((parser.value("gain")).toDouble());
> //this->set_rx_freq((parser.value("freq")).toDouble());
>
>
> //=
> //Set-up streaming:
> //=
> uhd::device_addr_t streamer_args(streamargs);
> std::vector rx_channel_nums;
>
> rx_graph = usrpDevice->create_graph("rx_graph");
>
> for(int i = 0; i < numChannels; i++)
> {
> /*
> //Check if agc0-block is available:
> if(!usrpDevice->has_block(agc0_id))
> {

Re: [USRP-users] USRP X310 uhd 4.0 fpga rfnoc img download

2019-02-08 Thread Jonathon Pendlum via USRP-users
Hi Paul,

The rfnoc-devel branch is deprecated. You should build off the master
branch or UHD-3.13 branch with the cmake flag "-DENABLE_RFNOC=ON". You can
then use uhd_image_downloader. The image package only includes images with
the default RFNoC blocks. For the X310, the default image has two DDC and
two DUC RFNoC blocks. You'll need to build a custom image if you want to
use other blocks.

Jonathon

On Tue, Feb 5, 2019 at 8:35 AM Paul Marian Stoica via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hi,
>
> I succesfully installed UHD 4.0.0.rfnoc-devel-702-geec24d7b from source on
> Ubuntu 16.04 and when I launched uhd_images_downloader it doesn't download
> the rfnoc images.
>
> In /usr/local/share/uhd/images I can only see regular images, nothing with
> RFNOC in it's name. Is there somewhere else where I can download the rfnoc
> images for X310?
>
> Thank you!
>
> ___
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
___
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com


Re: [USRP-users] USRP X310 Ubuntu 16.04 LowLatency Timing Problems Possibly Because of UHD Drivers

2019-02-07 Thread Marcus D. Leech via USRP-users

On 02/07/2019 08:50 AM, akin soysal via USRP-users wrote:


Dear all,


We are trying to make the OpenAirInterface 5G SW work on our own setup 
with NI USRPs. We are trying to use it with the following configuration:



sudo ./benchmark_rate --args 
"type=x300,addr=10.10.1.5,master_clock_rate=184.32e6" --rx_rate 
61.44e6 --tx_rate 61.44e6 --channels="0"



For different UHD versions we get different results. Firstly, we know 
that the OAI setup in France is using the following driver and gives 
the following output:



---

[0m[PHY]  Checking for USRPs :UHD 003.009.007-0-g50839059(3.9.7)
[0m[PHY]  Found USRP X300
[0m[PHY]  ru_thread_prach() RACH waiting for RU to be configured
-- X300 initialization sequence...
-- Connecting to niusrpriorpc at localhost:5444...
-- Using LVBITX bitfile 
/usr/local/share/uhd/images/usrp_x310_fpga_HGS.lvbitx...

[0m[PHY]  ru_thread_prach() RACH waiting for RU to be configured
[0m[PHY]  ru_thread_prach() RACH waiting for RU to be configured
[0m[PHY]  ru_thread_prach() RACH waiting for RU to be configured
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:184.32
-- Detecting internal GPSDO Found an internal GPSDO: LC_XO, 
Firmware Rev 0.929a

---


We tried the same configuration, but we got errors:


---

ulak@5g-NR-gNB:/usr/local/lib/uhd/examples$ sudo ./benchmark_rate 
--args "type=x300,addr=10.10.1.5,master_clock_rate=184.32e6" --rx_rate 
61.44e6 --tx_rate 61.44e6 --channels="0"

[sudo] password for ulak:
linux; GNU C++ version 5.4.0 20160609; 
Boost_105800;UHD_003.009.007-0-g50839059



Creating the usrp device with: 
type=x300,addr=10.10.1.5,master_clock_rate=184.32e6...

-- X300 initialization sequence...
-- Determining maximum frame size... 8000 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:184.32
-- Detecting internal GPSDO No GPSDO found
-- Initialize Radio0 control...
-- Performing register loopback test... pass

UHD Error:
The daughterboard manager encountered a recoverable error in init.
Loading the "unknown" daughterboard implementations to continue.
The daughterboard cannot operate until this error is resolved.
EnvironmentError: IOError: Radio ctrl (A) packet parse error - 
AssertionError: packet_info.packet_count == (seq_to_ack & 0xfff)

  in uint64_t radio_ctrl_core_3000_impl::wait_for_ack(bool)
  at 
/home/ulak/uhd/uhd/host/lib/usrp/cores/radio_ctrl_core_3000.cpp:264
Error: EnvironmentError: IOError: Radio ctrl (A) packet parse error - 
AssertionError: packet_info.packet_count == (seq_to_ack & 0xfff)

  in uint64_t radio_ctrl_core_3000_impl::wait_for_ack(bool)
  at /home/ulak/uhd/uhd/host/lib/usrp/cores/radio_ctrl_core_3000.cpp:264

---


By the way, we have bought CBX 120MHz daughterboards instead of CBX 
40MHz but would that actually create any problems? I thought it is 
just the RF difference but maybe some configuration is necessary from 
the drivers?



Then we downloaded and compiled the latest UHD version:


---

[PHY]   UHD version3.13.1.HEAD-0-gbbce3e45 (3.13.1)
[PHY]   Checking for USRP with args 
type=x300,addr=10.10.1.5,master_clock_rate=184.32e6,fpga=HG
[INFO] [UHD] linux; GNU C++ version 5.4.0 20160609; Boost_105800; 
UHD_3.13.1.HEAD-0-gbbce3e45

Found USRP x300
Found USRP x300
[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Maximum frame size: 8000 bytes.
[INFO] [X300] Radio 1x clock: 184.32 MHz
[INFO] [0/DmaFIFO_0] Initializing block control (NOC ID: 
0xF1F0D000)

[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1301 MB/s)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1309 MB/s)
[INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD1001)
[INFO] [0/Radio_1] Initializing block control (NOC ID: 0x12AD1001)
[INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0)
[INFO] [0/DDC_1] Initializing block control (NOC ID: 0xDDC0)
[INFO] [0/DUC_0] Initializing block control (NOC ID: 0xD0C0)
[INFO] [0/DUC_1] Initializing block control (NOC ID: 0xD0C0)
[PHY]   ru_thread_prach() RACH waiting for RU to be configured
[PHY]   device_init() sample_rate:6144
[WARNING] [RFNOC] The requested decimation is odd; the user should 
expect passband CIC rolloff.

Select an even decimation to ensure that a halfband filter is enabled.
Decimations factorable by 4 will enable 2 halfbands, those factorable 
by 8 will enable 3 halfbands.

decimation = dsp_rate/samp_rate -> 3 = (184.32 MHz)/(61.44 MHz)

[PHY]   cal 0: freq 35.00, offset 77.00, diff 
2262291232.00
[PHY]   cal 1: freq 266000.00, offset 81.00, diff 
1422291232.00
[PHY]   cal 2: freq 23.00, offset 81.00, diff 
1062291232.00
[PHY]   cal 3: freq 188000.00, offset 82.00, diff 
642291232.00
[PHY]   cal 4: freq 81600.00, offset 85.00, diff 
421708768.00

[PHY]   RX 

Re: [USRP-users] USRP X310 Remote Configuration

2018-08-03 Thread Michael West via USRP-users
To expand on #2, the TX is limited by the 10 GbE link and the DRAM
bandwidth.  The 10 GbE link limitation is resolved by using both SFP+ ports
as 10 GbE ports.  The DRAM limitation is not so easy to overcome.  The DRAM
bandwidth is ~600 Msps, but it is used as a FIFO, so the bandwidth is cut
in half to ~300 Msps.  That bandwidth is shared by all TX channels, which
is the true limitation of the TX rate.  If a custom RFNoC replay block is
created in place of the DMA FIFO, the full 200 Msps bandwidth per channel
is available.

Regarding #3, there is an example RFNoC replay block in the works.  I
cannot say exactly when it will be available, but it will probably be
fairly soon.  I have been told a month or so.

Regards,
Michael

On Tue, Jul 31, 2018 at 7:41 AM, Rob Kossler via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hi Farnaz,
> Regarding #1, the USRP can be either Tx, Rx, or both, but it does not
> affect maximum streaming rates.  The 10Gbe link is bi-directional and can
> handle a maximum of 300 MS/s on a single link in both directions.  You can
> use both links such that you can receive both channels of the X310 at 200
> MS/s.
>
> Regarding #2, yes.  The USRP itself perhaps can handle the 200 MS/s per
> channel on transmit, but the PC just can't keep the streaming at that rate
> without hiccups.  The best you can get is 100 MS/s per channel on Tx.
>
> Regarding 3, not sure.
>
> Rob
>
> On Tue, Jul 31, 2018 at 10:34 AM Farnaz Chamanzadeh 
> wrote:
>
>> Dear Rob,
>>
>> 1. Can you explain if the USRP may be configured only in receive/transmit
>> mode or is it also possible to configure in a single mode (a pure
>> transmitter or a pure receiver) using both optical interfaces for the task?
>>
>> 2. In the first remark in your email, you mentioned that the
>> host-to-USRP streaming does not work at 200 MS/s for the transmit case.
>> Does it mean that in the  USRP-to-host mode it supports 200MS/s  per
>> channel in receiving mode while the host to USRP supports only 100MS/s
>> per channel?
>>
>> 3. About storing the samples on the USRP, does anyone know that if Ettus
>> has any plans to add this capability to the USRPs?
>>
>>
>> Best,
>> Farnaz
>>
>> On Mon, Jul 30, 2018 at 6:27 PM, Jason Matusiak <
>> ja...@gardettoengineering.com> wrote:
>>
>>> I've actually done this with success, unfortunately, I am not allowed to
>>> share it :(.  It wasn't too hard, I used a core in the block to hold the
>>> data, and then I just repeated it when I sent it out over and over.
>>>
>>> The catch was that there was a little bit of an issue within rfnoc at
>>> the time (you can see mailing lists conversations from back then in the
>>> archives) that kept it from kicking off at startup (an enable switch worked
>>> fine though).  Jonathon P helped with a patch to get me going, but that
>>> obviously has been mainlined by now since they have a siggen working (it
>>> didn't exist yet when I did my block).  The issue had something to do with
>>> the block sending data before everything have been initialized and came up
>>> properly.
>>>
>>> So it isn't too bad to create one.  Good luck!
>>>
>>>
>>>
>>> - Original Message -
>>> Subject: Re: [USRP-users] USRP X310 Remote Configuration
>>> From: "Rob Kossler via USRP-users" 
>>> Date: 7/30/18 9:33 am
>>> To: "Farnaz Chamanzadeh" 
>>> Cc: "usrp-users" 
>>>
>>> Perhaps look at the RFNoC siggen block. You will need to add some
>>> component such as a block memory or fifo to store the samples on the fpga
>>> and then you will need a way to populate the memory and then play it out
>>> when desired.
>>>
>>> Rob
>>>
>>> On Mon, Jul 30, 2018 at 3:49 AM Farnaz Chamanzadeh <
>>> farnaz.c...@gmail.com> wrote:
>>>
>>>> Dear Rob,
>>>> Thanks for your helpful response. The reason that we need to use a
>>>> switch is due to hour host hardware limits, which only have one 10GBE.
>>>> About the second remark in your email, do you have an example or a
>>>> reference where a similar case was implemented which we can use  as a
>>>> guideline for our implementation?
>>>>
>>>> Best regards,
>>>> Farnaz
>>>>
>>>> On Thu, Jul 26, 2018 at 7:52 PM, Rob Kossler  wrote:
>>>>
>>>>> Hi Farnaz,
>>>>> A couple of remarks and questions
>>>>> - Remark

Re: [USRP-users] USRP X310 Remote Configuration

2018-07-31 Thread Rob Kossler via USRP-users
Hi Farnaz,
Regarding #1, the USRP can be either Tx, Rx, or both, but it does not
affect maximum streaming rates.  The 10Gbe link is bi-directional and can
handle a maximum of 300 MS/s on a single link in both directions.  You can
use both links such that you can receive both channels of the X310 at 200
MS/s.

Regarding #2, yes.  The USRP itself perhaps can handle the 200 MS/s per
channel on transmit, but the PC just can't keep the streaming at that rate
without hiccups.  The best you can get is 100 MS/s per channel on Tx.

Regarding 3, not sure.

Rob

On Tue, Jul 31, 2018 at 10:34 AM Farnaz Chamanzadeh 
wrote:

> Dear Rob,
>
> 1. Can you explain if the USRP may be configured only in receive/transmit
> mode or is it also possible to configure in a single mode (a pure
> transmitter or a pure receiver) using both optical interfaces for the task?
>
> 2. In the first remark in your email, you mentioned that the host-to-USRP
> streaming does not work at 200 MS/s for the transmit case. Does it mean
> that in the  USRP-to-host mode it supports 200MS/s  per channel in
> receiving mode while the host to USRP supports only 100MS/s per channel?
>
> 3. About storing the samples on the USRP, does anyone know that if Ettus
> has any plans to add this capability to the USRPs?
>
>
> Best,
> Farnaz
>
> On Mon, Jul 30, 2018 at 6:27 PM, Jason Matusiak <
> ja...@gardettoengineering.com> wrote:
>
>> I've actually done this with success, unfortunately, I am not allowed to
>> share it :(.  It wasn't too hard, I used a core in the block to hold the
>> data, and then I just repeated it when I sent it out over and over.
>>
>> The catch was that there was a little bit of an issue within rfnoc at the
>> time (you can see mailing lists conversations from back then in the
>> archives) that kept it from kicking off at startup (an enable switch worked
>> fine though).  Jonathon P helped with a patch to get me going, but that
>> obviously has been mainlined by now since they have a siggen working (it
>> didn't exist yet when I did my block).  The issue had something to do with
>> the block sending data before everything have been initialized and came up
>> properly.
>>
>> So it isn't too bad to create one.  Good luck!
>>
>>
>>
>> - Original Message -
>> Subject: Re: [USRP-users] USRP X310 Remote Configuration
>> From: "Rob Kossler via USRP-users" 
>> Date: 7/30/18 9:33 am
>> To: "Farnaz Chamanzadeh" 
>> Cc: "usrp-users" 
>>
>> Perhaps look at the RFNoC siggen block. You will need to add some
>> component such as a block memory or fifo to store the samples on the fpga
>> and then you will need a way to populate the memory and then play it out
>> when desired.
>>
>> Rob
>>
>> On Mon, Jul 30, 2018 at 3:49 AM Farnaz Chamanzadeh 
>> wrote:
>>
>>> Dear Rob,
>>> Thanks for your helpful response. The reason that we need to use a
>>> switch is due to hour host hardware limits, which only have one 10GBE.
>>> About the second remark in your email, do you have an example or a
>>> reference where a similar case was implemented which we can use  as a
>>> guideline for our implementation?
>>>
>>> Best regards,
>>> Farnaz
>>>
>>> On Thu, Jul 26, 2018 at 7:52 PM, Rob Kossler  wrote:
>>>
>>>> Hi Farnaz,
>>>> A couple of remarks and questions
>>>> - Remark 1: in order to get 200 MS/s transmit streaming, you will NEED
>>>> to have the samples on the USRP. The host-to-USRP streaming does not work
>>>> at 200 MS/s for the transmit case (unless something has recently changed).
>>>> The host-to-USRP max for transmit is 100 MS/s per channel
>>>> - Remark 2: that leads into your question about having the samples
>>>> stored on the USRP rather than streamed from host.  This is not presently a
>>>> capability, but can be added with some modest FPGA work.  I have been
>>>> desiring such capability for a couple of years - I hope that Ettus adds
>>>> such capability in the future.
>>>> - Question 1: why do you plan to use a 10gbe switch with a single
>>>> connection to the host PC?  Why not have multiple 10Gbe links at the PC
>>>> which connect to each USRP individually.  A NIC such as Intel XL-710
>>>> provides 4 10gbe links.
>>>>
>>>> Rob
>>>>
>>>>
>>>> On Thu, Jul 26, 2018 at 12:13 PM Farnaz Chamanzadeh via USRP-users <
>>>> usrp-users@lists.ettus.com> wrote:
>>&g

Re: [USRP-users] USRP X310 Remote Configuration

2018-07-31 Thread Farnaz Chamanzadeh via USRP-users
Dear Rob,

1. Can you explain if the USRP may be configured only in receive/transmit
mode or is it also possible to configure in a single mode (a pure
transmitter or a pure receiver) using both optical interfaces for the task?

2. In the first remark in your email, you mentioned that the host-to-USRP
streaming does not work at 200 MS/s for the transmit case. Does it mean
that in the  USRP-to-host mode it supports 200MS/s  per channel in
receiving mode while the host to USRP supports only 100MS/s per channel?

3. About storing the samples on the USRP, does anyone know that if Ettus
has any plans to add this capability to the USRPs?


Best,
Farnaz

On Mon, Jul 30, 2018 at 6:27 PM, Jason Matusiak <
ja...@gardettoengineering.com> wrote:

> I've actually done this with success, unfortunately, I am not allowed to
> share it :(.  It wasn't too hard, I used a core in the block to hold the
> data, and then I just repeated it when I sent it out over and over.
>
> The catch was that there was a little bit of an issue within rfnoc at the
> time (you can see mailing lists conversations from back then in the
> archives) that kept it from kicking off at startup (an enable switch worked
> fine though).  Jonathon P helped with a patch to get me going, but that
> obviously has been mainlined by now since they have a siggen working (it
> didn't exist yet when I did my block).  The issue had something to do with
> the block sending data before everything have been initialized and came up
> properly.
>
> So it isn't too bad to create one.  Good luck!
>
>
>
> - Original Message -
> Subject: Re: [USRP-users] USRP X310 Remote Configuration
> From: "Rob Kossler via USRP-users" 
> Date: 7/30/18 9:33 am
> To: "Farnaz Chamanzadeh" 
> Cc: "usrp-users" 
>
> Perhaps look at the RFNoC siggen block. You will need to add some
> component such as a block memory or fifo to store the samples on the fpga
> and then you will need a way to populate the memory and then play it out
> when desired.
>
> Rob
>
> On Mon, Jul 30, 2018 at 3:49 AM Farnaz Chamanzadeh 
> wrote:
>
>> Dear Rob,
>> Thanks for your helpful response. The reason that we need to use a switch
>> is due to hour host hardware limits, which only have one 10GBE.
>> About the second remark in your email, do you have an example or a
>> reference where a similar case was implemented which we can use  as a
>> guideline for our implementation?
>>
>> Best regards,
>> Farnaz
>>
>> On Thu, Jul 26, 2018 at 7:52 PM, Rob Kossler  wrote:
>>
>>> Hi Farnaz,
>>> A couple of remarks and questions
>>> - Remark 1: in order to get 200 MS/s transmit streaming, you will NEED
>>> to have the samples on the USRP. The host-to-USRP streaming does not work
>>> at 200 MS/s for the transmit case (unless something has recently changed).
>>> The host-to-USRP max for transmit is 100 MS/s per channel
>>> - Remark 2: that leads into your question about having the samples
>>> stored on the USRP rather than streamed from host.  This is not presently a
>>> capability, but can be added with some modest FPGA work.  I have been
>>> desiring such capability for a couple of years - I hope that Ettus adds
>>> such capability in the future.
>>> - Question 1: why do you plan to use a 10gbe switch with a single
>>> connection to the host PC?  Why not have multiple 10Gbe links at the PC
>>> which connect to each USRP individually.  A NIC such as Intel XL-710
>>> provides 4 10gbe links.
>>>
>>> Rob
>>>
>>>
>>> On Thu, Jul 26, 2018 at 12:13 PM Farnaz Chamanzadeh via USRP-users <
>>> usrp-users@lists.ettus.com> wrote:
>>>
>>>> Dears,
>>>>
>>>> To be more specific, we want to control multiple USRPs with one
>>>> (remote) computer. We would like to stream known and periodic signal from
>>>> each USRP. The sequence on each USRP is unique and is different from other
>>>> USRPs.
>>>>
>>>>  Since the samples from each USRP are known, it would be more
>>>> convenient if we can generate the samples once and preferably store them
>>>> locally on each USRP. In this configuration,  we want to use the host
>>>> computer to send control commands to the USRPs specifying when each of them
>>>> must transmit its specific samples. The USRPs are assumed to be
>>>> synchronized, so the control commands from the host will generate a TDMA
>>>> scheme. Each USRP will start signal transmission upon receiving the control
>>>> command fro

Re: [USRP-users] USRP X310 Remote Configuration

2018-07-30 Thread Jason Matusiak via USRP-users
I've actually done this with success, unfortunately, I am not allowed to share 
it :(.  It wasn't too hard, I used a core in the block to hold the data, and 
then I just repeated it when I sent it out over and over.
 
The catch was that there was a little bit of an issue within rfnoc at the time 
(you can see mailing lists conversations from back then in the archives) that 
kept it from kicking off at startup (an enable switch worked fine though).  
Jonathon P helped with a patch to get me going, but that obviously has been 
mainlined by now since they have a siggen working (it didn't exist yet when I 
did my block).  The issue had something to do with the block sending data 
before everything have been initialized and came up properly.
 
So it isn't too bad to create one.  Good luck!
 
 
- Original Message ----- Subject: Re: [USRP-users] USRP X310 Remote 
Configuration
From: "Rob Kossler via USRP-users" 
Date: 7/30/18 9:33 am
To: "Farnaz Chamanzadeh" 
Cc: "usrp-users" 

 Perhaps look at the RFNoC siggen block. You will need to add some component 
such as a block memory or fifo to store the samples on the fpga and then you 
will need a way to populate the memory and then play it out when desired.
Rob


  On Mon, Jul 30, 2018 at 3:49 AM Farnaz Chamanzadeh  
wrote:
 Dear Rob,  Thanks for your helpful response. The reason that we need to use a 
switch is due to hour host hardware limits, which only have one 10GBE. 
About the second remark in your email, do you have an example or a reference 
where a similar case was implemented which we can use  as a guideline for our 
implementation? 
 
Best regards,
Farnaz


 On Thu, Jul 26, 2018 at 7:52 PM, Rob Kossler  wrote:
  Hi Farnaz, A couple of remarks and questions
- Remark 1: in order to get 200 MS/s transmit streaming, you will NEED to have 
the samples on the USRP. The host-to-USRP streaming does not work at 200 MS/s 
for the transmit case (unless something has recently changed). The host-to-USRP 
max for transmit is 100 MS/s per channel
- Remark 2: that leads into your question about having the samples stored on 
the USRP rather than streamed from host.  This is not presently a capability, 
but can be added with some modest FPGA work.  I have been desiring such 
capability for a couple of years - I hope that Ettus adds such capability in 
the future.
- Question 1: why do you plan to use a 10gbe switch with a single connection to 
the host PC?  Why not have multiple 10Gbe links at the PC which connect to each 
USRP individually.  A NIC such as Intel XL-710 provides 4 10gbe links.
 
Rob
 


  On Thu, Jul 26, 2018 at 12:13 PM Farnaz Chamanzadeh via USRP-users 
 wrote:
 Dears,  
To be more specific, we want to control multiple USRPs with one (remote) 
computer. We would like to stream known and periodic signal from each USRP. The 
sequence on each USRP is unique and is different from other USRPs. 
 
 Since the samples from each USRP are known, it would be more convenient if we 
can generate the samples once and preferably store them locally on each USRP. 
In this configuration,  we want to use the host computer to send control 
commands to the USRPs specifying when each of them must transmit its specific 
samples. The USRPs are assumed to be synchronized, so the control commands from 
the host will generate a TDMA scheme. Each USRP will start signal transmission 
upon receiving the control command from the host computer. I would like to know 
that:
 
1. Is it possible to store the samples on the USRPs? or should we stream the 
samples from the host computer to the USRPs for each transmission?
2.  Can we use the full bandwidth and 200MS/s in this setup?  
3. After knowing the answer to the previous question,  I would like to know how 
we can implement it? do you happen to have a demo or an example that can guide 
us in this implementation? 
 
Best,
Farnaz
 
 
 
 
 

 On Wed, Jun 27, 2018 at 4:50 AM, Michael West  wrote:
   Hi Farnaz,
 
To clarify and expand on Marcus' comments, the answer is maybe.  You can do 
burst captures and transmissions at full rate and you can even use timed 
commands to synchronize them, but there are limitations.  If you can describe 
in more detail what you want to do, we can more clearly tell you if it is 
possible.  How many channels do you plan to do simultaneously?  How many 10 GbE 
connections between the host and switch?  How many 10 GbE connections between 
each USRP and the switch?
 
There is buffering of the TX samples on the X310 and it is configurable.  The 
current default is 32 MB.  The DRAM is a total of 1 GB, and it can be divided 
up however necessary.
 
Regards,
Michael


 On Mon, Jun 25, 2018 at 12:23 PM, Marcus Müller via USRP-users 
 wrote:
 Dear Fernaz,
 
 you can't cheat 10Gig bandwidth! If you time-share any medium, then
 it's bandwidth must be shared. Since ethernet is de facto a timesharing
 thing, anyway, no, this won't work

Re: [USRP-users] USRP X310 Remote Configuration

2018-07-30 Thread Rob Kossler via USRP-users
Perhaps look at the RFNoC siggen block. You will need to add some component
such as a block memory or fifo to store the samples on the fpga and then
you will need a way to populate the memory and then play it out when
desired.

Rob

On Mon, Jul 30, 2018 at 3:49 AM Farnaz Chamanzadeh 
wrote:

> Dear Rob,
> Thanks for your helpful response. The reason that we need to use a switch
> is due to hour host hardware limits, which only have one 10GBE.
> About the second remark in your email, do you have an example or a
> reference where a similar case was implemented which we can use  as a
> guideline for our implementation?
>
> Best regards,
> Farnaz
>
> On Thu, Jul 26, 2018 at 7:52 PM, Rob Kossler  wrote:
>
>> Hi Farnaz,
>> A couple of remarks and questions
>> - Remark 1: in order to get 200 MS/s transmit streaming, you will NEED to
>> have the samples on the USRP. The host-to-USRP streaming does not work at
>> 200 MS/s for the transmit case (unless something has recently changed). The
>> host-to-USRP max for transmit is 100 MS/s per channel
>> - Remark 2: that leads into your question about having the samples stored
>> on the USRP rather than streamed from host.  This is not presently a
>> capability, but can be added with some modest FPGA work.  I have been
>> desiring such capability for a couple of years - I hope that Ettus adds
>> such capability in the future.
>> - Question 1: why do you plan to use a 10gbe switch with a single
>> connection to the host PC?  Why not have multiple 10Gbe links at the PC
>> which connect to each USRP individually.  A NIC such as Intel XL-710
>> provides 4 10gbe links.
>>
>> Rob
>>
>>
>> On Thu, Jul 26, 2018 at 12:13 PM Farnaz Chamanzadeh via USRP-users <
>> usrp-users@lists.ettus.com> wrote:
>>
>>> Dears,
>>>
>>> To be more specific, we want to control multiple USRPs with one (remote)
>>> computer. We would like to stream known and periodic signal from each USRP.
>>> The sequence on each USRP is unique and is different from other USRPs.
>>>
>>>  Since the samples from each USRP are known, it would be more
>>> convenient if we can generate the samples once and preferably store them
>>> locally on each USRP. In this configuration,  we want to use the host
>>> computer to send control commands to the USRPs specifying when each of them
>>> must transmit its specific samples. The USRPs are assumed to be
>>> synchronized, so the control commands from the host will generate a TDMA
>>> scheme. Each USRP will start signal transmission upon receiving the control
>>> command from the host computer. I would like to know that:
>>>
>>> 1. Is it possible to store the samples on the USRPs? or should we stream
>>> the samples from the host computer to the USRPs for each transmission?
>>> 2.  Can we use the full bandwidth and 200MS/s in this setup?
>>> 3. After knowing the answer to the previous question,  I would like to
>>> know how we can implement it? do you happen to have a demo or an example
>>> that can guide us in this implementation?
>>>
>>> Best,
>>> Farnaz
>>>
>>>
>>>
>>>
>>>
>>>
>>> On Wed, Jun 27, 2018 at 4:50 AM, Michael West 
>>> wrote:
>>>
 Hi Farnaz,

 To clarify and expand on Marcus' comments, the answer is maybe.  You
 can do burst captures and transmissions at full rate and you can even use
 timed commands to synchronize them, but there are limitations.  If you can
 describe in more detail what you want to do, we can more clearly tell you
 if it is possible.  How many channels do you plan to do simultaneously?
 How many 10 GbE connections between the host and switch?  How many 10 GbE
 connections between each USRP and the switch?

 There is buffering of the TX samples on the X310 and it is
 configurable.  The current default is 32 MB.  The DRAM is a total of 1 GB,
 and it can be divided up however necessary.

 Regards,
 Michael

 On Mon, Jun 25, 2018 at 12:23 PM, Marcus Müller via USRP-users <
 usrp-users@lists.ettus.com> wrote:

> Dear Fernaz,
>
> you can't cheat 10Gig bandwidth! If you time-share any medium, then
> it's bandwidth must be shared. Since ethernet is de facto a timesharing
> thing, anyway, no, this won't work:
> Since you need to push through all the data through a single 10GigE
> connection, your 10 gigabits per second need to be divided along *all
> simultaneously operating* USRPs. So, if you have, say 10 USRPs, and all
> should be working at the same time, you've only got 1 gigabit per
> second per USRP, which limits you to about 25 MSample/s per USRP. It's
> really the same principle as a single internet access being shared by
> all people attached to the same router.
>
> Now, if these USRPs *don't* have to transmit all at the same time, then
> more is possible.
>
> > Also, does anyone know if it is possible to store the samples on the
> transmit USRPs?
>
> I'll go with a: no, at least probably not 

Re: [USRP-users] USRP X310 Remote Configuration

2018-07-30 Thread Farnaz Chamanzadeh via USRP-users
Dear Rob,
Thanks for your helpful response. The reason that we need to use a switch
is due to hour host hardware limits, which only have one 10GBE.
About the second remark in your email, do you have an example or a
reference where a similar case was implemented which we can use  as a
guideline for our implementation?

Best regards,
Farnaz

On Thu, Jul 26, 2018 at 7:52 PM, Rob Kossler  wrote:

> Hi Farnaz,
> A couple of remarks and questions
> - Remark 1: in order to get 200 MS/s transmit streaming, you will NEED to
> have the samples on the USRP. The host-to-USRP streaming does not work at
> 200 MS/s for the transmit case (unless something has recently changed). The
> host-to-USRP max for transmit is 100 MS/s per channel
> - Remark 2: that leads into your question about having the samples stored
> on the USRP rather than streamed from host.  This is not presently a
> capability, but can be added with some modest FPGA work.  I have been
> desiring such capability for a couple of years - I hope that Ettus adds
> such capability in the future.
> - Question 1: why do you plan to use a 10gbe switch with a single
> connection to the host PC?  Why not have multiple 10Gbe links at the PC
> which connect to each USRP individually.  A NIC such as Intel XL-710
> provides 4 10gbe links.
>
> Rob
>
>
> On Thu, Jul 26, 2018 at 12:13 PM Farnaz Chamanzadeh via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Dears,
>>
>> To be more specific, we want to control multiple USRPs with one (remote)
>> computer. We would like to stream known and periodic signal from each USRP.
>> The sequence on each USRP is unique and is different from other USRPs.
>>
>>  Since the samples from each USRP are known, it would be more
>> convenient if we can generate the samples once and preferably store them
>> locally on each USRP. In this configuration,  we want to use the host
>> computer to send control commands to the USRPs specifying when each of them
>> must transmit its specific samples. The USRPs are assumed to be
>> synchronized, so the control commands from the host will generate a TDMA
>> scheme. Each USRP will start signal transmission upon receiving the control
>> command from the host computer. I would like to know that:
>>
>> 1. Is it possible to store the samples on the USRPs? or should we stream
>> the samples from the host computer to the USRPs for each transmission?
>> 2.  Can we use the full bandwidth and 200MS/s in this setup?
>> 3. After knowing the answer to the previous question,  I would like to
>> know how we can implement it? do you happen to have a demo or an example
>> that can guide us in this implementation?
>>
>> Best,
>> Farnaz
>>
>>
>>
>>
>>
>>
>> On Wed, Jun 27, 2018 at 4:50 AM, Michael West 
>> wrote:
>>
>>> Hi Farnaz,
>>>
>>> To clarify and expand on Marcus' comments, the answer is maybe.  You can
>>> do burst captures and transmissions at full rate and you can even use timed
>>> commands to synchronize them, but there are limitations.  If you can
>>> describe in more detail what you want to do, we can more clearly tell you
>>> if it is possible.  How many channels do you plan to do simultaneously?
>>> How many 10 GbE connections between the host and switch?  How many 10 GbE
>>> connections between each USRP and the switch?
>>>
>>> There is buffering of the TX samples on the X310 and it is
>>> configurable.  The current default is 32 MB.  The DRAM is a total of 1 GB,
>>> and it can be divided up however necessary.
>>>
>>> Regards,
>>> Michael
>>>
>>> On Mon, Jun 25, 2018 at 12:23 PM, Marcus Müller via USRP-users <
>>> usrp-users@lists.ettus.com> wrote:
>>>
 Dear Fernaz,

 you can't cheat 10Gig bandwidth! If you time-share any medium, then
 it's bandwidth must be shared. Since ethernet is de facto a timesharing
 thing, anyway, no, this won't work:
 Since you need to push through all the data through a single 10GigE
 connection, your 10 gigabits per second need to be divided along *all
 simultaneously operating* USRPs. So, if you have, say 10 USRPs, and all
 should be working at the same time, you've only got 1 gigabit per
 second per USRP, which limits you to about 25 MSample/s per USRP. It's
 really the same principle as a single internet access being shared by
 all people attached to the same router.

 Now, if these USRPs *don't* have to transmit all at the same time, then
 more is possible.

 > Also, does anyone know if it is possible to store the samples on the
 transmit USRPs?

 I'll go with a: no, at least probably not like you hope it is. Can you
 elaborate on your use case? Maybe we can help you if we better
 understand what you're trying to implement, from a bit of distance?

 Best regards,
 Marcus

 On Mon, 2018-06-25 at 20:32 +0200, Farnaz Chamanzadeh via USRP-users
 wrote:
 > Dear all,
 >
 >  I want to connect multiple USRP X310 to one host PC and control them
 > all 

Re: [USRP-users] USRP X310 Remote Configuration

2018-07-26 Thread Rob Kossler via USRP-users
Hi Farnaz,
A couple of remarks and questions
- Remark 1: in order to get 200 MS/s transmit streaming, you will NEED to
have the samples on the USRP. The host-to-USRP streaming does not work at
200 MS/s for the transmit case (unless something has recently changed). The
host-to-USRP max for transmit is 100 MS/s per channel
- Remark 2: that leads into your question about having the samples stored
on the USRP rather than streamed from host.  This is not presently a
capability, but can be added with some modest FPGA work.  I have been
desiring such capability for a couple of years - I hope that Ettus adds
such capability in the future.
- Question 1: why do you plan to use a 10gbe switch with a single
connection to the host PC?  Why not have multiple 10Gbe links at the PC
which connect to each USRP individually.  A NIC such as Intel XL-710
provides 4 10gbe links.

Rob


On Thu, Jul 26, 2018 at 12:13 PM Farnaz Chamanzadeh via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Dears,
>
> To be more specific, we want to control multiple USRPs with one (remote)
> computer. We would like to stream known and periodic signal from each USRP.
> The sequence on each USRP is unique and is different from other USRPs.
>
>  Since the samples from each USRP are known, it would be more
> convenient if we can generate the samples once and preferably store them
> locally on each USRP. In this configuration,  we want to use the host
> computer to send control commands to the USRPs specifying when each of them
> must transmit its specific samples. The USRPs are assumed to be
> synchronized, so the control commands from the host will generate a TDMA
> scheme. Each USRP will start signal transmission upon receiving the control
> command from the host computer. I would like to know that:
>
> 1. Is it possible to store the samples on the USRPs? or should we stream
> the samples from the host computer to the USRPs for each transmission?
> 2.  Can we use the full bandwidth and 200MS/s in this setup?
> 3. After knowing the answer to the previous question,  I would like to
> know how we can implement it? do you happen to have a demo or an example
> that can guide us in this implementation?
>
> Best,
> Farnaz
>
>
>
>
>
>
> On Wed, Jun 27, 2018 at 4:50 AM, Michael West 
> wrote:
>
>> Hi Farnaz,
>>
>> To clarify and expand on Marcus' comments, the answer is maybe.  You can
>> do burst captures and transmissions at full rate and you can even use timed
>> commands to synchronize them, but there are limitations.  If you can
>> describe in more detail what you want to do, we can more clearly tell you
>> if it is possible.  How many channels do you plan to do simultaneously?
>> How many 10 GbE connections between the host and switch?  How many 10 GbE
>> connections between each USRP and the switch?
>>
>> There is buffering of the TX samples on the X310 and it is configurable.
>> The current default is 32 MB.  The DRAM is a total of 1 GB, and it can be
>> divided up however necessary.
>>
>> Regards,
>> Michael
>>
>> On Mon, Jun 25, 2018 at 12:23 PM, Marcus Müller via USRP-users <
>> usrp-users@lists.ettus.com> wrote:
>>
>>> Dear Fernaz,
>>>
>>> you can't cheat 10Gig bandwidth! If you time-share any medium, then
>>> it's bandwidth must be shared. Since ethernet is de facto a timesharing
>>> thing, anyway, no, this won't work:
>>> Since you need to push through all the data through a single 10GigE
>>> connection, your 10 gigabits per second need to be divided along *all
>>> simultaneously operating* USRPs. So, if you have, say 10 USRPs, and all
>>> should be working at the same time, you've only got 1 gigabit per
>>> second per USRP, which limits you to about 25 MSample/s per USRP. It's
>>> really the same principle as a single internet access being shared by
>>> all people attached to the same router.
>>>
>>> Now, if these USRPs *don't* have to transmit all at the same time, then
>>> more is possible.
>>>
>>> > Also, does anyone know if it is possible to store the samples on the
>>> transmit USRPs?
>>>
>>> I'll go with a: no, at least probably not like you hope it is. Can you
>>> elaborate on your use case? Maybe we can help you if we better
>>> understand what you're trying to implement, from a bit of distance?
>>>
>>> Best regards,
>>> Marcus
>>>
>>> On Mon, 2018-06-25 at 20:32 +0200, Farnaz Chamanzadeh via USRP-users
>>> wrote:
>>> > Dear all,
>>> >
>>> >  I want to connect multiple USRP X310 to one host PC and control them
>>> > all from that Pc, using one  10Gigabit Ethernet switch. My question
>>> > is that if it is possible to stream from each USRP in a different
>>> > time slot using the full bandwidth and 200MS/s in a setup similar to
>>> > the picture below?
>>> >
>>> > Also, does anyone know if it is possible to store the samples on the
>>> > transmit USRPs?
>>> >
>>> >
>>> >
>>> >
>>> > Best,
>>> > Farnaz
>>> >
>>> > ___
>>> > USRP-users mailing list
>>> > USRP-users@lists.ettus.com
>>> > http:

Re: [USRP-users] USRP X310 Remote Configuration

2018-07-26 Thread Farnaz Chamanzadeh via USRP-users
Dears,

To be more specific, we want to control multiple USRPs with one (remote)
computer. We would like to stream known and periodic signal from each USRP.
The sequence on each USRP is unique and is different from other USRPs.

 Since the samples from each USRP are known, it would be more convenient if
we can generate the samples once and preferably store them locally on each
USRP. In this configuration,  we want to use the host computer to send
control commands to the USRPs specifying when each of them must transmit
its specific samples. The USRPs are assumed to be synchronized, so the
control commands from the host will generate a TDMA scheme. Each USRP will
start signal transmission upon receiving the control command from the host
computer. I would like to know that:

1. Is it possible to store the samples on the USRPs? or should we stream
the samples from the host computer to the USRPs for each transmission?
2.  Can we use the full bandwidth and 200MS/s in this setup?
3. After knowing the answer to the previous question,  I would like to know
how we can implement it? do you happen to have a demo or an example that
can guide us in this implementation?

Best,
Farnaz






On Wed, Jun 27, 2018 at 4:50 AM, Michael West 
wrote:

> Hi Farnaz,
>
> To clarify and expand on Marcus' comments, the answer is maybe.  You can
> do burst captures and transmissions at full rate and you can even use timed
> commands to synchronize them, but there are limitations.  If you can
> describe in more detail what you want to do, we can more clearly tell you
> if it is possible.  How many channels do you plan to do simultaneously?
> How many 10 GbE connections between the host and switch?  How many 10 GbE
> connections between each USRP and the switch?
>
> There is buffering of the TX samples on the X310 and it is configurable.
> The current default is 32 MB.  The DRAM is a total of 1 GB, and it can be
> divided up however necessary.
>
> Regards,
> Michael
>
> On Mon, Jun 25, 2018 at 12:23 PM, Marcus Müller via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Dear Fernaz,
>>
>> you can't cheat 10Gig bandwidth! If you time-share any medium, then
>> it's bandwidth must be shared. Since ethernet is de facto a timesharing
>> thing, anyway, no, this won't work:
>> Since you need to push through all the data through a single 10GigE
>> connection, your 10 gigabits per second need to be divided along *all
>> simultaneously operating* USRPs. So, if you have, say 10 USRPs, and all
>> should be working at the same time, you've only got 1 gigabit per
>> second per USRP, which limits you to about 25 MSample/s per USRP. It's
>> really the same principle as a single internet access being shared by
>> all people attached to the same router.
>>
>> Now, if these USRPs *don't* have to transmit all at the same time, then
>> more is possible.
>>
>> > Also, does anyone know if it is possible to store the samples on the
>> transmit USRPs?
>>
>> I'll go with a: no, at least probably not like you hope it is. Can you
>> elaborate on your use case? Maybe we can help you if we better
>> understand what you're trying to implement, from a bit of distance?
>>
>> Best regards,
>> Marcus
>>
>> On Mon, 2018-06-25 at 20:32 +0200, Farnaz Chamanzadeh via USRP-users
>> wrote:
>> > Dear all,
>> >
>> >  I want to connect multiple USRP X310 to one host PC and control them
>> > all from that Pc, using one  10Gigabit Ethernet switch. My question
>> > is that if it is possible to stream from each USRP in a different
>> > time slot using the full bandwidth and 200MS/s in a setup similar to
>> > the picture below?
>> >
>> > Also, does anyone know if it is possible to store the samples on the
>> > transmit USRPs?
>> >
>> >
>> >
>> >
>> > Best,
>> > Farnaz
>> >
>> > ___
>> > USRP-users mailing list
>> > USRP-users@lists.ettus.com
>> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>> ___
>> USRP-users mailing list
>> USRP-users@lists.ettus.com
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>
>
___
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com


Re: [USRP-users] USRP X310 Remote Configuration

2018-06-26 Thread Michael West via USRP-users
Hi Farnaz,

To clarify and expand on Marcus' comments, the answer is maybe.  You can do
burst captures and transmissions at full rate and you can even use timed
commands to synchronize them, but there are limitations.  If you can
describe in more detail what you want to do, we can more clearly tell you
if it is possible.  How many channels do you plan to do simultaneously?
How many 10 GbE connections between the host and switch?  How many 10 GbE
connections between each USRP and the switch?

There is buffering of the TX samples on the X310 and it is configurable.
The current default is 32 MB.  The DRAM is a total of 1 GB, and it can be
divided up however necessary.

Regards,
Michael

On Mon, Jun 25, 2018 at 12:23 PM, Marcus Müller via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Dear Fernaz,
>
> you can't cheat 10Gig bandwidth! If you time-share any medium, then
> it's bandwidth must be shared. Since ethernet is de facto a timesharing
> thing, anyway, no, this won't work:
> Since you need to push through all the data through a single 10GigE
> connection, your 10 gigabits per second need to be divided along *all
> simultaneously operating* USRPs. So, if you have, say 10 USRPs, and all
> should be working at the same time, you've only got 1 gigabit per
> second per USRP, which limits you to about 25 MSample/s per USRP. It's
> really the same principle as a single internet access being shared by
> all people attached to the same router.
>
> Now, if these USRPs *don't* have to transmit all at the same time, then
> more is possible.
>
> > Also, does anyone know if it is possible to store the samples on the
> transmit USRPs?
>
> I'll go with a: no, at least probably not like you hope it is. Can you
> elaborate on your use case? Maybe we can help you if we better
> understand what you're trying to implement, from a bit of distance?
>
> Best regards,
> Marcus
>
> On Mon, 2018-06-25 at 20:32 +0200, Farnaz Chamanzadeh via USRP-users
> wrote:
> > Dear all,
> >
> >  I want to connect multiple USRP X310 to one host PC and control them
> > all from that Pc, using one  10Gigabit Ethernet switch. My question
> > is that if it is possible to stream from each USRP in a different
> > time slot using the full bandwidth and 200MS/s in a setup similar to
> > the picture below?
> >
> > Also, does anyone know if it is possible to store the samples on the
> > transmit USRPs?
> >
> >
> >
> >
> > Best,
> > Farnaz
> >
> > ___
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> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
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>
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Re: [USRP-users] USRP X310 Remote Configuration

2018-06-25 Thread Marcus Müller via USRP-users
Dear Fernaz,

you can't cheat 10Gig bandwidth! If you time-share any medium, then
it's bandwidth must be shared. Since ethernet is de facto a timesharing
thing, anyway, no, this won't work:
Since you need to push through all the data through a single 10GigE
connection, your 10 gigabits per second need to be divided along *all
simultaneously operating* USRPs. So, if you have, say 10 USRPs, and all
should be working at the same time, you've only got 1 gigabit per
second per USRP, which limits you to about 25 MSample/s per USRP. It's
really the same principle as a single internet access being shared by
all people attached to the same router.

Now, if these USRPs *don't* have to transmit all at the same time, then
more is possible.

> Also, does anyone know if it is possible to store the samples on the
transmit USRPs?

I'll go with a: no, at least probably not like you hope it is. Can you
elaborate on your use case? Maybe we can help you if we better
understand what you're trying to implement, from a bit of distance?

Best regards,
Marcus
  
On Mon, 2018-06-25 at 20:32 +0200, Farnaz Chamanzadeh via USRP-users
wrote:
> Dear all,
> 
>  I want to connect multiple USRP X310 to one host PC and control them
> all from that Pc, using one  10Gigabit Ethernet switch. My question
> is that if it is possible to stream from each USRP in a different
> time slot using the full bandwidth and 200MS/s in a setup similar to
> the picture below?
> 
> Also, does anyone know if it is possible to store the samples on the
> transmit USRPs?
> 
> 
> 
> 
> Best,
> Farnaz
> 
> ___
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> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

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Re: [USRP-users] USRP X310 Calibration error

2018-05-18 Thread Marcus Müller via USRP-users
Hi Kunal,

How did you install UHD? is there a chance you've got conflicting uhd 
installations, or updated parts of your system since you've built UHD yourself 
(if you did that)?

Best regards,
Marcus

On 17 May 2018 17:08:43 GMT+02:00, kunal sankhe via USRP-users 
 wrote:
>Hi,
>
>I am trying to measure IQ Imbalance of USRP X310 with UBX-160
>daughtboard
>
>After running *uhd_cal_rx_iq_balance*, I got following error:
>
>
>terminate called after throwing an instance of
>'boost::exception_detail::clone_impl
>>'
>what():  boost: mutex lock failed in pthread_mutex_lock: Invalid
>argument
>Aborted (core dumped)
>
>
>The output of USRP Probe is following:
>
>linux; GNU C++ version 5.4.0 20160609; Boost_105800;
>UHD_003.011.000.git-106-g1b70b3e7
>
>-- X300 initialization sequence...
>-- Determining maximum frame size... 1472 bytes.
>-- Setup basic communication...
>-- Loading values from EEPROM...
>-- Setup RF frontend clocking...
>-- Radio 1x clock:200
>-- Detecting internal GPSDO No GPSDO found
>-- [DMA FIFO] Running BIST for FIFO 0... pass (Throughput: 1304.3MB/s)
>-- [DMA FIFO] Running BIST for FIFO 1... pass (Throughput: 1309.5MB/s)
>-- [RFNoC Radio] Performing register loopback test... pass
>-- [RFNoC Radio] Performing register loopback test... pass
>-- [RFNoC Radio] Performing register loopback test... pass
>-- [RFNoC Radio] Performing register loopback test... pass
>-- Performing timer loopback test... pass
>-- Performing timer loopback test... pass
>  _
> /
>|   Device: X-Series Device
>| _
>|/
>|   |   Mboard: X310
>|   |   revision: 11
>|   |   revision_compat: 7
>|   |   product: 30818
>|   |   mac-addr0: 00:80:2f:17:6e:03
>|   |   mac-addr1: 00:80:2f:17:6e:04
>|   |   gateway: 192.168.10.1
>|   |   ip-addr0: 192.168.10.2
>|   |   subnet0: 255.255.255.0
>|   |   ip-addr1: 192.168.20.2
>|   |   subnet1: 255.255.255.0
>|   |   ip-addr2: 192.168.30.2
>|   |   subnet2: 255.255.255.0
>|   |   ip-addr3: 192.168.40.2
>|   |   subnet3: 255.255.255.0
>|   |   serial: 3123D76
>|   |   FW Version: 5.1
>|   |   FPGA Version: 33.0
>|   |   RFNoC capable: Yes
>|   |
>|   |   Time sources:  internal, external, gpsdo
>|   |   Clock sources: internal, external, gpsdo
>|   |   Sensors: ref_locked
>|   | _
>|   |/
>|   |   |   RX Dboard: A
>|   |   |   ID: UBX-160 v2 (0x007e)
>|   |   |   Serial: 312289F
>|   |   | _
>|   |   |/
>|   |   |   |   RX Frontend: 0
>|   |   |   |   Name: UBX RX
>|   |   |   |   Antennas: TX/RX, RX2, CAL
>|   |   |   |   Sensors: lo_locked
>|   |   |   |   Freq range: 10.000 to 6000.000 MHz
>|   |   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
>|   |   |   |   Bandwidth range: 16000.0 to 16000.0 step 0.0 Hz
>|   |   |   |   Connection Type: IQ
>|   |   |   |   Uses LO offset: No
>|   |   | _
>|   |   |/
>|   |   |   |   RX Codec: A
>|   |   |   |   Name: ads62p48
>|   |   |   |   Gain range digital: 0.0 to 6.0 step 0.5 dB
>|   | _
>|   |/
>|   |   |   RX Dboard: B
>|   |   | _
>|   |   |/
>|   |   |   |   RX Frontend: 0
>|   |   |   |   Name: Unknown (0x) - 0
>|   |   |   |   Antennas:
>|   |   |   |   Sensors:
>|   |   |   |   Freq range: 0.000 to 0.000 MHz
>|   |   |   |   Gain Elements: None
>|   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz
>|   |   |   |   Connection Type: IQ
>|   |   |   |   Uses LO offset: No
>|   |   | _
>|   |   |/
>|   |   |   |   RX Codec: B
>|   |   |   |   Name: ads62p48
>|   |   |   |   Gain range digital: 0.0 to 6.0 step 0.5 dB
>|   | _
>|   |/
>|   |   |   TX Dboard: A
>|   |   |   ID: UBX-160 v2 (0x007d)
>|   |   |   Serial: 312289F
>|   |   | _
>|   |   |/
>|   |   |   |   TX Frontend: 0
>|   |   |   |   Name: UBX TX
>|   |   |   |   Antennas: TX/RX, CAL
>|   |   |   |   Sensors: lo_locked
>|   |   |   |   Freq range: 10.000 to 6000.000 MHz
>|   |   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
>|   |   |   |   Bandwidth range: 16000.0 to 16000.0 step 0.0 Hz
>|   |   |   |   Connection Type: QI
>|   |   |   |   Uses LO offset: No
>|   |   | _
>|   |   |/
>|   |   |   |   TX Codec: A
>|   |   |   |   Name: ad9146
>|   |   |   |   Gain Elements: None
>|   | _
>|   |/
>|   |   |   TX Dboard: B
>|   |   | _
>|   |   |/

Re: [USRP-users] USRP X310 External reference power level

2017-09-04 Thread Marcus D. Leech via USRP-users
On 09/04/2017 04:45 PM, Iñaki Landerreche (Inaki Landerreche) via 
USRP-users wrote:

Hi,
The external reference's maximum power level limit is +15dBm. how much 
is the minimum level? Is there any recommended or reliable level for 
this signal?

Thanks,
Iñaki

That input feeds an LVDS mux, and is clamped to about 1.2V max on the 
output of the balun.


My guess would be anything between about +10dBm to +15dBm would be reliable.


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