Re: [ARTIQ] TTL + slow DACs

> Since this is another piece of hardware and the processing constraints as well > as the electrical constraints are so different, it seems prudent to account > for > these differences. Consider doing proper galvanic isolation with a fiber: > ground potential differences easily > -- and even in

Re: [ARTIQ] TTL + slow DACs

On Thu, Mar 31, 2016 at 5:29 PM, Slichter, Daniel H. (Fed) wrote: >> We'll probably want a few dozen TTLs, broken out on SMA, so the FMC panel >> is not an option there. >> >> We can remove PCIe indeed, but keeping the WR oscillators is probably a >> good idea as they

Re: [ARTIQ] DSP gateware

> to allow for FPGA selection and to rush the funding I have done a design > study and implemented a basic DSP output channel for the ARTIQ DSP > hardware. A 1.25 GS/s, 16 bit, "smart" channel pair would do > > o0 = u0 + i0 * a0 * cos(f0 * t + p0) + q1 * a1 * sin(f1 * t + p1) > o1 = u1 + q0 * a0

Re: [ARTIQ] TTL + slow DACs

> We'll probably want a few dozen TTLs, broken out on SMA, so the FMC panel > is not an option there. > > We can remove PCIe indeed, but keeping the WR oscillators is probably a > good idea as they can be used for clock synchronization with the master. For the purpose of a TTL card, I would

Re: [ARTIQ] TTL + slow DACs

for this purpose one can use this board http://www.ohwr.org/projects/spec/wiki there is available also stand-alone aluminium box.The cost can be lowered by factor of two when WR oscillators, PCie chip and memory is not mounted. Just leave FPGA,supply and FMC connector. Greg On 31 March 2016 at

Re: [ARTIQ] TTL + slow DACs

Well, yes, providing that you find charger that won't fail after 500 hours :) -Original Message- From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk] Sent: Thursday, March 31, 2016 12:42 PM To: Grzegorz Kasprowicz Cc: Slichter, Daniel H. (Fed)

Re: [ARTIQ] DSP gateware

Yes, but for such speed you don't need to match better than several mm. Greg On 31 March 2016 at 13:51, Robert Jördens wrote: > On Thu, Mar 31, 2016 at 8:51 AM, Florent Kermarrec > wrote: > > When choosing between Artix7 or Kintex7 you also have to

Re: [ARTIQ] TTL + slow DACs

Well, we can use in this case the AMC board plugged into dual AMC box which has 4 SFPs. In some cases this could be an overkill, but it is working solution. http://www.ohwr.org/projects/amc-ubackplane-sfp/wiki On 31 March 2016 at 12:05, Sébastien Bourdeauducq wrote: > On

Re: [ARTIQ] FW: initial specification of the project

Re DAC clock: presumably, the plan is to distribute a 10MHz (or 100MHz, or whatever) clock with really low close-in phase noise to each MCH, and then from each MCH to the AMCs via the backplane. Why not send this from the AMC to the FMC boards via the FMC connectors? Then, have the FMC board

Re: [ARTIQ] FW: initial specification of the project

well, there are verified OH designs of such cards: 32 channel TTL IO http://www.ohwr.org/projects/fmc-dio-32chttla/wiki slow DAC card with some IOs and slow ADCs. http://www.ohwr.org/projects/fmc-dac100m14b16cha-adc2m14b4cha/wiki On 31 March 2016 at 01:45, Slichter, Daniel H. (Fed) <

Re: [ARTIQ] FW: initial specification of the project

On 31 March 2016 at 04:58, Sébastien Bourdeauducq wrote: > On Wednesday, 30 March 2016 9:37:51 PM HKT Grzegorz Kasprowicz wrote: > > Well, you don't have to write it. > > It is already available for RTOS and linux. > > We are not using RTOS or Linux. > you can also program it

Re: [ARTIQ] DSP gateware

Hello, When choosing between Artix7 or Kintex7 you also have to consider that Artix7 only have HR IOs which mean they don't have ODELAYE2 primitives and we are currently using them in the actual DDR PHY for leveling. Also when choosing XC7A200T you will stuck to this FPGA on your board because