[ARTIQ] 2018 ARTIQ/Sinara User Survey

Please follow the link below to access a quick poll to evaluate how ARTIQ and Sinara is being used by the research community. The results of the survey are public. Knowing the number, location and interests of users helps plan future technical development, meetings and enhance the case for

[ARTIQ] ARTIQ/Sinara, fedtech.io

In the US there are several programs that aim to take ideas originating in gov't labs and shepherd them toward commercial use. It looks like ARTIQ/Sinara got the attention of some of these program managers. I've been asked to gauge interest of the ARTIQ/Sinara community to participate in this

Re: [ARTIQ] ARTIQ Digest, Vol 50, Issue 2

> It would be good to get the interpolation running, both to improve spectral > purity and to put the hardware through its paces before we move on to the > next design revision (I'd love to see synchronisation at max DAC clock > rate). I agree with @hartytp on this. Pushing digitization artifacts

Re: [ARTIQ] We have ARTIQ RF out of Sayma!

SAWG RF output wasn't working on my builds when I last had Sayma in hand. Good to know that its now working. On Wed, May 23, 2018 at 9:53 PM, Sébastien Bourdeauducq <s...@m-labs.hk> wrote: > On Thursday, May 24, 2018 02:16 AM, Joe Britton wrote: >> >> Has M-Labs teste

Re: [ARTIQ] We have ARTIQ RF out of Sayma!

To clarify, by "testing SAWG" I mean looking for two-tone RF using SAWG. Now as in Jan HMC830 isn't needed for this test. On Wed, May 23, 2018 at 2:16 PM, Joe Britton <joe.britton@gmail.com> wrote: > Has M-Labs tested SAWG on Sayma since the DRAM, Ethernet, gateware bug &

Re: [ARTIQ] We have ARTIQ RF out of Sayma!

Has M-Labs tested SAWG on Sayma since the DRAM, Ethernet, gateware bug patching in recent months? On Tue, Jan 23, 2018 at 2:43 AM, Sébastien Bourdeauducq via ARTIQ < artiq@lists.m-labs.hk> wrote: > Hi, > > We are pleased to announce that the ARTIQ SAWG is now working on the Sayma > board. See

Re: [ARTIQ] monthly status report

Thank you SB. This looks like a huge amount of work in the last month. It was really cool to see how quickly RISC-V was added. Awesome! When do you expect to look for phase synchronization of SAWG in the analog signal? On Sun, May 6, 2018 at 12:19 AM, Sébastien Bourdeauducq via ARTIQ

Re: [ARTIQ] Sinara (Kasli, Urukul, Novo, Zotino...) batch sizing

Robert, Please post a quote from Technosystem for qty 1-10, 11-20, 21-50. It's hard for groups to project volume without knowing price brackets. In keeping with the open philosophy of the platform I encourage everyone to use the wiki to communicate anticipated volume (Robert's link [2]). -Joe On

[ARTIQ] Sayma bootstrapping

UMD has received a complete set of Sayma hardware from WUT. So we're ready to test M-Labs components. Please advise on how to get started. -Joe ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] Error Installing Rust

Lauren, Why are you trying to compile rust from scratch? Have you had success using the pre-compiled conda-distributed version? http://www.m-labs.hk/artiq/manual-master/developing.html#artiq-anaconda-development-environment On Fri, Sep 22, 2017 at 7:40 PM, Lopez, Lauren M via ARTIQ

Re: [ARTIQ] Example Ion Trap Code

Hi All. I'd like to introduce Arpit Agrawal. He's a physics graduate student at UMD and recently joined my group at JQI/ARL. His background is in computer science and quantum information theory. He has a masters degree in physics from IIT-Bombay. The plan is that Arpit's thesis work will be

Re: [ARTIQ] ARTIQ SPI PHY, differential driving

Migen subsignal definition looks like for spi when driven single-ended by the FPGA. ("spi", 0, Subsignal("clk", Pins("LPC:LA13_N")), Subsignal("cs_n", Pins("LPC:LA14_N")), Subsignal("mosi", Pins("LPC:LA17_CC_P")), Subsignal("

[ARTIQ] ARTIQ SPI PHY, differential driving

What's the right way to use ARTIQ to drive SPI devices across the VHDCI bus? The SPIMaster interface appears to take only a single signal for each of clk, cs_n, mosi and miso. Has anybody yet interfaced with an SPI device using VHCDI? -Joe ___ ARTIQ

[ARTIQ] Should we use StackExchange?

Have you ever had ARTIQ questions that weren't quite covered in the official documentation? - How do I get data into Mathematica for offline analysis? - How do I get data into MATLAB/Mathematica for offline analysis? - How do I program a 2-dim scan and plot the results? - What configuration

Re: [ARTIQ] Pipistrello Install Issue

Also be sure you're using ARITQ 2.x. See Release Notes. https://github.com/m-labs/artiq/blob/471605ec1ed951f9033472a19c04287494978d49/RELEASE_NOTES.rst On Thu, Jul 27, 2017 at 6:43 PM, Chris Ballance via ARTIQ wrote: > Hi, > > Do not try to install from source -

Re: [ARTIQ] July status report

Thank you for the update. Please consider adding more explicit references to the codebase in the monthly reports. This helps new users get oriented and experienced users review what's new. Here's an example of what I have in mind based on the July 1 status report. "We have developed a mechanism

[ARTIQ] program files for testing Sinara

I've posted some of the ARTIQ program files I'm using to test the Sinara gateware/software. https://github.com/jbqubit/sinara-testing -Joe ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6

Octopart Avnet costs for 1 unit XC7A100T-2CSG324C $131.22 XC7A50T-2CSG324C $74.98 Greg, What is the cost differential between 50T-2 and 100T-2 assuming Xilinx open source pricing? -Joe ___ ARTIQ mailing list

[ARTIQ] Survey of ARTIQ User Community (April 2017)

Dear ARTIQ Friends, I've made a quick google poll to gauge the activity of the ARTIQ user community. It only takes 5 minutes to fill out. If you are using ARTIQ or just lurking in the wings please fill it out.

Re: [ARTIQ] Fwd: Sinara multi-crate / DRTIO switches

> * The decision we want to taking here is whether we will support only > the simple hierarchy of a single Metlino *directly* connected to a > bunch of terminal child devices devices (Sayma, Kasli) or whether we > allow support for hierarchies deeper than a single level of DRTIO > links to be

Re: [ARTIQ] Sinara multi-crate / DRTIO switches

> does anyone have serious plans to use more than one Sinara crate? Absolutely. One of my primary motives for supporting DRTIO is coordination of multiple crates. Use case is ARTIQ coordinating entanglement distribution between a pair of qubit systems (each with its own crate) separated by an

Re: [ARTIQ] Fwd: proposed uTCA hardware for ARTIQ; Sayma, Metlino, Kasli and friends

Based on feedback from m-labs, Greg at Warsaw Technical University (WUT) and ARTIQ users I've updated the microTCA hardware plan. Here's a recap of the changes. ## ### Changes to sayma_motherboard 1) An UltraScale Kintex FPGA will be used in lieu of Kintex7. The

Re: [ARTIQ] ARTIQ-1.0 feature freeze

On 2/19 we had a google hangout and discussed the v1.0 release. People present were Daniel, Joe, David L. and SB. Robert reviewed minutes. Here's a recap of the release schedule we agreed to follow. * April 1: testing starts on official 1.0RC (for both Linux and Windows 7) *

Re: [ARTIQ] Dropping 32-bit packages

I think it's fine to kill the 32-bit Linux version. The 32-bit Windows version is preferred over 64-bit. Reasons... * 32-bit binaries runs on 64-bit or 32-bit Windows OSs * In may be the case that ARTIQ is installed on Windows machines for the purpose of acting as a Device Manager for a bespoke

Re: [ARTIQ] ARTIQ Compatibility with VIRTEX 7 FPGA

Hi Zach. Thanks for the question. Porting ARTIQ to the VC707 probably isn't very hard but would likely cost more in time than buying a KC705 ($1700). If you'd like to get up and running quickly I recommend using the KC705. Is there a feature on the VC707 that you need that's not available on the

Re: [ARTIQ] November status report

Thank you for the progress report. Some questions. Regarding 2), can you say more about the new MiSoC. What's new about it? What does it mean for "builds to be out-of-tree?" Regarding 3), is the Startup Kernel in addition to the previously implemented Default Kernel? -Joe On Mon, Nov 23, 2015

Re: [ARTIQ] <1 ns output resolution

>The current circuitry will add several hundred ps of peak-to-peak jitter at a >minimum. > This is more reasonable if you are talking about a signal that stays on just > one > board, but again you will need to do some careful engineering. It's worse than that. In June I tested the legacy (circa

Re: [ARTIQ] ARTIQ API Changes :: python3.5, datasets, setattr_*

Changes in experiment logging API. See changes in examples/master/repository/arguments_demo.py https://github.com/m-labs/artiq/commit/d13b368a6575ac7ac932b8fe5dc680d7503bcd53 On Thu, Oct 15, 2015 at 10:21 PM, Sébastien Bourdeauducq <s...@m-labs.hk> wrote: > On 10/16/2015 12:0

[ARTIQ] conda channel change

Just FYI, after 31st of August binstar.org will be deprecated, everybody should use anaconda.org - https://anaconda.org/m-labs/. * remove the following line from ~/.condarc - http://conda.binstar.org/fallen/channel/dev * remove artiq $ conda uninstall artiq * follow instructions here

[ARTIQ] Distributed Real-Time I/O (DRTIO) upgrade to ARTIQ, clock stability

Sometime in 2015 I'm aiming for an extension to ARTIQ for low-latency, high-bandwidth optical interconnect for ARTIQ peripherals. This underpins several applications. For example, * streamlined real-time control of lab peripherals used by trapped-ion and neutral atom AMO groups; real-time means

[ARTIQ] LED example

This should work, right? I'm using KC705 in Penning lab. No blinking. The core device runs mandelbrot.py fine. from artiq import * def input_led_state(): return int(input(Enter desired LED state: )) class LED(EnvExperiment): def build(self): self.attr_device(core)

Re: [ARTIQ] Qt and pyqtgraph

Impulse is an extension for the Eclipse IDE that supports visualization of a wide array of time-series data. I don't have any experience with it but found it while browsing. Its written in Java and is free to use for non-commercial/research applications. It may be more inspirational than a useful

[ARTIQ] Duke control system

Scalable Digital Hardware for a Trapped Ion Quantum Computer http://arxiv.org/abs/1504.00035 ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] external triggering; optical dipole force beatnote

What about fixing the cabling and/or devices so that this does not happen? There may be a problem with the grounding of the coaxial cables, poor quality cables, or poorly designed devices (if the crosstalk is coming from different channels from the same source). Of course we strive to do

Re: [ARTIQ] shallow parameter histories

on the master as Robert suggests is the way to go. -Joe On Fri, Mar 20, 2015 at 5:38 PM, Robert Jördens jord...@gmail.com wrote: Hello, On Thu, Mar 19, 2015 at 11:38 AM, Sebastien Bourdeauducq s...@m-labs.hk wrote: Hi, On Wednesday, March 18, 2015 09:22 PM, Joe Britton wrote: Ok

Re: [ARTIQ] debug vs logic analyzer

On Tuesday, March 24, 2015 02:41 AM, Robert Jordens wrote: Hmm. What is the scope of py2llvm debugging symbols? Just code locations and then stack/traceback? The traceback will be pretty flat as long as we don't have functions, or do you want to add support for functions at the same time We

Re: [ARTIQ] duty cycle management

the dutycycle management preformed on the core device. I don't think this would pose a computational problem since the dutycycle pulse sequence could be computed at the end of each experiment (OK if it takes many micro-seconds). -Joe Joe Britton NIST - Div 688 325 Broadway Boulder, CO 80305

Re: [ARTIQ] ARTIQ future details

Ok. Can we assume you consider it a manual operation to extract the duty cycle of a gpio in an experiment and how you use that number is all left up to you? Then this sounds just like a use case for the soft logic analyzer and would depend on it. No. I don't think this approach works.

[ARTIQ] Fwd: ARTIQ future details

At last week's meeting we discussed prioritizing several items on the ARTIQ todo list. My interest is in getting Artiq into a form where real experiments can be done in the lab. The aim is to provide concrete feedback based on what's happening in the lab. It is understood that the user interface

Re: [ARTIQ] KC705 support

:57 PM, Yann Sionneau y...@m-labs.hk wrote: Agreed, here are patches which fix this: Those patches should apply after the previous ones I sent you, except that they contain the LPC: addition that you added manually. Regards, Yann On 2015-02-25 20:20, Joe Britton wrote: The user clock SMA

Re: [ARTIQ] KC705 support

-labs.hk wrote: Hi, On Wednesday, March 04, 2015 09:35 PM, Joe Britton wrote: CC main.o main.c:58:12: warning: ‘load_object’ defined but not used [-Wunused-function] static int load_object(void *buffer, int length) ^ main.c:68:12: warning: ‘run_kernel’ defined but not used

Re: [ARTIQ] kc705 flashing woes

: abort boot F7:boot from serial Booting from flash... Error: Invalid flash boot image length 0x Booting from serial... sL5DdSMmkekro Timeout No boot medium found On Sun, Mar 1, 2015 at 4:01 PM, Joe Britton joe.brit...@gmail.com wrote: What remains to be done before a test of the DDS/TTL

Re: [ARTIQ] kc705 flashing woes

What remains to be done before a test of the DDS/TTL adapter board is possible? -Joe On Sat, Feb 28, 2015 at 4:39 PM, Sebastien Bourdeauducq s...@m-labs.hk wrote: Hi, we found the problem with the KC705 flashing. When the XM105 FMC card is plugged in, it opens a switch on the KC705 between

Re: [ARTIQ] feedback on ARTIQ tutorial

In planning for Sebastein's upcoming visit I'd like to propose a) homework in advance for physicists b) topics to cover in a group tutorial. Please comment on additions/subtractions to the list below. -Joe Homework in advance of hands-on ARTIQ has adoped several tools and standards that

Re: [ARTIQ] artiq dependencies

I advocate adding options to setup.py to include these dependencies if a user want's them. I think it would make sense to fork external dependencies into m-labs/artiq so that dependencies don't break over time. -Joe On Wed, Jan 28, 2015 at 8:39 AM, Yann Sionneau y...@m-labs.hk wrote: Hello,

Re: [ARTIQ] driver integration

On Mon, Jan 26, 2015 at 7:05 PM, Sébastien Bourdeauducq s...@m-labs.hk wrote: On 01/27/2015 10:03 AM, Joe Britton wrote: class LED(AutoDB): class DBKeys: led = Device() penning_rotating_wall = Device() penning_rotating_wall.set_freq_all_phase_continuous(0.05

Re: [ARTIQ] PXI6733 controller

Thank you for the question Yann. I spoke with John Gabler and Dan Slichter here at NIST and came up with the following advice. There's no need for the 6733 controller to run on a Linux machine. I've found the NI libraries on Windows to be reasonably straightforward (NI-DAQmx libraries with C++).

Re: [ARTIQ] PXI6733 controller

, Joe Britton wrote: * The waveform advance pulse to the 6733 is what causes its output to transition from one ADC channel (voltage) to another. We usually generate this pulse from the FPGA not from a periodic clock (eg crystal oscillator). This makes it possible to a) conserve memory

Re: [ARTIQ] ARTIQ development system

. - Robert and I confirmed that the development system can successfully compile and write the Artiq .bit file to a Papilio Pro. This was tested on a Windows 7 host OS. Joe Britton NIST - Div 688 325 Broadway Boulder, CO 80305 303.497.7295 *brit...@nist.gov* brit...@nist.gov

Re: [ARTIQ] Phase Control

Thank you for offering several API alternatives Sebastian. I can't think of any scenario where the phase behavior of a DDS would need to change in the midst of an experiment. It's also probably technically easier to set a DDS's phase behavior at the outset of an experiment sequence. Daniel,