Hi Aditya
I think by changing PLL control register setting u sud b able to achieve your
goal.(also u will require som sw changes)
look in reg.h of ath5k
/*
* PHY PLL (Phase Locked Loop) control register
*/
#define AR5K_PHY_PLL0x987c
#define AR5K_PHY_PLL_20MHZ
On Thu, 2009-08-20 at 04:41 -0700, shashi raj singh wrote:
Hi Aditya
I think by changing PLL control register setting u sud b able to achieve your
goal.(also u will require som sw changes)
look in reg.h of ath5k
The question is not how to do it in the chipset. The question is how to
make
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Pavel Roskin a écrit :
On Thu, 2009-08-20 at 04:41 -0700, shashi raj singh wrote:
Hi Aditya
I think by changing PLL control register setting u sud b able to
achieve your goal.(also u will require som sw changes) look in
reg.h of ath5k
The
Hi,
Thanks for your prompt responses.
Another member posted some time back that the 'iw' command can set the
bandwidth to be 40 MHz in addition to the default 20. So I guess
user-level API support is already built in for this kind of change.
Don't we just need to extend it's implementation to
On Thu, Aug 20, 2009 at 10:16 AM, Benoit
PAPILLAULTbenoit.papilla...@free.fr wrote:
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Pavel Roskin a écrit :
On Thu, 2009-08-20 at 04:41 -0700, shashi raj singh wrote:
Hi Aditya
I think by changing PLL control register setting u sud b able to
