Re: [casper] Question about using DRAM for ADC Data Storage on RFSoC

Hi Yunfan, Access to the DRAM is not yet supported. It is something that we want to achieve, although not much work is being done on that at the moment. If working on making DRAM work is something that interests you we welcome contributions and can help get you started on the right path.

Re: [casper] Question about the RFSoC Clock Configuration

Hi Yufan, Sorry this did not resolve your issues. I believe I see the issue now and am sorry I did not catch this earlier. In your previous screenshots for the configuration of the RFDC the PLL reference clock input is set to 245.76 MHz when it should be set to 491.52 MHz. The LMX file you are

Re: [casper] Question about the RFSoC Clock Configuration

Hi Yunfan, Could you please try the `m2021a-dev` branch of `mlib_devel` and see if it helps resolve your issues with setting up the clock configuration? This development branch has new changes and adjustments that make simpler and

Re: [casper] Connection Problem on RFSoC 4*2 Board

Hi Yunfan, Some debugging suggestions below: > On Feb 8, 2024, at 12:50 PM, Yunfan Zhang wrote: > > Dear CASPER Team, > > I am a student who is trying to create the CASPER environment for our RFSoC > 4*2 board. > > The problem I have currently encountered that, I cannot actually connect

Re: [casper] Help with casperfpga / RFSoC

Hi Emiliano, On boot, the CASPER RFSoC image is expecting to be connected to a network where a DHCP server is running. This can be changed, but is the default behavior. From the information you provided it appears that there is no DHCP server that is offering IP addresses. In your screenshoot

Re: [casper] Help with setting up RFSoC

5881d00406fa4f68eee63064799b8e5b28a41a>): >>> git clone https://github.com/xilinx/device-tree-xlnx.git >>> >>> Below are screenshots of the Matlab crash at startup: >>> >>> >>> >>> Here is the log file: >>>

Re: [casper] Help with setting up RFSoC

Heystek, Matlab crashing: You had said earlier that you were on Ubuntu 20.04? Is this still the case? Toolflow error: Can you send me the commit hash for your current head of the Xilinx device tree repo? Mitch > On Oct 31, 2023, at 1:52 PM, Heystek Grobler wrote: > > > Hey Kaj, Mitch,

Re: [casper] RFSoC not supported

Hi Aman, This is an inconsistency in the `casper-astro/tutorials_devel` repository. The `activate_platform.sh` script does not have a case to handle an `rfsoc` option. However, RFSoC is supported within the tutorials. As long as you have completed the “Getting Started With RFSoC

Re: [casper] Installing the toolchain (segfault!)

Hi Emiliano, Try removing `es1` from the part configuration portion that the ZCU208 Simulink mask does here . Then also remove `-es1` from line 42 where on the ’speed’ parameter. The

Re: [casper] ISSUE GENERATING .DTBO FILE

Hi Harshal, Sorry you have this issue. This a bit strange. Have you verified that Vitis is installed? Depending on how you installed the suite of Xilinx tools it is possible to have missed Vitis. If Vitis is, could you then make sure you can launch it as the same user that you use to launch

Re: [casper] zcu216_tut_onehundred_gbe.slx

Hi Gianni, I haven’t noticed that the PHY particularly cares, neither does my Arista switch. However, I can't promise it works with every upstream device in recognizing how the lanes are presented. That being said, how the PHY presents the lanes is shown in the following image. This is

Re: [casper] zcu216_tut_onehundred_gbe.slx

Hi Dave, Thank you for helping out here. Yes, the four SFP28 ports on the ZCU216 aggregate in an implementation of a CAUI-4 PHY making a logical 100GBASE-CR/SR/LR/KR-4 link from the 4 SFP28 lanes. Mitch > On Jul 31, 2023, at 1:03 AM, David Harold Edward MacMahon > wrote: > > Hi, Mitch, >

Re: [casper] Doubts about clocking in RFSOC4x2

Hi Ross,Thanks for sharing this information. I would be very keen to help out with porting this tool you have to RFSoC 4x2. It sounds awesome.I’ll reach out to you in a separate email. MitchOn Jun 14, 2023, at 4:55 PM, 'Ross Martin' via casper@lists.berkeley.edu wrote:Hi Sebastian,I have an app

Re: [casper] How to monitor the 100Gbe port on a RFSoC 4x2 ?

Ken, The 100 GbE ethernet is not a processing system attached core in the typical sense like your NIC on your servers. These are connected directly to the fabric of the FPGA and are polled using their memory map register. The 100 GbE is covered in tutorial 4 for the RFSoC tutorials. More is

Re: [casper] Installing the toolchain

Kaj, When installing Vivado, at the installation configuration window there is a drop down for installing RFSoC engineering silicon parts. This needs to be selected. The default parts in the toolflow are engineering silicon (ES). Probably bad defaults now that when you buy a 216/208 or any

Re: [casper] viability of VCU128 eval board as production CASPER instrument

Hi Jonathan, To chime in under the “other” category… We have recently added six RFSoC platforms to CASPER. (Three Xilinx eval boards: ZCU111, ZCU216, ZCU208. The Xilinx education platform PYNQ RFSoC 2x2. Two boards from HiTech Global: HTG-ZRF16-29DR, and the 49DR version.) For ALPACA, we have

Re: [casper] Simulink window does not open when Matlab is started by startsg

Hi Kaj, For RFSoC as long as you are using Vivado <= 2020.2 you can still use System Generator with entry started using `./startsg`. Model Composer is replacing (really just wrapping) System Generator in future releases of Vivado/Vitis >= 2021. When setting up the RFSoC in the tools I know I

Re: [casper] ZCU111 upload

Hi Lawrence, Were you able to get some form of linux running? If you were then the next step would be to install tcpborphserver from source. From there you can use the command line tcpborphserver or casperfpga to upload the casper generated .fpg file. If you know how the tool flow generates

Re: [casper] ZCU111 toolflow

Hi Lawrence, Yes, the platform file is sparse. Right now it is enough to get the test model working but would need to be extended to include other onboard clocks, GPIO, etc. No, PYNQ is not mandatory and is independent of what is supported in the tool flow right now for the ZCU111. However,