Hi Charles:
The Roach C/C++ library is already part of Roach PowerPC Linux OS. The OS
running on Roach is call Borph developed by the Berkeley Uni.
All the registers and buffer will be visible as part of the OS device driver
after the BOF file is excuted.
Your C executable file has to be
Hi Andrew:
Thanks a lot for your graceful help. It is very clear for me.
Cheers
Wan
-Original Message-
From: Andrew Martens [mailto:martens.and...@gmail.com]
Sent: Thursday, 28 April 2011 9:19 PM
To: Francois Kapp
Cc: Cheng, Wan (CASS, Marsfield); millen...@skatelescope.org;
Hi:
I want to install the casper library to windows 64bits. But will the mkbof.exe
work in windows 64bits? Or someone has the 64bits version mkbof.exe?
Thanks
Wan
Hi:
I have not update my library for some time. Today after I upgrade to the latest
library, I find the delay of converter in pfb_real_fir becomes Nan.
This is the details of the error:
The parameters set for this block did not match the expected signatures.
Specifically,
- The block was
Hi Jason:
The plots you sent is a accumulated result or it is a single FFT output.
Thanks
Wan
-Original Message-
From: Jason Manley [mailto:jasonman...@gmail.com]
Sent: Thursday, 17 June 2010 7:31 PM
To: Cheng, Wan (CASS, Marsfield)
Cc: casper@lists.berkeley.edu
Subject: Re: Green
Hi Jason:
I guess if I build my own blocks with 'i' or 'j' as a loop, it would be a
problem.
But if I If I did not write any matlab scripts and only use the casper library
standard green block, I would not be affect. Is this right?
And could you clarify in which case user can overwrite the
Hi Dan:
Thanks a lot. Your suggestions are really useful and helpful.
Cheers
Wan
-Original Message-
From: Dan Werthimer [mailto:d...@ssl.berkeley.edu]
Sent: Monday, 18 January 2010 11:43 AM
To: Cheng, Wan (CASS, Marsfield)
Cc: jasonman...@gmail.com; casper@lists.berkeley.edu
Subject:
Hi Dan:
Thanks for your information again. But I am not still not very sure about how
the noise floor steps is generated.
Do you believe this is because I am using the maximum dynamic range?
I can achieve some improvement if I use smaller dynamic range?
Thanks
Wan
-Original
Hi Jason:
Thanks for your important information.
But one point I could not understand is the shift bits of FFT.
I guess it is used to shift the output at every FFT stage. So why data only in
top 10 bits? 10 bits data multiplies 8 bits coeff, the data should be in all 18
bits?
Wan
Hi Aaron:
Thanks for your reminding. I am pretty sure my input is quite low compared to
the full scale.
Thanks again.
Wan
From: Aaron Parsons [mailto:aaronrpars...@gmail.com]
Sent: Wednesday, 13 January 2010 3:19 PM
To: Dan Werthimer
Cc:
Hi Glenn:
I updated casper library last week. I found the 32K FFT could not generate
right output even I modified the max coefficient depth to 13 which helps me fix
this problem last time.
16K FFT is all right.
Any suggestions?
Thanks a lot.
Wa n
From: G
Hi Andrew:
Thanks. Your answer is very clear and solve my problem. I should divide it by
2^9 to get right power level.
And I still could not understand one thing:
The casper fft spectrum output for a single carrier (1 point) looks much
narrower than mablab float point fft and fix point fft(3
Hi Jason:
Thanks for your quick reply. But I am still not sure how I can use KATCP to
transfer binary files.
What I did is to capture the output of wordread command which is in ASCII and
transfer the data back to my program. I only can see the ASCII data. Is there
any other way to read it?
Hi Jason:
As Kjetil mentioned, we are only working on OS. The OS crash and network
problem appears without our program running.
Cheers
Wan
-Original Message-
From: Jason Manley [mailto:jasonman...@gmail.com]
Sent: Wednesday, 4 November 2009 7:22 PM
To: Wormnes, Kjetil (ATNF,
Hi Jason:
Thanks for you help.
But I could not find the tut4 in workshop. Could you please provide me the
exact link? Thanks.
As I know, the KATCP only provide data in ASCII. Is this right? And for KATCP,
all command and data are transferred by network. But we expeirence some network
failure
Hi Jason:
I guess the latest CPLD is quite important for us.
But for Uboot, I am not sure. Will all PPC registers be re-initialized again in
the linux core? Or the linux core use default value initialized by Uboot? Will
Uboot load OS into Dram before set the program pointer to the OS start
Hi Jason:
Could you please let me know how do you get data using KATCP?
I also used KATCP for a while. But I can not find an efficient way to read a
large mount data from FPGA, like 1GB data stored in the Dram. And there are a
few difficulties as well. Such as, network is not reliable, OS
Hi Jason:
Thanks for your information.
We did experience the SSH error, such as bad packet length or Corrupted MAC
address. I am not exactly sure if it is a software bug or not. I had used SSH
for a long time. I did not see any connection broken so frequently like Roach.
The Ethernet problem
Hi:
Is there anyway I can get the FPGA or Roach temperature?
Thanks
Wan
Hi David:
Thanks for your information. But I find after update to the head release, I
could not compile my design any more.
An error is received:
#
## Block objects creation ##
#
Problem with block: a10hs1/XSG core config
Error using ==
Hi David:
It seems to start working now. But I have not finished the compiling.
I check the mhs file, the function is implemented correctly. Hope all pin
definition are right.
Wan
-Original Message-
From: David George [mailto:david.geo...@ska.ac.za]
Sent: Friday, 16 October 2009
Hi David:
I recompile the kernel without OHCI. And the disk write is much faster. Problem
is solved.
Thanks a lot.
Cheers
Wan
-Original Message-
From: David George [mailto:david.geo...@ska.ac.za]
Sent: Thursday, 15 October 2009 6:31 PM
To: Wormnes, Kjetil (ATNF, Marsfield)
Cc:
Hi David:
Thanks for your information. My problem is I did not add a more entry in the
core_info.tab file. Now I could read and write the ADC control memory space.
But I meet another problem immediately. It seems that only one of 6 bus2ip_ce
will response my read and write.
Is there anyone
Hi:
Is there any instructions to set the bit width of PFB and FFT?
When I set output bitwidth of PBF to 25, I get a wrong spectrum output. But it
works well when the bitwidth is set to 18.
I guess something might be over flow in the FFT block.
Any idea on the bitwidth of PFB and FFT?
Thanks
Hi Andrew:
Thank you so much Andrew. It is very clear for me.
Cheers
Wan
From: Andrew Martens [mailto:martens.and...@gmail.com]
Sent: Thursday, 25 June 2009 4:06 PM
To: Cheng, Wan (ATNF, Marsfield)
Cc: casper@lists.berkeley.edu
Subject: Re: [casper] about the
Hi Andrew:
Thanks for your information.
I am still not sure on next two options in fft_wideband_real:
Number bits above which to store stage's coeffcients in BRAM
Number bits above which to store stage's delay in BRAM
Thanks
Wan
From: Andrew Martens
Hi:
Could anyone give me some idea on the function of shift input pin of FFT?
I find some example design set it to all 1s. This means every stage are set to
shift 1. What does this mean?
Thanks
Wan
Hi:
After reading the memo of sync pulse, I still feel a little bit confused.
I use a PFB in my design. So I guess I have to include the order of PFB into
the calculation.
The order of PFB is 2. But there are two stage in the PFB. There are 2 taps in
the second stage as well. So I set the
Hi David:
Thanks you for your help. I rebuild my design today. It seems all right now. I
can read valid data from all diff pairs.
I might not do right thing in the first build. Thanks for your information
again.
By the way, the in capsper 10.1 trunk, I did not find the pin allocation for
the
Hi Henry:
Could you please tell me where are they? I could not see the 3 wire control pin
constraints in the gen_ucf.m of @xps_adc.
Thanks
Wan
-Original Message-
From: Henry Chen [mailto:hche...@ssl.berkeley.edu]
Sent: Friday, 19 June 2009 10:22 AM
To: Cheng, Wan (ATNF, Marsfield)
HI George:
Thanks for your help.
I find ADC chip is not set into a right mode because only 2 of 4 diff pairs
give me right data. So I find the 3 wire control pins are not allocated in the
UCF file. I modify the UCF file according to the schematic.
But I find I still could not get right data
Hi Glenn:
Thanks for your quick answer. Now I could read ADC data from Roach through the
snap_bram. But unfortunately, it seems that the data I read is not right.
I am using the tcpborphserver at port 7147.The command is wordread. Do you have
some experience with Roach?
Thanks
Wan
Hi Glenn:
Thanks for your help. The only thing I am surprised is I could read the
snap_ram out by specifying the offset.
Cheers
Wan
From: G Jones [mailto:glenn.calt...@gmail.com]
Sent: Wednesday, 27 May 2009 11:31 AM
To: Cheng, Wan (ATNF, Marsfield)
Cc:
Hi Jason:
We have found what the problem is.
I have to use reboot command before I shutdown or reboot Roach. Or the file
system might be broken. I think this is why.
But why reboot could not work? I am told the runlevel could not determined.
Following information is given:
roach:~# reboot
Hi Janson:
Only update the Uboot and Roach core? My understanding is the new uboot will
boot from USB stick instead of on board busybox? Or the busybox on board also
need to be upgraded?
Thanks
Wan
-Original Message-
From: Jason Manley [mailto:jasonman...@gmail.com]
Sent: Tuesday, 26
Hi Jason:
Thanks for you great help. I reformat my USB stick and copy a fresh Roach core
into it.
Then I insert the following configuration into /etc/network/interfaces with VI.
auto eth0
iface eth0 inet static
address 130.155.199.211
netmask 255.255.240.0
gateway 130.155.192.2
Then I reboot
Hi David:
Thanks for your answer. But I am afraid this core is not included into the
released 10.1 library. Could you please email this core to me?
Thanks
Wan
-Original Message-
From: David George [mailto:david.geo...@ska.ac.za]
Sent: Wednesday, 14 January 2009 5:18 PM
To: Cheng, Wan
I know the ROACH card is tested, but any body has the controller code or
library?
Thanks.
Wan
Hi:
I am working with 10.1 library.
For the following code in the adc_interface.vhd
ADC_DATA_DDR: for i in adc_dataeveni'range generate
adc_dataeveni_ddr: ddr_input port map (
clk = adc_clk,
d = adc_dataeveni(i),
qrise = adc_datai_ddr(i + 24),
qfall = adc_datai_ddr(i + 8)
);
Hi Henry:
Thanks Henry. I guess the pcores ports creation are quite different from class
to class. Some class, like ADC, some ports information are created from
constructor function because these ports could not be seen in the simulink
design. Some classes, like xps_bram, are created from
Hi Henry:
Thanks for your great help.
And by the way, I find the Xilinx gateway out block which I drag from the
Xilinx blockset can not been identified by the command:
gateways_blk_out = find_system(blk,
'FollowLinks','on','LookUnderMasks','all','masktype','Xilinx Gateway Out Block')
But the
Hi Henry:
Why we have to use bee_xps to generate the bitstream instead useing sysgen?
Wan
-Original Message-
From: Henry Chen [mailto:hche...@ssl.berkeley.edu]
Sent: Friday, 21 November 2008 10:23 AM
To: Cheng, Wan (ATNF, Marsfield)
Cc: martens.and...@gmail.com;
Hi John:
Could you tell me where is the snap block? Is it a customized block?
Thanks
Wan
-Original Message-
From: John Ford [mailto:jf...@nrao.edu]
Sent: Saturday, 8 November 2008 12:33 AM
To: Cheng, Wan (ATNF, Marsfield)
Cc: casper@lists.berkeley.edu
Subject: Re: [casper] Question on
Hi Henry:
Thanks for your reply. I am not sure what's your mean that 2^11 real FFT gives
2^10 complex channels. Could you please give me deeper explanation?
My understanding is only half output sequence is positive frequency and the
output sequence is separated into two.
So the pulse period
Hi Andrew:
Thanks. I change the sync period. But it looks still wrong. I put the modified
mdl file again. Anybody could find something wrong?
The attached are the mdl file and the output wave.
Thanks
Wan
From: Andrew Martens [mailto:martens.and...@gmail.com]
Hi Andrew:
Another strange thing is I still get the output no matter I set Sync to 0 or
1. I think Sync could be considered as a sync reset signal. I should not get
anything out if I fix the sync to 1.
Wan
From: Andrew Martens [mailto:martens.and...@gmail.com]
Hi all:
I build a very basic module with PFB and FFT. But the output looks not right.
Anybody has anyidea? What's wrong with it?
The attached is the mdl file.
Thanks.
Wan
RFI_test5.mdl
Description: RFI_test5.mdl
HI Laura:
Thanks for your help. You are right. If I set more samples per period, it is
more difficult for me to find the difference. I setup the sine wave according
your setting, the difference is obvious.
I think you explanation for the ADC internal structure is correct. The extra
delay in
Hi Laura:
When I set the sample time of sine wave to 1/8, all outputs are still same. I
look at the subsystem of ADC module, and I find, except O1 has 1 more cycle
delay, all other channel have same function. I am not sure how the ADC is
implement. Do you have any idea?
Thanks
Wan
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