Hi everyone,
from what I understand the adc5g can easily sample 2.2GHz bandwidth at 8
bit without a great effort in the design phase.
I'd like to understand how portable would it be a design using roach1+iADC
with 400MHz bandwidth to a roach1+adc5g setup sampling 2.2GHz bandwidth,
just by
i suggest you contact mo ohady at digicom electronics
for pricing and availability of adc's and roach boards.
m...@digicom.org
casper collaborators might already have a design similar to
what you need.
are you building a correlator? or a spectrometer?
how many frequency channels? how many adc
The roach 1 will only work at the speeds you are interested at with
the dmux 2:1 option at 4 bits. I think the max speed at 8 bits is
about 3.2GSPS and that is due to the ZDOK interface.
I'm sure with significant effort in planahead you could achieve 5GSPS
on a low resolution correlator in a
you can probably to sample faster than 3.2Gsps 8 bit on a roach1
if you use the -2 speed grade fpga. you can look at the fpga
data sheets to find their max lvds bit rate for the -1 and -2 speed grades.
note that if you want to use the 5Gsps 4 bit ADC, that that's
a different adc board - you can
Hi All,
Could someone summarize this discussion for me re: the case I am interested
in, which is as follows? I have a need for a dual-pol spectrometer
covering an RF of at least 1-18 GHz (0.5-18 GHz is better). From the
discussion, it sounds like one option is to use the 1x5GSPs board at 1:1
hi dale,
your plan sounds good to me.
the adc08-5000 yellow block for roach2 demuxes by 16,
so a 5Gsps sample rates means a 312.5 MHz FPGA rate.
312 MHz fpga rate is not easy to acheive - you need to learn how
to use the plan ahead software, and you can't pack the fpga full.
how many spectral
Thanks Dan. I think I should get a couple of these ADCs and maybe John's
design and give it a try! John, how many channels does your design use
over 2.5 GHz? We would want of order 20,000, if that is possible.
Regards,
Dale
On Fri, Jan 24, 2014 at 7:48 PM, Dan Werthimer
Hi Ross,
Thanks for the info -- I've actually got a 5 Gsps ROACH2 (demux 1:1)
pocket correlator compiled, and the final piece of the puzzle was
getting the ADCs running properly (I only got hold of the hardware
relatively recently). But it's always reassuring to know someone else
is using a
Hi Jack,
Great work! The oversample mode is not something I realized existed!
Previously when we've been able to get the tools to use HIGH bandwidth
mode we could get away with just shifting the MMCM clock phase to
remove glitches on the interface (i.e. no IODELAY adjustments). Have
you tried
On 15 January 2014 16:28, Primiani, Rurik rprimi...@cfa.harvard.edu wrote:
Hi Jack,
Great work! The oversample mode is not something I realized existed!
Me neither -- I eventually stumbled across it in the SelectIO
Resources guide. (Where the order of the SERDES module outputs are
documented
Hi Jack and Rurik,
I'm very excited to hear that the adc could run at exact 5GSPS mode (2
channels, demux 1:1) . I'd like to follow the modification, but the vhdl is
something that I'm not familiar. I wonder if it is possible that the module
could be merged into the sma-wideband github, or help
Hi Weiwei,
I'll leave it up to Rurik to merge or not the changes into
sma-wideband, but in the meantime, the changes (along with LOTS of
other modifications to other parts of the library) are in my repo at
https://github.com/jack-h/mlib_devel
Alternatively, if you've got the latest mlib_devel
Oh, that's clear! I followed it and got the design compiled successfully
in Simulink. Thanks Jack!
Best,
Weiwei
On Wed, Jan 15, 2014 at 12:35 PM, Jack Hickish jackhick...@gmail.comwrote:
Hi Weiwei,
I'll leave it up to Rurik to merge or not the changes into
sma-wideband, but in the
Hi all,
Like Weiwei, I'm trying to use the ADC5g at 5 Gsps. I've played with a
simple ADC to snap model, and (as Rurik warned) getting reliable data
capturing is difficult at this speed. I've tried per-bit calibration
of input data streams via IODELAYs in conjunction with phase-shifting
of the
Hi Rurik,
I have a question of the adc5g yellow block. I can meet the time
requirement by relocating the adc pblock (ZDOK_0_1_1) in planahead (e.t.
modify the .ucf constrain file), but I'm not sure if I'm allowed to do so.
Maybe I should not move the pblocks, and come out other way to meet the
Hi Weiwei,
Removing that pblock is fine if you are using Rev. 2 of the ROACH2
(which is the default). That pblock is unfortunately left over from
the Rev. 1 days and should probably be removed... or at least only
conditionally added depending on what revision is being targeted.
Best,
Rurik
On
Hi Weiwei,
In most cases, as long as you run your design below the
successfully-compiled-for clock rate, i.e. the clock rate at which the
Xilinx tools have guaranteed timing for you, you should be okay. This
is complicated by the fact that the clock goes through an MMCM which
has various
Hi,
I have trouble to compile the adc clock rate of asiaa_adc5g block at
2500MHz.
Block parameter: two-channel, ZDOK0, demux 1:1 .
System: roach2, clock source:adc0_clk, clock rate: 312.5MHz)
The error is as follows:
Creating block object: xps_adc5g
Problem with block:
Hi,
Which version of mlib_devel are you using?
Rurik
On Tue, Nov 5, 2013 at 11:16 PM, Weiwei Sun su...@uw.edu wrote:
Hi,
I have trouble to compile the adc clock rate of asiaa_adc5g block at
2500MHz.
Block parameter: two-channel, ZDOK0, demux 1:1 .
System: roach2, clock source:adc0_clk,
I tried the casper-astro, ska-sa, sma-wideband. None of them seemly works.
Weiwei
On Tue, Nov 5, 2013 at 10:20 PM, Primiani, Rurik
rprimi...@cfa.harvard.eduwrote:
Hi,
Which version of mlib_devel are you using?
Rurik
On Tue, Nov 5, 2013 at 11:16 PM, Weiwei Sun su...@uw.edu wrote:
Hi,
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