On 2024-06-13 4:30 p.m., Dave Dunfield via cctalk wrote:
I think the 86 came at a good time/place because the 8080 series had become
quite popular in microcomputers
and designers were feeling the limits of a 8-bit architecture - the 86 provided
a fairly powerful (for the time) and
easy upgrade
On 2024-06-13 12:06 p.m., Paul Koning via cctalk wrote:
On Jun 13, 2024, at 2:00 PM, Chuck Guzis via cctalk
wrote:
On 6/13/24 10:32, Paul Koning via cctalk wrote:
Huh? There is no direct connection between word length, register count, and
pipeline length.
Indeed. There are architecture
On 2024-06-13 11:32 a.m., Paul Koning via cctalk wrote:
e up an entire chassis, 750-ish logic modules.
You never see a gate level delays on a spec sheet.
Our pipeline is X delays + N delays for a latch.
Gate level delays are not interesting for the machine user to know. What is interesting
On Thu, 13 Jun 2024, Jonathan Stone wrote:
> > The architecture designers cheated however even in the original ISA in
> > that moves from the MD accumulator did interlock. I guess they figured
> > people (either doing it by hand or by writing a compiler) wouldn't get
> >that right anyway. ;)
>
>
On Thu, 13 Jun 2024 at 18:22, Jonathan Stone via cctalk <
cctalk@classiccmp.org> wrote:
>
> On Thursday, June 13, 2024 at 03:00:22 PM PDT, Maciej W. Rozycki via
> cctalk wrote:
>
> > The architecture designers cheated however even in the original ISA in
> > that moves from the MD accumulator did
Chuck Guzis wrote:
> Scarcely innovative. 64 bit architectures predated the 64-bit x86 by
> decades. Call it a natural evolution.
I'm kinda surprised that nobody has mentioned this ...
But.. even less innovative than that! - the subject mentions "8086" and 46
years - the 8086 was only a 16 bi
On Thu, 13 Jun 2024, Paul Koning via cctalk wrote:
> MIPS, perhaps? It has "delay slots". The one that remains is the
> branch delay slots, which in modern designs is presumably merely an
> annoying crock that requires extra pain to implement but is actually
> required because it changes the
On Thursday, June 13, 2024 at 03:00:22 PM PDT, Maciej W. Rozycki via cctalk
wrote:
> The architecture designers cheated however even in the original ISA in
> that moves from the MD accumulator did interlock. I guess they figured
> people (either doing it by hand or by writing a compiler) woul
On Thu, 13 Jun 2024, Jonathan Stone via cctalk wrote:
> MIPS is of course (allegedly) an acronym for "Microprocessor without
> Interlocked Pipeline Stages".
>
> No interlocking between pipeline stages mean no hardware avoidance
> (delays, pipeline bubbles) of hazards. So hardly surprising that
> On Jun 13, 2024, at 2:00 PM, Chuck Guzis via cctalk
> wrote:
>
> On 6/13/24 10:32, Paul Koning via cctalk wrote:
>> Huh? There is no direct connection between word length, register count, and
>> pipeline length.
> Indeed. There are architectures with NO user-addressable registers.
> So
> On Jun 13, 2024, at 12:15 PM, CAREY SCHUG via cctalk
> wrote:
>
> I think I recall an early processor that did out of order execution, without
> checking, meaning you could have
>
> add xxx to accumulator
> store accumulator in zzz
>
> and the store could happen before the add if there w
On Thursday, June 13, 2024 at 12:56:09 PM PDT, Christian Kennedy via cctalk
wrote:
[[ ...compiler, or human writing assembler, responsible for avoiding hazards in
MIPS delay slots ]]
MIPS is of course (allegedly) an acronym for "Microprocessor without
Interlocked Pipeline Stages".
No
Even earlier than the TPU on the 68332 is the communications
co-processor built into the 68302. This predate the entire CPU-32 family.
On 6/13/2024 10:56 AM, Adrian Godwin via cctalk wrote:
Even without things like system management mode, there are lots of speed-up
features on modern processor
On 6/13/24 13:08, Bill Degnan via cctalk wrote:
> There are a few historic locations. I think I remember driving past the
> original house / garage where Apple started, but I am not sure it's public
> knowledge.
The HP garage in Palo Alto is a state historic landmark:
https://en.wikipedia.org/wi
"What to use in place of 586?"
Unreliable sources told me that the name "Pentium" was chosen in a
contest; what was second place??
It was said that Intel chose to not use "586", because
competitors were competing and/or cheating on the numbers
a 386 level chip being called "486xx", 486 level c
There are a few historic locations. I think I remember driving past the
original house / garage where Apple started, but I am not sure it's public
knowledge.
On Thu, Jun 13, 2024 at 3:15 PM anders--- via cctalk
wrote:
> Hi,
>
> Soon I will travel to US and San Francisco/San José Area. Any tips
On 6/13/24 09:33, Adrian Godwin via cctalk wrote:
I may be wrong, but wasn't that a feature of early RISC, possibly the Sparc
? You were compiling to microcode rather than CISC assembler, so you got to
think about pipelining in the instruction stream. Just about feasible in
assembler but perfec
> On Jun 13, 2024, at 8:14 AM, Bill Degnan via cctalk
> wrote:
>
> Thanks. The Iliac IV was highlighted in the Sept (?) 1971 Scientific
> American, the Iliac I was in service from around 1956ish so I was curious
> about where the Iliac II fit it, it's less well-known of a machine.
> Bill
Wi
Hi,
Soon I will travel to US and San Francisco/San José Area. Any tips for
vintage computing and surpuls electronics?
CHM is manatory, I'll go there. It would have been nice to see the PDP-1
in action, but I suscpect that we will not make it when it's
demonstrated.
/Anders
On 6/12/24 09:52, Jon Elson via cctalk wrote:
On 6/12/24 03:02, Peter Corlett via cctalk wrote:
Fun factoid: despite modern x86 being clocked ~1000x
faster than ye olde
6502, there's not much in it between them when it comes
to interrupt
response time. If all goes well, x86 takes "only" a
hu
> On Jun 11, 2024, at 11:52 PM, ben via cctalk wrote:
>
> On 2024-06-10 10:18 a.m., Joshua Rice via cctalk wrote:
>> On 10/06/2024 05:54, dwight via cctalk wrote:
>>> No one is mentioning multiple processors on a single die and cache that is
>>> bigger than most systems of that times complete
On 6/13/24 10:32, Paul Koning via cctalk wrote:
> Huh? There is no direct connection between word length, register count, and
> pipeline length.
Indeed. There are architectures with NO user-addressable registers.
Some have memory-mapped registers, where a "register number" is merely
shorthand
> On Jun 12, 2024, at 9:39 PM, Mike Katz via cctalk
> wrote:
>
> Maybe they are thinking that because it is oil it will work like an oil can
> load.
But oil can loads use the oil for cooling; a resistor (typically made of
carborundum) is the actual load.
paul
On 6/13/2024 4:04 AM, Dave Wade G4UGM via cctalk wrote:
-Original Message-
From: Douglas Taylor via cctalk
Sent: Wednesday, June 12, 2024 10:22 PM
To: General Discussion: On-Topic and Off-Topic Posts
Cc: Douglas Taylor
Subject: [cctalk] Dilog Multifunction MQ-100 board
Hopefully I can
I may be wrong, but wasn't that a feature of early RISC, possibly the Sparc
? You were compiling to microcode rather than CISC assembler, so you got to
think about pipelining in the instruction stream. Just about feasible in
assembler but perfectly sensible if the compiler was doing the work.
To t
On 2024-06-13 9:40 a.m., Jon Elson via cctalk wrote:
AACK! Sorry, that was supposed to be F-16!
The divide bug strikes again.
Jon
What would one use today instead of the 586?
Ben.
Even without things like system management mode, there are lots of speed-up
features on modern processors that result in variable execution times -
things like caching and pipelining. With sufficient care these can
sometimes be made predictable but there are certain common needs that
have always f
I think I recall an early processor that did out of order execution, without
checking, meaning you could have
add xxx to accumulator
store accumulator in zzz
and the store could happen before the add if there weren't sufficient
instructions between the two.
I *DON'T* recall if it was designed
On Thursday (06/13/2024 at 10:46AM -0500), Jon Elson via cctalk wrote:
> On 6/12/24 22:32, Gavin Scott via cctalk wrote:
> > Is it possible they were thinking about really old FAX paper which
> > might have been wet to support marking via an electric discharge
> > through it (and to (slightly) redu
On 6/12/24 22:32, Gavin Scott via cctalk wrote:
Is it possible they were thinking about really old FAX paper which
might have been wet to support marking via an electric discharge
through it (and to (slightly) reduce the frequency with which the
receiving machine caught fire)?
Yes, there was te
Thanks. The Iliac IV was highlighted in the Sept (?) 1971 Scientific
American, the Iliac I was in service from around 1956ish so I was curious
about where the Iliac II fit it, it's less well-known of a machine.
Bill
On Wed, Jun 12, 2024 at 6:16 PM Marvin Johnston via cctalk <
cctalk@classiccmp.or
Bill Degnan wrote:
> Thanks Dave - It has been many years since I genned a N* disk. I don't
> always have success with the port assigning but eventually I get it to work.
Although my Altair was "fully expanded" when I first owned it, I was involved
with it quite some time before that:
At Univers
> -Original Message-
> From: Douglas Taylor via cctalk
> Sent: Wednesday, June 12, 2024 10:22 PM
> To: General Discussion: On-Topic and Off-Topic Posts
> Cc: Douglas Taylor
> Subject: [cctalk] Dilog Multifunction MQ-100 board
>
> Hopefully I can find someone who has a manual for this qb
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