On Mon, Jul 25, 2016 at 01:46:43PM -0700, Guy Sotomayor Jr wrote:
>> On Jul 25, 2016, at 1:34 PM, Sean Conner wrote:
>> It was thus said that the Great Peter Corlett once stated:
>>> Unsurprisingly, the x86 ISA is brain-damaged here, in that some
>>> instructions (e.g. inc") only affect some bits
> On Jul 25, 2016, at 1:34 PM, Sean Conner wrote:
>
> It was thus said that the Great Peter Corlett once stated:
>>
>> Unsurprisingly, the x86 ISA is brain-damaged here, in that some instructions
>> (e.g. inc") only affect some bits in EFLAGS, which causes a partial register
>> stall. The recom
It was thus said that the Great Peter Corlett once stated:
>
> Unsurprisingly, the x86 ISA is brain-damaged here, in that some instructions
> (e.g. inc") only affect some bits in EFLAGS, which causes a partial register
> stall. The recommended "fix" is to avoid such instructions.
I'm not follow
> On Jul 25, 2016, at 12:19 PM, Chuck Guzis wrote:
>
> On 07/25/2016 02:31 AM, Peter Corlett wrote:
>
>> Eliminating condition codes just moves the complexity from the ALU to
>> the branch logic (which now needs its own mini-ALU for comparisons),
>> and there's not much in it either way. Where
On 07/25/2016 02:31 AM, Peter Corlett wrote:
> Eliminating condition codes just moves the complexity from the ALU to
> the branch logic (which now needs its own mini-ALU for comparisons),
> and there's not much in it either way. Where it *does* win is that
> the useful instructions are all single-
On Mon, Jul 25, 2016 at 05:54:51AM -0600, ben wrote:
[...]
> The other factor is that the 3 big computers at the time IBM 360/370's PDP 10
> and PDP 11 where machines when the Dragon Book came out thus you favored
> register style code generators. Later you got the Pascal style one pass
> generator
On 7/25/2016 3:31 AM, Peter Corlett wrote:
On Fri, Jul 22, 2016 at 11:59:59AM -0700, Chuck Guzis wrote:
[..]
Something that's always bothered me about three-address architectures like
ARM is why there is the insistence on that scheduling bottleneck, the
condition code register? You can see how t
On Fri, Jul 22, 2016 at 11:59:59AM -0700, Chuck Guzis wrote:
[..]
> Something that's always bothered me about three-address architectures like
> ARM is why there is the insistence on that scheduling bottleneck, the
> condition code register? You can see how two-address architectures like the
> x80
> On Jul 22, 2016, at 8:10 PM, Cameron Kaiser wrote:
>
>>> It's not. Peter is talking about a four-bit field in the
>>> instructions. You're talking about a six-bit field in the program
>>> counter.
>>
>> Something that's always bothered me about three-address architectures
>> like ARM is why
> > It's not. Peter is talking about a four-bit field in the
> > instructions. You're talking about a six-bit field in the program
> > counter.
>
> Something that's always bothered me about three-address architectures
> like ARM is why there is the insistence on that scheduling bottleneck,
> the
On 22/07/2016 21:23, "Pete Turnbull" wrote:
> On 22/07/2016 20:36, Adrian Graham wrote:
>> On 22/07/2016 10:04, "Pete Turnbull" wrote:
>
>>> If you have those, I would strongly recommend you arrange an offsite
>>> backup. Say, about 170 miles north via the A14/A1 :-)
>>
>> I remember why I've
On 22/07/2016 20:36, Adrian Graham wrote:
On 22/07/2016 10:04, "Pete Turnbull" wrote:
If you have those, I would strongly recommend you arrange an offsite
backup. Say, about 170 miles north via the A14/A1 :-)
I remember why I've never fired them up, this is the label on the one with
the Be
-Topic and Off-Topic Posts"
Sent: Friday, July 22, 2016 3:36 PM
Subject: Re: Reproduction micros
On 22/07/2016 10:04, "Pete Turnbull" wrote:
On 22/07/2016 00:33, Adrian Graham wrote:
On 22/07/2016 00:07, "Liam Proven" wrote:
There were only a few
made. They we
On 22/07/2016 10:04, "Pete Turnbull" wrote:
> On 22/07/2016 00:33, Adrian Graham wrote:
>> On 22/07/2016 00:07, "Liam Proven" wrote:
>>
There were only a few
made. They were used internally during development - hence the podule to
connect it to a Beeb, which provided the I/O ear
On 07/21/2016 11:34 PM, Lars Brinkhoff wrote:
> It's not. Peter is talking about a four-bit field in the
> instructions. You're talking about a six-bit field in the program
> counter.
Something that's always bothered me about three-address architectures
like ARM is why there is the insistence o
Lars Brinkhoff writes:
> The link you posted above says "Sophie maintains that "inspired by"
> isn't the right choice of words." [...] I'm just genuinely curious
> exactly which features of the 6502 and ARM instruction sets people
> think are so alike?
I've always interpreted the "inspired by" d
On 22 July 2016 at 10:26, Pete Turnbull wrote:
> I took that as "SA110 came in a plastic QFP, ..., with threaded shanks".
>
> I see that what you evidently meant was "the Alpha, which had threaded
> shanks".
Well, no, I meant to write exactly what I did write, drawing a
comparison between the two
On 22/07/2016 00:56, Paul Koning wrote:
PLCC and PQFP both are plastic packages with leads on all 4 sides.
But PLCC specifically means a package with J-leads: the legs come out
the package side, go straight down, and tuck under the package in a
J-shaped curve. PQFP (and variations with similar a
On Thu, Jul 21, 2016 at 09:55:26PM -0600, ben wrote:
[...]
> A read and cuss item I see. Thank you, but it seems it is still big $$$ for
> good compiler to follow the ever changing rules.
Eh? The LLVM backend generates excellent code for at least x86 and ARM, and is
effectively BSD-licenced.
On 22/07/2016 00:33, Adrian Graham wrote:
On 22/07/2016 00:07, "Liam Proven" wrote:
There were only a few
made. They were used internally during development - hence the podule to
connect it to a Beeb, which provided the I/O early on - and in the later
stages before the Archimedes launch in 19
On 22/07/2016 00:07, Liam Proven wrote:
On 21 July 2016 at 23:26, Pete Turnbull
wrote:
There were only a few made. They were used internally during
development - hence the podule to connect it to a Beeb, which
provided the I/O early on - and in the later stages before the
Archimedes launch i
On 22/07/2016 00:07, Liam Proven wrote:
On 21 July 2016 at 23:26, Pete Turnbull
Hmm. Never seen one like that. None of the ones I've seen in
real life are PQFPs, and none have a heatsink.
Perhaps you misread my message.
Ah, I misunderstood. You wrote:
The SA110 came in a plastic QFP,
Liam Proven writes:
> Peter Corlett wrote:
>> In ARM, *all* instructions can be predicated. Because instructions
>> are 32 bits wide, it has the luxury of allocating four bits to select
>> from one of 16 possible predicates based on the CPU flags.
>
> If I understand it correctly, this caused consi
> An occasionally forgotten feature is that ALU operations also have a S-bit to
> indicate whether they should update the flags based on the result, or leave
> them alone.
Power ISA also has this feature (the so-called "dot" instructions). It also
has special forms of instructions for setting the
> On Jul 21, 2016, at 8:55 PM, ben wrote:
>
> On 7/21/2016 9:34 PM, Guy Sotomayor Jr wrote:
>>
>>> On Jul 21, 2016, at 6:53 PM, ben wrote:
>>>
>>> On 7/20/2016 10:42 AM, Pete Turnbull wrote:
On 20/07/2016 16:44, Paul Koning wrote:
> It is true that a few RISC architectures are
On 7/21/2016 9:34 PM, Guy Sotomayor Jr wrote:
On Jul 21, 2016, at 6:53 PM, ben wrote:
On 7/20/2016 10:42 AM, Pete Turnbull wrote:
On 20/07/2016 16:44, Paul Koning wrote:
It is true that a few RISC architectures are not very scrutable.
Itanium is a notorious example, as are some VLIW machin
> On Jul 21, 2016, at 6:53 PM, ben wrote:
>
> On 7/20/2016 10:42 AM, Pete Turnbull wrote:
>> On 20/07/2016 16:44, Paul Koning wrote:
>>
>>> It is true that a few RISC architectures are not very scrutable.
>>> Itanium is a notorious example, as are some VLIW machines. But many
>>> RISC machines
On 7/20/2016 10:42 AM, Pete Turnbull wrote:
On 20/07/2016 16:44, Paul Koning wrote:
It is true that a few RISC architectures are not very scrutable.
Itanium is a notorious example, as are some VLIW machines. But many
RISC machines are much more sane. MIPS and ARM certainly are no
problem for
On 07/21/2016 04:56 PM, Paul Koning wrote:
> PLCCs have fairly limited lead counts; they were common for 44 lead
> packages, and perhaps a bit more.
I"ve probably got more 68 pin PLCCs than anything else; I've got various
ICs in 84 pin PLCC, including a some CPLDs and CPUs (e.g., 80C188EB).
The co
> On Jul 21, 2016, at 7:07 PM, Liam Proven wrote:
>
> ...
>> They're all plastic pin grid array
>> packages. No heatsink at all. Nor does the datasheet for the PQFP show
>> anything related to a heatsink. It also shows a PLCC version; no heatsink
>> there either, and again I've never seen on
On 22/07/2016 00:07, "Liam Proven" wrote:
>> There were only a few
>> made. They were used internally during development - hence the podule to
>> connect it to a Beeb, which provided the I/O early on - and in the later
>> stages before the Archimedes launch in 1987, several were loaned to softwa
On 21 July 2016 at 23:26, Pete Turnbull wrote:
> Um, isn't that pretty much what I wrote? I'm pretty sure the first
> batch(es) weren't rated for the full 200.
I don't know; I'm basing this comment mainly on Wikipedia.
>
> Hmm. Never seen one like that. None of the ones I've seen in real lif
On 21 July 2016 at 22:22, Peter Corlett wrote:
> On Wed, Jul 20, 2016 at 09:02:41PM +0200, Liam Proven wrote:
>> On 19 July 2016 at 17:04, Peter Corlett wrote:
> [...]
>>> RISC implies a load-store architecture, so that claim is redundant.
>> Could you expand on that, please? I think that IKWYM b
On Thu, 2016-07-21 at 17:20 +0200, Liam Proven wrote:
> On 21 July 2016 at 16:45, Lars Brinkhoff wrote:
> > I have both the ARM and the 6502 instruction sets very fresh in my mind
> > right now. I don't see how the ARM could be a 6502 knockoff, even
> > without that sauce. Care to explain in mor
On 21/07/2016 15:12, Liam Proven wrote:
On 21 July 2016 at 15:24, Pete Turnbull wrote:
But a StrongARM [ ... ] initially ran 3 times as
fast [ ... ] and eventually SA-110 ran to over 200MHz) yet
uses less power.
OK. I think the first announced StrongARM, the SA110, was announced as
running
Liam Proven writes:
> On 21 July 2016 at 16:45, Lars Brinkhoff wrote:
>> I have both the ARM and the 6502 instruction sets very fresh in my mind
>> right now. I don't see how the ARM could be a 6502 knockoff, even
>> without that sauce. Care to explain in more detail?
>
> This is a matter of hi
> On Jul 21, 2016, at 4:22 PM, Peter Corlett wrote:
>
> ...
> A predicated instruction is one that does or does not execute based on some
> condition. CISC machines generally use condition codes (aka flags), and only
> have predicated branch instructions. Branch-not-equal, that kind of things.
>
> On Jul 21, 2016, at 4:22 PM, Peter Corlett wrote:
>
> On Wed, Jul 20, 2016 at 09:02:41PM +0200, Liam Proven wrote:
>> On 19 July 2016 at 17:04, Peter Corlett wrote:
> [...]
>>> RISC implies a load-store architecture, so that claim is redundant.
>> Could you expand on that, please? I think tha
In ARM, *all* instructions can be predicated.
Until recently.
On Wed, Jul 20, 2016 at 09:02:41PM +0200, Liam Proven wrote:
> On 19 July 2016 at 17:04, Peter Corlett wrote:
[...]
>> RISC implies a load-store architecture, so that claim is redundant.
> Could you expand on that, please? I think that IKWYM but I'm not sure.
A load-store architecture is one wher
On 21 July 2016 at 16:45, Lars Brinkhoff wrote:
> I have both the ARM and the 6502 instruction sets very fresh in my mind
> right now. I don't see how the ARM could be a 6502 knockoff, even
> without that sauce. Care to explain in more detail?
This is a matter of historical record, AIUI.
http
Peter Corlett writes:
> IMO, it's the predicated instructions that is ARM's special sauce and
> the real innovation that gives it a performance boost. Without those,
> it'd be just a 32 bit wide 6502 knockoff.
I have both the ARM and the 6502 instruction sets very fresh in my mind
right now. I d
> On Jul 21, 2016, at 8:38 AM, Liam Proven wrote:
>
> On 20 July 2016 at 21:29, Paul Koning wrote:
>> I don't remember the earlier ARM designs, but it was my impression that
>> DEC's StrongARM was the one that made really large strides in low power
>> (especially power per MHz of clock speed)
On 21 July 2016 at 15:24, Pete Turnbull wrote:
>
> Yes and no. StrongARM was even lower power as well as faster. If you're
> suggesting that that's just evolution due to things like reduced process
> size, I possibly agree. But a StrongARM has many times as many transistors
> as an ARM3 (for ex
On 21/07/2016 13:38, Liam Proven wrote:
On 20 July 2016 at 21:29, Paul Koning
wrote:
I don't remember the earlier ARM designs, but it was my impression
that DEC's StrongARM was the one that made really large strides in
low power
Hmm. That wasn't my impression at the time, no.
The big deal w
On 20 July 2016 at 21:29, Paul Koning wrote:
> I don't remember the earlier ARM designs, but it was my impression that DEC's
> StrongARM was the one that made really large strides in low power (especially
> power per MHz of clock speed). Interestingly enough, StrongARM was one of
> the few (an
> On Jul 20, 2016, at 6:28 PM, Pete Turnbull wrote:
>
> On 20/07/2016 20:29, Paul Koning wrote:
>
>> I don't remember the earlier ARM designs, but it was my impression
>> that DEC's StrongARM was the one that made really large strides in
>> low power (especially power per MHz of clock speed).
On 20/07/2016 20:29, Paul Koning wrote:
I don't remember the earlier ARM designs, but it was my impression
that DEC's StrongARM was the one that made really large strides in
low power (especially power per MHz of clock speed). Interestingly
enough, StrongARM was one of the few (and the first?)
> On Jul 20, 2016, at 3:02 PM, Liam Proven wrote:
>
> ...
> I think it's fair to say that ARM was a relatively early RISC
> implementation *in term of single chip processors*, that it was
> remarkably simple compared to others of that time (as in, smaller,
> more reduced, fewer transistors, etc.
On 19 July 2016 at 17:04, Peter Corlett wrote:
> From there, it seems to be saying that the essence of the invention is that
> the
> ARM ISA is RISC, it is a load-store architecture, and the CPU was pipelined.
>
> RISC implies a load-store architecture, so that claim is redundant.
Could you expa
On 20 July 2016 at 19:34, Cameron Kaiser wrote:
>> Also, RISC does not use, or need, microcode.
>
> I'm not sure what you mean by this, but (for example) many POWER
> implementations have microcode (example: the 970/G5, which is descended from
> POWER4).
Isn't the general belief that many success
On 20 July 2016 at 17:44, Paul Koning wrote:
> It is true that a few RISC architectures are not very scrutable. Itanium is
> a notorious example, as are some VLIW machines.
Hang on. Itanium is not RISC -- it *is* VLIW. Isn't it?
--
Liam Proven • Profile: http://lproven.livejournal.com/profil
> > > Also, RISC does not use, or need, microcode.
> >
> > I'm not sure what you mean by this, but (for example) many POWER
> > implementations have microcode (example: the 970/G5, which is descended from
> > POWER4).
>
> What I meant is that I had no idea such things existed. Very curious.
> Le
On 7/20/16 10:34 AM, Cameron Kaiser wrote:
>> Also, RISC does not use, or need, microcode.
>
this confuses architecture and implementation
the Ridge 32 has a RISC instruction set, but was implemented in micrcode
> On Jul 20, 2016, at 1:53 PM, Swift Griggs wrote:
>
> On Wed, 20 Jul 2016, Paul Koning wrote:
>> The closest to microcode I'd ever heard of before is the "epicode" in
>> Alpha. Or was that Prism?
>
> PALcode? That's sort of an amalgamation of microcode and emulation, IIRC.
> I don't know wh
On Wed, 20 Jul 2016, Paul Koning wrote:
> The closest to microcode I'd ever heard of before is the "epicode" in
> Alpha. Or was that Prism?
PALcode? That's sort of an amalgamation of microcode and emulation, IIRC.
I don't know what 'epicode' is, though.
-Swift
> On Jul 20, 2016, at 1:34 PM, Cameron Kaiser wrote:
>
>> Also, RISC does not use, or need, microcode.
>
> I'm not sure what you mean by this, but (for example) many POWER
> implementations have microcode (example: the 970/G5, which is descended from
> POWER4).
What I meant is that I had no id
> Also, RISC does not use, or need, microcode.
I'm not sure what you mean by this, but (for example) many POWER
implementations have microcode (example: the 970/G5, which is descended from
POWER4).
--
personal: http://www.cameronkaiser.com/ --
Cameron Kaise
> > It is true that a few RISC architectures are not very scrutable.
> > Itanium is a notorious example, as are some VLIW machines. But many
> > RISC machines are much more sane. MIPS and ARM certainly are no
> > problem for any competent assembly language programmer.
>
> Indeed. I've written a
On 20/07/2016 16:44, Paul Koning wrote:
It is true that a few RISC architectures are not very scrutable.
Itanium is a notorious example, as are some VLIW machines. But many
RISC machines are much more sane. MIPS and ARM certainly are no
problem for any competent assembly language programmer.
> On Jul 20, 2016, at 9:56 AM, Noel Chiappa wrote:
>
>> From: Paul Koning
>
>>> I always felt that RISC meant 'making the basic cycle time as fast as
>>> possible by finding the longest path through the logic - i.e. the
>>> limiting factor on the cycle time - and removing it (thereby making th
On 20/07/2016 14:56, Noel Chiappa wrote:
My formulation for RISC had two parts, though: not just minizing the cycle
time, but doing so by doing things that (as a side-effect) make the
instruction set less capable.
At least for some RISC, that's more than a side effect. While at Acorn
in abou
> From: Paul Koning
>> I always felt that RISC meant 'making the basic cycle time as fast as
>> possible by finding the longest path through the logic - i.e. the
>> limiting factor on the cycle time - and removing it (thereby making the
>> instruction set less rich); then repe
On Tue, Jul 19, 2016 at 9:36 AM, Paul Koning wrote:
> RISC, as a term, may come from IBM, but the concept goes back at least as far
> as the CDC 6000 series. Pipelining, to the CDC 7600.
Possibly depending on exactly how you define it, pipelining may go
back to the IBM 7030 "Stretch" (1961). Al
On Sat, Jul 16, 2016 at 6:25 AM, Peter Corlett wrote:
> On Thu, Jul 14, 2016 at 01:03:31PM -0600, ben wrote:
> [...]
>> I had hopes on the Amiga until they came out with the 2000*.
>> * Lets add a brain dead cpu and run DOS.
>
> The A2088 was an add-in option. Back in the day, only one of my A2000
On 7/19/2016 9:04 AM, Peter Corlett wrote:
On Tue, Jul 19, 2016 at 03:30:19PM +0200, Liam Proven wrote: [...]
There's a hint here, though:
https://www.epo.org/learning-events/european-inventor/finalists/2013/wilson/feature.html
From there, it seems to be saying that the essence of the
invent
> On Jul 19, 2016, at 12:10 PM, Noel Chiappa wrote:
>
>> From: Paul Koning
>
>> The article, as usual, talks about a whole bunch of things that are
>> much older than the author seems to know.
>
> "The two most common things in the universe are hydrogen and stupidity." OK,
> so technically it'
> From: Paul Koning
> The article, as usual, talks about a whole bunch of things that are
> much older than the author seems to know.
"The two most common things in the universe are hydrogen and stupidity." OK,
so technically it's ignorance, not stupidity, but in my book it's stupid t
> On Jul 19, 2016, at 11:04 AM, Peter Corlett wrote:
>
> On Tue, Jul 19, 2016 at 03:30:19PM +0200, Liam Proven wrote:
> [...]
>> There's a hint here, though:
>> https://www.epo.org/learning-events/european-inventor/finalists/2013/wilson/feature.html
>
> From there, it seems to be saying that th
On Tue, Jul 19, 2016 at 03:30:19PM +0200, Liam Proven wrote:
[...]
> There's a hint here, though:
> https://www.epo.org/learning-events/european-inventor/finalists/2013/wilson/feature.html
>From there, it seems to be saying that the essence of the invention is that the
ARM ISA is RISC, it is a loa
On 19 July 2016 at 06:30, Eric Smith wrote:
>
> I've seen this claim in the past. I've looked over the chipset design,
> and I don't think it did any more wonderful a job of supporting cheap
> commodity DRAM than the other common chipsets of the era. Perhaps
> someone with greater familiarity with
On Mon, Jul 18, 2016 at 9:59 AM, Liam Proven wrote:
> In detailed
> technical ways I confess I do not fully understand, the ARM2 and its
> chipset's design was optimised to work with cheap DRAM with relatively
> slow cycle times.
I've seen this claim in the past. I've looked over the chipset desi
On 17 July 2016 at 20:54, Peter Corlett wrote:
> I think it should be quite obvious from the prices why the Amiga 2000 didn't
> ship with a 68020 as standard.
Exactly so.
This is part of the brilliance of the Archimedes, AIUI. In detailed
technical ways I confess I do not fully understand, the
On 17 Jul 2016, at 17:28, Liam Proven wrote:
[...]
> Again with the "braindead" jibes. You have not clarified or explained
> what your objection to the machine was.
We perhaps forget just how eyewateringly expensive these things were. They were
"braindead" because to build them "properly" would
On 16 July 2016 at 19:16, Christian Corti
wrote:
> The A2000 did *not* have a built-in hard disk, that was the A3000. The A2000
> was just an "updated" A1000 in a large desktop case with Zorro slots...
> completely braindead.
Again with the "braindead" jibes. You have not clarified or explained
w
A2000HD had the built in hard drive.
-Original Message-
From: Christian Corti
Sent: Saturday, July 16, 2016 1:16 PM
To: General Discussion: On-Topic and Off-Topic Posts
Subject: Re: Reproduction micros
On Sat, 16 Jul 2016, Peter Corlett wrote:
main compelling feature of the A2000
On Sat, 16 Jul 2016, Peter Corlett wrote:
main compelling feature of the A2000 was the built-in hard disk.
The A2000 did *not* have a built-in hard disk, that was the A3000. The
A2000 was just an "updated" A1000 in a large desktop case with Zorro
slots... completely braindead.
Christian
Peter Corlett writes:
> Commodore UK also released the A1500 which was an A2000 without hard
> disk but with an extra floppy drive, i.e. the same spec as a typical
> A500 gaming rig. It apparently flew off the shelves, although I'm not
> sure why given it cost somewhat more than the A500 equivale
On Thu, Jul 14, 2016 at 01:03:31PM -0600, ben wrote:
[...]
> I had hopes on the Amiga until they came out with the 2000*.
> * Lets add a brain dead cpu and run DOS.
The A2088 was an add-in option. Back in the day, only one of my A2000-owning
friends had a bridgecard. I was given a demo, and it was
On 14 July 2016 at 21:03, ben wrote:
> * Lets add a brain dead cpu and run DOS.
Oh, come on, for the time, it was OK.
DOS compatibility looked like it'd be a selling point, although it
didn't actually prove to be a big one AIUI.
The A2000 came out in '87, the same year as the 68030, so includin
On 7/14/2016 8:50 AM, Swift Griggs wrote:
I do wish I'd got the chance to use Amigas to do something "real" when
they were state of the art. That or I wish I'd had an A500 the day they
hit the shelves and had all the cool games. I'm sure that would have been
a lot of fun.
I had hopes on the Am
On 12 July 2016 at 18:10, Steve Browne wrote:
> The ZX Spectrum Next is going to be interesting http://www.specnext.com/
>
> Look at that industrial design! Designed by Rick Dickinson who was behind
> the ZX80,ZX81, ZX Spectrum, Spectrum Plus and QL
It's pretty but they're only renders so fa
On 14 July 2016 at 17:56, Brad H wrote:
> My question about the FPGA Amigas is can you not just emulate pretty much
> anything on a PC these days? I never tried Amiga emulation (if I have the
> real thing I always go to that). Not sure how much the emulators can
> handle.
Yes you can, and somet
org] On Behalf Of Swift
Griggs
Sent: Thursday, July 14, 2016 7:50 AM
To: General Discussion: On-Topic and Off-Topic Posts
Subject: RE: Reproduction micros
On Wed, 13 Jul 2016, Brad H wrote:
> I think the Amiga project is neat, although personally I'm not sure
> I'd find a need for on
On Wed, 13 Jul 2016, Brad H wrote:
> I think the Amiga project is neat, although personally I'm not sure I'd
> find a need for one.
I have an Amiga 3000 (my personal favorite), but I have limited space so I
can only have about two "classic" systems set up at once (and those are
usually SGI mach
On Thu, Jul 14, 2016 at 12:44:19AM -0500, Sam O'nella wrote:
> I haven't built or marketed anything myself but i believe if i understood
> correctly from several folks who have that vga was a cheaper choice due to
> licensing costs for dvi or hdmi at the time.
Parts of DVI are patented, but ther
> -Original Message-
> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Sam
> O'nella
> Sent: 14 July 2016 06:44
> To: General Discussion: On-Topic and Off-Topic Posts
>
> Subject: RE: Reproduction micros
>
> I haven't built or market
Original message
The thing about the Amiga was its wow factor -- I remember
walking into Compucentre (Canadian chain) in the mid-80s.. and there's all
the computers from 8 bit heaven and their 16 color graphics (if you were
lucky).. and then there's this one computer on a pedes
I haven't built or marketed anything myself but i believe if i understood
correctly from several folks who have that vga was a cheaper choice due to
licensing costs for dvi or hdmi at the time.
Not sure if vga is past that point or open but when keeping home brew kits
cheap for us hobbyists e
It's pretty cool seeing what people are doing out there. I like when people
replicate things that are super rare -- like the Mark-8, SCELBI, etc.And
it's definitely cool to see projects like the Altair clone, with its big
empty case, all the hardware being emulated by a tiny little replacement
On 7/13/2016 5:29 PM, Dave Wade wrote:
-Original Message-
From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of ben
Sent: 14 July 2016 00:24
To: cctalk@classiccmp.org
Subject: Re: Reproduction micros
On 7/13/2016 3:53 PM, Dave Wade wrote:
The modern replacements have the
> -Original Message-
> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of ben
> Sent: 14 July 2016 00:24
> To: cctalk@classiccmp.org
> Subject: Re: Reproduction micros
>
> On 7/13/2016 3:53 PM, Dave Wade wrote:
>
> >
> > The modern repl
On 7/13/2016 3:53 PM, Dave Wade wrote:
The modern replacements have the advantage they can use a "modern" VGA
display, SD-Card for data not slow cassette tape.
So you ARE THE EVIL ONE! I had to pick up a "MODERN" VGA and can not do
any thing with the *#%&!@* wide screen. Even GOOD TV like S
> -Original Message-
> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of ben
> Sent: 13 July 2016 19:49
> To: cctalk@classiccmp.org
> Subject: Re: Reproduction micros
>
> On 7/12/2016 10:41 AM, Dave Wade wrote:
> > There is an on-going C
On 7/12/2016 10:41 AM, Dave Wade wrote:
There is an on-going CoCo 3 in FPGA.
http://www.brianholman.com/retrocompute/files/coco3fpga.html
Spectrum III
http://www.mike-stirling.com/retro-fpga/zx-spectrum-on-an-fpga/comment-page-
1/
but lots more about
Dave
Strange ... how all the computers
On 12 July 2016 at 21:41, Swift Griggs wrote:
> On Tue, 12 Jul 2016, Steve Browne wrote:
> > The ZX Spectrum Next is going to be interesting
> http://www.specnext.com/
>
> Wow! I hope that takes off. It's beautiful. Plus, in other news, they will
> ship schematics! Wow.
>
> > Look at that ind
On Tue, 12 Jul 2016, Rod Smallwood wrote:
> Well I could do front and back panels. In fact anything that needs silk
> screening. Rod (Panelman) Smallwood
As a hobbyist I've made a few tee-shirts, bags, and other items using a
real silk screen, transparencies, photo resist emulsion, PVC inks, and
On Tue, 12 Jul 2016, Steve Browne wrote:
> The ZX Spectrum Next is going to be interesting http://www.specnext.com/
Wow! I hope that takes off. It's beautiful. Plus, in other news, they will
ship schematics! Wow.
> Look at that industrial design! Designed by Rick Dickinson who was
> behind
On Tue, 12 Jul 2016, Eric Christopherson wrote:
> MEGA65 FPGA-based Commodore 65 remake: http://mega65.org/
That project looks amazing! Does anyone know how far along they are? The
web page is dated 2015, but that probably doesn't mean much. However, it's
clear they aren't shipping, yet.
One t
> -Original Message-
> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Kurt K
> Sent: 12 July 2016 19:10
> To: General Discussion: On-Topic and Off-Topic Posts
>
> Subject: Re: Reproduction micros
>
> I haven't heard of these projects.
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