coreboot documentation directory and have known bugs and or
> feature requests render in an equivelent manner?
>
>
> On 5/12/21 6:48 pm, Matt B wrote:
>
> From my point of view, I'd be very grateful if we could get this
>> community strongly engaged in getting upstream coreboot builds
there's always a tradeoff.
> > >>>
> > >>> From my point of view, I'd be very grateful if we could get this
> > >>> community strongly engaged in getting upstream coreboot builds
> working
> > >>> on, e.g., chromeb
>
> It's just software, so it could certainly be done. How much work would
> be involved is the right question. Alas, I have no idea. One needs to
> study the AGESA sources to tell, I guess.
>
This question has come up time and time again:
What would actually be involved in {"cleaning up","doing
>
> On a side note is there any kind of crowd sourcing platform / escrow
> service for GPL projects? I know it's been talked about, and there have
> been attempts made. But as far as I can tell, nothing has ever prospered.
If someone wanted to work with one of the approved coreboot contractors
My two cents regarding funding:
There are quite a lot of concerned users who use AGESA platforms, but
aren't able to directly contribute to development (documentation and guides
are indeed thin). Funding through the usual channels for the overall
coreboot project seems to be impractical for
It's definitely preferable to have platforms working in-tree rather than
out of tree. This is a *significant* portion of coreboot's supported
platforms and sends a strong signal to anyone using or considering them
that they can just forget about the coreboot project because the rug may be
pulled
Greetings,
What is the status of native raminit on haswell? It's the first generation
that doesn't have a native implementation.
I did find some seemingly successful past work [1] but what happened to it?
Did it run into a blocker issue or was it just abandoned in favor of other
priorities?
[1]
Would the DT/MT board be expected to work?
On Sat, Oct 16, 2021 at 4:04 PM Matt B wrote:
> A question about Optiplex 7010 motherboards:
>
> It appears (at least to me) that the DT and MT variants of the 7010 use
> the same motherboard, different from the SFF.
> The docs specify
A question about Optiplex 7010 motherboards:
It appears (at least to me) that the DT and MT variants of the 7010 use the
same motherboard, different from the SFF.
The docs specify the SFF version. Has any testing been done on the DT/MT
motherboard?
The only mention in the documentation:
> There
's all still there if
> they know the tag.
>
> On Tue, Oct 5, 2021 at 1:02 PM Matt B wrote:
> >
> > I should note I'm not 100% sure what they're doing there.
> >
> > Are there any more of these buggy pentiums left in the coreboot tree?
> (If he chooses to update) I
ght be worth adding the text of this comment (modified as
> needed) to the CL so that in years to come people understand the
> reasons.
>
> On Tue, Oct 5, 2021 at 12:51 PM Matt B wrote:
> >
> > A quick google turned this up:
> >
> https://chromium.googlesource.com/chro
A quick google turned this up:
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-3.0/arch/x86/kernel/cpu/intel.c#253
On Tue, Oct 5, 2021 at 4:06 AM Julian Stecklina <
julian.steckl...@cyberus-technology.de> wrote:
> On Tue, 2021-10-05 at 09:29 +0300, Kyösti Mälkki wrote:
> What coreboot problems that we have seen in the past are we actually
solving with these rewrites?
To be a bit more blunt, what is expected to be improved by writing it in
python?
Utilities, eg. to analyse blobs?
Menu and configuration of builds?
Packing blobs for flashing?
I could see some
Hello,
Thanks Angel. To clarify, the part of the chipset you're referring to would
be the memory controller on the CPU, yes? Not somewhere on the southbridge?
Thanks,
-Matt
On Wed, Sep 8, 2021 at 11:33 AM Angel Pons wrote:
> Hi Matt, list,
>
> On Wed, Sep 8, 2021 at 3:29 PM Matt
Would an Ivybridge CPU even be expected to work with RDIMMs? Was this
something anticipated when native raminit was written?
-Matt
On Mon, Sep 6, 2021 at 6:00 PM Michał Żygowski
wrote:
> Hi Matthew,
>
> On 8/31/21 11:46 PM, Matt B wrote:
> > Hello Patrick,
> >
> > T
HRB 17519
> Geschäftsführung: Sebastian Deutsch, Eray Basar
>
> Datenschutzhinweise nach Art. 13 DSGVO
>
> On Fri, Aug 13, 2021 at 9:46 PM Matt B wrote:
> >
> > Greetings,
> >
> > I gather that while native ram init is very far along and quite
> featureful, i
Greetings,
I gather that while native ram init is very far along and quite featureful,
it doesn't support ECC. I'm interested to know if there have been past
attempts at it, and what might be required for it to work.
In the unofficial mapping [1] it looks like there's just one register to
turn
I'm not touchin' any of this.
Reminds me an awful lot of the story of the PowerVR leak's cautionary tale:
https://libv.livejournal.com/26972.html
-Matt
On Thu, Aug 6, 2020 at 3:40 PM Simon Newton wrote:
>
>
Hi,
Doing a quick google this comes up, where it seems someone else looked at
this CPU before:
https://www.mail-archive.com/search?l=coreboot@coreboot.org=subject
:"\[coreboot\]+Re\%3A+About+support+for+my+netbook"=newest=1
It seems there's no support for this CPU/chipset in coreboot, ao at the
Hi,
Noticed someone running a GA-B75M-D3V with coreboot but that it hadn't had
a status report since 2017. I did notice that GA-B75M-D3H is still around
though with a status from may of 2019.
Is the GA-B75M-D3H supported in the latest master? What's the difference
between these two?
Thanks,
Hi,
Quick question before I go out and buy a different motherboard for my G505s:
To those who have a dual-GPU G505s and have enabled the recent support for
the dGPU, does DRI_PRIME GPU offloading work?
Thanks,
-Matt
PS. Could here be an option created to enable/disable the dGPU at boot
>
> Further work is required to make it stable and cross-platform.
>
What is it that triggers the instability (freezing?)? Does it have to do
with the the nvidia drivers?
What do you mean by cross-platform? are there other laptops which might
benefit from it?
Sincerely,
-Matt
On Fri, Feb 28,
Is [1] the current, most recent work on supporting nvidia Optimus?
It seems to be fairly complete (aside from some stability issues) and
frequently worked on.
-Matt
[1] https://review.coreboot.org/c/coreboot/+/28380
On Thu, Feb 20, 2020 at 2:28 PM Matt B wrote:
> Hi,
>
> As I u
Hi,
As I understand it, the only thing missing with regard to nvidia dGPUs on
Coreboot are the ACPI calls to turn them on and off at run-time, which is
what Optimus is. Things like DRI_PRIME and similar work just fine as long
as the dGPU is running, even under nouveau.
What is the current status
Hello,
4.11-400
What is the extra -400? It doesn't seem like a commit hash.
Sincerely,
-Matt
On Thu, Dec 12, 2019 at 5:23 PM Kyösti Mälkki
wrote:
> On Thu, Dec 12, 2019 at 11:58 AM Mike Banon wrote:
> >
> > It would be nice if this "drop time" could be extended until at least
> > mid
:
> On 09.12.2019 05:36, Matt B wrote:
>
> Hi,
>
> Hi Matt,
>
>
> Thanks for the pointer.
>
> I need a bit more context here, being completely unfamiliar with how
> coreboot works.
> I've never done any non-userspace programming, and this is the first time
>
unchanged?
Sincerely,
-Matt
[1] https://review.coreboot.org/c/coreboot/+/37453/9
[2] https://review.coreboot.org/c/coreboot/+/37440/10
[3] src/mainboard/asus/am1i-a/romstage.c (for reference:
https://pastebin.com/kSka2YL7)
On Sun, Dec 8, 2019 at 6:57 PM Kyösti Mälkki
wrote:
> On Mo
Hi,
I have heard an unverified rumour that Atom substitutes the ME for an ARM
microcontroller running Trustzone.
If this is the case however, it's possible it's only for bringup, in which
case it's not too much different from the inaccessible micrcontrollers
already present in most x86 silicon.
As somebody who's abused the hell out of pcie extenders (I have over three
meters of pcie-over-cheap-usb3.0-cable in one box) I've never had an
obvious issue so it seems pretty tolerant. You probably just won't get the
same transfer speed.
I would check if any drives you have show up as being
If so, is there an option to test the C bootblock in the menu somewhere?
Thanks,
-Matt
On Sun, Dec 8, 2019 at 5:19 PM Matt B wrote:
> Ok. I'm kind of annoyed at myself now.
>
> Your thread revealed the answer. The stock bios will boot if the dimm is
> in either slot. Corebo
>
> Regards,
>
> Eli
> On 08/12/2019 19:43, Matt B wrote:
>
> Hi,
>
> In the spirit of board report coverage, I pulled out the (used, but new to
> me) AM1I-A I have and spent a day or two trying to install the latest
> coreboot on it.
>
> The board boots fine und
I've also left the board for an hour or two, just in case this was slow ram
training or something
-Matt
On Sun, Dec 8, 2019 at 1:43 PM Matt B wrote:
> Hi,
>
> In the spirit of board report coverage, I pulled out the (used, but new to
> me) AM1I-A I have and spent a day or two tryin
Hi,
In the spirit of board report coverage, I pulled out the (used, but new to
me) AM1I-A I have and spent a day or two trying to install the latest
coreboot on it.
The board boots fine under the stock bios, and returns to working order if
flashed with my backup, but shows little signs of life
Hi,
I noted this on this thread's companion regarding AGESA, but I'd be willing
to put up some money on https://www.bountysource.com/ for migration away
from ROMCC_BOOTBLOCK.
I could have sworn asus/am1i-a mentioned over there was a BinaryPI board.
Thoughts?
Sincerely,
-Matt
On Wed, Dec 4,
Hi,
Regarding lenovo/g505s, asus/am1i-a, and maybe some others (suggestions
welcome!) I'd be willing to put up some money on
https://www.bountysource.com/ for their migration away from ROMCC_BOOTBLOCK.
Thoughts?
Sincerely,
-Matt
On Wed, Dec 4, 2019 at 10:26 AM Michal Zygowski
wrote:
>
>
Hello,
Adding to this, it would also be good to have what
CPUs/chipsets/superIOs/etc coreboot supports. As I mentioned in another
thread, this information is currently very disparate and out of date and
can only really discovered by asking on this mailing list.
Sincerely,
-Matt
On Mon, Oct
Neat. I've seen a few of these pop up every couple of months.
A lot of them seems to be sold from the UK, dunno why.
-Matt
On Fri, Oct 4, 2019 at 12:18 PM Ivan Ivanov wrote:
> Mike found a good condition G505S with top A10-5750M CPU preinstalled,
> being sold for a good price:
>
>
>
Hello,
Shifting away from the focus of [1] I'm interested in how hard it would be
to port coreboot to the AM1M-A. This board seems to be a larger version of
the supported AM1I-A and is known to officially support ECC. (the manuals
for the AM1I-A [2] and AM1M-A [3])
The porting guide at [4] is
otherboard can be found at:
https://www.intel.com/content/dam/support/us/en/documents/motherboards/server/s1200kp/sb/g38894002_s1200kp_tps_r1_1.pdf
On Sun, Sep 29, 2019 at 1:58 PM Lance Zhao wrote:
> https://github.com/IntelFsp/FSP that shall have all the current platform
> that FSP can sup
Hello,
I'm trying to check the potential compatibility of the s1200kp intel server
board. [1] It's mini-itx and supports ECC ram, making it attractive for use
in a NAS device. (cases with multiple hotswap bays and room for an itx
board abound, but few itx boards have ECC capability)
The chipset
2xxx or something) support that.
>
> Buffered/Registered RAM exists for servers that need to use large amounts
> of RAM, hundreds of GB or even a TB or more (for multi-CPU systems).
>
> -Alberto
> On 26/09/19 03:34, Matt B wrote:
>
> Hello,
>
> This might be a du
in a couple of weeks.
Sincerely,
-Matt
On Mon, Sep 23, 2019 at 8:06 PM Matt B wrote:
> Hello,
>
> That has short but very informative indeed. Thank you. :)
>
> Even if the pinout is the same, is it possible that some connections have
> been left disconnected or comp
Hello,
That has short but very informative indeed. Thank you. :)
Even if the pinout is the same, is it possible that some connections have
been left disconnected or components unpopulated on the board, which would
prevent ECC from working?
As a more general porting question, what steps should
Greetings,
The AM1I-A [1] is supported by Coreboot, while the AM1M-A [2] is not. The
latter seems to be a larger version of the first, with more
expansion options.
For the smaller 'I' not much is stated in the manual [3] except to check
the "qualified vendor list" on ASUS' site. It does list
>
> There is essentially no interest for new board ports on AGESA/binaryPI,
> these platforms have mostly survived in the tree due to commercial support
> to maintain them.
>
This seems to be untrue when boards like the Asus AM1I-A were ported as
recently as last year. [1] It's a AMD family 16h
Kyösti Mälkki said:
> AFAICS, that platform codebase even suffers from cache coherency issues
> while executing from cache-as-ram; there has been indications that
> increased spinlock usage in romstage causes boot failures and/or reset
> loops.
>
Where do you see this? Has it been reported?
Hello,
I'd be happy to kick more than a few bucks towards hardware or other costs.
Just need to know where to send it.
I'll also drop a post over on r/Libreboot.
Sincerely,
-Matt
On Tue, Sep 17, 2019 at 1:33 PM Timothy Pearson <
tpear...@raptorengineering.com> wrote:
> I'd be happy to
Hello,
Are there any up-to-date references you're aware of, for those interested?
-Matt
On Fri, Sep 13, 2019 at 8:44 AM Michal Zygowski
wrote:
> Thank you for response. I already got that working actually yesterdays
> evening :)
>
> If you mean the white paper A Tour Beyond BIOS with the UEFI
Greetings all,
Patrick gregori said:
> Mostly chatter on IRC, to be honest. Part of the intent of this mail was
> to surface this more officially.
>
It would be helpful to carry over more details when porting discussions
from IRC. It is always good to be specific how something is broken, not
-- Forwarded message -
From: Matt B
Date: Tue, Sep 3, 2019 at 1:05 AM
Subject: Re: [coreboot] Re: Web site revamp
To: David Hendricks
Building on that, postmarketOS (which in some ways feels like a weird
sister project to coreboot?) does this thing where they display 3 random
>
> Where I take issue still is that we're nowhere near 100%. On modern
> platforms we're somewhere below 50% and oftentimes well below that. The
> wording is confusing and misleading as-is. ... What is to be gained by
> hiding the reality of the situation from non-technical users visiting the
>
Hello,
This seems to be a fairly accurate assessment of the situation, imo.
It's disappointing to see people shocked by inclusion of binary components
and left with a very negative impression. I've seen coreboot particularly
derided by people who first learn about libreboot from the FSF and
, making it possible to boot windows from within linuxboot-based
payloads.
Sincerely,
-Matthew Bradley
On Wed, Jun 12, 2019 at 11:55 PM Matt B wrote:
> Hi,
>
>
>> I think SeaBIOS already has an option to build a multiboot image. In
>> either case you could also (i
>
> I believe S3 resume path is PSP assisted. When x86 core reset is
> deasserted some parts of the memory controller PHY have already been
> programmed by PSP or SMU firmwares.
(No PSP present on the G505s)
> You should consider binaryPI mostly broken for the purpose of S3
> suspend/resume.
>
Is a lack of C bootblock support common to all family 15h platforms?
(Including the G505s and any others?)
In other words, would it only need to be implemented once for all of these
systems?
Sincerely,
-Matthew Bradley
On Thu, Aug 15, 2019 at 11:50 AM Kyösti Mälkki
wrote:
> Hi
>
> The
Hello,
A couple of years ago I saw Ron's talk on NERF. An acquaintance who
maintains a fleet of machines expressed some interest in NERF. He wants to
boot linux instead of windows, which isn't supported by his (extremely
recent) build of UEFI. (no legacy support whatsoever)
The closest thing I
windows 12 would you need tianocore?
> > >
> > > Need is a harsh word, but the simple answer to a simple question is
> yes,
> > > you do.
> > >
> > > You can use SeaBIOS, but Windows does not officially support legacy
> BIOS
> > > since
ing
>
> On Fri, Apr 12, 2019, 11:46 AM Rafael Send
> wrote:
>
>> Good question, I'd be interested in the answer to this as well if anyone
>> has some insight.
>>
>> Cheers,
>> R
>>
>> On Fri, Apr 12, 2019 at 7:45 AM Matt B
>> wrote:
>>
Hello,
This is perhaps naive, but it's a question that I've been thinking about
for a while.
Pretty much all AMD GPUs (both integrated and otherwise, including PCIe
cards) rely on vgabios blobs for init and to support the driver(s).
>From what I've heard, the people writing open source drivers
-- Forwarded message -
From: Matt B
Date: Mon, Jun 3, 2019 at 7:19 PM
Subject: Re: [coreboot] Re: Starting the coreboot 4.10 release process
To: Mike Banon
On a side note, when more than one option is possible, it's good to know
which the tester used.
Hypothetical example: did
-- Forwarded message -
From: Matt B
Date: Sat, Jun 1, 2019 at 12:17 PM
Subject: Re: [coreboot] Re: ASUS KGPE-D16 ECC disabled by default
To: Kinky Nekoboi
Hi,
So configuring ECC to be on by default in nvram has no effect?
Sincerely,
-Matt
On Sat, Jun 1, 2019 at 11:08 AM
That's pretty impressive, imho. Especially the ability to figure out some
of the steps it goes through during boot.
With AMD suddenly putting out more capable chips, they and the PSP might
become more relevant.
Sincerely,
-Matt
On Fri, May 31, 2019 at 6:05 AM Kinky Nekoboi
wrote:
> Nice
> > On Tue, May 21, 2019 at 12:45 PM Robin C wrote:
> >> Hi,
> >>
> >> Thanks for all info. I wont try coreboot with this board... I hope that
> one day AMD mainboards will be much supported.
> >>
> >> Recetly many security breaches had been
Hi,
Looks like as of this thread there were issues detecting any CPU newer than
a K10:
https://mail.coreboot.org/pipermail/coreboot/2012-April/069394.html
At some point someone tried to get family 15h to work as well, but ran into
issues bringing up sata:
0x31 0x00 0xE3
On Thu, May 9, 2019 at 7:03 PM Matt B wrote:
> Hi,
>
> I didn't get a different binary (at least, using this method) when
> charging the battery, nor did I get different results when doing so under
> full CPU load under linux.
>
> Getting frustrated with the
Hi,
I didn't get a different binary (at least, using this method) when charging
the battery, nor did I get different results when doing so under full CPU
load under linux.
Getting frustrated with the livecd I took a break and tried Hardware
Monitor under windows. The "GPU voltage" was static at
;
> > Best regards,
> > Mike Banon
> >
> > [1] https://review.coreboot.org/c/coreboot/+/31944
> > [2]
> https://www.reddit.com/r/coreboot/comments/ar8v7d/if_your_g505s_does_not_have_a_discrete_gpu/
> > [3] http://dangerousprototypes.com/docs/Lenovo_G505S_hacking
> >
While I think it's great that it worked, I'd recommend flashing with a
programmer before hotswapping the bios chip.
You could work through compiling a fresh copy of coreboot on another
computer, or if someone knows how to extract the bios image from an asus
download you could try restoring that.
That method of emergency recovery with a USB stick has already been wiped
out by installing coreboot.
-Matt
On Mon, Apr 29, 2019 at 4:09 PM Pablo Correa Gómez
wrote:
> Hello and thank you in advance for your time.
>
> I recently bought a KGPE-D16 motherboard with a single AMD Opeteron
>
Out of curiosity, what payload are you using?
-Matthew
On Sun, Apr 14, 2019 at 8:22 AM Enkelena Haxhiu
wrote:
> I am using lenovo thinkpad x230. It has Linux on its ssd, Debian to be
> precise.
>
> You are saying that just because the new hdd has windows, its not booting
> on it?
>
> Regards,
Greetings,
>From what I can find, Linux can only chainload another linux kernel. (via
kexec) Does this mean that a Linux payload like LinuxBoot cannot be used to
boot Windows or another OS, either directly or by chainloading another
payload from CBFS?
It's nice that a Linux payload can provide
On Tue, Mar 26, 2019 at 2:44 PM Matt B wrote:
> Hi,
>
> Good to hear. Does having a regular 2.5 inch drive present affect your
> ability to do this?
>
> The above wiki notes that an msata drive is used as cache whenever such a
> drive is present under the stock BIOS on
Hi,
Does anyone know of a payload (or payloads) that would allow booting from
an mSATA SSD within the second MiniPCI Express slot in an X230 thinkpad?
http://www.thinkwiki.org/wiki/Category:X230 notes that it's possible under
the stock BIOS when a HDD is not present, but is it possible under
Would it make the most sense to put locking option in coreboot's
board-specific code, since the method varies between boards? Could a common
ACPI call for it be provided that could be called by a payload or OS later
if it's present?
-Matt
On Sun, Feb 17, 2019 at 8:48 PM Frank Beuth wrote:
>
So, if one does not have a dGPU, one should not set
CONFIG_MULTIPLE_VGA_ADAPTERS and the appropriate tables will be filled in
with the vbios for the iGPU. And the dGPU will not be initialized. (or
attempted, since it doesn't exist)
If one does have a dGPU, then only information for the dGPU will
>
> Early 16h systems (Jaguar) are safe because they don't have a
> PSP
Safe yes, but not helpful in coming to grips with the PSP.
> > On Sun, Feb 17, 2019 at 12:18 AM Matt B
> wrote:
> >
> > As for the patching, afaik AMD has released patches for all of t
This fairly interesting stuff. With the fairly wide range of attacks
(arbitrary code execution and faking signatures for modules) maybe some
sort of runtime "psp-cleaner" might be possible, but it would probably be a
crushingly difficult undertaking.
It's somewhat unclear form the slides, but it
Out of curiosity, is there a config to disable the dGPU to save power if
one is present?
Thanks,
-Matt
On Sat, Feb 16, 2019 at 9:12 AM Kyösti Mälkki
wrote:
>
>
> On Sat, Feb 16, 2019 at 3:49 PM Mike Banon wrote:
>
>> I almost completed refining the HJK's dGPU patches and discrete GPU is
from
around 2008.
-Matt
On Thu, Feb 14, 2019 at 7:56 PM ron minnich wrote:
> On Thu, Feb 14, 2019 at 9:29 AM Matt B wrote:
> >
> > Hi,
> >
> > I was helping a friend with a bios issue (we may have an involuntary
> coreboot convert on our hands ;) ) and realiz
>
> Actually that's what we do in the FILO payload.
What is libflashrom used for in FILO? Was it intended at some point that
FILO be able to reflash the BIOS, or is it being used for something like
reading the flash chip in order to load other things?
-Matt
On Thu, Feb 14, 2019 at 3:45 PM Nico
Hi,
I was helping a friend with a bios issue (we may have an involuntary
coreboot convert on our hands ;) ) and realized that a lot of BIOSs provide
a way for the BIOS to flash itself but Coreboot doesn't.
For Coreboot afaik the only two methods available are to flash with a
programmer or to
I need to pick a better email client, or remember to say "reply all"
-- Forwarded message -----
From: Matt B
Date: Sun, Nov 25, 2018 at 2:59 PM
Subject: Re: [coreboot] Supported Motherboards
To:
I also don't see "drop it and if someone likes it they'll work
Hi,
One thing I just noticed about the page:
https://www.coreboot.org/Board:asus/kgpe-d16
Here "Crossfire XDMA" is listed as needing testing. If nobody has been able
to test this, and you (or someone else) has the opportunity this might be
an interesting thing to test.
After learning that this
I'm definitely interested in helping fund the Origami-EC's development.
I've been kicking around the idea of sending him an email on the subject
for about a month or two.
(not to mention, working open-source EC firmware could potentially benefit
a LOT of other x86 boards)
-Matt
On Sun, Sep 23,
://git.code.paulk.fr/gitweb/?p=origami-ec.git;a=summary
I haven't heard anything more up to date. It appears the author also has
his hands full with some (pretty cool) replicant work.
-Matt
On Sun, Sep 23, 2018 at 1:26 PM Matt B wrote:
> Hi,
> I'm in basically the same situation, having just got a g505
Hi,
I'm in basically the same situation, having just got a g505s. I'm looking
at chronicling my experience on an ifixit article as I go, though I don't
really have any time right now while in class. Right now the winter break
looks most likely for some serious coreboot fun.
Sadly, the ebay seller
Hi,
My deepest apologies if this doesn't show up in the right spot, despite
editing the subject. I'm a dummy and I'm switching off digest mode right
now.
I'm no expert on microcode but I'll share my personal stance which I think
is pretty reasonable and practical. As the saying goes, the best
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