Re: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?

16.05.2011 19:31, Marc Jones пишет: 2. CMOS is not a good place for platform options either. It is good for runtime options, but I don't think that there are many options for users to change. What options users would change and how will they change them? CMOS options could even go into the devic

[coreboot] Support for K10/K10.5 on old AM2-only boards

Hi all. I experimented with K10+ CPUs and boards that doesn't support them, and on some boards it's possible to start new CPUs with BIOS from board on same (or closely relative, like GeForce7025/NForce520 pair) chipset - possible with some bugs, possible without all working fuctions, or even

Re: [coreboot] Support for K10/K10.5 on old AM2-only boards

29.06.2010 09:55, and...@jenbo.dk wrote: NVIDIA based boards are not supported as NVIDIA isn't providing documentation. So in what way was made support of ck804/mcp55? Reversing original BIOS? Irc_tables can be generated using a tool in the utils folder. Devicetree is basically that you get fro

Re: [coreboot] Asus M2A-VM

29.06.2010 15:46, Jason Self пишет: Indeed; I've never soldered/desoldered anything in my life. I thought that Flashrom was used to get Coreboot onto the board. I clearly misunderstand the purpose of Flashrom if physical modification is also needed. If that's specific to the M2A-VM perhaps I shou

Re: [coreboot] Support for K10/K10.5 on old AM2-only boards

29.06.2010 23:17, Anders Jenbo пишет: I think it was some one with in AMD who had access to the NDA documentations for those two chips, it was a lucky coincident and it is not likely to happen again. -Anders You don't need to rewrite low-level routines for K8/K10(K10.5); it's enough to mak

Re: [coreboot] romcc.c

18.07.2010 15:25, ali hagigat пишет: What util/romcc/romcc.c does? It is over 25000 lines of code! You tried to read romcc.1 ? :) -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Fintek f71882

05.08.2010 22:51, Joe Korty пишет: I've been thinking it would be a nice little hardware project to make my own little bios switcher. Regards, Joe This solution is already present. It's named 'top hat', used mostly for reflashing soldered chips and it's easily maked for a hour just from 2

Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?

06.08.2010 12:52, Oskar Enoksson пишет: What happens if I can't boot? Do I have to buy some hardware flash programming dongle? Yes, of course. But it'll be better to buy (or ask in some PC service) spare 4Mbit LPC flash -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/ma

[coreboot] Wyse S10 Geode GX2

mistake somewhere? .config and bootlog attached. Thanks, Andrew bootlog Description: Binary data coreboot_config Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Wyse S10 Geode GX2

_DEBUG_CAR is not set # CONFIG_DEBUG_PIRQ is not set # CONFIG_HAVE_DEBUG_SMBUS is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_REALMODE_DEBUG is not set # CONFIG_TRACE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set CONFIG_POWER_BUTTON_FORCE_DISABLE=y # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set Thanks, Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Wyse S10 Geode GX2

39268 fallback/payload 0x34240payload 52463 config 0x40f80raw 2955 (empty)0x41b40null 778584 Am I missing something obvious, have I got the configuration wrong? Thanks, Andrew > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Wyse S10 Geode GX2

> Hi Andrew, > > I am interested in getting coreboot running on the Wyse S50, and am also > wondering if the VSA for the LX will work on these devices. Have you > actually found source code for the GX2? Or only a compiled VSA? > Hi Jamie, I haven't found any different so

Re: [coreboot] Wyse S10 Geode GX2

s (in this case) Slackware perfectly as below. I haven't got gxfb setup so there is no video at the moment, I'll start to run some tests tomorrow and let you know how I get on. Thanks, Andrew boot_log: coreboot-4.0-5512-g6e56de3 Mon Feb 17 19:03:04 GMT 2014 starting... done cpuRegInit

Re: [coreboot] Wyse S10 Geode GX2

-Jamie > Thanks, but I just followed the instructions others have written! I haven't had much time to look at it again, but I'm planning to make a start at trying to get ACPI working. I've read through the suggestions on the website and I've extracted the DSDT table, now I

[coreboot] Usefull hardware data

Following uid313's instructions from http://ubuntuforums.org/showthread.php?t=961975 /* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * * Contains the IRQ Routing Table dumped directly from your * memory, which BIOS sets up. * * Doc

Re: [coreboot] Alternate for serial port debug messages

and doing so would be a bad idea anyway. Thanks Vikram Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Alternate for serial port debug messages

Vikram Narayanan wrote: On Sat, May 14, 2011 at 8:35 AM, Gregg Levine wrote: On Thu, May 12, 2011 at 6:28 AM, Andrew Goodbody wrote: Vikram Narayanan wrote: ok. I am planning to buy one. Please share your thoughs on which one to buy. NET20DC, it is the simplest, the cheapest by far and

Re: [coreboot] SPI flashing

S pin is connected to the SPI controller to the #CS pin on the external SPI flash chip in order to select that chip instead. Does that sound like a possibility? -- Andrew. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] SPI flashing

Andrew Morgan wrote: On 06/07/11 12:23, Andreas Galauner wrote: Also the pinout is kind of "weird": 1#CS 2#CS 3SI 4NC 5SO 6VCC 7SCK 8GND Why is CS# connected to two pins? The resistance between those two pins is 1 Ohm, so they are connecte

[coreboot] Coreboot on AMD Geode; No VGA

ode vga output. Any help would be great. Regards Andrew Bolster <http://andrewbolster.info/blog/?utm_source=correspondence&utm_medium=email&utm_campaign=Personal%2BEmail><http://www.linkedin.com/in/andrewbolster><http://facebook.com/andrew.bolster><http://twitte

Re: [coreboot] Coreboot on AMD Geode; No VGA

On 12 July 2011 15:31, Benjamin Henrion wrote: > On Tue, Jul 12, 2011 at 3:18 PM, Andrew Bolster > wrote: > > > > I only started looking into coreboot yesterday, so forgive the > incoming naivety. > > Can anyone point me in the direction of how to set up coreboot + se

Re: [coreboot] Coreboot on AMD Geode; No VGA

On 12 July 2011 18:44, Peter Stuge wrote: > Andrew Bolster wrote: > > Can anyone point me in the direction of how to set up coreboot + > > seabios so that it actually uses the VGA? > > Are you sure there actually is VGA? For the Geode SC series it was > neccessary

Re: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock

Sorry but my replies are having problems getting to the list. Greylisting is not supported by the company mail system. On 07/12/11 18:42, Pete Batard wrote: On 2011.07.12 07:15, Andrew Goodbody wrote: Instead of attempting (and failing) to achieve universal support I'll start with the

Re: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock

from the output of superiotool. Additionally if it was done in such a way that the serial transport could be easily replaced by USB debug instead then we could really have something that would be useful for new boards. Andrew -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] Coreboot on AMD Geode; No VGA

Also, Nils, that patch description implies that VGA is working but on switching from X to console, gets messed up. That is not the problem that I'm having. I literally get nothing coming out of the VGA device. Regards Andrew Bolster <http://andrewbolster.info/blog/?utm_source=corres

Re: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock

On 07/13/11 22:25, Pete Batard wrote: On 2011.07.13 12:03, Andrew Goodbody wrote: I'll start with the aside, that if "failing" means instantly supporting more than 90% of Intel based motherboards produced in the last 10 years Yes, universal means everything. If you do not sup

[coreboot] MSI E350IA-E45 Board Developments

and do you want an understudy to help out? I'm not very experienced in this area but I'm stubborn, so would love to actually contribute something useful back to the community for a change! PS, Anyone else can answer too... :P [1] http://comments.gmane.org/gmane.linux.bios/65839 Regards A

[coreboot] Flashing via TPM

a way to force the board to look at the TPM/LPC socket? Regards Andrew Bolster <http://andrewbolster.info/blog/?utm_source=correspondence&utm_medium=email&utm_campaign=Personal%2BEmail><http://www.linkedin.com/in/andrewbolster><http://facebook.com/andrew.bolster><http:/

Re: [coreboot] Flashing via TPM

Tom, Thank you for your response. I'll investigate the SPI angle. Is there any structure for collecting information like this within the coreboot community about specific boards for those of us who are more soft than hardware? Regards Andrew Bolster <http://andrewbolster.info/blog/?ut

Re: [coreboot] Flashing via TPM

MSI E3650? Regards Andrew Bolster <http://andrewbolster.info/blog/?utm_source=correspondence&utm_medium=email&utm_campaign=Personal%2BEmail><http://www.linkedin.com/in/andrewbolster><http://facebook.com/andrew.bolster><http://twitter.com/bolster> No trees were kille

[coreboot] Patch to add F71808A support to superiotool

Regards Andrew Bolster <http://andrewbolster.info/blog/?utm_source=correspondence&utm_medium=email&utm_campaign=Personal%2BEmail><http://www.linkedin.com/in/andrewbolster><http://facebook.com/andrew.bolster><http://twitter.com/bolster> No trees were killed t

[coreboot] Patch to add F71808A support to superiotool (ignore previous)

Regards Andrew Bolster <http://andrewbolster.info/blog/?utm_source=correspondence&utm_medium=email&utm_campaign=Personal%2BEmail><http://www.linkedin.com/in/andrewbolster><http://facebook.com/andrew.bolster><http://twitter.com/bolster> No trees were killed t

[coreboot] ASROCK e350m1 ASSERTION FAIL on CPU capability detection / No serial

800_early_setup ASSERTION FAILED: file 'src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c', line 1388 Also, as florz already mentioned, applying the relevant patch ( http://review.coreboot.org/#change,139), the serial port is dead. Regards Andrew Bolster <http://andrewbolster.info/blo

Re: [coreboot] Fwd: [PATCH v3 1/1] libpayload: add support for finding and parsing Coreboot BIOS tables

On Sun, 21 Aug 2011 17:01:28 -0700 Philip Prindeville wrote: > Attached. oookay. I'll await a formal patch with all the cc's, etc. As for the "upstream" version: if/when this patch is merged, it *is* the upstream version. The coreboot tree will need to drop the old version and migrate to the

Re: [coreboot] New patch to review for coreboot: 73b5bba Prepare the BIOS data areas before device init.

idea how coreboot organises its memory map or how that relates to SeaBIOS etc. but unless you can guarantee that no software that will run on this machine will be upset by your values I would suggest sticking with the classic legacy values instead. Andrew -- coreboot mailing list: coreboot

Re: [coreboot] New patch to review for coreboot: 73b5bba Prepare the BIOS data areas before device init.

the reason to have it up at 0xf6000? Linux will boot happily with it at 0x9c000 or even somewhat lower, as it must to boot with a standard BIOS. Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Interesting device enumeration problem

Marc Jones wrote: It is legitimate to disable the first function and expect the others to work. No, I don't think so. You need function 0 in order to read the multi-function flag. Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Phoenix Technologies and General Software

reselling it? I am guessing the former. ron Phoenix are still selling it. http://www.phoenix.com/en/Embedded/Products/Core+Bios+Products/Embedded+BIOS/default.htm Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Phoenix Technologies and General Software

greg wrote: Now Andrew if we could track down a collection of Tadpole VME bus based boards wearing the M68K family of processors.. (Ignore that remark fellow Coreboot participants, that's a side-remark to Andrew G. Now if I could only find a spare VME chasis to put this here TP43M

Re: [coreboot] USB POST card

ce when in that mode. It's probably very pricey, well out of range of most hobbyists though. I have not seen any public specs on how the POST codes work either. Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] USB POST card

ed in restricted environments. PCI seems to be going away and even when it is present port 80h does not always work by default, it can need configuring. Support for passing POST codes or even progress strings over USB debug devices would be very useful indeed. Andrew -- coreboot mailing list: cor

[coreboot] Asus M2N4-SLI details

Attached is the output of various tools run on an Asus M2N4-SLI board. Looks like mptable didn't work correctly? -- Andrew. /* * This file is part of the coreboot project. * * Copyright (C) 200x TODO * * This program is free software; you can redistribute it and/or modify * it

Re: [coreboot] CBFS issues on 440BX boards

CBFS header at fffeffe0 magic is ERROR: No valid CBFS header found! CBFS: Could not find file fallback/coreboot_ram Jumping to image. Booting from the vendor BIOS into Linux then swapping to the Coreboot ROM and typing 'reboot' made it get further, if that helps. -- Andrew

Re: [coreboot] [PATCH] D945GCLF

ful to somebody. It should be enough to get RAM init working. Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Seabios: PCI interrupt routing question

rrupt line in use behind a plug-in bridge. Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [RFC] CMOS options

roll over. I know we are past Y2K so this is unlikely to produce a bug in practice but there is the possibility for an unexpected change in the contents if that position is used for any other purpose. It is a 'well known' position and can be read/written by an OS. Andrew -- coreboot ma

Re: [coreboot] [RFC] CMOS options

hecksums with no user confirmation. On Phoenix a CMOS checksum error is only a warning, you may not even notice it had happened. By the time you see a prompt about entering Setup or continue, defaults were loaded long ago. The BIOS owns the machine, it has no interest in preserving corrupt C

Re: [coreboot] [RFC] CMOS options

have used have a maximum space of 256 bytes that includes the RTC. Where does the extra come from? Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] ASRock E350M1 video option ROM?

get you 64KB of unintialised data. There is nothing in those instructions to access the video BIOS AFAICT. Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Patch merged into coreboot/master: c35c461 Invalidate cache before first jump

. The write back may also need functional memory which will not be there at least from power on. Also note that these instructions are 486+ only. Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Binary blobs in the source tree (was: Re: New patch to review for coreboot: e4fc528 Add the memory reference code binary for sandybridge chipsets)

by the CPU in a different operating mode but it most certainly does go away and come back and the CPU state has changed by doing so. So it is a slippery slope and we have already started on it and I see no practical way back now. Andrew PS I am really excited to see SandyBridge support coming

Re: [coreboot] how to assign irq to a device

list. Is the motherboard using coreboot? If so then please tell us the exact motherboard and where the coreboot code came from. Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] how to assign irq to a device

On 14/10/12 05:12, WANG Siyuan wrote: hi, Andrew thank you. this issue has been solved by updating the acpi routing The ACPI routing tables are a description of the underlying hardware configuration. If you have not also changed the hardware configuration then you may well have an invalid

Re: [coreboot] BIOS Savior (RD1-PMC4/8X) unavailable? Build my own?

, for each of the two devices, strapping one to a '0' and the other to '1', flip the switch and invert both values. You can use a DPDT switch for this. Connect all other lines 1:1. Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco

through the pain of alternate key enrolment rather than an absolute requirement. Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco

On 02/01/13 17:08, ron minnich wrote: On Mon, Dec 31, 2012 at 11:23 AM, David Hubbard wrote: Andrew has good points. Technically there's nothing about Secure Boot that can be proven to exclude alternative OS's such as Linux. While that is technically true, I am starting to see

Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco

On 02/01/13 19:28, David Hubbard wrote: Andrew, Ron, what's your take on http://mjg59.dreamwidth.org/20916.html ? Specifically: "This is part of Windows 8's fast boot support - the keyboard may not be initialised until after the OS has started." OK, the feature is deferr

Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco

just x86. Don't believe me? Read about ARM systems and Windows 8. I have yet to see Linux or Android on an iPad. WinRT (not Win8) on ARM is little different, if at all. It will have no effect whatsoever on other tablets. They do not control all ARM tablets and never will. Andrew -- c

Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco

does not mean perfect. Fixed just means takes longer to overcome than anyone cares to invest in it. Sorry but "this will be broken because everything before it has been broken" is not a credible critique; that is the inductive fallacy. Andrew -- coreboot mailing list: coreboot@cor

Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco

scale linearly per user to me. Security is not free. There will always be a cost. Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco

On 05/01/13 00:10, ron minnich wrote: Andrew, so far, I don't find your arguments very convincing. Can you explain to me why Intel would want to control what OS is run on their chipsets? Intel are an active contributor to the Linux kernel for their display drivers. Andrew -- cor

Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco

On 05/01/13 02:11, David Hubbard wrote: Hi Andrew, On Fri, Jan 4, 2013 at 5:09 PM, Andrew Goodbody mailto:ajg4tadp...@gmail.com>> wrote: Enrol your own key. Sign your own kernel. Seems to scale linearly per user to me. Security is not free. There will always be a cost.

Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco

On 05/01/13 08:26, Patrick Georgi wrote: Am 2013-01-05 01:03, schrieb Andrew Goodbody: coreboot can never be "the Solution to the Secure Boot Fiasco" until it can offer better security than Secure Boot. We do. Same level of verifiable boot (by doing signature checks on loaded code) w

Re: [coreboot] Tyan S2895 SATA, USB, ethernet not working

On 02/03/13 22:27, Andrew Basterfield wrote: On 02/03/13 17:54, Andrew Basterfield wrote: Hi I have put coreboot+seabios on an old Tyan S2895 I have just retired when the 2nd CPU socket stopped working probably because some of the caps are bulging... it is stable anyways on 1 CPU with Tyan

Re: [coreboot] Tyan S2895 SATA, USB, ethernet not working

On 03/03/13 14:18, Andrew Goodbody wrote: On 03/03/13 14:04, Andrew Basterfield wrote: Due to the lack of CPU in socket #2 the board becomes a little crippled; 2nd PCIe slot and 2nd ethernet no are longer available; maybe coreboot would work OK with both sockets populated but the single socket

Re: [coreboot] Tyan S2895 SATA, USB, ethernet not working

On 03/03/13 14:04, Andrew Basterfield wrote: Due to the lack of CPU in socket #2 the board becomes a little crippled; 2nd PCIe slot and 2nd ethernet no are longer available; maybe coreboot would work OK with both sockets populated but the single socket configuration has not been encountered

Re: [coreboot] Tyan S2895 SATA, USB, ethernet not working

On 03/03/13 14:28, Andrew Basterfield wrote: Hi Andrew The lack of 2nd PCIe and ethernet is expected behavior when the 2nd socket is empty - please see the following ftp://ftp.tyan.com/manuals/m_s2895_101.pdf Please see 2nd 'NOTE' section 2.4 page 18 Looking at the system ar

Re: [coreboot] Tyan S2895 SATA, USB, ethernet not working

On 03/03/13 16:48, Andrew Goodbody wrote: On 03/03/13 14:28, Andrew Basterfield wrote: Hi Andrew The lack of 2nd PCIe and ethernet is expected behavior when the 2nd socket is empty - please see the following ftp://ftp.tyan.com/manuals/m_s2895_101.pdf Please see 2nd 'NOTE' section 2

Re: [coreboot] Tyan S2895 SATA, USB, ethernet not working

On 04/03/13 20:46, Andrew Basterfield wrote: On 03/03/13 16:48, Andrew Goodbody wrote: You say it is stable with one CPU using the Tyan BIOS so it is at least possible to use the board as is. There is certainly code in the S2895 devtree and mptable to allow for the missing devices caused by a

Re: [coreboot] Tyan S2895 SATA, USB, ethernet not working

On 04/03/13 23:21, Andrew Goodbody wrote: On 04/03/13 20:46, Andrew Basterfield wrote: On 03/03/13 16:48, Andrew Goodbody wrote: You say it is stable with one CPU using the Tyan BIOS so it is at least possible to use the board as is. There is certainly code in the S2895 devtree and mptable to

Re: [coreboot] the seabios reboot in the post process

s way since the IBM PC AT. If you write to 0x70 with bit 7 reset then you risk releasing any pending NMI. If the interrupt vectors are not initialised then you always need to set bit 7 when writing to 0x70. Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] unexpected exception errors loading vga rom

int lines. As such it is not a good place to try and draw inferences from as it has a lot of capabilities not included in a normal PCI device. Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] status of coreboot on Asus A8N-E

not available of course). Uwe. I doubt it's an IRQ issue. The IRQ was used in CGA/EGA adapters to signal frame sync in order to allow updating of the screen without causing flicker. This has not been an issue since the introduction of the original VGA adapter, IIRC. Andrew -- cor

[coreboot] HP NetServer E 800

getting the chipset information, etc. I'll try. I also have 4 older 'scrap' machines which I can have a play with. Two of them have very similar, socketed, ROM chips so that looks good. -- Andrew. -+-[:05]-+-02.0 D-Link System Inc DGE-528T Gigabit Ethernet Adapter [1186:4300

[coreboot] Flashrom on Soyo SY-7VCA

Hi, I have a Soyo SY-7VCA motherboard. Flashrom does not automatically detect the ROM chip but if I specify the type manually then it will read the data. I am told that I need a board enable for this board. I have attached the output of 'lspci -vn'. -- Andrew. 00:00.0 0600: 1106

Re: [coreboot] [PATCH] flashrom: board enable for soyo sy-7vca.

Acked-by: Andrew Morgan Here's the output from running flashrom after the patch: flashrom v0.9.0-r599 No coreboot table found. Found chipset "VIA VT82C686A/B", enabling flash write... OK. Found board "Soyo SY-7VCA", enabling flash write... OK. Calibrating delay lo

[coreboot] Soyo SY-6BA+ III

I have attached the output of 'lspci -vn' on my Soyo SY-6BA+ III board. (Not to be confused with the other Soyo board yesterday!) -- Andrew. 00:00.0 0600: 8086:7190 (rev 03) Flags: bus master, medium devsel, latency 32 Memory at d800 (32-bit, prefetchable)

Re: [coreboot] [Patch] Flashrom: board enable for Soyo SY-6BA+III.

Acked-by: Andrew Morgan Some output below, it wrote the ROM just fine. :) flashrom v0.9.0-r601 No coreboot table found. Found chipset "Intel PIIX4/4E/4M", enabling flash write... OK. Calibrating delay loop... OK. Found chip "SST SST39SF020A" (256 KB) at physical addre

Re: [coreboot] [PATCH] flashrom: AMD Am29F010A/B and SiI 3112 support

Acked-By: Andrew Morgan I have this flash chip on a SiI 3112 board. I have tested read, write, verify and erase all work. -- Andrew. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Soyo SY-6BA+ III

Hi, Here is the output of 'lspci -tvnn', 'superiotool -dV', 'getpir', and 'mptable' run on the (beautifully named) Soyo SY-6BA+ III motherboard. -- Andrew. /* * This file is part of the coreboot project. * * Copyright (C) 200x TODO *

Re: [coreboot] [PATCH] Add support for the Soyo SY-6BA+ III board

Uwe Hermann wrote: Hi, On Sat, Jun 20, 2009 at 02:34:24AM +0100, Andrew Morgan wrote: Here is the output of 'lspci -tvnn', 'superiotool -dV', 'getpir', and 'mptable' run on the (beautifully named) Soyo SY-6BA+ III motherboard. Thanks, please s

Re: [coreboot] [PATCH] Add support for the Soyo SY-6BA+ III board

Uwe Hermann wrote: Hi, On Sat, Jun 20, 2009 at 02:34:24AM +0100, Andrew Morgan wrote: Here is the output of 'lspci -tvnn', 'superiotool -dV', 'getpir', and 'mptable' run on the (beautifully named) Soyo SY-6BA+ III motherboard. Thanks, please s

[coreboot] [PATCH] flashrom: Add support for Hyundai HY29F002T

Add support to flashrom for Hyundai HY29F002T on the assumption it is the same as other *29F002T chips. Running 'flashrom -r' finds the chip and reads what looks like a BIOS image, other than that it is un-tested. Signed-off-by: Andrew Morgan --- Once I de-solder these chips an

Re: [coreboot] [PATCH] flashrom: Add support for Hyundai HY29F002T

Peter Stuge wrote: Andrew Morgan wrote: Gigabyte GA-7ZXR has two of them for its DualBIOS™. Switching between chips seems to be done in software... Very useful. Gigabyte owns a patent involving a timer and a software handshake. Interesting... That software has to be stored

Re: [coreboot] Extension to inteltool and a request

: fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pse36 mmx fxsr sse up bogomips: 668.18 clflush size: 32 cache_alignment: 32 address sizes: 36 bits physical, 32 bits virtual power management: -- Andrew. Intel CPU: Processor Type: 0, Family 6, Model 7, Stepping

[coreboot] Intel's BIOS Implementation Test Suite

I'm a lurker here (keep up the great work everyone! <3), but I saw this and thought it looked relevant to coreboot development that a link should be posted. http://biosbits.org/ Quoting from the website: The Intel BIOS Implementation Test Suite (BITS) provides a bootable pre-OS environment for

Re: [coreboot] [PATCH] ASUS P2B-LS support, RAM detection for 440BX, add Slot 1 CPU, Microcode for Intel Tualatin CPUs

640MB. If this is a limitation of the chipset that's fine, but maybe it could print a warning message if that is the case? A single 16MB module did not boot. Log: -- coreboot-4.0-r5184M-Andrew Thu Mar 4 21:19:28 GMT 2010 starting... SMBus controller enabled Northbridge prior to SDRAM init

Re: [coreboot] [PATCH] sb600: don't load verb for codec

ridge code. They cannot be inferred by the driver so they absolutely should be done by coreboot. So they should be moved to motherboard specific code not dropped entirely. Andrew -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Supermicro H8QME-2+ mct_d fatal exit.

Sorry, neglected to send original reply to list. Knut Kujat wrote: Andrew Goodbody escribió: Knut Kujat wrote: Any suggestions ? The vendor BIOS is doing some initialisation that coreboot is not. This init survives a short shutdown but is lost after a longer period without power. Yes

Re: [coreboot] [PATCH] ASUS P2B-LS support, RAM detection for 440BX, add Slot 1 CPU, Microcode for Intel Tualatin CPUs

Joseph Smith wrote: That's easy... so you do something like this: As I understand it that only works if there is a DIMM in the 4th slot. Otherwise you'll set a four slot system with the 3 slot configuration leading to incorrect routing of clocks. Andrew -- coreboot mailing list

Re: [coreboot] [PATCH] ASUS P2B-LS support, RAM detection for 440BX, add Slot 1 CPU, Microcode for Intel Tualatin CPUs

Joseph Smith wrote: Also, one could always use serialice on a 4 slot system with factory bios to see how they deterime it The factory BIOS does not have to determine it. It knows the configuration of the board it is running on. It can use a build time setting. Andrew -- coreboot

Re: [coreboot] [PATCH] ASUS P2B-LS support, RAM detection for 440BX, add Slot 1 CPU, Microcode for Intel Tualatin CPUs

t or remembering how to do ISA. -- Andrew. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Wyse S10 Information

ogos? Yes, lots of questions and no answers. I suppose it depends which laws of which countries you care about. :) If I wasn't sure I would probably post a URL to the list, linking to whatever it was I wanted to share. -- Andrew. -- coreboot mailing list: coreboot@coreboot.org http:/

Re: [coreboot] [PATCH] SeaBIOS CD/DVD abbreviations

Just a small point, the "ROM" bit isn't really needed. The fact that CDs are read-only is pretty much irrelevant. No other type of disk gets -ROM or -RAM stuck on the end of it. Also some CDs aren't read only... -- Andrew. -- coreboot mailing list: corebo

Re: [coreboot] problems with M2V-MX SE + VGA

isabled because the VGA BIOS isn't run. I don't know exactly what this might prove but it is something to try anyway. -- Andrew. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Del firmware malware

se them on your own server! Something like this obviously has to have pretty good access to the main computer. Even if the Dell computer 'code on flash on the motherboard which we're not going to call firmware' isn't anything like iLO, this is another place for firmware based

[coreboot] Trouble linking coreinfo payload

+0x370): undefined reference to `__udivdi3' collect2: ld returned 1 exit status make: *** [/home/andrew/offtime/coreboot/coreboot/payloads/coreinfo/build/coreinfo.elf] Error 1 I'm running Gentoo Linux on an x86_64 machine with no 32-bit libraries, and no kernel support for 32-bit

[coreboot] Trouble compiling tint payload

I'm having trouble compiling the tint payload. When following the instructions on the wiki at http://www.coreboot.org/Tint, I get an error about lpgcc. I've figured out I need to make the following change to the Makefile: --- Makefile.old2010-08-23 10:11:33.979039352 -0400 +++ Makefil

Re: [coreboot] Trouble linking coreinfo payload

On 08/23/2010 03:35 AM, Stefan Reinauer wrote: It's missing libgcc. You will at least need a 32bit libgcc in your system. I suggest you use the compiler build by the script in util/crossgcc/ however Worked like a charm, thanks. I'll be writing some more mails about other payloads I'm having tr

Re: [coreboot] Trouble compiling tint payload

I figured out the problem right after sending this: when I set $CC, it overwrites the makefile variable that tells it to use lpgcc, so lpgcc isn't getting used. I changed all occurrences of "CC" in the tint makefile to "MYCC", and it compiled correctly. Is there a less hackish way I should s

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