From: Steve Chen sc...@mvista.com
Simplify code to calculate MMC/SD memory clock divide.
In the original code, much of the logic were dedicated to rounding
up the memory clock divide (mmc_push_pull). The code can be simplified
by rounding up in the algorithm itself.
Original code has
Hi Andre,
SPRS488e.pdf defines the performance measurement procedure. Please follow it
for reproducing the numbers.
According to it, the first I and P frame process call's numbers needs to be
excluded while averaging. Also, the measurement should not be done for the
first instance that is run
Display driver for TI DM646x EVM
Signed-off-by: Manjunath Hadli m...@ti.com
Signed-off-by: Brijesh Jadav brijes...@ti.com
Signed-off-by: Chaithrika U S chaithr...@ti.com
These patches add the display driver support for TI DM646x EVM.
This patch set has been tested for basic display functionality
Video Port Interface driver
Add VPIF driver for DM646x. This code be used by the display and
capture drivers.
This version has some incorporated the review comments.
Signed-off-by: Manjunath Hadli m...@ti.com
Signed-off-by: Brijesh Jadav brijes...@ti.com
Signed-off-by: Chaithrika U S
Platform specific display device setup for DM646x EVM
Add platform device and resource structures. Also define a platform specific
clock setup function that can be accessed by the driver to configure the clock
and CPLD.
This patch is dependent on a patch submitted earlier, which adds
Pin Mux and
Display driver for VPIF
Adds the VPIF display driver and the associated header file.
The patch includes the review comments like adding macors for the debug
statements. The subdevice registering now uses v4l2_i2c_new_probed_subdev().
Some other updates are simplification of the ISR and merging of
Makefile and Kconfig changes
Modifies and adds the video Makefiles and Kconfig files to support DM646x Video
display device
Signed-off-by: Manjunath Hadli m...@ti.com
Signed-off-by: Brijesh Jadav brijes...@ti.com
Signed-off-by: Chaithrika U S chaithr...@ti.com
---
Applies v4l-dvb repository
Andrea,
We are looking into this now. Thanks for the heads up.
Sincerely,
Chase Maupin
Software Applications
Catalog DSP Products
e-mail: chase.mau...@ti.com
phone: (281) 274-3285
-Original Message-
From: davinci-linux-open-source-boun...@linux.davincidsp.com
Hi all,
We are using DM6446 based board in the project. We have an issue with the write
speed through the ATA. On the other end of the bus is an ATA-SATA converter
connected to a SATA-DVD writer. The required write speed we need is close 10 M
bits/sec, whereas we are getting only 2.8 M
Hi all,
I am using a DM6446 based board. In my application, I have allocated buffers
for the Video Capture and Video Resizer devices through the ioctls. I have
mmap'd those buffers too. When I take a frame from the Capture to Resizer, I am
left only with a memcpy option.
As it has its
Gopal,
ATA on DaVinci can very well do 25MBps provided the device can sustain it. Pl.
refer to the LSP data sheets for further information.
There seems something definitely wrong w.r.t 2.8Mbps figure that you are
quoting. Have you checked that the device supports DMA ?
regards
swami
Hi all,
We are experiencing a strange behavior in our system.
We have a DVR and streaming board that uses for that purposes a dm355 board
with the latest updates from Texas.
The problem we have is that from times to times we cannot reach the board
for telnet, the board does not respond to ping.
Hi guys,
I'm using the Montavista kernel for 2.6.18_pro500, but this is more of
a generic SPI question.
I'm trying to write a peripheral driver which uses the SPI.
I have set up the SPI bus on SPI1, and I can initiate transfers over
the wires (Logic analyser shows me line states)
However, the
On Fri, 2009-05-08 at 17:41 +0100, Kieran Bingham wrote:
Hi guys,
I'm using the Montavista kernel for 2.6.18_pro500, but this is more of
a generic SPI question.
I'm trying to write a peripheral driver which uses the SPI.
I have set up the SPI bus on SPI1, and I can initiate transfers over
On Friday 08 May 2009, Kieran Bingham wrote:
The following 8bits will clock the value of the register back to the master
i.e.: to read the value 0x02 from register 0x03 the following
transaction would occur
MOSI:
0x03##
MISO
0x##02
where ## are don't cares
I can't seem to get this
Hi all,
I am trying to write a driver for SD ver. 2.0 in which the structure of CSD
(Card Specific Data) is different from SD Ver. 1.0. Can anybody please tell me
what is the new structure of CSD for SD 2.0 Version because some of the fields
in Ver. 2.0 are dropped, some are extended and
Why don't you setup the capture/resizer hardware in continuous mode so
that the resizer and capture blocks are linked together? This way, the
resizer hardware gets the frame directly from the capture block (as
opposed to doing each as a separate operation and tying them together
through DDR
On Friday 08 May 2009, Davinci Developer wrote:
I am trying to write a driver for SD ver. 2.0
Doesn't the current Linux driver already handle that?
___
Davinci-linux-open-source mailing list
Davinci-linux-open-source@linux.davincidsp.com
Tom Wheeler twhee...@control4.com writes:
Kevin,
Here is an interesting bit of info.
I masked the bank0 interrupt in EINT1 and the dm9000 is still running.
This should eliminate the bank0 interrupt from being generated to the
core.
That partially solves the problem, but if any other
Can anyone please tell me how can we program the Nand Flashes during production
cycle. The nand flash has to be programmed before it is mounted on board and it
must be programmed with all - ubl, uboot, kernel, filesystem using some kind of
binary file that combines all of them.
-Vijay
After a bit more debugging on the GPIO interrupt issues, I think there
is a fundamental hardware limitation in having flexibility of using
GPIO bank interrupts and direct interrupts at the same time.
In order to configure a GPIO as an interrupt (either banked or
direct), you have to set the
Kevin,
I had tried Tom's patch to use the direct interrupts and it worked fine (no
netdev transmit errors) until recently. But it stopped working with the latest
on linux-davinci git (has GPIO driver changes from Dave). Basically the link
itself is not getting detected.
Thanks
Sneha
On Friday 08 May 2009, Kevin Hilman wrote:
After a bit more debugging on the GPIO interrupt issues, I think there
is a fundamental hardware limitation in having flexibility of using
GPIO bank interrupts and direct interrupts at the same time.
And to clarify: a bank is 16 interrupts, and the
On Friday 08 May 2009, Narnakaje, Snehaprabha wrote:
I had tried Tom's patch to use the direct interrupts and it
worked fine (no netdev transmit errors) until recently.
But it stopped working with the latest on linux-davinci git
(has GPIO driver changes from Dave). Basically the link
itself
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