From: Thor Thayer ttha...@opensource.altera.com
The Arria10 SDRAM and ECC system differs significantly from the
Cyclone5 and Arria5 SoCs. This patch adds support for the Arria10
SoC.
1) IRQ handler needs to support SHARED IRQ
2) Support sberr and dberr address reporting.
Signed-off-by: Thor
From: Thor Thayer ttha...@opensource.altera.com
The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits
for the CycloneV/ArriaV SoCs in preparation for the Arria10 support.
Signed-off-by: Thor Thayer
From: Thor Thayer ttha...@opensource.altera.com
This series of patches adds support for the Arria10 EDAC. The
SDRAM controller and ECC registers are significantly different
from the CycloneV/ArriaV but common areas could be abstracted.
Thor Thayer (4):
edac, altera: Generalize driver to use DT
From: Thor Thayer ttha...@opensource.altera.com
The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. The memory size is calculated in
the bootloader and passed via the device tree. Using this device
tree size is more generic than using the
From: Thor Thayer ttha...@opensource.altera.com
Altera's Arria10 SoC interconnect requires a 32 bit write for APB
peripherals. The current spi-dw driver uses 16bit accesses in
some locations. Use function pointers to support 32 bit accesses
but retain legacy 16 bit access.
Signed-off-by: Thor
From: Thor Thayer ttha...@opensource.altera.com
Instead of clearing the RxU, RxO, and TxO IRQs individually with
3 register reads, a single read of the ICR register will do the
same thing.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
Signed-off-by: Andy Shevchenko
From: Thor Thayer ttha...@opensource.altera.com
Altera's Arria10 architecture requires a 32bit write accesses for
APB peripherals. The current spi-dw driver uses 16bit accesses in
some locations. This patch updated the bindings with an optional
field in the devicetree to select 32bit accesses.
From: Thor Thayer ttha...@opensource.altera.com
The Altera Arria10 SoC interconnect requires 32 bit write accesses to
APB peripherals. The DesignWare SPI peripheral registers are on 32bit
boundaries so this patch is minimal. Function pointers are used to select
32bit access or 16bit accesses
From: Thor Thayer ttha...@opensource.altera.com
The Altera Arria10 SoC requires 32 bit accesses to peripherals. The
DesignWare SPI peripheral registers are on 32bit boundaries so this
patch is minimal. Function pointers are used to select 32bit access
or 16bit accesses.
Thor Thayer (2):
From: Thor Thayer ttha...@opensource.altera.com
Altera's Arria10 SoC requires a 32 bit access for peripherals.
The current spi-dw driver uses 16bit accesses in some locations.
Use function pointers to support 32 bit accesses and not break
legacy 16 bit access.
Signed-off-by: Thor Thayer
From: Thor Thayer ttha...@opensource.altera.com
Altera's Arria10 architecture requires a 32bit accesses for
peripherals. The current spi-dw driver uses 16bit accesses in
some locations. This patch updated the bindings with an optional
field the devicetree can use to select 32bit accesses.
From: Thor Thayer ttha...@opensource.altera.com
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model.
Each type of ECC is individually configurable.
The SDRAM ECC is a separate Kconfig option
From: Thor Thayer ttha...@opensource.altera.com
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM properly.
http://www.spinics.net/lists/devicetree/msg51117.html
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for L2 cache on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Split OCRAM
From: Thor Thayer ttha...@opensource.altera.com
This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process in the platform specific code.
v2 changes:
- Split On-Chip RAM ECC platform initialization into
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for On-Chip RAM on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Split OCRAM ECC
From: Thor Thayer ttha...@opensource.altera.com
The SDRAM EDAC requires SDRAM configuration/initialization before
SDRAM is accessed (in the preloader). Having a module compile is
not desired so force to be built into kernel.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v3: Added
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for L2 cache on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Split OCRAM
From: Thor Thayer ttha...@opensource.altera.com
This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process in the platform specific code.
v2 changes:
- Split On-Chip RAM ECC platform initialization into
From: Thor Thayer ttha...@opensource.altera.com
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM properly.
http://www.spinics.net/lists/devicetree/msg51117.html
From: Thor Thayer ttha...@opensource.altera.com
The SDRAM EDAC requires SDRAM configuration/initialization before
SDRAM is accessed (in the preloader). Having a module compile is
not desired so force to be built into kernel.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v3: Added
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for On-Chip RAM on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Split OCRAM ECC
From: Thor Thayer ttha...@opensource.altera.com
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model.
The SDRAM ECC is a separate Kconfig option because:
1) the SDRAM preparation can take almost 2
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for On-Chip RAM on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Split OCRAM ECC
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for L2 cache on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Split OCRAM
From: Thor Thayer ttha...@opensource.altera.com
The SDRAM EDAC requires SDRAM configuration/initialization before
SDRAM is accessed (in the preloader). Having a module compile is
not desired so force to be built into kernel.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v3: Added
From: Thor Thayer ttha...@opensource.altera.com
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM properly.
http://www.spinics.net/lists/devicetree/msg51117.html
From: Thor Thayer ttha...@opensource.altera.com
This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process in the platform specific code.
v2 changes:
- Split On-Chip RAM ECC platform initialization into
From: Thor Thayer ttha...@opensource.altera.com
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model.
The SDRAM ECC is a separate Kconfig option because:
1) the SDRAM preparation can take almost 2
From: Thor Thayer ttha...@opensource.altera.com
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model. All
Altera EDAC functions live in altera_edac.c.
Signed-off-by: Thor Thayer
From: Thor Thayer ttha...@opensource.altera.com
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM properly.
http://www.spinics.net/lists/devicetree/msg51117.html
From: Thor Thayer ttha...@opensource.altera.com
This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process in the platform specific code.
v2 changes:
- Split On-Chip RAM ECC platform initialization into
From: Thor Thayer ttha...@opensource.altera.com
The SDRAM EDAC requires SDRAM configuration/initialization before
SDRAM is accessed (in the preloader). Having a module compile is
not desired so force to be built into kernel.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v3: Added
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for On-Chip RAM on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Split OCRAM ECC
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for L2 cache on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Split OCRAM
From: Thor Thayer ttha...@opensource.altera.com
Add 2 SPI nodes to SOCFPGA device tree.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Remove extra files. Move SPIDEV into board specific file.
v3: Remove dts file since SPIDEV is not allowed.
v4: Remove bus-num since it is
From: Thor Thayer ttha...@opensource.altera.com
This patch adds the SPI nodes to the SOCFPGA device tree. Both
nodes are left in the disabled state since no devices are
present on the development boards.
Thor Thayer (1):
arm: dts: socfpga: Add SPI nodes to SOCFPGA DT.
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for L2 cache on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Split OCRAM
From: Thor Thayer ttha...@opensource.altera.com
This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process in the platform specific code.
Thor Thayer (4):
arm: socfpga: Enable L2 Cache ECC on startup.
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for On-Chip RAM on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Split OCRAM ECC
From: Thor Thayer ttha...@opensource.altera.com
Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using
the EDAC_DEVICE framework. The EDAC manager abstracts the common probe
functionality and test triggers. The L2 Cache and OCRAM files handle
the specific memory functions (alloc
From: Thor Thayer ttha...@opensource.altera.com
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM properly.
http://www.spinics.net/lists/devicetree/msg51117.html
From: Thor Thayer ttha...@opensource.altera.com
Add 2 SPI nodes to SOCFPGA device tree.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Remove extra files. Move SPIDEV into board specific file.
v3: Remove dts file since SPIDEV is not allowed.
---
arch/arm/boot/dts/socfpga.dtsi
From: Thor Thayer ttha...@opensource.altera.com
This patch adds the SPI nodes to the SOCFPGA device tree. Both
nodes are left in the disabled state since no devices are
present on the development boards.
Thor Thayer (1):
arm: dts: socfpga: Add SPI nodes to SOCFPGA DT.
From: Thor Thayer ttha...@opensource.altera.com
Add 2 SPI nodes to SOCFPGA device tree.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Remove extra files. Move SPIDEV into board specific file.
---
arch/arm/boot/dts/socfpga.dtsi | 24
From: Thor Thayer ttha...@opensource.altera.com
This patch series is used to enable the spidev as a child of the
SPI device tree node. This patch was tested on the Altera
SOCFPGA platform.
Thor Thayer (2):
spi: dw: Initialize of_node to discover device tree node children
arm: dts: socfpga:
From: Thor Thayer ttha...@opensource.altera.com
Add 2 SPI nodes to SOCFPGA device tree. Update copyright.
Update spi-dw.txt with bus-num as an optional property.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
Documentation/devicetree/bindings/spi/spi-dw.txt |1 +
From: Thor Thayer ttha...@opensource.altera.com
1. The of_node element must be initialized to enable discovery of node
children. The discovery takes place in the of_register_spi_devices() function.
2. Grabbing the bus-num from the device tree.
3. Update the SOCFPGA configuration.
Signed-off-by:
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for L2 cache and OCRAM on machine
startup. In both cases, the ECC has to be enabled before data
is stored in memory otherwise the ECC will fail on reads.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
From: Thor Thayer ttha...@opensource.altera.com
Adding the device tree entries needed to support the Altera L2
cache and OCRAM EDAC.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
arch/arm/boot/dts/socfpga.dtsi | 20 +++-
1 file changed, 19 insertions(+), 1
From: Thor Thayer ttha...@opensource.altera.com
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC_DEVICE framework. The EDAC
manager abstracts the common probe functionality and
test triggers. The L2 Cache and OCRAM files handle
the specific memory functions.
From: Thor Thayer ttha...@opensource.altera.com
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove
From: Thor Thayer ttha...@opensource.altera.com
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Use the SDRAM controller registers to calculate memory size
From: Thor Thayer ttha...@opensource.altera.com
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Use the SDRAM controller registers to calculate memory size
From: Thor Thayer ttha...@opensource.altera.com
The Altera SDRAM controller and EDAC support are added in this
patch series. The SDRAM controller is an MFD so that multiple
drivers can access it's registers.
Thor Thayer (3):
mfd: altera: Add Altera SDRAM Controller
edac: altera: Add Altera
From: Thor Thayer ttha...@altera.com
Thor Thayer (3):
devicetree: Addition of the Altera SDRAM Controller. Add the
Altera SDRAM controller bindings and device tree changes to the
Altera SoC project.
devicetree: Addition of the Altera SDRAM EDAC. Add the Altera
SDRAM
From: Thor Thayer ttha...@altera.com
Altera SDRAM EDAC bindings and device tree changes to the Altera SoC project.
Signed-off-by: Thor Thayer ttha...@altera.com
---
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
v4,v5: No changes - bump version for consistency.
From: Thor Thayer ttha...@altera.com
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.
Signed-off-by: Thor Thayer ttha...@altera.com
---
v2: Use the SDRAM controller registers to calculate memory size
instead of the
From: Thor Thayer ttha...@altera.com
Add the Altera SDRAM controller bindings and device tree changes to the Altera
SoC project.
Signed-off-by: Thor Thayer ttha...@altera.com
---
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from
From: Thor Thayer ttha...@altera.com
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
Signed-off-by: Thor Thayer ttha...@altera.com
---
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
v4,v5: No changes - bump version for
From: Thor Thayer ttha...@altera.com
Add the Altera SDRAM controller bindings and device tree changes to the Altera
SoC project.
Signed-off-by: Thor Thayer ttha...@altera.com
---
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from
[PATCHv6 1/3] dt: bindings: Addition of the Altera SDRAM controller
[PATCHv6 2/3] dt: bindings: Addition of the Altera SDRAM EDAC
[PATCHv6 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM
--
To unsubscribe from this list: send the line unsubscribe devicetree in
the body of a message to
From: Thor Thayer ttha...@altera.com
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from SDRAM controller bindings.
v5: No Change, bump version for consistency.
v6: Only map the ctrlcfg register as syscon.
Signed-off-by: Thor Thayer
From: Thor Thayer ttha...@altera.com
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
v4,v5: No changes - bump version for consistency.
v6: Assign ECC registers in SDRAM controller to EDAC
Signed-off-by: Thor Thayer ttha...@altera.com
---
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM controller to the EDAC driver.
Thor Thayer (3):
Addition of the Altera SDRAM controller bindings and device tree
changes to the Altera SoC project.
Addition of the Altera SDRAM EDAC bindings and device tree
From: Thor Thayer ttha...@altera.com
Addition of the driver to support the Altera SDRAM Controller.
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.
v2: Use the SDRAM controller registers to calculate memory size
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM EDAC bindings and device tree changes
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
v4,v5: No changes - bump version for consistency.
v6: Assign ECC registers in SDRAM controller to EDAC
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM Controller bindings and device tree changes.
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from SDRAM controller bindings.
v5: No Change, bump version for consistency.
[PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM
[PATCHv5 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC
[PATCHv5 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM
--
To unsubscribe from this list: send the line unsubscribe devicetree in
the body of a message to
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
v4,v5: No changes - bump version for consistency.
Signed-off-by: Thor Thayer
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from SDRAM controller bindings.
v5: No Change,
From: Thor Thayer ttha...@altera.com
This patch adds EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controllers.
- The SDRAM Controller registers are shared with the FPGA bridge so
these are accessed through the syscon interface.
- The configuration of the SDRAM memory
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.
v2: Changes to SoC SDRAM EDAC code.
v3: Implement code suggestions for SDRAM EDAC code.
v4: Remove syscon from SDRAM controller bindings.
Signed-off-by:
[PATCHv4 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM
[PATCHv4 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC
[PATCHv4 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM Controller
--
To unsubscribe from this list: send the line unsubscribe devicetree in
the body of a
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
v4: No changes - bump version for consistency.
Signed-off-by: Thor Thayer
This patch adds EDAC support for the Altera CycloneV and ArriaV
SoC SDRAM Controller.
[PATCHv3 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM
[PATCHv3 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC
[PATCHv3 3/3] edac: altera: Add EDAC support for Altera SDRAM
--
To unsubscribe
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.
---
v2: Changes to SoC EDAC source code.
v3: Fix typo in device tree documentation.
Signed-off-by: Thor Thayer ttha...@altera.com
---
From: Thor Thayer ttha...@altera.com
---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To Cc list. Add maintainer
information.
v3: EDAC driver cleanup based on comments from Mailing list.
Signed-off-by: Thor Thayer ttha...@altera.com
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project. The syscon parameter
is included here because the SDRAM EDAC bits are shared with the SDRAM
configuration bits.
---
v2: Changes to SoC SDRAM EDAC code.
V3:
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.
---
v2: Update the mailing list to include the EDAC mailing list.
Signed-off-by: Thor Thayer ttha...@altera.com
To: Rob Herring robherri...@gmail.com
To:
From: Thor Thayer ttha...@altera.com
Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers are used by the FPGA bridge so
these are accessed through the syscon interface.
- The configuration of the SDRAM memory size for the EDAC
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.
---
v2: Update the mailing list to include the EDAC mailing list.
Signed-off-by: Thor Thayer ttha...@altera.com
To: Rob Herring robherri...@gmail.com
To: Pawel Moll
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.
Signed-off-by: Thor Thayer ttha...@altera.com
To: Rob Herring robherri...@gmail.com
To: Pawel Moll pawel.m...@arm.com
To: Mark Rutland mark.rutl...@arm.com
To: Ian
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.
Signed-off-by: Thor Thayer ttha...@altera.com
To: Rob Herring robherri...@gmail.com
To: Pawel Moll pawel.m...@arm.com
To: Mark Rutland mark.rutl...@arm.com
To:
From: Thor Thayer ttha...@altera.com
Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers are used by the FPGA bridge so
these are accessed through the syscon interface.
- The configuration of the SDRAM memory size for the EDAC
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.
Signed-off-by: Thor Thayer ttha...@altera.com
To: Rob Herring rob.herr...@calxeda.com
To: Pawel Moll pawel.m...@arm.com
To: Mark Rutland mark.rutl...@arm.com
From: Thor Thayer ttha...@altera.com
Addition of the Altera SDRAM controller registers to the
Altera SoC project. These registers are shared by future
drivers such as ECC and the FPGA bridge.
Signed-off-by: Thor Thayer ttha...@altera.com
To: Rob Herring rob.herr...@calxeda.com
To: Pawel Moll
87 matches
Mail list logo
