On Thursday 07 February 2002 12:37 pm, Jose Fonseca wrote:
Could someone of the 3D gurus enlighten this question? More
specifically, what is pseudo DMA and what is the relationship between
DMA and the PIO and MMIO modes?
psuedo DMA is where you pass a DMA-able command buffer to an
On Monday 18 February 2002 10:35 pm, Keith Whitwell wrote:
The rings are in agp space. It's a bug in the security model of the i810,
it's arcane, but believe me it's real.
Which leaves it open to attack because the AGP space isn't covered by the
protection system. Got to wonder what they
Frank C. Earl wrote:
On Monday 18 February 2002 10:35 pm, Keith Whitwell wrote:
The rings are in agp space. It's a bug in the security model of the i810,
it's arcane, but believe me it's real.
Which leaves it open to attack because the AGP space isn't covered by the
protection
Frank C. Earl wrote:
On Thursday 14 February 2002 10:33 am, Keith Whitwell wrote:
I haven't had a good look at security on either of these cards, but it's
definitely worth doing, both to find out if we're doing too little and if
we're doing too much.
I've been looking at the i810
On Monday 18 February 2002 12:07 pm, Keith Whitwell wrote:
The i810 has a security model that makes insecure commands in batch buffers
into noops. Unfortunately there is a hole in the security model: you can
emit a batch buffer with blit commands in it that blit insecure commands
onto the
On Monday 18 February 2002 01:07 pm, Keith Whitwell wrote:
A followup here... I'm looking at the i810 documentation and the source tree
now.
The i810 has a security model that makes insecure commands in batch buffers
into noops. Unfortunately there is a hole in the security model: you
Frank C. Earl wrote:
On Monday 18 February 2002 12:07 pm, Keith Whitwell wrote:
The i810 has a security model that makes insecure commands in batch buffers
into noops. Unfortunately there is a hole in the security model: you can
emit a batch buffer with blit commands in it that blit
Ugh... Ok, I see, I understand. What a shame. Really, it is- the driver as
it stands ends up being SLOWER than a mach64 under Utah-GLX. Yes, Utah-GLX
was less secure, but to be so much slower as to have the same gears framerate
with a PIII-600 as I got with a PII-450 on a supposedly
On Friday 08 February 2002 07:09 pm, José Fonseca wrote:
Does this mean that client code can lock the card but is not really
capable of putting the security of the system in danger?
Depends on what you define as in danger. It won't allow a user to commit
local or remote exploits to gain
Frank C. Earl wrote:
On Friday 08 February 2002 07:09 pm, José Fonseca wrote:
Does this mean that client code can lock the card but is not really
capable of putting the security of the system in danger?
Depends on what you define as in danger. It won't allow a user to
commit
local
Frank C. Earl wrote:
The command pathway doesn't seem to allow for that. Only the blit
pathway.
I've coded only inbound to the aperture writes with that pathway, but not
outbound (there's very little that anything other than the X server needs
to
do that sort of thing).
How do you
From what I understood from Alexander and Keith replies, DMA allows not
only to copy raw data (e.g., textures, z-buffers, vertexs) from the
system memory to the card's memory but also allows to automate the
card's registers programming in a way which is different of the PIO or
MMIO modes. Am I
On Friday 08 February 2002 11:03 am, Jose Fonseca wrote:
Keith, is pseudo DMA a hardware feature of Matrox cards or just a
software hack for debugging purposes?
I'm not Keith, but I'll venture an answer. It's a software hack that was in
the Utah-GLX drivers for the G200/G400 and RagePRO
Hi Frank,
On 2002.02.08 22:04 Frank C . Earl wrote:
On Thursday 07 February 2002 12:37 pm, Jose Fonseca wrote:
Their glossary (http://utah-glx.sourceforge.net/faq.html#AEN364) gives
the definition of PIO, DMA and Pseudo DMA.
PsuedoDMA is pushing the command data in a DMA-able format to
PIO = Programmable IO.
Registers that are possibly in x86 IO address space or PCI config
space.
Today these are just memory mapped registers where the CPU has direct
access.
DMA = DirectMemoryAccess.
Typically an engine on a chip which trasnfers data forth and back.
It
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