- Am 16. Sep 2024 um 15:24 schrieb David Edelsohn dje@gmail.com:
> On Mon, Sep 16, 2024 at 9:15 AM Sebastian Huber <
> sebastian.hu...@embedded-brains.de> wrote:
>
>> - Am 16. Sep 2024 um 15:02 schrieb David Edelsohn dje@gmail.com:
>>
>>
- Am 16. Sep 2024 um 15:02 schrieb David Edelsohn dje@gmail.com:
> On Sun, Sep 15, 2024 at 7:29 PM Sebastian Huber <
> sebastian.hu...@embedded-brains.de> wrote:
>
>> Hello,
>>
>> the PowerPC SPE port was obsoleted in GCC 8. It was moved from the general
keep a
back-end up to date. How much work would it be roughly to bring the PowerPC SPE
port from GCC 8 to the current version? Is this in the range of person weeks,
months, years?
Kind regard, Sebastian
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r+blub -mfloat-abi=hard -marm -mlibarch=armv7-a+simd
-march=armv7-a+simd END ...
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On 25.06.24 14:53, Sebastian Huber wrote:
On 24.06.24 16:06, Sebastian Huber wrote:
On 28.04.22 10:16, Sebastian Huber wrote:
Hello,
I test currently the Ada support for RTEMS in GCC 12. We have a
-mthumb -march=armv7-a+simd -mfloat-abi=hard multilib for which the
Ada RTS is built like this
On 24.06.24 16:06, Sebastian Huber wrote:
On 28.04.22 10:16, Sebastian Huber wrote:
Hello,
I test currently the Ada support for RTEMS in GCC 12. We have a
-mthumb -march=armv7-a+simd -mfloat-abi=hard multilib for which the
Ada RTS is built like this:
make[4]: Entering directory
'/tmp
On 28.04.22 10:16, Sebastian Huber wrote:
Hello,
I test currently the Ada support for RTEMS in GCC 12. We have a -mthumb
-march=armv7-a+simd -mfloat-abi=hard multilib for which the Ada RTS is
built like this:
make[4]: Entering directory
'/tmp/sh/b-gcc-arm-rtems6/arm-rtems6/thumb/ar
On 14.05.24 08:03, Sebastian Huber wrote:
Hello,
the ZynqMP APU RAM start addresses are far away from 0x0:
Sorry, I selected the wrong mailing list.
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ould it be possible to add
a NULL pointer protection page?
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desired calling convention, and also to
optimize them for our purposes. */
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on is actually
needed) and compile that locally in the libatomic build dir. That
shouldn't need changes to libgcc or libstdc++, should it?
Yes, this would also work. I can probably duplicate the gthr
configure/Makefile stuff from libstdc++ for this.
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fault implementation of libatomic.
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On 04.11.22 09:27, Sebastian Huber wrote:
Hello,
even recent 32-bit architectures such as RISC-V do not support 64-bit
atomic operations. Using -fprofile-update=atomic for the 32-bit RISC-V
RV32GC ISA yields:
warning: target does not support atomic profile update, single mode is
On 07.12.22 10:09, Richard Biener wrote:
On Wed, Dec 7, 2022 at 9:51 AM Sebastian Huber
wrote:
On 06.12.22 17:08, Richard Biener wrote:
Likely. I'd use the gimple_build () API from gimple-fold.h which
builds the expression(s) to a gimple_seq creating necessary temporaries
on-the-fl
e/EB/sebastian_h/src/gcc/gcc/passes.cc:2145
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
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On 05/12/2022 08:44, Richard Biener wrote:
On Mon, Dec 5, 2022 at 8:26 AM Sebastian Huber
wrote:
On 08/11/2022 11:25, Richard Biener wrote:
It would be great to have a code example for the construction of the "if
(f()) f();".
I think for the function above we ne
to:
li a4,1
amoadd.w a5,a4,0(a0)
addia5,a5,1
seqza5,a5
addia4,a0,4
amoadd.w zero,a5,0(a4)
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fa
going edge and then redirect edges to form a half-diamond.
move_sese_in_condition has most of that CFG manipulation (but
it performs sth different)
Thanks, I will probably able to do this with a bit trial and error.
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On 05.11.22 12:18, Richard Biener wrote:
On Fri, Nov 4, 2022 at 9:28 AM Sebastian Huber
wrote:
Hello,
even recent 32-bit architectures such as RISC-V do not support 64-bit
atomic operations. Using -fprofile-update=atomic for the 32-bit RISC-V
RV32GC ISA yields:
warning: target does not
Yes, but this approach would also work on big-endian architectures. You
just have to use other addresses. I guess the compiler knows for which
endianess it generates code.
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re available.
3. Else use a library call (libatomic).
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):
#define CC1_SPEC "%{G*}"
For each target you would have to check if you have to provide some
extra times for CC1_SPEC through copy and paste.
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On 20.07.22 15:01, Alexander Monakov wrote:
On Wed, 20 Jul 2022, Sebastian Huber wrote:
On 20/07/2022 13:41, Alexander Monakov wrote:
On Wed, 20 Jul 2022, Sebastian Huber wrote:
How does Ada get its default TLS model?
You shouldn't need to do anything special, GCC automatically se
On 20/07/2022 13:41, Alexander Monakov wrote:
On Wed, 20 Jul 2022, Sebastian Huber wrote:
How does Ada get its default TLS model?
You shouldn't need to do anything special, GCC automatically selects
initial-exec or local-exec for non-PIC (including PIE).
I am not sure, for this test pr
On 20/07/2022 10:43, Sebastian Huber wrote:
Hello,
RTEMS applications are usually fully statically linked together with the
operating system. So, we can use the -ftls-model=local-exec TLS model.
The default value for this option is defined in common.opt:
ftls-model=
Common Joined
)
Init(TLS_MODEL_GLOBAL_DYNAMIC)
-ftls-model=[global-dynamic|local-dynamic|initial-exec|local-exec] Set
the default thread-local storage code generation model.
Would it be possible to customize the default value for RTEMS?
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On 21/06/2022 15:24, Jakub Jelinek wrote:
On Tue, Jun 21, 2022 at 03:13:19PM +0200, Sebastian Huber wrote:
Hello,
I noticed that several division related routines provided by libgcc such as
__divdi3, __moddi3 and __umoddi3 have references to _Unwind_Resume for the
sparc-rtems target. For
d
code. I tried to reproduce it with a simple division by zero test case,
but this didn't work:
unsigned f(unsigned i)
{
return i / 0;
}
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t -o
/tmp/sh/b-rtems/arm/realview_pbx_a9_qemu/testsuites/ada/ada_nsecs.exe
/opt/rtems/7/lib/gcc/arm-rtems7/12.0.1/thumb/armv7-a+simd/hard/adainclude/s-secsta.ads:288:9:
sorry, unimplemented: Thumb-1 'hard-float' VFP ABI
The s-secsta.ads seems to be from the right multilib directory
(
ct?
Kind regards,
Sebastian
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ess of the value of the size argument.
I would not give an advice on using the nonnull attribute here. This
attribute could have pretty dangerous effects in the function definition
(removal of null pointer checks).
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On 16/08/2021 18:50, Jason Merrill wrote:
On Mon, Aug 16, 2021 at 9:51 AM Sebastian Huber
wrote:
On 16/08/2021 14:33, Martin Liška wrote:
On 8/12/21 4:31 PM, Sebastian Huber wrote:
This would be suitable for me, however, I am not sure if you want such
a customization feature just for a
On 16/08/2021 14:33, Martin Liška wrote:
On 8/12/21 4:31 PM, Sebastian Huber wrote:
This would be suitable for me, however, I am not sure if you want such
a customization feature just for a niche operating system.
I don't see a reason why not.
Please send a patch.
Ok, good. I will t
On 12/08/2021 16:29, Martin Liška wrote:
On 8/12/21 4:12 PM, Sebastian Huber wrote:
On 12/08/2021 16:08, Martin Liška wrote:
On 7/21/21 2:44 PM, Sebastian Huber wrote:
Hello,
while testing this patch
https://www.google.com/search?client=firefox-b-e&q=gcc+enable_runtime_checking
On 12/08/2021 16:08, Martin Liška wrote:
On 7/21/21 2:44 PM, Sebastian Huber wrote:
Hello,
while testing this patch
https://www.google.com/search?client=firefox-b-e&q=gcc+enable_runtime_checking
I noticed that __gcov_info_to_gcda() uses abort(). This is due to
(from tsystem.h):
#i
On 10/08/2021 09:59, Richard Biener wrote:
On Tue, Aug 10, 2021 at 8:07 AM Sebastian Huber
wrote:
On 09/08/2021 14:13, Richard Biener wrote:
But I guess using 32bit counters on sparc-rtems might be the way to
go ...
Yes, you somehow just have to make sure that your test programs don&#
E > 32
typedef gcov_type __INT64_TYPE__;
typedef gcov_type_unsigned __UINT64_TYPE__;
#else
typedef gcov_type __INT32_TYPE__;
typedef gcov_type_unsigned __UINT32_TYPE__;
#endif
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pho
n define.
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n, arg);
else
dump_unsigned (0, dump_fn, arg);
}
But I guess using 32bit counters on sparc-rtems might be the way to
go ...
Yes, you somehow just have to make sure that your test programs don't
overflow the counters.
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On 09/08/2021 12:22, Richard Biener wrote:
On Mon, Aug 9, 2021 at 8:52 AM Sebastian Huber
wrote:
Hello,
I would like to use gcov for a multi-threaded program running on an SMP
machine using a 32-bit SPARC/LEON3 target. This target supports
HAVE_atomic_compare_and_swapsi but not
On 09/08/2021 08:51, Sebastian Huber wrote:
Hello,
I would like to use gcov for a multi-threaded program running on an SMP
machine using a 32-bit SPARC/LEON3 target. This target supports
HAVE_atomic_compare_and_swapsi but not HAVE_atomic_compare_and_swapdi.
Unfortunately we have:
/* Return
n a
multi-threaded program I guess.
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On 22/07/2021 14:15, Richard Biener wrote:
On Wed, Jul 21, 2021 at 2:45 PM Sebastian Huber
wrote:
Hello,
while testing this patch
https://www.google.com/search?client=firefox-b-e&q=gcc+enable_runtime_checking
I noticed that __gcov_info_to_gcda() uses abort(). This is due to (from
tsyst
e abort here optionally? Can this be defined for
example by a target configuration header like gcc/config/rtems.h?
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used by frontends.
Thanks, this worked.
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me a hint what needs to be added so that this object
is created? The object is placed in a linker set.
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On 22/01/2021 10:46, Sebastian Huber wrote:
Hello,
for RTEMS we have in gcc/config/rtems.h the following LIB_SPEC:
#undef LIB_SPEC
#define LIB_SPEC "%{!qrtems:" STD_LIB_SPEC "} " \
"%{qrtems:%{!nostdlib:%{!nodefaultlibs:" \
"--start-group -lrtemsbsp -lrtem
} "
SANITIZER_SPEC " \
+ %{fprofile-arcs|fprofile-generate*|coverage:-lgcov} " \
+ SANITIZER_SPEC " " SYSTEM_LINK_SPEC " \
%{!nostdlib:%{!r:%{!nodefaultlibs:%(link_ssp)
%(link_gcc_c_sequence)}}}\
%{!nostdlib:%{!r:%{!nostartfiles:%E}}} %{T*} \n%
On 14/01/2021 15:16, Sebastian Huber wrote:
Hello,
I try to add a nios2 multilib to support the "Nios II Floating Point
Hardware 2 Component":
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_nios2_custom_instruction.pdf
If I add all custom in
rror: switch '-mcustom-round' has no effect unless
'-fno-math-errno' is specified [-Werror]
I am not sure how to fix this.
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to get the
data from the target.
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On 10/11/2020 17:23, Sebastian Huber wrote:
I am not sure how I can make the new section read-only. Currently, it
is writable:
.section .gcov_info,"aw"
.align 2
.type .LPBX2, @object
.size .LPBX2, 4
.LPBX2:
.long .LPBX0
I c
bably need also a patch for the GCC options documentation, test
cases, a GCC bootstrap on Linux, release notes, ...? Do I have to wait
for the GCC 11 development start?
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Hallo Martin,
On 10/11/2020 13:05, Martin Liška wrote:
On 11/9/20 6:45 PM, Sebastian Huber wrote:
Hello,
Hello.
There was a similar need some time ago:
https://gcc.gnu.org/legacy-ml/gcc/2019-11/msg9.html
Please take a look for a possible inspiration.
thanks for the pointer.
I
termination. Would such changes be
acceptable for GCC integration or is this too specific?
Kind regards,
Sebastian
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branch.
Thanks,
Sebastian
n could also be very very helpful. Any ideas?
Thank you!
Sebastian
[1] https://gcc.gnu.org/wiki/plugins
[2] https://gcc.gnu.org/legacy-ml/gcc/2016-02/msg4.html
[3] https://github.com/bedatadriven/renjin/
[4] https://github.com/mobanisto/gcc-bridge
[5] https://github.com/mobanisto/gcc-brid
Hi,
is somebody already working on backporting -moutline-atomics to gcc 8.x and 9.x
branches?
Thanks,
Sebastian
reinterpret_cast.
(pod_hash_traits::is_empty): Likewise.
This is ok for trunk.
Thanks.
This should now be fixed on master (r10-6434-
g1dae549dccfec1edb0cb4e65feadc4722bb3bcc8); I verified the build with
the patch with gcc, and Sebastian verified it with clang.
Thanks a lot for the quick fix. The
Hello,
I tried to build a recent GCC master on FreeBSD 12.1 and it failed with
a compile error:
$ clang --version
FreeBSD clang version 8.0.1 (tags/RELEASE_801/final 366581) (based on
LLVM 8.0.1)
Target: x86_64-unknown-freebsd12.1
Thread model: posix
InstalledDir: /usr/bin
../../gnu-mirror-
support them in GCC? I ask this so that I can plan my work to support it
for RTEMS. For example, are there plans to build them on top of ucontext?
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the passed gcov_info struct set (probably
related to 1)?
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smime.p7s
Description: S/MIME Cryptographic Signature
On 31/01/2019 11:07, Jakub Jelinek wrote:
On Thu, Jan 31, 2019 at 10:58:27AM +0100, Sebastian Huber wrote:
On 31/01/2019 10:56, Jakub Jelinek wrote:
On Thu, Jan 31, 2019 at 10:37:29AM +0100, Sebastian Huber wrote:
My problem is that our real-time operating system (RTEMS) is somewhere in
On 31/01/2019 10:56, Jakub Jelinek wrote:
On Thu, Jan 31, 2019 at 10:37:29AM +0100, Sebastian Huber wrote:
My problem is that our real-time operating system (RTEMS) is somewhere in
between a full blown Linux and the offload hardware. I would like to get rid
of stuff which depends on the Newlib
On 31/01/2019 10:29, Richard Biener wrote:
On Wed, Jan 30, 2019 at 3:46 PM Sebastian Huber
wrote:
Hello,
we would like to use libgomp in a quite constraint environment. In this
environment using for example the C locale support, errno, malloc(),
realloc(), free(), and abort() are problematic
gomp_strtol (env, &stride);
if (env == NULL)
return false;
A platform could then provide its own "config/*/strto.h" with an
alternative implementation.
Would this be acceptable after the GCC 9 release?
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On 17/01/2019 15:25, Sebastian Huber wrote:
On 17/01/2019 12:40, Eric Botcazou wrote:
I can build the trunk with a native
gnat --version
GNAT 8.2.1 20190103 [gcc-8-branch revision 267549]
Copyright (C) 1996-2018, Free Software Foundation, Inc.
This is free software; see the source for copying
failed (path includes full Git hashes).
Then I move the source and build roots to a shorter path, then build was
successful using the same configure options.
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On 17/01/2019 09:56, Sebastian Huber wrote:
Hello,
I tried to build the arm-rtems target with Ada support on the trunk
yesterday. It fails with:
/home/user/rtems-source-builder/rtems/build/arm-rtems6-gcc-0ca47588bd2e38bbfa427503968e08a6b8ab3166-newlib-068182e26c7b397df579b69a18f745092844d1b4
th GCC 7.4.0 it works and the s-oscons-tmplt.s dosn't look that much
different.
My native GNAT is:
gnat --version
GNAT 9.0.0 20190116 (experimental)
Copyright (C) 1996-2019, Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not eve
On 13/11/2018 21:20, Stafford Horne wrote:
On Tue, Nov 13, 2018 at 11:57:13AM -0600, Joel Sherrill wrote:
Sebastian confirmed he couldn't get a complete RTEMS build either.
I looked into this enough to spot that old or1k port's libgcc/config.host
has an extra_parts line for or1k-*-
l.lbz r11, 0(r3)
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Diese Nachricht ist keine geschäft
On Fri, Oct 12, 2018 at 2:14 PM Marc Glisse wrote:
> On Fri, 12 Oct 2018, Thomas Schwinge wrote:
>
> > Hmm, and without any OpenACC/OpenMP etc., actually the same problem is
> > also present when running the following code through the vectorizer:
> >
> >for (int tmp = 0; tmp < N_J * N_I; ++tm
tions : constant Boolean := True;
ZCX_By_Default: constant Boolean := False;
in system-rtems.ads.
Thanks, this worked.
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E
g/svn/gcc/trunk@247301
138bc75d-0d04-0410-961f-82ee72b054a4
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`__gnat_raise_nodefer_with_msg' follow
I cannot find it in the GCC sources:
grep -ri raise_nodefer_with_msg
gcc/ada/gcc-interface/trans.c: (get_identifier
("__gnat_raise_nodefer_with_msg"), NULL_TREE, ftype,
Who is supposed to provide an implementation of
__gnat_raise_node
> Subject: Re: Question regarding preventing optimizing out of register in
> expansion
>
> On 6/26/18 4:05 AM, Peryt, Sebastian wrote:
> > With some changes simplified implementation of my expansion is as follows:
> > tmp_op0 = gen_reg_rtx (mode);
> > emit_move_ins
m using those extra flags because I also want to use YMM2 and
ZMM2 in my instruction.
Does anyone have idea why might such thing happen? And how this can be overcome?
Thanks,
Sebastian
> -Original Message-
> Subject: Re: Question regarding preventing optimizing out of regis
Thank you very much! Your suggestions helped me figure this out.
Sebastian
-Original Message-
From: Nathan Sidwell [mailto:nathanmsidw...@gmail.com] On Behalf Of Nathan
Sidwell
Sent: Thursday, June 21, 2018 1:43 PM
To: Peryt, Sebastian ; gcc@gcc.gnu.org
Subject: Re: Question regarding
ks fine for -O0, but when I move to higher level optimizations
setting value into reg1 (lines before emit_clobber) are optimized out.
I already tried moving emit_clobber just after assignment but it doesn't help.
Could you please suggest how I can prevent it from happening?
Thanks,
Sebastian
GCC dumps, e.g.
related to passes.
You can do -fdump-- where type can be e.g. rtl and pass the pass
for which
you want to gather information. I suppose there is more to those dumps, but
this should get you started.
Sebastian
>
>
On 01/06/18 10:23, Michael Clark wrote:
On 1/06/2018, at 6:16 PM, Sebastian Huber
wrote:
On 29/05/18 20:02, Jim Wilson wrote:
Most variants include the C extension. Would it be possible to add -march=rv32g
and -march=rv64g variants?
The expectation is that most implementations will
On 31/05/18 11:08, Palmer Dabbelt wrote:
On Tue, 29 May 2018 11:02:58 PDT (-0700), Jim Wilson wrote:
On 05/26/2018 06:04 AM, Sebastian Huber wrote:
Why is the default multilib and a variant identical?
This is supposed to be a single multilib, with two names. We use
MULTILIB_REUSE to map the
ourse define your own
set of multilibs.
I am not a hardware developer, but I heard that the C extension is not
easy to implement in out of order machines. For example:
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-157.html
--
Sebastian Huber, embedded brains GmbH
Address : Dorniers
Hello Jim,
- Am 29. Mai 2018 um 20:27 schrieb Jim Wilson j...@sifive.com:
> On 05/28/2018 06:32 AM, Sebastian Huber wrote:
>> I guess, that the resolution of the weak reference to the undefined
>> symbol __deregister_frame_info somehow sets __deregister_frame_info to
>>
s0,sp,32
lla a5,f
sd a5,-24(s0)
ld a5,-24(s0)
beqz a5,.L3
ld a5,-24(s0)
jalr a5
.L3:
nop
ld ra,24(sp)
ld s0,16(sp)
addi sp,sp,32
jr ra
.size _start, .-_start
_WEAK void *__deregister_frame_info (const void *unused)
+{
+ (void)unused;
+ return 0;
+}
+
extern void *__deregister_frame_info_bases (const void *)
TARGET_ATTRIBUTE_WEAK;
extern void __do_global_ctors_1 (void);
then the example program links.
--
Sebastian Huber, embedded brains G
ems5/lib/:/lib/:/usr/lib/
-COLLECT_GCC_OPTIONS='-E' '-P' '-v' '-dD' '-march=rv64gc' '-mabi=lp64d'
+COLLECT_GCC_OPTIONS='-E' '-P' '-v' '-dD' '-march=rv64imafdc' '-mabi=lp64d'
This
Hi,
I'd like to ask what is the expected date for GCC branching to GCC-8 release
version?
I'm mostly interested because I'd like to know when it'll be ok again to add
new features?
Or are we still able to add them?
Thanks,
Sebastian
handling all
>communication
regarding GSoC participation and I believe you are a perfect candidate for
admin role next year.
Sebastian
> -Original Message-
> Sent: Thursday, March 29, 2018 7:08 PM
> Subject: Re: Google Summer of Code 2018: Call for mentors and ideas
>
&g
eone already said so WRT the m68k, but didn't
step up to do the conversion), but I think that unless we set a point
nothing is likely to happen.
How much work is it to convert the m68k to LRA. Is this person days,
weeks, months or years?
--
Sebastian Huber, embedded brains GmbH
Address
mp;cf_known_to_fail_type=allwords&cf_known_to_work_type=allwords&list_id=197687&product=gcc&query_format=advanced&short_desc=m32c&short_desc_type=allwordssubstr
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 1
On 04/01/18 16:03, Andreas Schwab wrote:
On Jan 04 2018, Sebastian Huber wrote:
/home/sh/src/gcc/gcc/config/nios2/nios2.h:436:31: error: expected '=',
',', ';', 'asm' or '__attribute__' before 'nios2_section_threshold'
extern
ed in gcc/hwint.h. Who is supposed to include
this file? Is this done via an #include or via a tm_file (gcc/config.gcc)?
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastia
On 05/12/17 15:17, Segher Boessenkool wrote:
Hi!
On Mon, Dec 04, 2017 at 03:34:09PM +0100, Sebastian Huber wrote:
I added support for the 64-bit PowerPC some months ago using a variant
of the ELFv2 ABI. I don't know which kind of long double support I use
on this target. This is difficul
entry=23, argv=, argv@entry=0x7fffd828) at
/scratch/svn-gcc/gcc/toplev.c:2194
#18 0x00446bdb in main (argc=23, argv=0x7fffd828) at
/scratch/svn-gcc/gcc/main.c:39
(gdb)
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189
X in thread A will be synchronized-with all non-atomic
and relaxed atomic loads from the same locations made in thread B
after F.
Where is the acquire fence or a load in the example?
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 1
On 16/10/17 12:31, David Brown wrote:
On 13/10/17 09:06, Sebastian Huber wrote:
Hello,
I would like to update the documentation of these compiler flags and
have some questions. The -ffunction-sections and -fdata-sections
documentation is currently:
Do these options affect the code
- Am 13. Okt 2017 um 20:39 schrieb David Edelsohn dje@gmail.com:
> On Fri, Oct 13, 2017 at 2:34 PM, Sebastian Huber
> wrote:
>
>>>> Do these options affect the code generation?
>>> They can affect code generation. By placing each object into its own
>
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