Re: [PATCH 02/11] AArch64: Add test cases for SVE types in OpenMP shared clause.

On 5/30/24 6:08 PM, Richard Sandiford wrote: Tejas Belagod writes: This patch tests various shared clauses with SVE types. It also adds a test scaffold to run OpenMP tests in under the gcc.target testsuite. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/omp/aarch64-sve-omp.exp: Ne

Re: [PATCH v3 #1/2] [rs6000] adjust return_pc debug attrs

on 2024/5/29 14:52, Alexandre Oliva wrote: > On May 27, 2024, "Kewen.Lin" wrote: > >> I wonder if it's possible to have a test case for this? > > gcc.dg/guality/pr54519-[34].c at -O[1g] are fixed by this patch on Nice! > ppc64le-linux-gnu. Are these the sort of test case you're interested Ye

Re: [PATCH v3 4/6] btf: add -fprune-btf option

On Thu, May 30, 2024 at 11:34 PM David Faust wrote: > > This patch adds a new option, -fprune-btf, to control BTF debug info > generation. Can you name it -gprune-btf instead? > As the name implies, this option enables a kind of "pruning" of the BTF > information before it is emitted. When enab

Re: [PATCH] vect: Support multiple lane-reducing operations for loop reduction [PR114440]

On Thu, May 30, 2024 at 3:28 PM Feng Xue OS wrote: > > >> Hi, > >> > >> The patch was updated with the newest trunk, and also contained some minor > >> changes. > >> > >> I am working on another new feature which is meant to support pattern > >> recognition > >> of lane-reducing operations in af

Re: [PATCH 1/6] vect: Add a function to check lane-reducing code [PR114440]

On Thu, May 30, 2024 at 4:45 PM Feng Xue OS wrote: > > This is a patch that is split out from > https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652626.html. > > Check if an operation is lane-reducing requires comparison of code against > three kinds (DOT_PROD_EXPR/WIDEN_SUM_EXPR/SAD_EXPR). Ad

Re: [PATCH 2/6] vect: Split out partial vect checking for reduction into a function

On Thu, May 30, 2024 at 4:48 PM Feng Xue OS wrote: > > This is a patch that is split out from > https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652626.html. > > Partial vectorization checking for vectorizable_reduction is a piece of > relatively isolated code, which may be reused by other plac

Re: [PATCH-1, rs6000] Add a new type of CC mode - CCBCD for bcd insns [PR100736, PR114732]

Hi Haochen, on 2024/5/30 11:14, HAO CHEN GUI wrote: > Hi Kewen, > > 在 2024/5/29 13:26, Kewen.Lin 写道: >> I can understand re-using "unordered" and "eq" will save some efforts than >> doing with unspecs, but they are actually RTL codes instead of bits on the >> specific hardware CR, a downside is t

[COMMITTED] testsuite: Adjust several dg-additional-files-options calls [PR115294]

A recent patch commit bdc264a16e327c63d133131a695a202fbbc0a6a0 Author: Alexandre Oliva Date: Thu May 30 02:06:48 2024 -0300 [testsuite] conditionalize dg-additional-sources on target and type added two additional args to dg-additional-files-options. Unfortunately, this completely broke se

Re: [PATCH 01/11] OpenMP/PolyInt: Pass poly-int structures by address to OMP libs.

Tejas Belagod writes: > On 5/30/24 6:28 PM, Richard Sandiford wrote: >> Tejas Belagod writes: >>> Currently poly-int type structures are passed by value to OpenMP runtime >>> functions for shared clauses etc. This patch improves on this by passing >>> around poly-int structures by address to avo

Re: [PATCH v3 2/2] Prevent divide-by-zero

On Thu, May 30, 2024 at 2:11 AM Patrick O'Neill wrote: > > From: Greg McGary Still a NACK. If remain ends up zero then /* Try to use a single smaller load when we are about to load excess elements compared to the unrolled scalar

Re: [PATCH] Fix some opindex for some options [PR115022]

On Thu, May 30, 2024 at 5:48 AM Andrew Pinski wrote: > > While looking at the index I noticed that some options had > `-` in the front for the index which is wrong. And then > I noticed there was no index for `mcmodel=` for targets or had > used `-mcmodel` incorrectly. > > This fixes both of those

Re: [PATCH 01/11] OpenMP/PolyInt: Pass poly-int structures by address to OMP libs.

On Fri, May 31, 2024 at 08:45:54AM +0100, Richard Sandiford wrote: > > When you say same way, do you mean the way SVE ABI defines the rules for > > SVE types? > > No, sorry, I meant that if the choice isn't purely local to a source > code function, the condition should be something like sizeless_

Re: [Patch, rs6000, aarch64, middle-end] Add implementation for different targets for pair mem fusion

Segher Boessenkool writes: > Hi! > > On Fri, May 31, 2024 at 01:21:44AM +0530, Ajit Agarwal wrote: >> Code is implemented with pure virtual functions to interface with target >> code. > > It's not a pure function. A pure function -- by definition -- has no > side effects. These things have side

Re: [PATCH 01/11] OpenMP/PolyInt: Pass poly-int structures by address to OMP libs.

Jakub Jelinek writes: > On Fri, May 31, 2024 at 08:45:54AM +0100, Richard Sandiford wrote: >> > When you say same way, do you mean the way SVE ABI defines the rules for >> > SVE types? >> >> No, sorry, I meant that if the choice isn't purely local to a source >> code function, the condition shou

RE: [PATCH 1/3] vect: generate suitable convert insn for int -> int, float -> float and int <-> float.

> -Original Message- > From: Richard Biener > Sent: Wednesday, May 29, 2024 5:41 PM > To: Hu, Lin1 > Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao ; > ubiz...@gmail.com > Subject: Re: [PATCH 1/3] vect: generate suitable convert insn for int -> int, > float > -> float and int <-> float. > >

Re: [COMMITTED] ggc: Reduce GGC_QUIRE_SIZE on Solaris/SPARC [PR115031]

Hi Eric, >> It turns out that this exhaustion of the 32-bit address space happens >> due to a combination of three issues: >> >> * the SPARC pagesize of 8 kB, >> >> * ggc-page.cc's chunk size of 512 * pagesize, i.e. 4 MB, and >> >> * mmap adding two 8 kB unmapped red-zone pages to each mapping

Re: [PATCH 2/4] resource.cc: Replace calls to find_basic_block with cfgrtl BLOCK_FOR_INSN

Hans-Peter Nilsson writes: > [...] > (Not-so-)fun fact: add_insn_after takes a bb parameter which > reorg.cc always passes as NULL. But - the argument is > *always ignored* and the bb in the "after" insn is used. > I traced that ignored parameter as far as > r0-81421-g6fb5fa3cbc0d78 "Merge datafl

[COMMITTED] build: Include minor version in config.gcc unsupported message

It has been pointed out to me that when moving Solaris 11.3 from config.gcc's obsolete to unsupported list, I'd forgotten to also move the minor version info, leading to confusing *** Configuration i386-pc-solaris2.11 not supported instead of the correct *** Configuration i386-pc-solaris2.11.3 n

Re: [Patch, rs6000, aarch64, middle-end] Add implementation for different targets for pair mem fusion

Ajit Agarwal writes: > Hello All: > > Common infrastructure using generic code for pair mem fusion of different > targets. > > rs6000 target specific specific code implements virtual functions defined > by generic code. > > Code is implemented with pure virtual functions to interface with target >

Re: [PATCH 6/7] OpenMP: Fortran front-end support for dispatch + adjust_args

Hi Tobias, Thanks for your comments. Here is an updated patch. On 28/05/2024 09:14, Tobias Burnus wrote: Paul-Antoine Arras: +  if (n->sym->ts.type != BT_DERIVED +  || !n->sym->ts.u.derived->ts.is_iso_c) +    { +  gfc_error ("argument list item %qs in "

[COMMITTED] fix: valid compiler optimization may fail the test

cxa4001 may fail with "Exception not raised" when the compiler omits the calls to To_Mapping, in accordance with 10.2.1(18/3): "If a library unit is declared pure, then the implementation is permitted to omit a call on a library-level subprogram of the library unit if the results are not nee

Re: [PATCH] rust: Do not link with libdl and libpthread unconditionally

Hi Richard, On 4/30/24 09:55, Richard Biener wrote: On Fri, Apr 19, 2024 at 11:49 AM Arthur Cohen wrote: Hi everyone, This patch checks for the presence of dlopen and pthread_create in libc. If that is not the case, we check for the existence of -ldl and -lpthread, as these libraries are r

Re: [Patch, rs6000, aarch64, middle-end] Add implementation for different targets for pair mem fusion

Reviewing my review :) Richard Sandiford writes: >> + >> + for (auto def : info->defs ()) >> +{ >> + auto set = dyn_cast (def); >> + if (set && set->has_any_uses ()) >> +{ >> + for (auto use : set->all_uses()) > > Nit: has_any_uses isn't necessary: the inner loop will simp

[PATCH] aarch64: Add missing ACLE macro for NEON-SVE Bridge

__ARM_NEON_SVE_BRIDGE was missed in the original patch and is added by this patch. Ok for trunk and a backport into gcc-14? gcc/ChangeLog: * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Add missing __ARM_NEON_SVE_BRIDGE.diff --git a/gcc/config/aarch64/aarch64-c.cc b

[PATCH v4 0/5] libgomp: OpenMP pinned memory for omp_alloc

This patch series is a rebase and partial rework of the v3 series I posted in December: https://patchwork.sourceware.org/project/gcc/list/?series=28237&state=%2A&archive=both The first patch from that series was already approved and committed, but the rest of the patch series remains to-do. Besi

[PATCH v4 1/5] libgomp, openmp: Add ompx_pinned_mem_alloc

Compared to the previous v3 posting of this patch, the enumeration of the "ompx" allocators have been moved to start at "100". - This creates a new predefined allocator as a shortcut for using pinned memory with OpenMP. The name uses the OpenMP extension space and is intended to be consi

[PATCH v4 4/5] libgomp, nvptx: Cuda pinned memory

From: Thomas Schwinge This patch was already approved, by Tobias Burnus (with one caveat about initialization location), but wasn't committed at that time as I didn't want to disentangle it from the textual dependencies on the other patches in the series. Use Cuda to pin me

[PATCH v4 3/5] openmp: -foffload-memory=pinned

Implement the -foffload-memory=pinned option such that libgomp is instructed to enable fully-pinned memory at start-up. The option is intended to provide a performance boost to certain offload programs without modifying the code. This feature only works on Linux, at present, and simply calls mloc

[PATCH v4 2/5] openmp: Add -foffload-memory

Add a new option. It's inactive until I add some follow-up patches. gcc/ChangeLog: * common.opt: Add -foffload-memory and its enum values. * coretypes.h (enum offload_memory): New. * doc/invoke.texi: Document -foffload-memory. --- gcc/common.opt | 16 +++

[PATCH v4 5/5] libgomp: fine-grained pinned memory allocator

This patch was already approved, by Tobias Burnus, in the v3 posting, but I've not yet committed it because there are some textual dependecies on the yet-to-be-approved patches. - This patch introduces a new custom memory allocator for use with pinned memory (in the case where

[PATCH] tree-optimization/115278 - fix DSE in if-conversion wrt volatiles

The following adds the missing guard for volatile stores to the embedded DSE in the loop if-conversion pass. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimization/115278 * tree-if-conv.cc (ifcvt_local_dce): Do not DSE volatile stores. * g++.dg/

Re: [PATCH v2 01/12] OpenMP: metadirective tree data structures and front-end interfaces

Hi Sandra, some observations/comments, but in general it looks good. Sandra Loosemore wrote: This patch adds the OMP_METADIRECTIVE tree node and shared tree-level support for manipulating metadirectives. It defines/exposes interfaces that will be used in subsequent patches that add front-end a

RE: [PATCH 1/3] vect: generate suitable convert insn for int -> int, float -> float and int <-> float.

On Fri, 31 May 2024, Hu, Lin1 wrote: > > -Original Message- > > From: Richard Biener > > Sent: Wednesday, May 29, 2024 5:41 PM > > To: Hu, Lin1 > > Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao ; > > ubiz...@gmail.com > > Subject: Re: [PATCH 1/3] vect: generate suitable convert insn for int

Re: [PATCH v10 2/5] Convert references with "counted_by" attributes to/from .ACCESS_WITH_SIZE.

On Thu, 30 May 2024, Qing Zhao wrote: > Including the following changes: > * The definition of the new internal function .ACCESS_WITH_SIZE > in internal-fn.def. > * C FE converts every reference to a FAM with a "counted_by" attribute > to a call to the internal function .ACCESS_WITH_SIZE. >

Re: [PATCH] rust: Do not link with libdl and libpthread unconditionally

On Fri, May 31, 2024 at 12:24 PM Arthur Cohen wrote: > > Hi Richard, > > On 4/30/24 09:55, Richard Biener wrote: > > On Fri, Apr 19, 2024 at 11:49 AM Arthur Cohen > > wrote: > >> > >> Hi everyone, > >> > >> This patch checks for the presence of dlopen and pthread_create in libc. > >> If that is

Re: [patch] libgomp: Enable USM for AMD APUs and MI200 devices

On 29/05/2024 13:15, Tobias Burnus wrote: This patch depends (on the libgomp/target.c parts) of the patch "[patch] libgomp: Enable USM for some nvptx devices", https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652987.html AMD GPUs that are either APU devices or MI200 [or MI300X] (with HSA_XNACK

Re: [PATCH v10 2/5] Convert references with "counted_by" attributes to/from .ACCESS_WITH_SIZE.

> On May 31, 2024, at 08:58, Richard Biener wrote: > > On Thu, 30 May 2024, Qing Zhao wrote: > >> Including the following changes: >> * The definition of the new internal function .ACCESS_WITH_SIZE >> in internal-fn.def. >> * C FE converts every reference to a FAM with a "counted_by" attribu

nvptx target: Global constructor, destructor support, via nvptx-tools 'ld' (was: nvptx: Support global constructors/destructors via 'collect2')

Hi! On 2022-12-02T14:35:35+0100, I wrote: > On 2022-12-01T22:13:38+0100, I wrote: >> I'm working on support for global constructors/destructors with >> GCC/nvptx > > See "nvptx: Support global constructors/destructors via 'collect2'" > attached; [...] > > Per my quick scanning of 'gcc/config.gcc'

[PATCH 1/5][v3] Avoid ICE with pointer reduction

There's another case where we can refer to neutral_op before eventually converting it from pointer to integer so simply do that unconditionally. * tree-vect-loop.cc (get_initial_defs_for_reduction): Always convert neutral_op. --- gcc/tree-vect-loop.cc | 15 +++ 1 file

[PATCH 2/5][v3] Adjust vector dump scans

The following adjusts dump scanning for something followed by successful vector analysis to more specifically look for 'Analysis succeeded' and not 'Analysis failed' because the previous look for just 'succeeded' or 'failed' is easily confused by SLP discovery dumping those words. * tree-v

[PATCH 3/5][v3] Do single-lane SLP discovery for reductions

The following performs single-lane SLP discovery for reductions. It requires a fixup for outer loop vectorization where a check for multiple types needs adjustments as otherwise bogus pointer IV increments happen when there are multiple copies of vector stmts in the inner loop. For the reduction e

[PATCH 5/5][v3] RISC-V: Avoid inserting after a GIMPLE_COND with SLP and early break

When vectorizing an early break loop with LENs (do we miss some check here to disallow this?) we can end up deciding to insert stmts after a GIMPLE_COND when doing SLP scheduling and trying to be conservative with placing of stmts only dependent on the implicit loop mask/len. The following avoids

[PATCH 4/5][v3] Reduce single-lane SLP testresult noise

The following avoids dumping 'vectorizing stmts using SLP' for single-lane instances since that causes extra testsuite fallout. * tree-vect-slp.cc (vect_schedule_slp): Gate dumping 'vectorizing stmts using SLP' on > 1 lanes. --- gcc/tree-vect-slp.cc | 3 ++- 1 file changed, 2 inse

Re: [Patch, rs6000, aarch64, middle-end] Add implementation for different targets for pair mem fusion

Hello Richard: On 31/05/24 3:23 pm, Richard Sandiford wrote: > Ajit Agarwal writes: >> Hello All: >> >> Common infrastructure using generic code for pair mem fusion of different >> targets. >> >> rs6000 target specific specific code implements virtual functions defined >> by generic code. >> >> C

[committed] alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]

any_divmod instructions are modelled with invalid RTX: [(set (match_operand:DI 0 "register_operand" "=c") (sign_extend:DI (match_operator:SI 3 "divmod_operator" [(match_operand:DI 1 "register_operand" "a") (match_operand:DI 2 "register_ope

[PATCH] Fix PR c++/109958: ICE taking the address of bound static member function brought into derived class by using-declaration

From: Simon Martin We currently ICE upon the following because we don't properly handle the overload created for B::f through the using statement. === cut here === struct B { static int f(); }; struct D : B { using B::f; }; void f(D d) { &d.f; } === cut here === This patch makes build_class_mem

Re: [PATCH 4/6] vect: Bind input vectype to lane-reducing operation

On Thu, May 30, 2024 at 4:53 PM Feng Xue OS wrote: > > The input vectype is an attribute of lane-reducing operation, instead of > reduction PHI that it is associated to, since there might be more than one > lane-reducing operations with different type in a loop reduction chain. So > bind each lane

[PATCH] [libstdc++] add _GLIBCXX_CLANG to workaround predefined __clang__

A proprietary embedded operating system that uses clang as its primary compiler ships headers that require __clang__ to be defined. Defining that macro causes libstdc++ to adopt workarounds that work for clang but that break for GCC. So, introduce a _GLIBCXX_CLANG macro, and a convention to tes

Re: [Patch, rs6000, aarch64, middle-end] Add implementation for different targets for pair mem fusion

On Fri, May 31, 2024 at 09:14:21AM +0100, Richard Sandiford wrote: > Segher Boessenkool writes: > > Hi! > > > > On Fri, May 31, 2024 at 01:21:44AM +0530, Ajit Agarwal wrote: > >> Code is implemented with pure virtual functions to interface with target > >> code. > > > > It's not a pure function.

Re: [Patch, rs6000, aarch64, middle-end] Add implementation for different targets for pair mem fusion

Ajit Agarwal writes: > On 31/05/24 3:23 pm, Richard Sandiford wrote: >> Ajit Agarwal writes: >>> Hello All: >>> >>> Common infrastructure using generic code for pair mem fusion of different >>> targets. >>> >>> rs6000 target specific specific code implements virtual functions defined >>> by gener

Re: [PATCH] [libstdc++] add _GLIBCXX_CLANG to workaround predefined __clang__

On 31/05/24 11:07 -0300, Alexandre Oliva wrote: A proprietary embedded operating system that uses clang as its primary compiler ships headers that require __clang__ to be defined. Defining that macro causes libstdc++ to adopt workarounds that work for clang but that break for GCC. So, introduc

Re: [PATCH 5/6] vect: Support multiple lane-reducing operations for loop reduction [PR114440]

On Thu, May 30, 2024 at 4:55 PM Feng Xue OS wrote: > > For lane-reducing operation(dot-prod/widen-sum/sad) in loop reduction, current > vectorizer could only handle the pattern if the reduction chain does not > contain other operation, no matter the other is normal or lane-reducing. > > Actually,

Re: [PATCH] fix PowerPC < 7 w/ Altivec not to default to power7

Hi Kewen, thank you for your reply. > on 2024/3/8 19:33, Rene Rebe wrote: > > This might not be the best timing -short before a major release-, > > however, Sam just commented on the bug I filled years ago [1], so here > > we go: > > > > Glibc uses .machine to determine assembler optimizations t

[PATCH] ifcvt: Clarify if_info.original_cost.

Hi, before noce_find_if_block processes a block it sets up an if_info structure that holds the original costs. At that point the costs of the then/else blocks have not been added so we only care about the "if" cost. The code originally used BRANCH_COST for that but was then changed to COST_N_INS

[PATCH] RISC-V: Add min/max patterns for ifcvt.

Hi, ifcvt likes to emit (set (if_then_else) (ge (reg 1) (reg2)) (reg 1) (reg 2)) which can be recognized as min/max patterns in the backend. This patch adds such patterns and the respective iterators as well as a test. This depends on the generic ifcvt change. Regtested on rv64gcv

Re: [Patch, aarch64, middle-end\ v4: Move pair_fusion pass from aarch64 to middle-end

Hello, I can't bootstrap using gcc 5.5 since this change. It fails with: .../gcc/pair-fusion.cc: In member function ‘bool pair_fusion_bb_info::fuse_pair(bool, unsigned int, int, rtl_ssa::insn_info*, rtl_ssa::in sn_info*, base_cand&, const rtl_ssa::insn_range_info&)’: .../gcc/pair-fusion.cc:1790

[PATCH] testsuite: Improve check-function-bodies

Improve check-function-bodies by allowing single-character function names. Also skip '#' comments which may be emitted from inline assembler. Passes regress, OK for commit? gcc/testsuite: * lib/scanasm.exp (configure_check-function-bodies): Allow single-char function names. Skip

[PATCH] AArch64: Add ACLE MOPS support

Add __ARM_FEATURE_MOPS predefine. Add support for ACLE __arm_mops_memset_tag. Passes regress, OK for commit? gcc: * config/aaarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Add __ARM_FEATURE_MOPS predefine. * config/aarch64/arm_acle.h: Add __arm_mops_memset_tag(). gc

Re: [PATCH] [libstdc++] add _GLIBCXX_CLANG to workaround predefined __clang__

On May 31, 2024, Jonathan Wakely wrote: > On 31/05/24 11:07 -0300, Alexandre Oliva wrote: >> --- a/libstdc++-v3/include/pstl/pstl_config.h [...] >> -#if defined(__clang__) >> +#if defined(__GLIBCXX__) ? defined(_GLIBCXX_CLANG) : defined(__clang__) > This file is also imported from upstream, like

Re: [PATCH] [libstdc++] add _GLIBCXX_CLANG to workaround predefined __clang__

So __clang__ is turning into the next __GNUC__ ;) In essence, inside libstdc++ code, __clang__ is going to mean Clang-compatible compiler and _GLIBCXX_CLANG then means it's the actual Clang compiler (or a vendor variant like Apple's). Would it make sense to adjust the Apple clang major version

[PATCH v2] c++/modules: Fix revealing with using-decls [PR114867]

On Tue, May 28, 2024 at 02:57:09PM -0400, Jason Merrill wrote: > On 5/26/24 09:01, Nathaniel Shead wrote: > > Is this approach OK? Alternatively I suppose we could do a deep copy of > > the overload list when this occurs to ensure we don't affect existing > > referents, would that be preferable? >

Re: [PATCH v3 4/6] btf: add -fprune-btf option

On 5/31/24 00:07, Richard Biener wrote: > On Thu, May 30, 2024 at 11:34 PM David Faust wrote: >> >> This patch adds a new option, -fprune-btf, to control BTF debug info >> generation. > > Can you name it -gprune-btf instead? Yes, sure. I think I followed -feliminate-unused-debug-types, but I

Re: [PATCH] testsuite: Improve check-function-bodies

Wilco Dijkstra writes: > Improve check-function-bodies by allowing single-character function names. > Also skip '#' comments which may be emitted from inline assembler. > > Passes regress, OK for commit? > > gcc/testsuite: > * lib/scanasm.exp (configure_check-function-bodies): Allow single

Re: [PATCH] AArch64: Add ACLE MOPS support

Wilco Dijkstra writes: > Add __ARM_FEATURE_MOPS predefine. Add support for ACLE __arm_mops_memset_tag. > > Passes regress, OK for commit? > > gcc: > * config/aaarch64/aarch64-c.cc (aarch64_update_cpp_builtins): > Add __ARM_FEATURE_MOPS predefine. > * config/aarch64/arm_acl

Re: [PATCH v3 4/6] btf: add -fprune-btf option

> Am 31.05.2024 um 17:58 schrieb David Faust : > >  > >> On 5/31/24 00:07, Richard Biener wrote: >>> On Thu, May 30, 2024 at 11:34 PM David Faust wrote: >>> >>> This patch adds a new option, -fprune-btf, to control BTF debug info >>> generation. >> >> Can you name it -gprune-btf instead? >

Re: [PATCH] AArch64: Add ACLE MOPS support

Hi Richard, > I think this should be in a push_options/pop_options block, as for other > intrinsics that require certain features. But then the intrinsic would always be defined, which is contrary to what the ACLE spec demands - it would not give a compilation error at the callsite but give assem

Re: [PATCH] AArch64: Add ACLE MOPS support

Hi Wilco, On Fri, May 31, 2024 at 6:38 PM Wilco Dijkstra wrote: > Hi Richard, > > > I think this should be in a push_options/pop_options block, as for other > > intrinsics that require certain features. > > But then the intrinsic would always be defined, which is contrary to what > the > ACLE sp

Re: [PATCH] AArch64: Add ACLE MOPS support

Wilco Dijkstra writes: > Hi Richard, > >> I think this should be in a push_options/pop_options block, as for other >> intrinsics that require certain features. > > But then the intrinsic would always be defined, which is contrary to what the > ACLE spec demands - it would not give a compilation er

Re: [Patch, rs6000, aarch64, middle-end] Add implementation for different targets for pair mem fusion

Hello Richard: On 31/05/24 8:08 pm, Richard Sandiford wrote: > Ajit Agarwal writes: >> On 31/05/24 3:23 pm, Richard Sandiford wrote: >>> Ajit Agarwal writes: Hello All: Common infrastructure using generic code for pair mem fusion of different targets. rs6000 target

Re: [Patch, aarch64, middle-end\ v4: Move pair_fusion pass from aarch64 to middle-end

Marc Poulhiès writes: > Hello, > > I can't bootstrap using gcc 5.5 since this change. It fails with: > > .../gcc/pair-fusion.cc: In member function ‘bool > pair_fusion_bb_info::fuse_pair(bool, unsigned int, int, rtl_ssa::insn_info*, > rtl_ssa::in > sn_info*, base_cand&, const rtl_ssa::insn_range

Re: [PATCH] [libstdc++] add _GLIBCXX_CLANG to workaround predefined __clang__

On May 31, 2024, Matthias Kretz wrote: > So __clang__ is turning into the next __GNUC__ ;) Yeah :-( > So passing -D__clang__=17 -D_GLIBCXX_CLANG=1 is possible? Should it be? I thought setting them independently could give us some testing flexibility, thought it's not for the faint of heart ;-)

[PATCH v2] [libstdc++] add _GLIBCXX_CLANG to workaround predefined __clang__

On May 31, 2024, Alexandre Oliva wrote: >> So either don't change this line at all, or just do a simple >> s/__clang__/_GLIBCXX_CLANG/ > If c++config can be counted on, I'd be happy to do that, but I couldn't > tell that it could. Here's what I've retested on x86_64-linux-gnu and, slightly adju

Re: [PATCH v6 1/8] Improve must tail in RTL backend

> I think the ultimate knowledge if a call can or cannot be implemented as > tail-call lies within calls.cc/expand_call: It is inherently > target and ABI specific how arguments and returns are layed out, how the > stack frame is generated, if arguments are or aren't removed by callers > or cal

MAINTAINERS: Add myself to Write After Approval and DCO

ChangeLog: * MAINTAINERS: Add myself to Write After Approval and DCO. Signed-off-by: Pengxuan Zheng --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e2870eef2ef..6444e6ea2f1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -743,6 +743,7

RE: [PATCH] aarch64: testsuite: Explicitly add -mlittle-endian to vget_low_2.c

> > Pengxuan Zheng writes: > > > vget_low_2.c is a test case for little-endian, but we missed the > > > -mlittle-endian flag in r15-697-ga2e4fe5a53cf75. > > > > > > gcc/testsuite/ChangeLog: > > > > > > * gcc.target/aarch64/vget_low_2.c: Add -mlittle-endian. > > > > Ok, thanks. > > > > If you'd l

[PATCH] check_GNU_style: Use raw strings.

Hi, this silences some warnings when using check_GNU_style. I didn't expect this to have any bootstrap or regtest impact but I still ran it on x86 - no change. Regards Robin contrib/ChangeLog: * check_GNU_style_lib.py: Use raw strings for regexps. --- contrib/check_GNU_style_lib.py |

Re: [PATCH v2] c++/modules: Fix revealing with using-decls [PR114867]

On 5/31/24 11:57, Nathaniel Shead wrote: On Tue, May 28, 2024 at 02:57:09PM -0400, Jason Merrill wrote: What if we're revealing without exporting? That is, a using-declaration in module purview that isn't exported? Such a declaration should still prevent discarding, which is my understanding o

Re: [PATCH] Fix PR c++/109958: ICE taking the address of bound static member function brought into derived class by using-declaration

On 5/31/24 09:58, Simon Martin wrote: From: Simon Martin We currently ICE upon the following because we don't properly handle the overload created for B::f through the using statement. === cut here === struct B { static int f(); }; struct D : B { using B::f; }; void f(D d) { &d.f; } === cut he

Re: [PATCH] Fix PR c++/111106: missing ; causes internal compiler error

On 5/30/24 07:31, Simon Martin wrote: We currently fail upon the following because an assert in dependent_type_p fails for f's parameter === cut here === consteval int id (int i) { return i; } constexpr int f (auto i) requires requires { id (i) } { return i; } void g () { f (42); } === cut here

Re: [PATCH] c-family: Introduce the -Winvalid-noreturn flag from clang with extra tuneability

On 5/29/24 09:58, Julian Waters wrote: Currently, gcc warns about noreturn marked functions that return both explicitly and implicitly, with no way to turn this warning off. clang does have an option for these classes of warnings, -Winvalid-noreturn. However, we can do better. Instead of just

Re: [RFC][PATCH] PR tree-optimization/109071 - -Warray-bounds false positive warnings due to code duplication from jump threading

> On May 23, 2024, at 07:46, Richard Biener wrote: > > On Wed, May 22, 2024 at 8:53 PM Qing Zhao wrote: >> >> >> >>> On May 22, 2024, at 03:38, Richard Biener >>> wrote: >>> >>> On Tue, May 21, 2024 at 11:36 PM David Malcolm wrote: On Tue, 2024-05-21 at 15:13 +, Qing Zhao

Re: [PATCH 1/2] xtensa: Simplify several MD templates

On Fri, May 31, 2024 at 07:23:13PM +0900, Takayuki 'January June' Suwa wrote: > No functional changes. > > gcc/ChangeLog: > > * config/xtensa/predicates.md > (subreg_HQI_lowpart_operator, xtensa_sminmax_operator): > New operator predicates. > * config/xtensa/xtensa-protos.

Re: [PATCH 2/2] xtensa: Prepend "(use A0_REG)" to sibling call CALL_INSN_FUNCTION_USAGE instead of emitting it as insn at the end of epilogue

On Fri, May 31, 2024 at 07:24:48PM +0900, Takayuki 'January June' Suwa wrote: > No functional changes. > > gcc/ChangeLog: > > * config/xtensa/xtensa-protos.h (xtensa_expand_call): > Add the third argument as boolean. > (xtensa_expand_epilogue): Remove the first argument. >

Re: [PATCH 2/6] vect: Split out partial vect checking for reduction into a function

Ok. Updated as the comments. Thanks, Feng From: Richard Biener Sent: Friday, May 31, 2024 3:29 PM To: Feng Xue OS Cc: Tamar Christina; gcc-patches@gcc.gnu.org Subject: Re: [PATCH 2/6] vect: Split out partial vect checking for reduction into a function O

Re: [PATCH] RISC-V: Add min/max patterns for ifcvt.

On 5/31/24 9:07 AM, Robin Dapp wrote: Hi, ifcvt likes to emit (set (if_then_else) (ge (reg 1) (reg2)) (reg 1) (reg 2)) which can be recognized as min/max patterns in the backend. This patch adds such patterns and the respective iterators as well as a test. This depends on

Re: [PATCH] ifcvt: Clarify if_info.original_cost.

On 5/31/24 9:03 AM, Robin Dapp wrote: Hi, before noce_find_if_block processes a block it sets up an if_info structure that holds the original costs. At that point the costs of the then/else blocks have not been added so we only care about the "if" cost. The code originally used BRANCH_COST

Re: [PING] [PATCH] RISC-V: Add Zfbfmin extension

On 5/30/24 5:38 AM, Xiao Zeng wrote: 1 In the previous patch, the libcall for BF16 was implemented: 2 Riscv provides Zfbfmin extension, which completes the "Scalar BF16 Converts":

Re: [PATCH 5/5][v3] RISC-V: Avoid inserting after a GIMPLE_COND with SLP and early break

On 5/31/24 7:44 AM, Richard Biener wrote: When vectorizing an early break loop with LENs (do we miss some check here to disallow this?) we can end up deciding to insert stmts after a GIMPLE_COND when doing SLP scheduling and trying to be conservative with placing of stmts only dependent on the

Re: [RFC/RFA] [PATCH 02/12] Add built-ins and tests for bit-forward and bit-reversed CRCs

On 5/28/24 12:44 AM, Richard Biener wrote: On Mon, May 27, 2024 at 5:16 PM Jeff Law wrote: On 5/27/24 12:38 AM, Richard Biener wrote: On Fri, May 24, 2024 at 10:44 AM Mariam Arutunian wrote: This patch introduces new built-in functions to GCC for computing bit-forward and bit-reverse

Re: RISC-V: Fix round_32.c test on RV32

On 5/27/24 4:17 PM, Jivan Hakobyan wrote: Ya, makes sense -- I guess the current values aren't that exciting for execution, but we could just add some more interesting ones... During the development of the patch, I have an issue with large numbers (2e34, -2e34). They are used in gfor

Re: [PATCH 5/5][v3] RISC-V: Avoid inserting after a GIMPLE_COND with SLP and early break

On Fri, May 31, 2024 at 9:41 PM Jeff Law wrote: > > On 5/31/24 7:44 AM, Richard Biener wrote: > > When vectorizing an early break loop with LENs (do we miss some > > check here to disallow this?) we can end up deciding to insert > > stmts after a GIMPLE_COND when doing SLP scheduling and trying >