Richard Sandiford rdsandif...@googlemail.com writes:
Robert Suchanek robert.sucha...@imgtec.com writes:
@@ -771,7 +771,8 @@ struct mips_cpu_info {
/* Infer a -mnan=2008 setting from a -mips argument. */
#define MIPS_ISA_NAN2008_SPEC \
- %{mnan*:;mips32r6|mips64r6:-mnan=2008}
+
Robert Suchanek robert.sucha...@imgtec.com writes:
Hi Robert,
The patch is OK, but will you please name the test something other than the
date?
OK. I'll change it to interrupt_handler-5.c, add a comment and commit after
approval for the new interrupt handler options.
I believe this
Andrew Bennett andrew.benn...@imgtec.com writes:
I have noticed that in the mips.exp dg-option handling code the isa and
arch_test_option_p variables are not updated after the pre-arch to arch
dependency handling. This means that if this code changes the
architecture the post-arch dependency
2015-07-09 Steve Ellcey sell...@imgtec.com
* config/mips/mti-linux.h (MIPS_SYSVERSION_SPEC): Update
to handle mips[32|64]r3 and mips[32|64]r5.
OK, thanks.
Matthew
Andrew Bennett andrew.benn...@imgtec.com writes:
The stack-1.c testcase fails when being compiled for micromips with the
-O0 optimization level. The reason is the testcase is expecting the
following sequence at the end of the function:
addiu $sp,$sp,16
jrc $31
But
Bernd Edlinger bernd.edlin...@hotmail.de writes:
Hi,brbrthis patch fixes a regression that was triggered by commit
r225260.brSee
pr66747 for details.brbrIs it OK for
trunk?brbrbrThanksbrBernd.br
Thanks Bernd. I was just reviewing this PR. I think it will probably be safer
to move
the fix
Bernd Edlinger bernd.edlin...@hotmail.de writes:
On Sat, 4 Jul 2015 09:04:41, Richard Sandiford wrote:
The final return here would also mishandle SEQUENCE PATTERNs.
The idea was that this function would only see real instructions,
so I think instead the FOR_EACH_SUBINSN should be here:
Maciej W. Rozycki ma...@linux-mips.org writes:
Richard, please have a look at my question below in a reference to your
previous statement.
On Thu, 18 Jun 2015, Steve Ellcey wrote:
OK, I checked in the prequel patch and here is a new copy of the
original patch based off of that (and with
Steve Ellcey steve.ell...@imgtec.com writes:
On Wed, 2015-06-17 at 19:44 +0100, Richard Sandiford wrote:
FWIW, to be specific, I think we're talking about every check except
the last two in mips.md:
and the one mips-ps-3d.md:
In particular, the two checks in mips.c should go.
Steve Ellcey steve.ell...@imgtec.com writes:
As follow-up to this patch, I forgot to include a testsuite patch to two
mips specific tests that fail with the new layout. These tests are
loongson specific and have includes of system headers in them. The way
mips.exp in
Hi Steve,
Having worked on the new layout I of course am happy with it. I think it
makes the cross compiled sysroots much easier to use for installing
on a target as well as making the library paths match for cross compiled
and native. A couple of minor things...
diff --git
Robert Suchanek robert.sucha...@imgtec.com writes:
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index c3755f5..976f844 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -19415,6 +19415,21 @@ mips_lra_p (void)
{
return mips_lra_flag;
}
+
+/*
Hi Robert,
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index
c3755f5..3c8ac30 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -19415,6 +19415,17 @@ mips_lra_p (void) {
return mips_lra_flag;
}
+
+/* Implement
The change for MIPS looks fine by visual inspection and I've built both
a default pie and default no-pie compiler. The default pie won't build
glibc but I am pretty sure it is not down to this patch. I haven't had
time to look into why it won't build though, something related to
selecting the CRT
We could add -mflip-micromips complementing -mflip-mips16 and use
that for testing too. Chances are it'd reveal further issues.
Looking at how
-mflip-mips16 has been implemented it does not appear to me adding
-mflip-micromips would be a lot of effort.
I'm in favour of adding such a
This patch fixes an internal compiler error when micromips/nomicromips
attributes are used.
The problem here was that the cached boolean attributes for the current
target did not agree with the uncached attributes throwing an assertion
error.
It appears that saving and restoring the
Hi Sameera,
Sameera Deshpande sameera.deshpa...@imgtec.com writes:
Changelog:
gcc/
* config/mips/mips.md (JOIN_MODE): New mode iterator.
(join2_load_StoreJOIN_MODE:mode): New pattern.
(join2_loadhi): Likewise.
(define_peehole2): Add peephole2 patterns to
Jeff Law l...@redhat.com writes:
On 05/11/2015 01:46 PM, Jeff Law wrote:
On 05/11/2015 01:44 PM, Steve Ellcey wrote:
On Mon, 2015-05-11 at 13:22 -0500, Segher Boessenkool wrote:
Hi Steve,
On Mon, May 11, 2015 at 10:50:02AM -0700, Steve Ellcey wrote:
This patch broke a number of MIPS
Segher Boessenkool seg...@kernel.crashing.org writes:
On Mon, May 11, 2015 at 08:16:41PM +, Matthew Fortune wrote:
Does this patch effectively change the canonicalization rules? The
following Still exists in md.texi:
@item
Within address computations (i.e., inside @code{mem
H.J. Lu hjl.to...@gmail.com writes:
On Mon, Apr 27, 2015 at 7:40 AM, Szabolcs Nagy szabolcs.n...@arm.com
wrote:
On 21/04/15 15:59, Matthew Fortune wrote:
Rich Felker dal...@libc.org writes:
On Tue, Apr 21, 2015 at 01:58:02PM +, Matthew Fortune wrote:
There does however appear
Szabolcs Nagy szabolcs.n...@arm.com writes:
On 08/05/15 15:25, Matthew Fortune wrote:
H.J. Lu hjl.to...@gmail.com writes:
On Mon, Apr 27, 2015 at 7:40 AM, Szabolcs Nagy
szabolcs.n...@arm.com
wrote:
On 21/04/15 15:59, Matthew Fortune wrote:
Rich Felker dal...@libc.org writes
Jeff Law l...@redhat.com writes:
On 05/08/2015 10:50 AM, Joseph Myers wrote:
Note that however the dynamic linker does properly need to save and
restore call-clobbered registers used for argument passing (because of
IFUNCs, user-provided malloc, audit hooks etc. that might affect them
Hi Matthew,
2015-04-21 15:24 GMT+01:00 Jiong Wang jiong.w...@arm.com:
2015-04-21 Jiong Wang jiong.w...@arm.com
gcc/
* loop-invariant.c (find_defs): Enable DF_DU_CHAIN build.
(vfp_const_iv): New hash table.
(expensive_addr_check_p): New boolean.
Steve Ellcey sell...@imgtec.com writes:
This patch changes the default processor for mips4 from the r8000 to
the
r1. There are several reasons for this change, the main one
being the difference in the r8000 madd instruction and the rest of the
mips4
family. The r8000 has a fused madd
2015-04-23 Steve Ellcey sell...@imgtec.com
* config/mips/mips.md: (*madd4mode) Remove accum_in attribute.
(*madd3mode): Ditto.
(*msub4mode): Ditto.
(*msub3mode): Ditto.
(*nmadd4mode): Ditto.
(*nmadd3mode): Ditto.
(*nmadd4mode_fastmath): Ditto.
Rich Felker dal...@libc.org writes:
On Tue, Apr 21, 2015 at 01:58:02PM +, Matthew Fortune wrote:
Szabolcs Nagy szabolcs.n...@arm.com writes:
Set up dynamic linker name for mips.
gcc/Changelog:
2015-04-16 Gregor Richards gregor.richa...@uwaterloo.ca
* config/mips
Szabolcs Nagy szabolcs.n...@arm.com writes:
Set up dynamic linker name for mips.
gcc/Changelog:
2015-04-16 Gregor Richards gregor.richa...@uwaterloo.ca
* config/mips/linux.h (MUSL_DYNAMIC_LINKER): Define.
I understand that mips musl is o32 only currently is that correct?
There
Sameera Deshpande sameera.deshpa...@imgtec.com writes:
Gentle reminder!
Thanks Sameera. Just a couple of comments inline below and a question
for Catherine at the end.
- Thanks and regards,
Sameera D.
On Monday 30 March 2015 04:58 PM, sameera wrote:
Hi!
Sorry for delay in sending
Gerald Pfeifer ger...@pfeifer.com writes:
On Thu, 5 Feb 2015, Matthew Fortune wrote:
Thanks Catherine. Good call to remove the markup while reviewing. I've
done one more pass on this to have the same phrasing used where
similar points are being made. I also added a comment about link
Steve Ellcey steve.ell...@imgtec.com writes:
On Mon, 2015-03-02 at 15:54 -0800, Matthew Fortune wrote:
Thanks for looking through and catching this.
I had conflicting thoughts on whether the new condition should
reference both !ISA_HAS_FP_CONDMOVE || ISA_HAS_SEL but if we take
Thanks for looking through and catching this.
I had conflicting thoughts on whether the new condition should
reference both !ISA_HAS_FP_CONDMOVE || ISA_HAS_SEL but if we take it
that FP_CONDMOVE is the only way to get an integer conditional
move based on an FP condition then that's fine.
Jakub Jelinek ja...@redhat.com writes:
On Tue, Feb 17, 2015 at 08:10:37PM +, Matthew Fortune wrote:
Ping. Please could you advise if I can approve MIPS changes to release
branches of if I need you/someone else to do so?
Any maintainer or reviewer can approve changes to the release
Ping. Please could you advise if I can approve MIPS changes to release branches
of if I need you/someone else to do so?
Thanks,
Matthew
-Original Message-
From: Matthew Fortune
Sent: 07 February 2015 08:22
To: ja...@redhat.com
Cc: Moore, Catherine (catherine_mo...@mentor.com); 'gcc
Hi Jakub,
I haven't done a backport to a release branch before. Could you tell me
who needs to approve this change, it only affects MIPS?
Thanks,
Matthew
-Original Message-
From: Matthew Fortune
Sent: 26 January 2015 16:30
To: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)
Cc
Maciej W. Rozycki ma...@linux-mips.org writes:
On Thu, 5 Feb 2015, Matthew Fortune wrote:
I'm OK with this change but I'd like Catherine to comment before
committing.
It seems a shame to duplicate the block of code but it is probably just
as
ugly to define a macro for the la/dla
Mike Stump mikest...@comcast.net writes:
On Feb 6, 2015, at 4:23 AM, Maciej W. Rozycki ma...@linux-mips.org
wrote:
This consideration made me realise I've had a patch outstanding for
some
10 years to convert all the `BAL x' instructions there to `BLTZAL $0,
x'.
This has always been a
[mailto:petar.jovano...@rt-rk.com]
Sent: 05 February 2015 19:28
To: gcc-patches@gcc.gnu.org; 'Maciej W. Rozycki'; Matthew Fortune
Subject: [PATCH v2][MIPS] fix CRT_CALL_STATIC_FUNCTION macro
v2:
- add ChangeLog entry
- use DLA instead of LA for n64
PTAL. Thanks.
Regards,
Petar
---
ChangeLog
the same phrasing used where similar
points are being made. I also added a comment about link compatibility
for FP64. Updated text is at the end.
Thanks,
Matthew
Thanks,
Catherine
-Original Message-
From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
Sent: Wednesday
Andrew Pinski pins...@gmail.com writes:
On Wed, Feb 4, 2015 at 8:46 AM, Matthew Fortune
matthew.fort...@imgtec.com wrote:
Hi Catherine,
I've made a first pass at writing up the MIPS changes for GCC 5.0.
Could you take a read and see what needs some more work?
One comment below
Hi Catherine,
I've made a first pass at writing up the MIPS changes for GCC 5.0.
Could you take a read and see what needs some more work?
Thanks,
Matthew
Index: htdocs/gcc-5/changes.html
Richard Sandiford rdsandif...@googlemail.com writes:
Matthew Fortune matthew.fort...@imgtec.com writes:
2015-01-23 Robert Suchanek robert.sucha...@imgtec.com
* config/mips/mips.c (mips_hard_regno_mode_ok_p): Prohibit
accumulators
for all vector modes.
This seems like
This is a minimal backport of features added to GCC 5 to enable use
of binutils 2.25 with GCC 4.9 for MIPS soft-float builds. Further
details in the PR:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64569
The commits which are being backported are listed below (the last
one is posted but
Richard Sandiford rdsandif...@googlemail.com writes:
Jeff Law l...@redhat.com writes:
On 01/15/15 03:13, Robert Suchanek wrote:
Robert, can you look at reload.c::reload_inner_reg_of_subreg and
verify that the comment just before its return statement is
effectively the situation you're in.
2015-01-23 Robert Suchanek robert.sucha...@imgtec.com
* config/mips/mips.c (mips_hard_regno_mode_ok_p): Prohibit
accumulators
for all vector modes.
This seems like a genuine bug and although it can only be triggered by
loongson or paired-single support it probably qualifies
This is a follow-up to a change [1] in glibc. It fixes the issue [2]
when jal can not reach a target in different region.
It has been tested with DejaGnu for mips32/o32, mips64/n32 and
mips64/n64.
Let me know what you think.
So to confirm, the issue is non-pic crt calling an init routine
I committed the following patch to wwwdocs having received approval
from Gerald.
Thanks,
Matthew
Index: htdocs/index.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/index.html,v
retrieving revision 1.953
diff -r1.953 index.html
54a55,59
Moore, Catherine catherine_mo...@mentor.com writes:
-Original Message-
From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
Sent: Monday, January 19, 2015 5:54 PM
To: Moore, Catherine
Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)
Subject: RE: [PATCH,MIPS] Only
Hi Catherine,
The new behaviour of the GCC driver passing floating point options like
-msoft-float to the assembler is essential for the new o32 ABI
extensions but is a change in behaviour. In particular GCC 5 used with
binutils 2.24 would require a user to fix any hand-crafted code that
Jeff Law l...@redhat.com writes:
On 01/15/15 03:13, Robert Suchanek wrote:
Robert, can you look at reload.c::reload_inner_reg_of_subreg and
verify that the comment just before its return statement is
effectively the situation you're in.
There are certainly cases where a SUBREG needs to
OK. The MIPS and Sparc ports are probably going to hit this the
hardest. So you've got a vested interest in dealing with any fallout
:-)
jeff
That's fine. The MIPS port has been widely tested and I cross tested it
on sparc-linux-gnu target so hopefully there won't any fallout.
On 2015.01.16 at 14:56 +0100, Markus Trippelsdorf wrote:
On 2015.01.14 at 17:10 +, Robert Suchanek wrote:
+ u = v;
+ r = b | a[4];
+ return e;
+
There is a missing } in the testcase.
Fixed in r219740 as obvious.
Thanks Markus.
Sorry about that, I must have broken it
/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6b73d31..1285633 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2015-01-15 Andrew Bennett andrew.benn...@imgtec.com
+ Matthew Fortune matthew.fort...@imgtec.com
+
+ * gcc.target/mips/call-saved
@@ -1,3 +1,9 @@
+2015-01-15 Matthew Fortune matthew.fort...@imgtec.com
+
+ * gcc.target/mips/mips.exp (mips-dg-options): -mips3d requires
+ -mno-micromips. MIPS32R1 and below require -mno-micromips.
+ -march=loongson* and -march=octeon* require -mno-micromips.
+
2015-01-15
Moore, Catherine catherine_mo...@mentor.com writes
Hi Matthew,
-Original Message-
From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
Sent: Tuesday, January 06, 2015 7:43 AM
To: Moore, Catherine
Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)
Subject: [MIPS
Richard Sandiford rdsandif...@googlemail.com writes:
Maciej W. Rozycki ma...@linux-mips.org writes:
On Wed, 14 Jan 2015, Richard Sandiford wrote:
I think we just have to accept that there are so many possible
combinations that we can't test everything that's potentially
relevant.
I think
Moore, Catherine catherine_mo...@mentor.com writes:
-Original Message-
From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
Sent: Wednesday, January 14, 2015 2:54 PM
To: Moore, Catherine
Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)
Subject: RE: [MIPS] Update
Moore, Catherine catherine_mo...@mentor.com writes:
gcc/
* config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Only infer an ISA
level from an ARCH; do not inject the default.
(MIPS_DEFAULT_ISA_LEVEL_SPEC): New macro split out from
MIPS_ISA_LEVEL_SPEC.
Richard Sandiford rdsandif...@googlemail.com writes:
Maciej W. Rozycki ma...@linux-mips.org writes:
On Tue, 13 Jan 2015, Andrew Bennett wrote:
The call-saved-{4-6}.c tests in the mips testsuite fail for
micromips.
The reason is
that micromips uses the swm and lwm instructions to
This patch adds support for the R6 [D]LSA instructions. The support
has been structured to allow MSA (when implemented) to turn on the
same instructions as they are also added by the MSA ASE.
I have continued to use the idea of 'ghost' options in the testsuite to
indicate what features are
The new behaviour of the GCC driver passing floating point options
like -msoft-float to the assembler is essential for the new o32 ABI
extensions but is a change in behaviour. In particular GCC 5 used with
binutils 2.24 would require a user to fix any hand-crafted code that
made use of
This is a minimal backport of features added to GCC 5 to enable use
of binutils 2.25 with GCC 4.9 for MIPS soft-float builds. Further
details in the PR:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64569
The commits which are being backported are listed below (the last
one is posted but not
I found while checking ToT test status...
define_insn implicitly wraps the pattern in a parallel if there are
multiple instructions. Several MIPS patterns have an explicit parallel
which is mostly handled correctly but the code in 'gen_insn' does not
manage to locate the clobbers inside an
Richard Sandiford rdsandif...@googlemail.com writes:
Matthew Fortune matthew.fort...@imgtec.com writes:
Richard Sandiford rdsandif...@googlemail.com writes:
Jeff Law l...@redhat.com writes:
On 01/09/15 04:32, Robert Suchanek wrote:
Hi Steven/Vladimir,
It's hard to say what
Richard Sandiford rdsandif...@googlemail.com writes:
Jeff Law l...@redhat.com writes:
On 01/09/15 04:32, Robert Suchanek wrote:
Hi Steven/Vladimir,
It's hard to say what the correct fix should be, but it sounds like
the address you get after the substitutions should be simplified
Robert Suchanek robert.sucha...@imgtec.com writes:
gcc/
* simplify-rtx.c (simplify_replace_fn_rtx): Simplify (lo_sum (high x)
(const (plus x offset))) to (const (plus x offset)).
The fix appears valid to me. Just some comments on the test case.
Update the ZC constraint for MIPSR6 to allow it to be used as the memory
operand for implementations of atomic operations. Also switch the internal
implementation of atomic operations to use ZC instead of ZR.
This fix accurately describes the memory constraints for the LL and SC
instructions.
The R6 patch introduced MIPS_ISA_LEVEL_SPEC into DRIVER_SELF_SPECS
for all configurations. One part of MIPS_ISA_LEVEL_SPEC is however
incompatible with those configurations which infer an ISA from an
ABI without specifically setting the default ISAs using
--with-arch-[32|64].
I.e. a generic
2014-12-24 Steve Ellcey sell...@mips.com
* config/mips/t-mti-linux (MULTILIB_EXCEPTIONS): Add exceptions
for mips32[r1] and mips64[r1] with -mnan=2008.
This is OK, but I think it may be best to fix t-mti-elf at the same
time even though it is probably building but with
Okay with those changes.
Committed as r218973
Thanks,
Matthew
gcc/
* config.gcc: Support mips*-img-linux* and mips*-img-elf*.
* config/mips/mti-linux.h: Support mips32r6 as being the default
arch.
* config/mips/t-img-elf: New.
* config/mips/t-img-linux: New.
This patch is OK to commit.
Committed as r218975
Thanks,
Matthew
Moore, Catherine catherine_mo...@mentor.com writes:
Hi Matthew,
-Original Message-
From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
Sent: Friday, November 14, 2014 6:07 PM
Overall, this patch looks really good. It took me a while to get
through it, but I only have
location in the
gcc/ChangeLog one?
Thanks,
Matthew
-Original Message-
From: Prachi Godbole
Sent: 26 November 2014 08:40
To: Matthew Fortune; gcc-patches@gcc.gnu.org
Subject: RE: [PATCH][MIPS] Fix P5600 memory cost
Committed with ChangeLog entry fixes.
Prachi
-Original
Richard Sandiford richard.sandif...@arm.com writes:
Maciej W. Rozycki ma...@codesourcery.com writes:
2014-11-17 Maciej W. Rozycki ma...@codesourcery.com
gcc/
* gcc/config/mips/mips.md (*jump_absolute): Use a branch when in
range, a jump otherwise.
Maciej
Richard Biener richard.guent...@gmail.com writes:
On Thu, Dec 4, 2014 at 8:59 AM, Benda Xu hero...@gentoo.org wrote:
Hello,
libc could be installed in a directory prefix. This patch provides a
way to specify such a prefix for gcc at configuration time.
I have only tested the patch
Changelog:
2014-12-03 Prachi Godbole prachi.godb...@imgtec.com
* config/mips/p5600.md (define_automaton, define_cpu_unit): Replace
p5600_agen_pipe and p5600_alu_pipe with p5600_agen_alq_pipe.
(p5600_int_arith_1, p5600_int_arith_2, p5600_int_arith_4): Change
Hi Prachi,
OK with fixes to the changelog entry:
latency not latency. Remember to tab in the changelog entry and split the
line as it will exceed 80 chars. Also two spaces between the date/name and
name/email. E.g.
2014-11-05 Prachi Godbole prachi.godb...@imgtec.com
*
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b577824..7b9b365 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2014-11-25 Matthew Fortune matthew.fort...@imgtec.com
Richard Biener richard.guent...@gmail.com writes:
On Sun, Nov 23, 2014 at 10:15 AM, Matthew Fortune
matthew.fort...@imgtec.com wrote:
Hi,
I have had to use this patch several times when performing cross testing
but I'm not sure if it is the right fix. The MIPS target testsuite runs
all
Hi,
I have had to use this patch several times when performing cross testing
but I'm not sure if it is the right fix. The MIPS target testsuite runs
all tests regardless of the current compiler configuration and downgrades
run tests to link tests and then to assembly tests depending on what
Andrew Pinski pins...@gmail.com writes:
On Wed, Nov 12, 2014 at 2:56 PM, Matthew Fortune
matthew.fort...@imgtec.com wrote:
Moore, Catherine catherine_mo...@mentor.com writes:
The patch looks good. Please fix up these couple of nits prior to
committing.
OK, thanks
2014 +0100
Add MIPS .module directive
commit 351cdf24d223290b15fa991e5052ec9e9bd1e284
Author: Matthew Fortune matthew.fort...@imgtec.com
Date: Tue Jul 29 11:27:59 2014 +0100
[MIPS] Implement O32 FPXX, FP64 and FP64A ABI extensions
I have updated the configure check for .module to check
Matthew Fortune matthew.fort...@imgtec.com writes:
(I'm not sure if I need approval from someone else for MIPS specific
top level 'configure' changes. I'm cautiously assuming I do for now.)
FWIW, MIPS maintainership covers all MIPS-specific code and documentation
(except for externally
Ok to commit?
gcc/
* config/mips/mips.c (mips_process_sync_loop): Place a nop in the
delay slot of the branch likely instruction.
With an updated ChangeLog to account for the changes in the callers, OK.
Matthew
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index
02268f3..368c6f0 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -12997,7 +12997,12 @@ mips_process_sync_loop (rtx_insn *insn, rtx
*operands)
This will sometimes be a delayed branch; see the write
The atomic-compare-exchange-3.c and atomic-op-3.c tests are failing when
using the -mfix-r1 option. This is due to the fact that the delay
slot of the branch instruction that checks if the atomic operation was
not successful can be filled with an operation that returns the output
result.
Maciej W. Rozycki ma...@codesourcery.com writes:
On Mon, 17 Nov 2014, Matthew Fortune wrote:
gcc/
* gcc/config/mips/mips.md (*jump_absolute): Use a branch when in
range, a jump otherwise.
OK.
I only got my head around this code last week otherwise I wouldn't
have known
-Original Message-
From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
Sent: Tuesday, November 18, 2014 12:22 PM
To: Rozycki, Maciej
Cc: gcc-patches@gcc.gnu.org; Moore, Catherine; Eric Christopher
Subject: RE: [PATCH] MIPS/GCC: Unconditional jump generation bug fix
From: Maciej W. Rozycki [mailto:ma...@codesourcery.com]
On Tue, 18 Nov 2014, Andrew Bennett wrote:
Produces (for the atomic operation):
.setnoat
sync
1:
ll $3,0($5)
and $1,$3,$4
bne $1,$7,2f
and
OK to apply?
2014-11-17 Maciej W. Rozycki ma...@codesourcery.com
gcc/
* gcc/config/mips/mips.md (*jump_absolute): Use a branch when in
range, a jump otherwise.
OK.
I only got my head around this code last week otherwise I wouldn't have
known whether this was
Eric Botcazou ebotca...@adacore.com writes:
IIRC, fill_eager and its related friends are all speculative in some
way
and aren't those precisely the ones that are causing us problems.
Also
note we have backends working around this stuff in fairly blunt ways:
I'd say that the PA back-end
This patch adds new triplets: mips*-img-linux* and mips*-img-elf*
The purpose of these triplets is essentially to provide a clear separation
between tools which support mips32r5 and below and tools which support
mips32r6 and above.
Thanks,
Matthew
/
* configure.ac: Add mips-img-elf
Moore, Catherine catherine_mo...@mentor.com writes:
The patch looks good. Please fix up these couple of nits prior to
committing.
OK, thanks for the second read through. One further amendment below, I'll
aim to commit later today.
Index: gcc/config/mips/mips.c
(for MIPS) https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01481.html,
although I have not been able to test this as there doesn't seem to be
any working MIPS/Loongson hardware in the Compile Farm;
I will post a patch to remove vec_shl and only support vec_shr for
little endian. This is on the
Moore, Catherine catherine_mo...@mentor.com writes:
The patch looks good. Please fix up these couple of nits prior to
committing.
OK, thanks for the second read through. One further amendment below,
I'll aim to commit later today.
Yes, that's better.
Committed as r217446
Sorry to follow myself up. I realised that the new configure options should
be documented in install.texi. The only change from V3 is the
doc/install.texi change.
The MIPS64 tests have completed without regression.
Regards,
Matthew
gcc/
* common/config/mips/mips-common.c
The patch below fixes the memory cost for P5600.
ChangeLog:
2014-11-05 Prachi Godbole prachi.godb...@imgtec.com
* config/mips/mips.c (mips_rtx_cost_data): Fix memory_letency cost for
p5600.
Please follow these instructions to add yourself to MAINTAINERS in the
write-after-approval
Hi Catherine,
The full patch is attached and the delta from v2 is inline below.
Testing (O32):
MIPS I - FP32, MIPS II - FP32, MIPS II - FPXX
MIPS32 - FP32, MIPS32 - FPXX, MIPS32 - FPXX ODDSPREG,
MIPS32R2 - FP32, MIPS32R2 - FPXX, MIPS32R2 - FPXX ODDSPREG,
MIPS32R2 - FP64, MIPS32R2 - FP64A
One
This patch fixes all failures in the MIPS target tests which were failing
because of
-Wimplicit-int or -Wimplicit-function-declaration.
+2014-11-05 Matthew Fortune matthew.fort...@imgtec.com
+
+ * gcc.target/mips/asm-1.c (bar): Add prototype.
+ * gcc.target/mips/call-1.c (f, h
Andrew Pinski pins...@gmail.com writes:
On Thu, Oct 30, 2014 at 11:30 PM, Zhenqiang Chen zhenqiang.c...@arm.com
wrote:
Thank you all for the comments. Patch is updated.
Bootstrap and no make check regression on X86-64.
No make check regression with Cortex-M0 qemu.
No performance
Steve Ellcey sell...@imgtec.com writes:
Here is another MIPS configuration patch, this one allows the mips
configuration to handle the --with-endian, --with-arch, and --with-abi
configure options. Basically instead of having targets set
MIPS_ABI_DEFAULT
and MIPS_ISA_DEFAULT directly in
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