Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Sunday, March 31, 2024 8:54 AM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH] RISC-V: Fix one unused varable in riscv_subset_list::parse
LGTM
On Sat, Mar 30
Kindly ping for this ice.
Pan
-Original Message-
From: Li, Pan2
Sent: Saturday, March 23, 2024 1:45 PM
To: Jeff Law ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Wang, Yanzhang ; Liu, Hongtao
Subject: RE: [PATCH v2
Committed, thanks Juzhe and Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, April 11, 2024 10:50 AM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for the vector return arg in mode
switch
I was thinking we may guarded
: Thursday, April 11, 2024 7:52 PM
To: Li, Pan2 ; Kito Cheng ;
juzhe.zh...@rivai.ai
Cc: gcc-patches
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for the vector return arg in mode
switch
On 4/11/24 05:03, Li, Pan2 wrote:
> Committed, thanks Juzhe and Kito.
>
> Pan
Hi Pan,
this commi
Thanks Edwin, should be one silly mistake, will fix it ASAP.
Pan
-Original Message-
From: Edwin Lu
Sent: Friday, April 12, 2024 5:20 AM
To: Li, Pan2 ; Bernd Edlinger ;
Kito Cheng ; juzhe.zh...@rivai.ai
Cc: gcc-patches
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for the vector return
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, April 12, 2024 2:11 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Li, Pan2
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in
TARGET_FUNCTION_VALUE_REGNO_P
LGTM。
juzhe.zh
ssage-
From: Kito Cheng
Sent: Friday, April 12, 2024 4:56 PM
To: Li, Pan2
Cc: juzhe.zh...@rivai.ai; gcc-patches
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in
TARGET_FUNCTION_VALUE_REGNO_P
Does FP reg also need gurared with TARGET_HARD_FLOAT? could you try to
compile that case with
Message-
From: Li, Pan2
Sent: Friday, April 12, 2024 6:58 PM
To: Kito Cheng
Cc: juzhe.zh...@rivai.ai; gcc-patches
Subject: RE: [PATCH v1] RISC-V: Bugfix ICE non-vector in
TARGET_FUNCTION_VALUE_REGNO_P
Sure thing, the FP_RETURN only acts on ABI_xxx similar to below:
#define FP_RETURN
Kindly ping^ for this ice fix.
Pan
-Original Message-
From: Li, Pan2
Sent: Saturday, April 6, 2024 8:02 PM
To: Li, Pan2 ; Jeff Law ; Robin Dapp
; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Wang, Yanzhang ; Liu, Hongtao
Subject
Sure, will revert b3b2799b872 and then file the patch for the xfail tests.
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, April 19, 2024 10:54 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: Re: [PATCH v1] RI
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Saturday, April 20, 2024 9:20 AM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for wv insn register overlap
LGTM.
juzhe.zh
Committed, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Saturday, April 20, 2024 7:46 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: Re: [PATCH] RISC-V: Add xfail test case for wv insn highest
Committed, thanks Juzhe.
Pan
From: 钟居哲
Sent: Sunday, April 21, 2024 7:59 AM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; rdapp.gcc ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for incorrect overlap on v0
lgtm
juzhe.zh...@rivai.ai
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, April 22, 2024 11:49 AM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for widening register
overlap of vf4/vf8
LGTM
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, April 22, 2024 2:40 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for highest-number regno
ternary overlap
LGTM
Sure thing. Sorry for that Fortran is not fully tested for this change, will
take a look into it ASAP.
Pan
From: 钟居哲
Sent: Tuesday, April 23, 2024 6:06 AM
To: patrick ; Li, Pan2 ; gcc-patches
Cc: kito.cheng ; rdapp.gcc
Subject: Re: Re: [PATCH v1] RISC-V: Adjust overlap attr after revert
al Message-
From: Palmer Dabbelt
Sent: Tuesday, April 23, 2024 8:43 AM
To: juzhe.zh...@rivai.ai
Cc: Patrick O'Neill ; Li, Pan2 ; Robin
Dapp ; gcc-patches@gcc.gnu.org; Kito Cheng
Subject: Re: Re: [PATCH v1] RISC-V: Revert RVV wv instructions overlap and
xfail tests
On Mon, 22 Apr 2024 1
-Original Message-
From: Patrick O'Neill
Sent: Tuesday, April 23, 2024 8:32 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Adjust overlap attr after revert d3544cea63d
and e65aaf8efe1
This pat
ARGET="-O0 -g"
make -j $(nproc) all-gcc && make install-gcc
3. ../__RISC-V_INSTALL___RV64/bin/riscv64-unknown-elf-gcc
gcc/testsuite/gcc.dg/graphite/pr111878.c -O3 -fgraphite-identity
-fsave-optimization-record -march=rv64gcv -mabi=lp64d -c -S -o -
Pan
-Original Message
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Wednesday, April 24, 2024 2:46 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for highpart overlap of
vext.vf
LGTM
Request review as this revert patch contains some manually resolved conflict
changes.
Passed the rv64gcv fully regression test with isl build.
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, April 24, 2024 8:59 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, April 24, 2024 9:11 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; rdapp@gmail.com
Subject: Re: [PATCH v1] Revert "RISC-V: Support highpart register overlap for
vwcvt&q
in Dapp
Sent: Wednesday, April 24, 2024 10:12 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: Re: [PATCH v1] Revert "RISC-V: Support highpart register overlap for
vwcvt"
> (define_insn "@pred_vwsll_scalar
is true currently.
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, April 24, 2024 10:38 PM
To: Robin Dapp ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: RE: [PATCH v1] Revert "RISC-V: Support highpart register overlap for
vwcvt"
> Just n
Committed, thanks Kito and Juzhe.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, April 25, 2024 2:24 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches ; Robin
Dapp
Subject: Re: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
LGTM, thanks :)
On Thu, Apr 25
Committed, thanks Kito and Juzhe.
Pan
From: Kito Cheng
Sent: Thursday, April 25, 2024 11:19 AM
To: 钟居哲
Cc: Li, Pan2 ; gcc-patches ; Robin
Dapp
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for highpart register
overlap of vwcvt
LGTM
juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, April 25, 2024 5:27 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2 ; Kito.cheng
Subject: Re: [PATCH v1] RISC-V: Add test cases for insn does not satisfy its
constraints [PR114714]
LGTM. THANKS
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, December 18, 2023 3:37 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v2] RISC-V: Bugfix for the RVV const vector
OK. LGTM. It's an obvious fix and not easy to add the
Oh, I see. Thanks Jeff for suggestion, will refine the commit log in V2.
Pan
-Original Message-
From: Jeff Law
Sent: Wednesday, December 20, 2023 12:03 PM
To: juzhe.zh...@rivai.ai; Li, Pan2 ; gcc-patches
Cc: Wang, Yanzhang ; kito.cheng
Subject: Re: [PATCH v1] RISC-V: Bugfix for the
Committed, thanks all.
Pan
From: juzhe.zh...@rivai.ai
Sent: Wednesday, December 20, 2023 7:18 PM
To: demin.han ; gcc-patches
Cc: Li, Pan2
Subject: Re: Re: [PATCH] RISC-V: Fix calculation of max live vregs
I see. LGTM. Thanks for explanation.
I will ask Li Pan commit it for you.
Thanks
Thanks all for comments, will have a try for riscv_v and send V2 if everything
goes well.
Pan
From: 钟居哲
Sent: Friday, December 22, 2023 6:44 AM
To: Jeff Law ; Li, Pan2 ; gcc-patches
Cc: Wang, Yanzhang ; kito.cheng
; richard.guenther ; Tamar
Christina
Subject: Re: Re: [PATCH v1] RISC-V
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Saturday, December 23, 2023 11:38 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ;
kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com
Subject: Re: [PATCH v2
n
> effective target test (check_effective_target_vect_variable_length perhaps?)
Sure, will have a try for this.
Pan
-Original Message-
From: Jeff Law
Sent: Sunday, December 24, 2023 1:20 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ;
kito.ch...@gmail.com; richard.guent...@gmail.com
S
d.
Sure, will have a try for making the -0.0 happen in aarch64.
Pan
-Original Message-
From: Jeff Law
Sent: Friday, December 29, 2023 12:39 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ;
kito.ch...@gmail.com; richard.guent...@gmail.com
Subject: Re
NOR_SIGNED_ZEROS (GET_MODE (x));
10874 return real_equal (CONST_DOUBLE_REAL_VALUE (x), &dconst0);
10875 }
I think that explain why we have +0.0 in aarch64 here.
Pan
-Original Message-
From: Jeff Law
Sent: Friday, December 29, 2023 9:04 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc
2 (set (reg:SF 136)
(mem/u/c:SF (lo_sum:DI (reg:DI 135)
(symbol_ref/u:DI ("*.LC0") [flags 0x82])) [0 S4 A32]))
"test.c":21:6 -1
(nil))
I will have a try to fix it in V3.
Pan
-Original Message-
From: Jeff Law
Sent: Saturday, December 30, 2023
--Original Message-
From: Richard Biener
Sent: Monday, January 8, 2024 6:45 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; kito.ch...@gmail.com; jeffreya...@gmail.com
Subject: Re: [PATCH v3] RISC-V: Bugfix for doesn't honor no-signed-zeros option
On Tue
misunderstanding.
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, January 9, 2024 9:22 AM
To: Richard Biener
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; kito.ch...@gmail.com; jeffreya...@gmail.com
Subject: RE: [PATCH v3] RISC-V: Bugfix for doesn't honor no-s
: Wednesday, January 10, 2024 1:46 AM
To: Richard Biener ; Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; kito.ch...@gmail.com
Subject: Re: [PATCH v3] RISC-V: Bugfix for doesn't honor no-signed-zeros option
On 1/8/24 03:45, Richard Biener wrote:
> On Tue, Jan 2, 2
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, January 10, 2024 3:12 PM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Refine unsigned avg_floor/avg_ceil
LGT
Thanks Richard, will delete the test case pr30957-1.c in patch V5.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, January 11, 2024 4:33 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; kito.ch...@gmail.com; jeffreya...@gmail.com
Subject
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, January 11, 2024 5:22 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; kito.ch...@gmail.com; jeffreya...@gmail.com
Subject: Re: [PATCH v5] LOOP-UNROLL: Leverage
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, January 12, 2024 10:54 AM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Update the comments of riscv_v_ext_mode_p [NFC]
OK
juzhe.zh
> Yes, I'm seeing the problem using glibc. Looking at our postcommit ci
> reports, it appears to only affect linux rv32gcv.
Just FYI. Double confirmed rv64gcv with glibc works well with this patch.
Pan
-Original Message-
From: Edwin Lu
Sent: Wednesday, January 17, 2024 9:45 AM
To: juz
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Wednesday, January 17, 2024 5:02 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Fix asm checks regression due to recent
middle-end change
LGTM
Committed, thanks Juzhe.
Pan
From: juzhe.zhong
Sent: Thursday, January 25, 2024 9:08 PM
To: Wang, Yanzhang
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; Li, Pan2
; Wang, Yanzhang
Subject: Re: [PATCH v2] RISC-V: remove param riscv-vector-abi. [PR113538]
lgtm
Replied Message
Thanks Kito for comments, rebase the upstream and always goes to GPR in V2.
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/644291.html
Pan
-Original Message-
From: Kito Cheng
Sent: Monday, January 29, 2024 9:23 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai
Thanks Kito, will add assertion here, and commit it if there is no surprise in
riscv regression test.
Pan
-Original Message-
From: Kito Cheng
Sent: Tuesday, January 30, 2024 8:54 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH
Thanks Kito. Committed with assertion, as well as pass the riscv regression
test.
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, January 30, 2024 9:11 PM
To: Kito Cheng
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: RE: [PATCH v2] RISC-V: Bugfix for
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Thursday, February 1, 2024 9:39 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ;
kito.ch...@gmail.com
Subject: Re: [PATCH v1] RISC-V: Cleanup the comments for the psabi
On 1/30
Sorry, it seems the log was eliminated by my cleanup script(s). Let me know
rerun one newlib for commit id 23cd2961bd2ff63583f46e3499a07bd54491d45c.
Pan
-Original Message-
From: Edwin Lu
Sent: Friday, February 2, 2024 1:43 AM
To: Li, Pan2 ; juzhe.zh...@rivai.ai; gcc-patches
Cc
Hi Edwin,
Just rerun the newlib and there is no ICE but still 160 dump failures as below.
Pan
-Original Message-
From: Li, Pan2
Sent: Friday, February 2, 2024 11:57 AM
To: Edwin Lu ; juzhe.zh...@rivai.ai; gcc-patches
Cc: Robin Dapp ; kito.cheng ;
jeffreyalaw ; palmer ; vineetg
returned by a[0-1].
Pan
-Original Message-
From: Edwin Lu
Sent: Saturday, February 3, 2024 8:29 AM
To: Li, Pan2 ; juzhe.zh...@rivai.ai; gcc-patches
Cc: Robin Dapp ; kito.cheng ;
jeffreyalaw ; palmer ; vineetg
; Patrick O'Neill
Subject: Re: [COMMITTED V3 1/4] RISC-V: Add non-ve
Not yet. It is long time since last round run, will make sure there is no
surprises from that.
Pan
From: juzhe.zh...@rivai.ai
Sent: Tuesday, February 6, 2024 4:11 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Bugfix for RVV
All passed, include overloaded and non-overloaded.
# of expected passes10885
Pan
From: Li, Pan2
Sent: Tuesday, February 6, 2024 4:17 PM
To: juzhe.zh...@rivai.ai; gcc-patches
Cc: Wang, Yanzhang ; kito.cheng
Subject: RE: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinisc ICE
Kinding ping for SAT_ADD.
Pan
-Original Message-
From: Li, Pan2
Sent: Sunday, April 7, 2024 3:03 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Wang, Yanzhang
; tamar.christ...@arm.com; richard.guent...@gmail.com;
Liu, Hongtao ; Li, Pan2
Subject
Kindly ping^^ for this ice fix.
Pan
-Original Message-
From: Li, Pan2
Sent: Thursday, April 18, 2024 9:46 AM
To: Jeff Law ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Liu, Hongtao
Subject: RE: [PATCH v2] DSE
Thanks Kito, sent v2 for addressing comments.
Pan
-Original Message-
From: Kito Cheng
Sent: Monday, April 29, 2024 2:37 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches
Subject: Re: [PATCH v1] RISC-V: Fix ICE for legitimize move on subreg
const_poly_move
> diff --git a/
Committed to trunk, thanks Kito.
Backported to releases/gcc-14, thanks Jakub.
Pan
-Original Message-
From: Jakub Jelinek
Sent: Monday, April 29, 2024 3:53 PM
To: Kito Cheng
Cc: Li, Pan2 ; Jeff Law ;
gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai
Subject: Re: [PATCH v2] RISC-V: Fix
.
Thanks Jeff, I will prepare a v3 for this with full and well tested results.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, April 29, 2024 11:20 PM
To: Li, Pan2 ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
06:#define REGMODE_NATURAL_SIZE(MODE)
sparc_regmode_natural_size (MODE)
Pan
-Original Message-----
From: Li, Pan2
Sent: Tuesday, April 30, 2024 3:17 PM
To: gcc-patches@gcc.gnu.org
Cc: jeffreya...@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Liu,
Hongtao ; richard.guent...@gma
> vtype here, which is the cheaper check so perform it early.
Sure thing.
Thanks again and will send the v4 with all comments addressed, as well as the
test results.
Pan
-Original Message-
From: Tamar Christina
Sent: Thursday, May 2, 2024 1:06 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.or
free to correct me.
Pan
-Original Message-
From: Tamar Christina
Sent: Thursday, May 2, 2024 11:26 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Liu, Hongtao
Subject: RE: [PATCH v3] Internal-fn: Introduce new intern
Pan
-Original Message-----
From: Tamar Christina
Sent: Thursday, May 2, 2024 8:58 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Liu, Hongtao
Subject: RE: [PATCH v3] Internal-fn: Introduce new internal function SAT
Try to invoke validate_subreg directly in v4 as below.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/650596.html
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, April 30, 2024 7:36 PM
To: gcc-patches@gcc.gnu.org
Cc: jeffreya...@gmail.com; juzhe.zh...@rivai.ai; kito.ch
Hi Vladimir,
Looks this patch results in some ICE in the rvv.exp of RISC-V backend, feel
free to ping me if more information is needed for reproducing.
= Summary of gcc testsuite =
| # of unexpected case / # of unique unexpected case
CC more RISC-V port people for awareness.
Pan
From: Li, Pan2
Sent: Thursday, May 9, 2024 11:25 AM
To: Vladimir Makarov ; gcc-patches@gcc.gnu.org
Subject: RE: [pushed][PR114810][LRA]: Recognize alternatives with lack of
available registers for insn and demote them.
Hi Vladimir,
Looks this
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, May 9, 2024 5:05 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Li, Pan2
Subject: Re: [PATCH v1] RISC-V: Make full-vec-move1.c test robust for
optimization
lgtm
juzhe.zh...@rivai.ai
Sure thing, see below PR.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013
Pan
From: Vladimir Makarov
Sent: Thursday, May 9, 2024 8:21 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Subject: Re: [pushed][PR114810][LRA]: Recognize alternatives with lack of
available registers for insn and demote
-Original Message-
From: Tamar Christina
Sent: Monday, May 13, 2024 5:10 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Liu, Hongtao
Subject: RE: [PATCH v4 1/3] Internal-fn: Support new IFN SAT_ADD for unsigned
Committed, thanks Juzhe and Kito. Let's wait for a while before backport to 14.
Pan
-Original Message-
From: Kito Cheng
Sent: Monday, May 13, 2024 10:11 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Fl
Ack, thanks Jeff and will fix it ASAP.
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, May 14, 2024 2:10 AM
To: Li, Pan2 ; Kito Cheng ;
juzhe.zh...@rivai.ai
Cc: gcc-patches
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16
scalar
On 5/13/24 9:00 AM
wice. It
> also fits better
> In the existing code.
Ack, will follow the existing code.
Pan
-Original Message-
From: Tamar Christina
Sent: Monday, May 13, 2024 11:03 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail
, we can add it back in future if we really changed cfg, will update in v5
(include vect patch 2/3) after all test passed.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, May 14, 2024 9:18 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.
> LGTM but you'll need an OK from Richard,
> Thanks for working on this!
Thanks Tamar for help and coaching, let's wait Richard for a while,😊!
Pan
-Original Message-
From: Tamar Christina
Sent: Wednesday, May 15, 2024 5:12 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.
Kindly ping, looks no build error from Linaro for arm.
Pan
-Original Message-
From: Li, Pan2
Sent: Friday, May 3, 2024 9:52 AM
To: gcc-patches@gcc.gnu.org
Cc: jeffreya...@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Liu,
Hongtao ; richard.guent...@gmail.com; Li, Pan2
> OK.
Thanks Richard for help and coaching. To double confirm, are you OK with this
patch only or for the series patch(es) of SAT middle-end?
Thanks again for reviewing and suggestions.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, May 16, 2024 4:10 PM
To: Li, Pan2
> For the series, the riscv specific part of course needs riscv approval.
Thanks a lot, have a nice day!
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, May 16, 2024 7:59 PM
To: Li, Pan2
Cc: Tamar Christina ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; kito
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, May 16, 2024 8:13 PM
To: Tamar Christina
Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Richard Sandiford
Subject: Re: [PATCH v2 1/3] Vect: Support loop len
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, May 16, 2024 8:19 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; tamar.christina
; Richard Biener ;
richard.sandiford ; Li, Pan2
Subject: Re: [PATCH v2 2/3] RISC-V: Implement vectorizable early exit with
vcond_mask_len
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, May 16, 2024 8:19 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; tamar.christina
; Richard Biener ;
richard.sandiford ; Li, Pan2
Subject: Re: [PATCH v2 3/3] RISC-V: Enable vectorizable early exit testsuite
RISC-V part
741824]:
# _2 = PHI <65535(2), _1(3)>
return _2;
}
Pan
-Original Message-
From: Tamar Christina
Sent: Wednesday, May 15, 2024 5:12 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Liu, Hongtao
Subject: RE: [
Committed with more comments, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Saturday, May 18, 2024 3:32 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: Re: [PATCH v6] RISC-V: Implement IFN SAT_ADD for
Thanks Tamer for enlightening, will have a try for the ingenious idea!
Pan
-Original Message-
From: Tamar Christina
Sent: Friday, May 17, 2024 10:46 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Liu, Hongtao
Hi Botcazou,
Just notice that this patch may result in some ICE when build libc++ for the
riscv port, details as below.
Please note not all configuration can reproduce this issue, feel free to ping
me if you cannot reproduce this issue. CC more riscv port people for awareness.
during GIMPLE pas
Thanks for quick response, 😉!
Pan
-Original Message-
From: Eric Botcazou
Sent: Sunday, May 19, 2024 5:40 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Robin
Dapp ; Jeff Law
Subject: Re: [PATCH] Add widening expansion of MULT_HIGHPART_EXPR
Committed, thanks Jeff. Let's wait for a while before backporting.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, May 20, 2024 12:23 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Liu, Hongtao
; richard.guent...@gmail.com
Subjec
Thanks Andrew for comments, updated in v2.
Pan
From: Andrew Pinski
Sent: Sunday, May 19, 2024 12:25 PM
To: Li, Pan2
Cc: GCC Patches ; 钟居哲 ; Kito
Cheng ; Tamar Christina ;
Richard Guenther
Subject: Re: [PATCH v1] Match: Extract integer_types_ternary_match helper to
avoid code dup [NFC]
On
ina
Sent: Monday, May 20, 2024 7:20 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com
Subject: RE: [PATCH v1] Match: Extract integer_types_ternary_match helper to
avoid code dup [NFC]
> -Original Message-
> F
> Thanks, looks good to me! You still need approval from a maintainer..
Thanks Tamar, let's wait for a while, 😊!
Pan
-Original Message-
From: Tamar Christina
Sent: Tuesday, May 21, 2024 11:19 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@g
, right?
My initial idea is to catch both the (IFN_ADD_OVERFLOW @0 @1) and
(IFN_ADD_OVERFLOW @1 @0).
It is unnecessary if IFN_ADD_OVERFLOW takes care of this already.
Pan
From: Andrew Pinski
Sent: Tuesday, May 21, 2024 7:40 PM
To: Li, Pan2
Cc: GCC Patches ; 钟居哲 ; Kito
Cheng ; Tamar Chris
a better understanding for this.
Pan
-Original Message-
From: Andrew Pinski
Sent: Tuesday, May 21, 2024 8:34 PM
To: Li, Pan2
Cc: GCC Patches ; 钟居哲 ; Kito
Cheng ; Tamar Christina ;
Richard Guenther
Subject: Re: [PATCH v1 1/2] Match: Support __builtin_add_overflow branch form
for unsigne
Committed, thanks Juzhe.
Pan
From: 钟居哲
Sent: Saturday, September 23, 2023 9:07 AM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Remove FP run test for ceil.
Ok
juzhe.zh...@rivai.ai<mailto:juzhe
Sure, will re-visit this part later.
Pan
-Original Message-
From: Kito Cheng
Sent: Saturday, September 23, 2023 3:47 PM
To: Li, Pan2
Cc: 钟居哲 ; gcc-patches ; Wang,
Yanzhang
Subject: Re: [PATCH v1] RISC-V: Remove FP run test for ceil.
I guess it just needs more checks than `target
Committed, thanks Juzhe.
Pan
From: 钟居哲
Sent: Sunday, September 24, 2023 2:06 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng ; patrick
Subject: Re: [PATCH v2] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init
LGTM
juzhe.zh
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Tuesday, September 26, 2023 11:18 AM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Rename rounding const fp function for refactor
LGTM
Committed as passed x86 bootstrap and regression test, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, September 26, 2023 7:35 PM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com
Subject: Re: [PATCH V2] MATCH: Optimize COND_ADD_LEN reduc
Committed as passed x86 bootstrap and regression test, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, September 26, 2023 7:35 PM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com
Subject: Re: [PATCH V3] MATCH: Optimize COND_ADD_LEN reduc
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, September 27, 2023 3:18 PM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com; jeffreya...@gmail.com
Subject: Re: [PATCH] ifcvt: Fix comments
On Wed, 27 Sep 2023, Juzhe-Zhong wr
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Wednesday, September 27, 2023 4:24 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Support FP roundeven auto-vectorization
LGTM
juzhe.zh
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