John Doty j...@noqsi.com writes:
I'd prefer a spice-prototype attribute, which would allow us to avoid many of
the difficulties without a confusing proliferation of attributes. For the
symbol nmos-3.sym, a suitable prototype might be:
M? #D #G #S #S $model-name L= W= AS= AD= PS= PD= M=
DJ Delorie d...@delorie.com writes:
The operation is select. PCB doens't know *why* you're selecting,
it's just selecting everything in a region. If you select the *element*
should it select the *whole* element, or just part of the element?
It is possible to make parts of an element
PCB 20100929 Debian Sid
When selecting elements (whatever) by left-draging a rectangle over the
canvas, pads on the deactivated far side are selected invisibly as well.
A subsequent ChangeClearSize(selectedpads,...) also changes the
invisibly selected pads on the backside.
My boardhouse told
Johnny Rosenberg gurus.knu...@gmail.com writes:
I created this symbol, it's the 74-series version of the 4066 (4
bilateral switches), called 744066 (as in 74LV4066, for example):
Symbol
/Symbol
The documentation of the symbol can be found at
DJ Delorie d...@delorie.com writes:
Make the far side hidden before selecting.
That's the point, I did! The pads select anyway.
Also, see MinMaskGap() to fix solder mask openings :-)
Well, I couldn't. I can only use actions that I know about. :-(
--
Stephan
Peter TB Brett pe...@peter-b.co.uk writes:
The slot attribute does not get promoted. Why can't I promote an
attribute after placement from the (ee) Element attribute edit window?
I just tried this. I placed a symbol, hit e e, right-clicked on the
inherited attribute that I wanted to
Stefan Salewski m...@ssalewski.de writes:
On Tue, 2011-01-04 at 21:14 +0100, Johnny Rosenberg wrote:
comment=Use 74_pwr.sym for supply
I wrote it some months ago...
A single 74_pwr.sym can not work for 14 and 16 pin parts, so I really
recommend to do not use a 74_pwr.sym at all, but one
John Griessen j...@ecosensory.com writes:
On 01/02/2011 04:14 PM, Stephan Boettcher wrote:
If you do not use it, why do you care about associating
netnames to traces?
That's not about auto DRC enforce drawing, it's about searching
for parts related to schematic and cross probing
Dan White d...@whiteaudio.com writes:
gnetlist: Option sort_port_value sorts spice-IO devs by value=.
SF: 3150019
This allows using the refdes' to indicate pinlabel and then using
value= to yield a meaningful ordering to a subckt's ports. My symbol
generator script uses the refdes for
John Griessen j...@ecosensory.com writes:
I wish we were attaching netnames to pcb trace segments as we create
them and using that to do auto enforce
Please don't!
Guess I need to try out that Auto enforce DRC feature -- I've never
purposely used it yet
Same here. If you do not use it,
Johnny Rosenberg gurus.knu...@gmail.com writes:
Den 2010-12-31 02:58:36 skrev Stephan Boettcher
boettc...@physik.uni-kiel.de:
kai-martin knaak k...@familieknaak.de writes:
Johnny Rosenberg wrote:
__
| |
| |o–––
|__|
Ah, those box shaped symbols
Johnny Rosenberg gurus.knu...@gmail.com writes:
No. That's the wrong conclusion.
Well, we'll see what will happen. I am still not 100% sure how to
create symbols in the first place, so I guess things will move very
slowly to begin with…
Maybe your time is better invested by using a small
Philipp Klaus Krause p...@spth.de writes:
Am 31.12.2010 16:31, schrieb Stephan Boettcher:
Maybe your time is better invested by using a small FPGA for whatever
you want to build, and learn Verilog to express the logic.
Depends how much fun can have from learning such stuff. A deadline
Johnny Rosenberg gurus.knu...@gmail.com writes:
Den 2010-12-31 16:31:42 skrev Stephan Boettcher
boettc...@physik.uni-kiel.de:
Johnny Rosenberg gurus.knu...@gmail.com writes:
No. That's the wrong conclusion.
Well, we'll see what will happen. I am still not 100% sure how to
create
Oliver King-Smith oliver...@yahoo.com writes:
Thank you for the info. Both the Ctrl-M idea from Levente and you suggestion
for pin labels worked well for me.
A lot of features in PCB are not easily discoverable. Discoverability
is a major quality factor with UI software.
Info-Key
kai-martin knaak k...@familieknaak.de writes:
Johnny Rosenberg wrote:
__
| |
| |o–––
|__|
Ah, those box shaped symbols.
Well, I don't like them. So none of them in my lib...
Those were invented by bureaucrats at a time when pen plotters had
John Doty j...@noqsi.com writes:
A better netlister for simulation is difficult as long as the gnetlist
front end has hard-coded semantics, especially for hierarchy and
slotting.
Last year (June 2009) LWN published a very nice series by Neil Brown
about successful design pattern in the Linux
Stefan Salewski m...@ssalewski.de writes:
I think one reason for start writing it was my desire to assign
attributes/classes to subnets, to transfer this information to PCB to
support manually- and auto-routing with already specified parameters for
traces.
Why do you need a gschem
John Doty j...@noqsi.com writes:
One crazy configuration was to reduce the number of bits/photon to
one, and thereby achieve two orders of magnitude better time
resolution than most people thought necessary while staying within
data transmission restrictions. I'm told that this has been the
Stefan Salewski m...@ssalewski.de writes:
OK, shame on me for missing that option. But I do not think that this
really proves that a gschem rewrite is obsolete.
I may believe that writing a second gschem editor is worse use of your
time than improving the existing one, but it is not up to me
k...@aspodata.se (Karl Hammar) writes:
Stephan:
Merry Christmas!
Thanks, Merry Christmas to youself!
...
=== Make elements small layouts ===
An element shall be defined as a small layout, same syntax, same
semantics. ...
That would be great.
=== Introduce the concept of
Peter Clifton pc...@cam.ac.uk writes:
All ideas.. I'm not coding anything on this in the foreseeable future ;)
... but, somebody must code the graphics to support new features, e.g.,
dehilighting all objects that are not part of the currently edited
sublayout instances. :-)
--
Stephan
Levente Kovacs leventel...@gmail.com writes:
On Sat, 25 Dec 2010 18:14:27 +0100
Stephan Boettcher boettc...@physik.uni-kiel.de wrote:
line layer=top ends=round 132 150 132 250 /line
I'd add a current netname to copper objects
line layer=top ends=round netname=GND 132 150 132 250 /line
Johnny Rosenberg gurus.knu...@gmail.com writes:
Hm… I start to regret that I asked the question in the first place…
Please don't.
--
Stephan
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Levente Kovacs leventel...@gmail.com writes:
The thing made post my previous message, is that it is very annoying when
unconnected line stays on PCB, and there is no chance to connect anything to
it. Even to the net it was formerly connected.
Well, that is a question of the HIDs, i.e.,
Johnny Rosenberg gurus.knu...@gmail.com writes:
At http://www.geda.seul.org/wiki/geda:gsch2pcb_tutorial the following
is written:
”When all the edits are done, it's very important when editing symbols
to do a Edit→Symbol Translate to zero before saving. Do that and then
save the symbol
kai-martin knaak k...@familieknaak.de writes:
Armin Faltl wrote:
you suggest it's good for something - what for?
Mechanics. These deviant holes may be used to solder the pcb
to a brass rod.
Anyway, I don't know what use some rocket scientist may find
for overlapping holes. PCB can do it,
kai-martin knaak k...@familieknaak.de writes:
From my notes:
• pcb feature request: Please put all the gerbers in a dedicated subdir
of the working directory by default. The name of the subdir should be
configurable.
Any default will seldom be what I'd need, since either the directory
DJ Delorie d...@delorie.com writes:
Bert Timmerman bert.timmer...@xs4all.nl writes:
I don't think it's a Good Thing (TM) that a User Manual is derived
from source code files, for this would require a person with gEDA-dev
priviliges to push changes into the git repository.
I originally
Johnny Rosenberg gurus.knu...@gmail.com writes:
Yet another newbie question then:
I tried to enter a value of a resistor
(/usr/share/gEDA/sym/analog/resistor-2.sym, my operating system is
Ubuntu 10.10) but the position of the value needs to be adjusted a
bit. How can I do that?
It
Peter TB Brett pe...@peter-b.co.uk writes:
On Wednesday 22 December 2010 19:17:14 Johnny Rosenberg wrote:
When I open a new page, a ”title block” is all I see, and there I can read
things like ”DRAWN BY”, ”TITLE”, ”REVISION” and so on. Am I supposed to
fill that in by using the Text tool
blueeag...@gmail.com writes:
I really like the gSchema program and after getting used to it, I find it
better than most I have tried. But the PCB program has a lot to be
desired. I could probably do it if all I needed was through hole, but I
need some custom parts. I could use KCAD I
Kai-Martin Knaak kn...@iqo.uni-hannover.de writes:
Pick one item a day and present it to the mailing list for comments?
Maybe not one item, but one set of related items a day? From your last
couple of lines, four of six items are about gschem text.
---)kaimartin(---
PS: This is what the
Steven Michalske smichal...@gmail.com writes:
See FAQ for pcb
This one? http://pcb.gpleda.org/faq.html
On Dec 18, 2010, at 12:01 PM, jeffrey antony jeffrey_ant...@yahoo.com wrote:
Hello,
Is there a functionality in PCB to rotate a component in 45 degree
instead of 90 degree
kai-martin knaak k...@familieknaak.de writes:
Stephan Boettcher wrote:
See FAQ for pcb
This one? http://pcb.gpleda.org/faq.html
No, this one:
http://geda.seul.org/wiki/geda:pcb_tips
Although the page name says pcb tips, it really contains
answers to frequently asked questions
DJ Delorie d...@delorie.com writes:
Layers in the footprint have to be mapped according to the principle
of least surprise.
Last we talked of this, I mentioned symbolic layer tags vs physical
layer tags. So footprints would have top/inner/bottom layers, boards
would have
DJ Delorie d...@delorie.com writes:
If you want to become a PCB committer, the process starts by writing
good patches, reviewing other people's patches, and being involved in
design discussions. When it gets to the point where the maintainers
are just checking in whatever you ask, you're in
Kai-Martin Knaak kn...@iqo.uni-hannover.de writes:
But if I try to access the produced pdf file with
lp -d PDF -t mosfet-node; mv $HOME/PDF/mosfet-node.pdf .
the second command seems to act on the state before the print command. If
there was no PDF file before, I get:
mv:
Kai-Martin Knaak kn...@iqo.uni-hannover.de writes:
Hi.
I just hit a legitimate use case for mirrored footprints:
A layout sketch for dead-bug-prototyping. That is, glue the component
with its back to the board and do the wires manually. However, there seems
to be no way to mirror a
chrysn chr...@fsfe.org writes:
hi geda-users,
in the process of cnc-milling a pcb with a custom shape using pcb2gcode
[1], i created a polygon on a separate layer. in the following
processing steps, i need a gerber file that contains just that polygon
(without holes for the pins, becaus
Markus Hitter m...@jump-ing.de writes:
Exactly. A rectangle, or any number of lines drawing another
area. Milled is always a rectangle, though.
Hmm, why? The outline layer is especially useful for boards that are
not rectangular shaped.
--
Stephan
John Griessen j...@ecosensory.com writes:
copying scheme files
cp: target `./gnetlist.scm' is not a directory
Seems like a simple usage problem of the cp program... maybe it goes away
the second time through?
This looks as if a variable that defines the target directory is
undefined or
Peter TB Brett pe...@peter-b.co.uk writes:
Obviously, since this is an unofficial branch, please don't submit
patches or bugs to the official gEDA trackers. ;-)
What is the reason why this cannot be merged soon/immediately? From the
description is seems to be a clean addition, that should not
Vanessa Ezekowitz vanessaezekow...@gmail.com writes:
On Mon, 1 Nov 2010 13:46:51 -0700
Steven Michalske smichal...@gmail.com wrote:
I code the latter way, writing a good low level API that has a simple
command line UI, then I add the GUI on top of it when it is warranted.
Which is
John Griessen j...@ecosensory.com writes:
Rearranging some sets of files' locations is faster by GUI than by
commands, since whole swaths of files can be moved at once after a
quick selection task done visually.
not, when I count the time for cleaning up after fat-fingering a mouse
button
Stefan Salewski m...@ssalewski.de writes:
What I wanted to say was: Move to current Layer makes not much sense
for footprints, because we can have inner layers,
it does make sense, sometimes ...
but we can not move footprints to that layers.
... pity
--
Stephan
Markus Hitter m...@jump-ing.de writes:
- Get that thing packaged as soon as a new release is done. Only
software developers install from source these days. As far as I can
see, Debian and the just released Ubuntu 10.10 still distribute the
Nov 2009 release.
I am using Debian unstable (sid).
Rick Collins gnuarm.2...@arius.com writes:
To be perfectly correct, anyone who needs more than 84x84 inch boards
will need to recompile PCB with 64-bit units. If it is me, I have no
idea how to, so I can not. But I don't plan to. If I need boards
larger than 84x84 inches, I will hire one
DJ Delorie d...@delorie.com writes:
PCB elements only have silk on the top layer, sorry.
But you could place the footprint on the bottom layer, if that helps.
--
Stephan
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k...@aspodata.se (Karl Hammar) writes:
I would like the file format to be programmable, at least at the
footprint level.
We had that: M4 footprints. I never liked those, I could not figure out
how to use them. But if you drop the parameters, and make a
non-parameterized top-level file for
I prefer:
# -*- makefile -*-
CSA-L%.sch: CSA-1.sch Makefile
sed 's,^\(refdes\|netname\)=,L$*_,' $ $@
CSA-N%.sch: CSA-2.sch Makefile
sed 's,^\(refdes\|netname\)=,N$*_,' $ $@
FSH-S%.sch: FSH-1.sch Makefile
sed 's,^\(refdes\|netname\)=,S$*_,' $ $@
Steven Michalske smichal...@gmail.com writes:
Now we may want to write a parser, and emitter, but that is a good
amount of work, to serialize a data structure in the code that could
be output be a data serializer that just works.
The emitter shall conserve order and formatting (probably not)
Phil Frost ind...@bitglue.com writes:
I would point out a valid YAML representation of the above is also:
{pin: {pinNumber: 2, pinName: rst, x1: 1234, y1: 4321, x2: 2345, y2: 4321,
layer: component}}
Neither sed nor awk can process XML or YAML the right way in all cases
without
DJ Delorie d...@delorie.com writes:
But I figure the top/inner/bottom class is what we need for
importing footprints. They'd be layered by class, not number, so they
can adapt to whatever number of layers the board has.
Rigid-Flex boards have pads on more than two layers. There are pads on
DJ Delorie d...@delorie.com writes:
And I think the only way to do ... in a non-kludgy way
Yet another example of you automatically putting down any idea that
isn't yours. Please stop that. Please consider the possibility that
someone might come up with a better (or even equally good) idea
Andrew Poelstra as...@sfu.ca writes:
On Sun, Sep 12, 2010 at 03:40:24PM -0400, DJ Delorie wrote:
With flex cable, top and bottom aren't limited to one layer each.
Aren't they?
No. Different areas of the cable may have extra layers or pcbs
attached, changing the number of layers in
DJ Delorie d...@delorie.com writes:
Now, the question becomes which is more fundamental?. I think
it's geometry.
A hole is the same geometry regardless of what level of the heirarchy
it's placed at. So let me rephrase: Why have seven geometric holes,
one for each layer, when we can have
John Doty j...@noqsi.com writes:
On Sep 5, 2010, at 10:43 AM, Stephan Boettcher wrote:
Yes, the gschem file format is much less accessible for
hand/awk/sed-editing than the pcb file format.
Huh? gschem format is *trivial* to parse in awk. Use rules like:
$1==L {
x1 = $2
y1
Stefan Salewski m...@ssalewski.de writes:
On Sun, 2010-09-05 at 09:30 -0600, John Doty wrote:
All of this discussion of formats misses the shining example that's
already in gEDA: the schematic format.
Yes. Recently I begun studying that format and started writing a parser
in Ruby -- really
kai-martin knaak k...@familieknaak.de writes:
Larry Doolittle wrote:
All the cutting, sed-ing and pasting of the subcircuits to multiple
instances, with replication of later changes on all copies is pretty
unflexible.
Agree 100%.
+1
Cloning, referencing, or whatever we may call it,
John Griessen j...@ecosensory.com writes:
It's not pie in the sky. Some of these ideas to use sets and lists
and groups are the easiest kind to implement... Zones in layout are
an easy part of what it already does, when we have more layers for
intermediate calculations. net attribs plus
Stefan Salewski m...@ssalewski.de writes:
On Mon, 2010-08-16 at 10:09 +0200, Stephan Boettcher wrote:
John Griessen j...@ecosensory.com writes:
If there is work put into partitioning a layout, can't we please have
hierarchical layout instead?
I have still problems to understand the goals
Tamas Szabo sza2k...@freemail.hu writes:
I would create a schematic symbol for AT91SAM7 device: 64 pins, lots
of them with multiplexed functions.
1. I can number pins round, 1 to 64 sequentially:
+ easily fit to the schematic, 4x16 pin
+ easy to create the symbol
- no functional
my...@iae.nl writes:
The minimum copper spacing is set to 10.0 mill and the distance between
the two polygons is 15 mill.
I usually get a lot of DRC violations on planes with multiple polygons,
although the polygon spacing is comfortably more than the DRC clearance
setting. Moving the
Gabriel Paubert paub...@iram.es writes:
Now the right solution to avoid having a proliferation
of symnbols might be to have a way to specify attributes
that map from pin name to pin numbers on every instance.
There _are_ attributes available that map from pinseq to pin number.
--
Stephan
DJ Delorie d...@delorie.com writes:
It works, for mm, um, in, and mil suffixes on any number:
{FLOATINGMM} { return parse_number(3937.0079); }
{FLOATINGUM} { return parse_number(3.9370079); }
{FLOATINGIN} { return parse_number(10.0); }
Mike Bushroe mbush...@gmail.com writes:
John,
Thanks for the clarification. I checked and I have created a unique
'name':'number' for each net attribute, and matched input to output names.
If a net is formed for each unique name:number, and all inputs and outputs
with that unique name are
timecop time...@gmail.com writes:
i'm pretty sure the guy is talking about a situation when
1) new user makes a board not knowing much about the tools involved
2) default via size is set smaller than default DRC check.
But isn't that perfect? When you start a new board it is mandatory to
John Luciani jluci...@gmail.com writes:
On Sat, Apr 10, 2010 at 6:58 PM, DJ Delorie d...@delorie.com wrote:
I can think of a few uses for your USB GPIO pod!-Patrick
I use it mostly for testing out new components. I have added a
micro-sd module for it, and most recently it's wired up to a
Eric Brombaugh ebrombau...@cox.net writes:
On Apr 11, 2010, at 2:59 AM, Stephan Boettcher wrote:
microSD are not required to support the SPI protocol. Do they usually
do? What brands?
Interesting. I've tried a half-dozen different brands and haven't had
any trouble with SPI support
gene glick carzr...@optonline.net writes:
This is the board:
http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb
Any idea if it is a good idea to just ignore these violations?
Blindly ignoring violations is probably not a good idea. Better to
understand them first.
Stephan Boettcher boettc...@physik.uni-kiel.de writes:
Thank you very much for you review!
I need to go now, when I am back later today I will tell you what the
board is supposed to do.
I did not dare to ask for so detailed reviews of this board, I just
wanted to present a test case where
Peter Clifton pc...@cam.ac.uk writes:
On Sat, 2010-03-27 at 08:57 +0100, Stephan Boettcher wrote:
gene glick carzr...@optonline.net writes:
This is the board:
http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb
Any idea if it is a good idea to just ignore
timecop time...@gmail.com writes:
Yep, look for example, at X2/C10 (at X=3426, Y=2381) it is so close to X2/R9
and X2/R5. How will you avoid solder bridges there? In fact, the solder
well, that particular area doesnt matter since they're actually
connected together anyway but yeah i agree
gene glick carzr...@optonline.net writes:
Stephan Boettcher wrote:
Stephan Boettcher boettc...@physik.uni-kiel.de writes:
I did not dare to ask for so detailed reviews of this board,
Hi Stephan,
Sorry about that - it's a habit of mine.
Please keep that habit alive!
Your system sounds
timecop time...@gmail.com writes:
Yep, look for example, at X2/C10 (at X=3426, Y=2381) it is so close to X2/R9
and X2/R5. How will you avoid solder bridges there? In fact, the solder
well, that particular area doesnt matter since they're actually
connected together anyway but yeah i agree
Stephan Boettcher boettc...@physik.uni-kiel.de writes:
Peter Clifton pc...@cam.ac.uk writes:
On Sat, 2010-03-27 at 08:57 +0100, Stephan Boettcher wrote:
gene glick carzr...@optonline.net writes:
This is the board:
http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb
Duncan Drennan duncan.dren...@gmail.com writes:
Double-clicking moves the cursor to the violation.
Yes, absolutely wonderful.
Except, ... it centers the cursor on violating entity, and does not show
the second entity that violates the clearance.
I've got 14 DRC violations left mostly on the
Peter Clifton pc...@cam.ac.uk writes:
On Fri, 2010-03-26 at 16:00 +0100, Stephan Boettcher wrote:
This is the board:
http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb
Any idea if it is a good idea to just ignore these violations?
Depends on how close to your fab's
Kai-Martin Knaak k...@familieknaak.de writes:
Sorry, I should have checked. Their domain is genuinely German:
http://basista.de
^^
BTW, the website just got a redesign. It looks much fancier than last
week. Their pcb service is high quality,though. Last time I
Vanessa Ezekowitz vanessaezekow...@gmail.com writes:
On Thu, 25 Feb 2010 14:57:20 -0800
Dave N6NZ n...@arrl.net wrote:
On Feb 25, 2010, at 10:45 AM, DJ Delorie wrote:
Everything in pcb supports non-90 arcs, except for the ability to
create them. Someone needs to come up with a
Stephan Boettcher boettc...@physik.uni-kiel.de writes:
Julian thepurl...@gmail.com writes:
Stephan,
Yes, you can do it, however you can't use the project file for the
process. Here's how:
gerbv --export=png --dpi=600 --foreground=#ffff
--foreground=#00ff0088 file1.gbx file2.gbx
Julian thepurl...@gmail.com writes:
Stephan,
Yes, you can do it, however you can't use the project file for the
process. Here's how:
gerbv --export=png --dpi=600 --foreground=#ffff
--foreground=#00ff0088 file1.gbx file2.gbx ...and so on
Hope this helps. Cheers--
Moin,
What I like to do: create an assembly drawing for my new shiny layout.
How: Using gerbv to export a PNG image at 600dpi, with the front copper
in translucent red, front paste in a little stronger red on top, to
better see the pads, the deeper layers in very light colors below, and
the
Dan McMahill d...@mcmahill.net writes:
Before switching I was a die hard word user.
Word? Wordstar! My first thesis war written with wordstar, on CP/M2.2.
Then I switched to LaTeX. And how proud I was, when EMTeX run faster on
my new 486DX33 notebook, than the TeX on the VAX at the
Peter Clifton pc...@cam.ac.uk writes:
On Sun, 2010-02-07 at 13:47 +0100, Florian Teply wrote:
Right, that would be the case.
I just wonder: if one changed the acceleration letters between translation,
say from Ne_w to Ne_u (going from english to german), would it still work?
Or
has the
gene glick carzr...@optonline.net writes:
Do you all use Latex for editing docs, or maybe open office or other?
I'm getting fed up with the open office bugs and starting to think
that Latex is a better alternative. Busy compiling Lyx as we speak.
My openoffice use is strictly read-only. For
:-)
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Dave N6NZ n...@arrl.net writes:
On Dec 27, 2009, at 6:12 PM, gene glick wrote:
A schematic represents different things to different people:
The technician likes the symbols to closely resemble the physical parts.
It makes working on the board easier since he doesn't need data sheets
in
Link l...@penguindevelopment.org writes:
Since I'm hand-fabbing this and will probably be drawing the lines
with a permanent marker, all traces should be at least 35 mil wide and
have a clearance of 25 mil or greater. I've used that method before;
it's a bit ugly, but it works - for very
Bill Gatliff b...@billgatliff.com writes:
Stephan Boettcher wrote:
Remotely related to this topic, I had this idea:
Often, there are several choices for footprint, model, whatever
attribute that need to to chosen at some point in the flow. We have
proposals
for a kind of database
Peter Clifton pc...@cam.ac.uk writes:
On Tue, 2009-11-17 at 17:10 -0500, DJ Delorie wrote:
What you want is a four-slot-slotted gate symbol, and a separate power
symbol. The slots permute across {gate 1, gate2} x {A-B inputs, B-A
inputs}. I.e. you can use the slotting to switch gates *or*
DJ Delorie d...@delorie.com writes:
The file format and internal data formats support it, but there's no
way other than editing the file to set width and height to different
values.
I do like that fact that the file format supports more general features.
But in this case I may rather prefer
Peter Clifton pc...@cam.ac.uk writes:
Thank you for coding!
Thanks for the feedback - it is the fact that I know others are using
the code which keeps me improving it beyond what I needed last time I
was designing PCBs.
Currently I do not do any layout work, but I'd like to try the new GL
Dave N6NZ n...@arrl.net writes:
Karl Hammar wrote:
n...@arrl.net:
Karl Hammar wrote:
Is there a way to organize alternative subparts in a project, e.g.
a cpu-card for one user will have one kind a bus-connector and for
another user another bus-connector, but still maintanable as one
Dave N6NZ n...@arrl.net writes:
Anyway, 80 engg+tech projects are long behind us. I've seen CPU design
projects with 350+ engineers and 10's of thousands of sheets of
schematics. When gEDA can scale to that, it will be a power tool.
Designs of this scale are still done by schematic entry
Kai-Martin Knaak k...@familieknaak.de writes:
The fix would have to be applied to each and every affected
back-end.
May I suggest to study this LWN article for how this kind of problem can
be solved in a future-proof way:
http://lwn.net/Articles/336262/
Steven Michalske smichal...@gmail.com writes:
pick a small set of some chips you care about. lets say a large
family of the AVR series.
To the symbol:
Add a virtual pin attribute
Add the pin map file attribute.
pinmap=ATmega16.fpm
device=ATmega16
footprint=TQFP44_10
{
Josef Wolf j...@raven.inka.de writes:
I'd prefer something more scriptable, since I expect to have _lots_ of
circuits. But at a first glance, it looks like the ps/eps outputs are
easy to postprocess.
Try gerbv, with a .gvp file as script. This allows to order and
color the layers as you
Stefan Salewski m...@ssalewski.de writes:
I have variable capacitors (trimmer) which two pins as symbol, but the
footprint has three pins, pin 1 and 3 are connected internally.
[...]
- Make a copy of a true 3 pin footprint and rename pin 3 to 1 (this is
what I did first.)
- Use the 3 pin
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