Hello,
Some XSPICE models have vector inputs and vector outputs. In such
cases, how to make gnetlist generate the correct netlist by putting the
node numbers or names within square brackets like this: [1 2 ]
Thanks for your help.
Anand
--
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Hello,
Some XSPICE models have vector inputs and vector outputs. In such
cases, how to make gnetlist generate the correct netlist by putting the
node numbers or names within square brackets like this: [1 2 ]
Thanks for your help.
Anand
--
Close Windows ! Open source !!
Dear Kai-Martin,
Thanks for your information. I will contact DJ.
Sincerely,
RSA
On Tue, Jul 12, 2011 at 5:06 AM, Kai-Martin Knaak
[1]k...@familieknaak.de wrote:
Ananda Murthy R S wrote:
I have noticed that XSPICE code models do not have corresponding
symbols. I
-input-file attribs]
In unknown file:
?: 4 [open-file attribs r]
unnamed port: In procedure open-file in expression (open-file str
OPEN_READ):
unnamed port: No such file or directory: attribs
It produces essentially the same error when using bom2.
Of course, the output.net
DJ Delorie wrote:
What is this attribs file it seems to be looking for and not finding?
Am I supposed to create this file? If so, where can I find a
description of it?
It's a list of attributes for which you want extracts.
http://geda.seul.org/wiki/geda:bom_readme
DJ,
Hello,
I have noticed that XSPICE code models do not have corresponding
symbols. I have prepared symbols for these code models. How to submit
them to be included in the official distribution of gEDA Suite?
Anand
--
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Free software from
Kai-Martin Knaak wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hi.
One of the electronics newbies I teach geda, hit a strange input mode in
gschem today. The GUI did not respond to the usual key-accels (ee, m,
i...). Instead, on the bottom right of the window the status line
Amond,
I had this problem too, until I found the refresh icon:
Add - component
In the Select Component... window, click on the circular arrows icon to
the right of the Filter box. That should refresh the listing without
restarting gschem.
Still using gschem 1.4.0.20080127. I sure hope they
designed. Authors have
done a pretty good job so far so I wouldn't be worried about their
qualifications. I would certainly not discourage them from further
work on their tool.
-r
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Kai-Martin Knaak wrote:
I just got aware of the open source mechanical CAD project freecad. It
hit the debian repository a month ago. Although it is still lacking
important features, much of the basic infrastructure is already up and
running.
Kelvin Gardiner wrote:
I use Ubuntu which has gschem 1.4. So I've downloaded the newest code
with git and compiled it. Given that there seems to be quite few changes
is there any plans to build a 1.6 Ubuntu package either for relase in
the Ubuntu repos or via a PPA.
Hi Kevin,
Please
John P. Doty wrote:
R. Bosch wrote:
B.t.w.: Just noticed that it's almost a year since 20081128 was
released. Any idea why it never came in Ubuntu? Which is still at
20080202... :-/
Hmm, Ubuntu Jaunty is at:
gEDA/gschem version 1.4.3.20081231
Be nice if 1.6
Hi all,
I make a schematic, find no fault in the DRC (gnetlist -g drc2
powerbox.sch).
I generated the pcb files with gsch2pcb Projectfile
I open the generated powerbox_pcb.net and spread out the footprints.
I import the netlist and see GND has been created even though it
doesn't exist in the
Stefan Salewski wrote:
T 1600 900 8 10 0 0 0 0 1
net=GND:2
T 1600 1470 8 10 0 0 0 0 1
Oh, that's a classic... :turning-red:
Tested and it works better now.
I use the stable 1.4.3 On Xubuntu 9.04. The 1.5.3/4 isn't available yet...
Thanks and I apologize...
to the circuit (a
small conductance between each node and the ground) but for some
reason it didn't work. Does anyone knows why?
Cheers,
-r
On Sun, Aug 23, 2009 at 10:23 PM, cedriccedric_li...@bbox.fr wrote:
Hi,
I am a ngspice newbie and I'd like to get a frequential transfer
function of a Wien filter
primitive devices)
had explicit knowledge of a netlist format.
Regards,
-r.
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support to it).
Regards,
-r.
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for writing the tool!
Regards,
-r.
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with C at all?
Fully agree.
The only exception is that part of functionality (reading and
interpreting gEDA file formats) could be abstracted out in a form of
libgeda library (still the netlister doesn't need to be written in
C/C++, just libgeda itself).
Regards,
-r
to do it is to implement this functionality in
Scheme (so that all front-end data structures are naturally available
to back-ends) but it is still OK to have this functionality in a
compiled core provided it doesn't hide design information from its
back-ends.
Regards,
-r
before you can build a scripting system around it.
On the gschem side I really like the idea of libgeda. IMHO everything
that touches user's data should go there and be wrapped with a clean
API. Tools like gschem, netlisters, importers etc should only issue
commands/listen to libgeda.
Cheers,
-r
Hi,
There is also an experimental ADMS add-in for ngspice. Not sure
whether it is usable now, though.
Cheers,
-r.
On Thu, Jul 23, 2009 at 9:44 AM, Svenn Are
Bjerkemsvenn.bjer...@googlemail.com wrote:
Hi,
I have been searching a bit on the net to try to find out if it is
possible to run
On Wed, Jul 1, 2009 at 2:58 AM, Dan McMahilld...@mcmahill.net wrote:
how does spNet compare to gnetman which is also an alternative
hierarchical spice netlister for gschem?
Sorry for silly question, where can I download it?
-r.
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to occur any
time soon. Even if we prepared a patch it would probably have to be
maintained separately.
Cheers,
-r.
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Anthony has
reused gnetlist or not - I couldn't care less. I haven't been using it
(and thus the whole geda) anyway.
Regards,
-r.
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.
-r.
On Tue, Jun 30, 2009 at 8:30 PM, Anthony Shanksyamazak...@gmail.com wrote:
That framework of that level of integration I don't think exists of
the gEDA flow as written since all of the tools are separate. The
easiest way I think this is doable is for there to but a button in
gschem
this information present and displayed on the top level
schematic (testbench) is very convenient from the design management
point of view. If it was to be added in a GUI or in makefile the
information would have to be stored and handled separately.
Regards,
-r
Rob Butts wrote:
What is the standard refdes for a crystal, I'm blanking? The generic
is a U, is this correct?
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DJ Delorie wrote:
I was thinking of an edit-arc option that lets you grab the endpoints
and drag them to new angles. If you grab the center, it moves the
arc. If you grab an enclosing-rectangle-corner, it resizes the arc.
http://www.delorie.com/pcb/tmp/arcedit.png
DJ Delorie wrote:
Just got a box of panels from Advanced Circuits. Five panels, ten
boards per panel (two each powermeter, usb-gpio pod, and three pod
modules - ten sets of boards total). Joy!
Unfortunately, I have no way of separating them into individual boards
yet. Sadness!
But I
available), I could write
some plugins, add tests/examples etc.
Cheers,
-r.
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On Wed, Mar 11, 2009 at 11:12 AM, 温宇杰 yujie@celestialsemi.cn wrote:
always @(posedge CLK or RESET) begin
if (RESET == 1) begin Q = 0;
end
I don't know much about iverilog but you may want to try this form:
always @(posedge CLK or posedge RESET) begin
Regards,
-r
integration method, its
transient simulation time step control is very brittle and output data
are saved in non-indexed text files.
Regards,
-r.
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to
run many small simulations in parallel and in such scenario other
simulators can be very pricey.
Regards,
-r
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be done technically, though.
BTW, some simulators preprocess the netlist and reduce parallel
devices into a single device with an m parameter set. This gives a
huge performance boost in extracted sims.
-r.
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access to
them to check it out.
That's incorrect. Both Spectre and Hspice treat devices with m1 as
single entities.
-r.
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the UART's
FIFO doesn't overflow.
-r
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Thank you all for the feedbacks. I looked a bit deeper into the
projects and my interests and figured that , I am not into GUI stuff
but would love to get my hands more dirty with things even down.
On Thu, Feb 12, 2009 at 9:56 AM, al davis ad...@freeelectron.net wrote:
3. Porting of missing
how this works.
How about placing your code on sourceforge or google code so that
anyone interested can look at it?
Thanks,
-r.
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Dear All,
I am Aanjhan doing my Masters in Electronics at EPFL, Lausanne,
Switzerland. A short introduction about me is present in the page
https://wiki.ubuntu.com/Aanjhan
I am part of the Fedora Electronics Laboratory team and also help in
keeping in sync with the packages in Ubuntu as part of
-key shortcuts. They tend to
slow down navigation and editing quite a bit. OTOH, I don't care much
about less frequent actions - I wouldn't even mind if these were only
accessible from the menu.
Regards,
-r
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-coded text buffers? What happens if you give
it an instance with e.g. 1 pins?
Regards,
-r
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not particularly attached to the current
configuration mechanism (although setting callbacks without this could
be difficult). I just don't think it is broken or particularly needs
an improvement. Actually, this is currently one of the gEDA's
strongest points.
Regards,
-r
flexible.
-r
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best to export gEDA
API over DBUS and allow external scripts to talk to gEDA tools
directly. This would free us from implementing yet another plugin/RPC
system. At this stage, improving the API itself is IMHO far more
important.
Regards,
-r
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and multi-slot symbols. People simply draw all the power
lines just like any other wires (sometimes even explicitly modeling
them with L/R/C circuits). Same with the cells (symbols in the PCB
world) - the closer the symbol is to its
schematic/RTL/layout/extracted view, the better, if only for LVS-ing
power domains (for noise
filtering and for power-down functions), well biasing, voltage drops,
ringing and ESD protection?
Regards,
-r
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switch between different models by configuration?
If this virtual library could store both symbols and schematics (as
well as netlists, models, ...) that would be great.
Regards,
-r.
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http
solution (or workaround, depending how to look at this) would be a
tool, similar to yours, that based on a configuration or a convention
dynamically overwrites the symbols so that gschem knows where to get
their schematics from.
Regards,
-r.
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this is where a donation system or a foundation
(GNU?) could help.
regards,
-r
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hierarchy-documentation)
(SEPARATOR no-action no-action)
(Hotkeys...help-hotkeyshelp-hotkeys)
(About... help-about help-about)))
Regards,
-r
database-related ideas discussed here:
- attaching to a (online?) symbol database. I don't know details -
that's PCB guys' toy.
- storing design data in a database. IMHO a good idea but not very popular here.
Regards,
-r.
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was not very well
supported by some FPGA backend tools but that might have changed by
now.
Regards,
-r
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.) on
the fly. It's a matter of a task complexity vs. tool complexity
trade-off.
Perhaps it could be generalized as a save/restore configuration
options function but it still wouldn't be as flexible scripts.
Regards,
-r.
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it
manually in Makefile.
Regards,
-r.
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, is a basic function users normally expect from any design
entry tool. Netlisting the design really is not the place where
Makefile should be _required_.
Regards,
-r.
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hand, if you are mostly interested in circuit
simulation try ltpice(+wine).
Regards,
-R.
On Tue, Nov 18, 2008 at 11:27 PM, Yamazaki R2 [EMAIL PROTECTED] wrote:
Has anybody made some kind of library manager like the cadence library
manager in icfb to manage schematics and symbols? Something
(highlighting nets).
Best regards,
-r.
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. There are exceptions, of course, (Peter, Werner, Ales,
sorry if I forgot someone) who are open to exchange ideas but more
often than not people here are hostile to anything that isn't a blind
praise for the project.
-r.
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if those have already been fixed - I
haven't used gnetlist since that time.
Regards,
-r.
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a part of the design flow, at least for parts of the system,
as well as does the extraction of the PCB parasitics.
-r.
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that plus...
* origin
* rotation
* location of documentation
Etc.
I.e. Use your imagination :-)
Borrowing from ASIC flow: width/length, number of pins.
-r.
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connections etc.
-r.
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usually to the extracted circuit simulations.
-r.
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it is necessary to start a large number of
simulations and then number of licenses becomes an issue. (BTW. that's
one of reasons why I would like to see monte-carlo analysis in
gnucap).
Then, once the deployment barrier is broken, there would be more
interest in building up on top of gEDA.
-r
On Jan 20, 2008 12:16 AM, Kai-Martin Knaak [EMAIL PROTECTED] wrote:
On Sat, 19 Jan 2008 20:24:42 +, a r wrote:
First of all: What do you refer to by cell? A schematic symbol, or a
pcb footprint?
As John said, I referred to any kind of data that belongs to a
particular block or component
, I can do it the other way
around or postprocess the netlist but it's an additional hassle.
-r.
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simulators that do not like such nested constructs.
3. There are special spice-subcircuit-IO components used for making
subcircuit pins. Does it mean the netlister cannot cope with normal
instance pins?
-r.
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in both gnetlist and its backends. But something went
wrong with them. I just can't help the feeling that it woudn't take
more than 2 days hacking to write a perl script generating a valid
spice netlist.
-r.
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attribute found
G 3 No valid value attribute found
D 1 unknown
.end
H. It would be interesting to see the schematic which
produced this netlist.
I have attached it to this mail.
-r.
test.tar.gz
Description: GNU Zip compressed data
On Jan 20, 2008 6:19 PM, John Doty [EMAIL PROTECTED] wrote:
On Jan 20, 2008, at 6:51 AM, a r wrote:
1. It forces me to add a simulation card to the schematic. In general
cases that something I'd like to avoid (it is OK for testbench
schematics, though).
I don't see why that's a big deal
a configuration option that by default disables evaluation
of the code embedded in user-defined cells.
2a. prompt for a permission to evaluate such a code.
-r.
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,
- all attributes and annotations soon become unreadable.
-r.
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: Sat, 19 Jan 2008 14:39:23 GMT
Cache-Control: max-age=600
ETag: 32
Connection: close
Content-Type: text/plain
v 20070818 1
T 300 900 5 10 0 0 0 0 1
device=PMOS_TRANSISTOR
[...]
Connection closed by foreign host.
-r.
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On Jan 19, 2008 6:35 PM, John Griessen [EMAIL PROTECTED] wrote:
a r wrote:
[jg] Library search path is a good concept for dealing with this.
Proven in chip design setting to be low enough hassle, flexible.
Can you tell me how to set this path? That's what I'm looking for.
[jg]It's
On Jan 19, 2008 7:53 PM, a r [EMAIL PROTECTED] wrote:
On Jan 19, 2008 6:35 PM, John Griessen [EMAIL PROTECTED] wrote:
a r wrote:
[jg] Library search path is a good concept for dealing with this.
Proven in chip design setting to be low enough hassle, flexible.
Can you tell me how
are component-level electronics designers in an academia environment
or electronics geeks. For industry, gschem lacks features. For
mainstream PCB designers, it has too steep learning curve.
Regards,
-r.
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a new gschem version.
If so, forthcoming gEDA
release should address that particular bug, with a moderately
re-architectured drawing model. (Just FYI).
I will have a look.
Thanks,
-r.
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http
be able to efficiently draw schematics with several
hundreds of instances on a single page (eg. extracted netlists).
-r.
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, let's not start another thread. EOT.
Cheers,
-r.
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conclusion.
-r.
On Jan 9, 2008 6:47 PM, John Doty [EMAIL PROTECTED] wrote:
On Jan 9, 2008, at 11:23 AM, a r wrote:
gschem should be able to efficiently draw schematics with several
hundreds of instances on a single page (eg. extracted netlists).
Why should gschem be able to efficiently draw
1.3.0. The rendering is, in fact, very fast now.
There is still some noticeable delay when the scene/backbuffer is
being updated, but the perceived speed is far better than when I tried
gschem last time.
-r.
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alive?
Cheers,
-r.
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function in fact. Still, I would rather put this knob in
an annotation tool options dialog.
Cheers,
-r.
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useful for my everyday work.
Cheers,
-r.
On Dec 31, 2007 6:57 PM, KURT PETERS [EMAIL PROTECTED] wrote:
I've just released a new version of KJWaves (available on sourceforge.net).
It has the ability to read GnuCap files (requested by Al Davis) and a fix to
the way log plots are displayed
Random ideas: try better supply decoupling or package, stop other FPGA
outputs when the clock generator is active (or at least put them far
from the generator outputs). Check PCB - especially for return current
paths of noisy signals.
-r.
On Nov 28, 2007 7:09 PM, Timothy Normand Miller [EMAIL
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