[gem5-users] How do I disable most statistics in the stats.txt under Atomic CPU

Hi All: In the Atomic CPU, only a function simulation is performed for enabling or debugging applications. The performance statistics of the architecture are not concerned. Therefore, only a small items are required, e.g. number of instructions or cycles. According to my

[gem5-users] 答复: Re: 答复: Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in Ruby-CHI and O3

Hi Busnot: I think the patch fix my problems if I set the SHARE L3 as inclusive, but if I set it as exclusive, the problem still exist. I have left the my problem and config description in the JIRA: https://gem5.atlassian.net/browse/GEM5-1185 -邮件原件- 发件人:

[gem5-users] 答复: Re: 答复: Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in Ruby-CHI and O3

Hi Busnot: I have tried the patch, but it still has the same assert. -邮件原件- 发件人: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] 发送时间: 2022年2月18日 15:20 收件人: gem5-users@gem5.org 抄送: Gabriel Busnot 主题: [gem5-users] Re: 答复: Does the gem5 v21.0.1.0 support to

[gem5-users] 答复: Re: 答复: Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in Ruby-CHI and O3

Hi Busnot: Thank you very much. I will have a try with the patch. If it can fix my problem, I will let you know. -邮件原件- 发件人: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] 发送时间: 2022年2月18日 15:20 收件人: gem5-users@gem5.org 抄送: Gabriel Busnot 主题: [gem5-users]

[gem5-users] Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in Ruby-CHI and O3

Hi All: Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in Ruby-CHI and O3? Or if anyone has ever bootup with it? ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] m5 resetstats cannot reset cache statistics

Hi All: I have found that m5 resetstats cannot reset cache statistics such as hit count/miss count/access both in classic and ruby, so I looked into the source code, I have found that in Cache-part sourcecode, there is no resetstats callback function in it. Am I right? If so, are

[gem5-users] 答复: Re: Multithread simulation using gem5 SE mode

Hi： I have more question: Can I run a program with dynamic link on SE? My host machine is aarch64, and my program is also an aarch64 ELF, the program can find all library on this host machine according to the result of “ldd”. 发件人: RTL Insn via gem5-users

[gem5-users] 答复: Re: restore with O3 hang when "bti" instrution meet

Hi Becker: Thanks for your reply. Now I have followed your modification, I can see that the "bti" instruction has been replaced by "nop", but it always hang here, so do you have any idea? 68338414857000: system.cpu: T0 : 0x7ff7e632d4: sub x21, x21, #1936 : IntAlu

[gem5-users] 撤回: Re: restore with O3 hang when "bti" instrution meet

Liyichao 将撤回邮件“[gem5-users] Re: restore with O3 hang when "bti" instrution meet”。 ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] 答复: Re: restore with O3 hang when "bti" instrution meet

Hi Becker: Thank for your reply. When I modify the code like yours, some error when I compile: scons: Building targets ... [ISA DESC] ARM/arch/arm/isa/main.isa -> generated/decoder-g.cc.inc, generated/decoder-ns.cc.inc, generated/decode-method.cc.inc,

[gem5-users] restore with O3 hang when "bti" instrution meet

Hi All: When I use my own filesystem by O3 restore, it will hang when "bti" instruction meet. Is this instruction make some error here? My gem5 version is v21.0.1.0 309440865500: system.cpu: T0 : 0x7ff7e632ec: stp 60309440865500: system.cpu: T0 : 0x7ff7e632ec. 0 : addxi_uop

[gem5-users] Failed to setup KVM memory region on centos7.6 host

Hi All: I have a problem when I use KVM on aarch64 server with centos 7.6 while it has no problem on the same aarch64 server with ubuntu18.04/ubuntu20.04. Gem5 version is v21.2.0.0/v21.1.x.x/v21.0.x.x Cmd: ./build/ARM/gem5.debug --debug-flags=Kvm ./configs/soc_base/fs.py -n 1

[gem5-users] isa functionally implementation

Hi All: I wonder if the semantics of ISA are already implemented in GEM5, but whether it actually implements its functionality in the architecture. For example, the armv8 instruction "ldnp" is defined in the standard that it initiates a direct load from the memory and will not be

[gem5-users] M5OPS problems

Hi All: I added M5OPS pseudo-instructions to a core computing part of my program code, but I now have a problem with M5OPS_RESETSTATS once I execute M5OPS_RESETSTATS and then M5OPS_DUMPSTATS. In the dump result, only eight system.mem_ctrls statistics are printed (32 mem_ctrls are

[gem5-users] 答复: Re: CHI prefetcher on V21

OK, let me create a jira issue now:) -邮件原件- 发件人: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] 发送时间: 2021年11月10日 19:51 收件人: gem5-users@gem5.org 抄送: Gabriel Busnot 主题: [gem5-users] Re: CHI prefetcher on V21 Hi, Prefetch implementation seems unchanged and incomplete since

[gem5-users] CHI prefetcher on V21

Hi All: Does latest GEM5 version support prefetcher on Ruby CHI now? On v21.0.1.0, I think the prefetcher on Ruby CHI does not support well, isn't it? ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to

[gem5-users] Re: m5 pesudo

22:56:48 Hello, The m5 magic operations (either via magic instructions or addresses) will work with all CPU models. Cheers, Jason On Sat, Oct 30, 2021 at 8:31 PM Liyichao via gem5-users mailto:gem5-users@gem5.org>> wrote: Hi All: Does “m5 --addr 0x1001 exit

[gem5-users] m5 pesudo

Hi All: Does "m5 --addr 0x1001 exit" take effect in the O3 system? ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] How to config autologin in ubuntu-18.04-arm64-docker.img from GEM5 website

Hi All: I want to launch gem5 with fs.py, and I don't know the default root password of ubuntu-18.04-arm64-docker.img, so how can I config auto-login with root user and without password need? Anyone has experience on it? ___ gem5-users

[gem5-users] 答复: Re: How to enable KVM unitest on ARM server

主题: [gem5-users] Re: How to enable KVM unitest on ARM server Hi, I just grepped through all of gem5's source, and, even ignoring capitalization, the string "KVM for" does not appear outside of a couple comments. I have no idea where that string is coming from, but it doesn't seem to be

[gem5-users] 答复: Re: How to enable KVM unitest on ARM server

2021 at 8:04 PM Liyichao via gem5-users mailto:gem5-users@gem5.org>> wrote: Hi All: My GEM5 V21.1.0.2 running on aarch64 server, but when I compile bitunion.test.opt, the compilation print will show “Info: KVM for null not supported on arm host.” scons build/NULL/base/bitunion.test

[gem5-users] How to enable KVM unitest on ARM server

Hi All: My GEM5 V21.1.0.2 running on aarch64 server, but when I compile bitunion.test.opt, the compilation print will show "Info: KVM for null not supported on arm host." scons build/NULL/base/bitunion.test.opt -j120 scons: Reading SConscript files ... Checking for linker -Wl,--as-needed

[gem5-users] 答复: explaination about command_window in MemCtrl.py

Hi all: Any one knows? Best regards Li Yichao 发件人: Liyichao 发送时间: 2021年10月13日 15:51 收件人: gem5 users mailing list 抄送: wuhailin 主题: explaination about command_window in MemCtrl.py Hi all: Now I’m working on researching LPDDR5 feature on GEM5. But I do not clearly know the parameter

[gem5-users] explaination about command_window in MemCtrl.py

Hi all: Now I'm working on researching LPDDR5 feature on GEM5. But I do not clearly know the parameter "command_window" in MemCtrl.py, and why the default value set to 10ns. In a workshop vedio for "Memory controller for LPDDR5", there is a formula "maxCommandsPerBurst = burst_length /

[gem5-users] 答复: gem5 v21.1 released!

Hi Bruce: I see the GEM5 resource mentioned on the GEM5 official website. Are all the resources provided in the GEM5 resource based on x86? For example, SPEC2017, are there AARCH64-based versions available for these resources? Best regards, Liyichao 发件人: Bobby Bruce via gem5-users

[gem5-users] instrutions statistics

Hi Jason: Previously, I have seen examples about the increase of kernel-mode instructions and user-mode instructions on the GEM5 official website. However, I cannot find them on the official website. The web page has been updated. If yes, where can I refer to these examples?

[gem5-users] add an instrution statistics in stats.txt

Hi All: How to add an instruction statistics item to distinguish the number of kernel-mode instructions and user-mode instructions? ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] scheduleInstStop use under aarch64 KVM mode

Hi All: The scheduleInstStop function is used to specify the number of instructions to stop the emulation. Currently, my GEM5 emulation under aarch64 KVM mode is to start 32 cores and then execute an identical binary on each core. Then I use the scheduleInstStop function to specify

[gem5-users] Re: 答复: Re: SPEC2017 in FS mode

Thank you for your reply. Any plans to support for aarch64？ 发件人： Hoa Nguyenmailto:hoangu...@ucdavis.edu>> 收件人： Liyichaomailto:liyic...@huawei.com>> 抄送： gem5 users mailing listmailto:gem5-users@gem5.org>> 主题： Re: 答复: [gem5-users] Re: SPEC2017 in FS mode 时间：

[gem5-users] Re: Compiling code to run in se mode

I think you have to compile with -static in se mode. 发件人： krishnan gosakan via gem5-usersmailto:gem5-users@gem5.org>> 收件人： gem5 users mailing listmailto:gem5-users@gem5.org>> 抄送： krishnan gosakanmailto:krishnan.gosa...@gmail.com>> 主题： [gem5-users]

[gem5-users] Re: Simulation aborts when number of instructions increases due to LSQUnit ERROR

I also have met this problem before on v20.0.0.3，for any other test binaries，and have no idea about it. 发件人： VEDIKA JITENDRA KULKARNI via gem5-usersmailto:gem5-users@gem5.org>> 收件人： gem5-usersmailto:gem5-users@gem5.org>> 抄送： VEDIKA JITENDRA KULKARNImailto:ved...@iitg.ac.in>> 主题： [gem5-users]

[gem5-users] 答复: Re: SPEC2017 in FS mode

Hi Hoa: Is the spec-2017 img just for X86? Does it support for AARCH64?Does it support for running with KVM+O3? -邮件原件- 发件人: Hoa Nguyen via gem5-users [mailto:gem5-users@gem5.org] 发送时间: 2021年5月19日 19:09 收件人: gem5 users mailing list 抄送: Hoa Nguyen 主题: [gem5-users] Re:

[gem5-users] test in Atomic is OK but in KVM is panic

Hi All: I have tested my simple program, if I use AtomicSimple CPU, the result is OK, but if I use X86KvmCpu, the result panic: My simple program source code is: #include int main() { unsigned int a = 0; unsigned long i; for (i=0;i<1000;i++) a++;

[gem5-users] 答复: Fail to bootup with KVM in se.py on X86 arch

going wrong. I would extend the panic on line 559 of vm.cc to also print the error code number so you can look it up. I believe you can use `errno` like normal after calling `ioctl`. For instance, you could add `strerror(errno)` to the panic. Cheers, Jason On Mon, May 10, 2021 at 12:49 AM Liy

[gem5-users] 答复: Fail to bootup with KVM in se.py on X86 arch

vm.cc to also print the error code number so you can look it up. I believe you can use `errno` like normal after calling `ioctl`. For instance, you could add `strerror(errno)` to the panic. Cheers, Jason On Mon, May 10, 2021 at 12:49 AM Liyichao via gem5-users mailto:gem5-users@gem5.org>> wrot

[gem5-users] 答复: Fail to bootup with KVM in se.py on X86 arch

rno)` to the panic. Cheers, Jason On Mon, May 10, 2021 at 12:49 AM Liyichao via gem5-users mailto:gem5-users@gem5.org>> wrote: Hi All: I use KVM CPU in se mode on X86 arch, but it showed a panic “KVM: Failed to create virtual CPU”. My host is X86 server of Intel 6148

[gem5-users] Re: Fail to bootup with KVM in se.py on X86 arch

)` to the panic. Cheers, Jason On Mon, May 10, 2021 at 12:49 AM Liyichao via gem5-users mailto:gem5-users@gem5.org>> wrote: Hi All: I use KVM CPU in se mode on X86 arch, but it showed a panic “KVM: Failed to create virtual CPU”. My host is X86 server of Intel 6148 and

[gem5-users] 答复: Fail to bootup with KVM in se.py on X86 arch

Cheers, Jason On Mon, May 10, 2021 at 12:49 AM Liyichao via gem5-users mailto:gem5-users@gem5.org>> wrote: Hi All: I use KVM CPU in se mode on X86 arch, but it showed a panic “KVM: Failed to create virtual CPU”. My host is X86 server of Intel 6148 and it can support kvm: lsmo

[gem5-users] 答复: Fail to bootup with KVM in se.py on X86 arch

ook it up. I believe you can use `errno` like normal after calling `ioctl`. For instance, you could add `strerror(errno)` to the panic. Cheers, Jason On Mon, May 10, 2021 at 12:49 AM Liyichao via gem5-users mailto:gem5-users@gem5.org>> wrote: Hi All: I use KVM CPU in se mode on

[gem5-users] Fail to bootup with KVM in se.py on X86 arch

Hi All: I use KVM CPU in se mode on X86 arch, but it showed a panic "KVM: Failed to create virtual CPU". My host is X86 server of Intel 6148 and it can support kvm: lsmod |grep kvm kvm_intel 172032 0 kvm 548864 1 kvm_intel irqbypass 16384 1

[gem5-users] does KVMCPU be supported on aarch64 in SE mode?

Hi All: I would like to use KVMCPU in SE mode on aarch64 so that I can use -fast-forward more quickly to fastforward non-interested instrutions, but I have seen that "fatal("KvmCPU can only be used in SE mode with x86")" in se.py, so any plans to support it on aarch64?

[gem5-users] no committedInsts in stats.txt with fastforward option in SE mode

Hi All: When I simulate with the fastforward and maxinsts parameters in SE mod, I only see sim_insts=my fastforward instructions in stats.txt after the maximum number of instructions exits. The value of committedInsts is not always 0 in switch_cpu.committedInsts, but if fastforward is

[gem5-users] Re: Running gem5 on arm64 linux machine

of course！ 发件人： Ahmad SB via gem5-usersmailto:gem5-users@gem5.org>> 收件人： gem5-usersmailto:gem5-users@gem5.org>> 抄送： ahmad.sb101mailto:ahmad.sb...@gmail.com>> 主题： [gem5-users] Running gem5 on arm64 linux machine 时间： 2021-05-01 02:13:22 Hello Is it possible to install and run gem5 on a arm64 linux

[gem5-users] swap partition in GEM5

Hi All: Currently, I want to test a workload with insufficient memory size, so tha it can swap with virtual harddisk. But the filesystem on GEM5 website only has a root partition and has not swap partition. So does GEM5 support bootup a filesystem with swap partition and root

[gem5-users] 答复: 答复: TimingCPU's IPC

clock=2GHz" on the command line that the CPU's clock is actually set to 2GHz. I strongly suggest using your own configuration files like in Learning gem5. Cheers, Jason On Tue, Apr 27, 2021 at 5:58 AM Liyichao via gem5-users mailto:gem5-users@gem5.org>> wrote: My cmd is ./build/ARM/

[gem5-users] 答复: TimingCPU's IPC

r configuration here? To be honest, it looks like the CPU is just running at 1GHz instead of 2. Is that possible? -- Dr. Bobby R. Bruce Room 2235, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net On Fri, Apr 23, 2021 at 3:52 AM Liyichao via gem5-users mailto:gem5-users@gem5

[gem5-users] TimingCPU's IPC

Hi All: As I know, Atomic or Timing CPU’s IPC is 1 IPC, but when I test a program in SE mode with –debug-flags=Exec, in the debug output file, I find that one instruction’s tick is incremented by 1000, my cpu frequency is 2 GHz. Does that mean that the IPC is 0.5(cycle=1000/500)?

[gem5-users] 答复: How to debug a program in GEM5 FS mode.

is helps. Boris -----"Liyichao via gem5-users" wrote: - To: "Boris Shingarov" , "gem5 users mailing list" From: "Liyichao via gem5-users" Date: 04/21/2021 04:42AM Cc: "Gabe Black" , "Liyichao" Subject: [gem5-users] : Re:

[gem5-users] 答复: Re: How to debug a program in GEM5 FS mode.

de* gem5, as part of the simulation. I don't know if anybody has tried that, but then gdb should work like it would on a real ARM host, more or less. Gabe On Tue, Apr 20, 2021 at 7:27 PM Liyichao via gem5-users wrote: Hi All: I am currently debugging a program with an SVE instr

[gem5-users] Re: How to debug a program in GEM5 FS mode.

but if it can run yours that's probably what you'll want to do. Another option would be to run gdb *inside* gem5, as part of the simulation. I don't know if anybody has tried that, but then gdb should work like it would on a real ARM host, more or less. Gabe On Tue, Apr 20, 2021 at 7:27 PM

[gem5-users] How to debug a program in GEM5 FS mode.

Hi All: I am currently debugging a program with an SVE instruction in the FS mode of GEM5. However, a segment error occurs in the program. Therefore, I want to locate which instruction is causing the error and check the contents of the register of the error instruction. What are the

[gem5-users] 答复: Re: DRAMCTRL self-refresh frequency

Sorry, I get the wrong info. My current tREFI is 3.9us, tXS is 360ns, tRFC is 350ns. 李翼超（Charlie） 华为技术有限公司 Huawei Technologies Co., Ltd. 部门：计算系统与组件开发部 [云与计算BG] 手　　机：15858232899 电子邮件：liyic...@huawei.com 地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06] 

[gem5-users] Re: DRAMCTRL self-refresh frequency

Thanks。my tRFI is 360ns，my tRFC is 0.682ns 李翼超 charlie Mobile：+86-15858232899 Email：liyic...@huawei.com 发件人： lsteiner--- via gem5-usersmailto:gem5-users@gem5.org>> 收件人： gem5-usersmailto:gem5-users@gem5.org>> 抄送：

[gem5-users] DRAMCTRL self-refresh frequency

Hi all: In GEM5, where can I modify the self refresh frequency or refresh rate in dramctrl? My DRAM is DDR4 2933MHz. e.g. I want to modify the self refresh frequency or rate to 32ms or 64ms(32Hz or 64Hz). ___ gem5-users mailing list --

[gem5-users] The sim_insts in stats.txt under O3 type seems to be wrong

Hi all: When I use se mode to execute an ELF under O3 type with Exec debug flags, the sim_insts in stats.txt is different with the lines of Exec debug output file. Sim_ints is 94189557, but Exec debug output file has 472187507 lines. I have test the same ELF on my aarch64 server

[gem5-users] 答复: HLT instrution

mo > -----Original Message- > From: Liyichao via gem5-users > Sent: 22 March 2021 03:10 > To: gem5 users mailing list > Cc: Liyichao > Subject: [gem5-users] HLT instrution > > Hi all: > > I wonder how can gem5 process “HLT” instruction in SE/FS mode? &

[gem5-users] HLT instrution

Hi all: I wonder how can gem5 process “HLT” instruction in SE/FS mode? I have seen that “HLT instructions aren't implemented, so treat them as undefined instructions.” in source code. ___ gem5-users mailing list --

[gem5-users] 答复: gem5 crash when mount by vio-9p protocol in KVM mode with more than 1 core

when using multiple cores with KVM, each core runs in its own thread. There's a way to add events to the event queue in another thread safely (ScopedMigration) which I'm assuming the v9 code is not using. Gabe On Sun, Mar 7, 2021 at 8:38 PM Liyichao via gem5-users mailto:gem5-users@gem5.org>>

[gem5-users] 答复: gem5 crash when mount by vio-9p protocol in KVM mode with more than 1 core

ent queue in another thread safely (ScopedMigration) which I'm assuming the v9 code is not using. Gabe On Sun, Mar 7, 2021 at 8:38 PM Liyichao via gem5-users mailto:gem5-users@gem5.org>> wrote: Hi All: When I use –vio-9p with fs_bigLITTLE.py, 1 core the mount cmd was ok, but more

[gem5-users] 答复: gem5 crash when mount by vio-9p protocol in KVM mode with more than 1 core

. Most of the time this is not an issue since gem5 is usually single threaded, but when using multiple cores with KVM, each core runs in its own thread. There's a way to add events to the event queue in another thread safely (ScopedMigration) which I'm assuming the v9 code is not using. Gabe

[gem5-users] Re: gem5 crash when mount by vio-9p protocol in KVM mode with more than 1 core

its own thread. There's a way to add events to the event queue in another thread safely (ScopedMigration) which I'm assuming the v9 code is not using. Gabe On Sun, Mar 7, 2021 at 8:38 PM Liyichao via gem5-users mailto:gem5-users@gem5.org>> wrote: Hi All: When I use �Cvio-9p with f

[gem5-users] gem5 crash when mount by vio-9p protocol in KVM mode with more than 1 core

Hi All: When I use –vio-9p with fs_bigLITTLE.py, 1 core the mount cmd was ok, but more than 1 core, mount cmd will cause GEM5 crash 1core: Gem5 cmd: ./build/ARM/gem5.opt --debug-flags=Exec -d /home/l00515693/m5out configs/example/arm/fs_bigLITTLE.py --cpu-type=kvm

[gem5-users] A problem of "Assertion `!load_inst->isExecuted()' failed.”"

Hi All: When I run a program with 1 core on ARM64 CPU O3 MODEL, I meet a problem of “Assertion `!load_inst->isExecuted()' failed.”: 8273246606240: system.N1Cluster.cpus.decode: Processing [tid:0] 8273246606240: system.N1Cluster.cpus.decode: [tid:0] Stall fom Rename stage detected.

[gem5-users] Re: KVM Doesn't Work

any plans to support gicv3 for kvm？ currently I use soft gic for kvm，but I think it will slow down the speed of kvm. 发件人： Giacomo Travaglinimailto:giacomo.travagl...@arm.com>> 收件人： gem5 users mailing listmailto:gem5-users@gem5.org>>;Liyichaomailto:liyic...@huawei.com>> 抄送： Tracy

[gem5-users] 答复: KVM Doesn't Work

You have to modify TIMER and GIC. diff --git a/src/dev/arm/GenericTimer.py b/src/dev/arm/GenericTimer.py index ed81b2471..aee15b738 100644 --- a/src/dev/arm/GenericTimer.py +++ b/src/dev/arm/GenericTimer.py @@ -98,6 +98,7 @@ Reference: # value, so this initial value will be discarded

[gem5-users] Re: Using multiple threads on host?

You have to use X86_64 host with X86_64 guest if you want to use KVM. 李翼超 charlie Mobile：+86-15858232899 Email：liyic...@huawei.com 发件人： bodunhu--- via gem5-usersmailto:gem5-users@gem5.org>> 收件人：

[gem5-users] CXL protocol model simulation support schedual in GEM5

Hi all: We are currently studying the CXL protocol. Do you have a development plan for the CXL protocol simulation model in the GEM5 community or have developers started to implement the model, including the driver, HOST/DEVICE module implementation, and consistency protocol? TKS!

[gem5-users] run pre-build binaries of aarch64 with error

Hi： I run the pre-build binaries of aarch64 test_std_thread , test_std_mutex and test_std_condition_variable on an aarch64 ubuntu18.04 OS server, which downloaded from https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/, I see the error execution below:

[gem5-users] 答复: Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27

Hi： I have use your Ubuntu 18.04 img to bootup, but I want to know how to modify to enable autologin with root and readfile from GEM5, also systemd service work normally. If I cp /init.gem5 to /sbin/init, although it can enable autologin and read script from GEM5,but system

[gem5-users] 答复: Re: 答复: Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27

On Mon, Nov 30, 2020 at 10:32 PM Liyichao via gem5-users mailto:gem5-users@gem5.org>> wrote: Hi: I download the img you mentioned, when I mount it on /media,it's wrong: root@ubuntu:/home/l00515693/fs-image_fx/disks# mount -o loop,offset=32256 /home/l00515693/fs-image_fx/

[gem5-users] 答复: 答复: Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27

it ARM with Ubuntu 18.04 or GLIBC 2.27 I'm running into the same issue as well. -Jiwon On Mon, Nov 30, 2020 at 10:32 PM Liyichao via gem5-users mailto:gem5-users@gem5.org>> wrote: Hi: I download the img you mentioned, when I mount it on /media,it's wrong: root@ubuntu:/home/

[gem5-users] some error in IDE CONTROLLER when I change the virtioblk to pci ide controller in fs_bigLITTLE.py

Hi all: When I change the virtioblk to ide in fs_bigLITTLE.py, and in KVM mode I setup a ceph with 3 blank disks, and when I write to these disks, some kernel message will show: [ 428.264131] ata1.01: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen [ 428.265631] ata1.01:

[gem5-users] 答复: Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27

Hi: I download the img you mentioned, when I mount it on /media,it's wrong: root@ubuntu:/home/l00515693/fs-image_fx/disks# mount -o loop,offset=32256 /home/l00515693/fs-image_fx/disks/ubuntu-18.04-arm64-docker.img /media/ mount: /media: wrong fs type, bad option, bad superblock

[gem5-users] how can I use ubuntu kernel 4.15.0 to bootup with fs.py

Hi All: I use gem5 .config which can bootup successfully with 4.14 kernel downloaded from gem5 website, but when I use this .config to compile ubuntu 18.04.5’s kernel(4.15.0), it can’t bootup with fs.py. It hanged here: root@ubuntu:/home/l00515693/gem5_1P1DIE#

[gem5-users] how to add more than 1 ide disk in gem5 fullsystem

hi all： how to add more than 1 ide disks in gem5 fullsystem？ I want to see that sda sdb sdc ... in OS so that I can test some distribution application like ceph. 李翼超 charlie Mobile：+86-15858232899

[gem5-users] how to enable ubuntu 18.04.5 rootfs in gem5

Hi: Anyone has experience on enabling Ubuntu 18.04.5 rootfs in gem5? From GEM5 website, the guaidance “Creating disk images for full system mode” was only suite for older Ubuntu rootfs, like 14.x, but the newer version of Ubuntu like 18.04 has many modifications.

[gem5-users] can not bootup with "--dual" option

Hi All: I use “--dual” to bootup with 2 system, but can not bootup them, when I delete “--dual”, it can be bootup. My cmd is “./build/ARM/gem5.opt configs/example/fs.py --cpu-type=ArmV8KvmCPU --kernel=vmlinux -n 1 --machine-type=VExpress_GEM5_V1

[gem5-users] failed to bootup with dist-gem5.sh on ARM

Hi All: I use the GEM5 v20.0.0.1 with dist-gem5.sh, my cmd is “bash $DIST_M5/util/dist/gem5-dist.sh -n 2 -r $DIST_M5/rundir -c $DIST_M5/ckptdir -s $DIST_M5/configs/dist/sw.py -f $DIST_M5/configs/example/fs.py --fs-args --kernel=$M5_PATH/binaries/vmlinux --machine-type=VExpress_GEM5_V1

[gem5-users] 答复: Re: Ethernet support for ARM FS simulation

diately and delete it! 发件人: Gabe Black [mailto:gabe.bl...@gmail.com<mailto:gabe.bl...@gmail.com>] 发送时间: 2020年11月5日 21:19 收件人: gem5 users mailing list mailto:gem5-users@gem5.org>> 抄送: Liyichao mailto:liyic...@huawei.com>> 主题: Re: [gem5-users] Re: Ethernet support for ARM FS simul

[gem5-users] Re: Ethernet support for ARM FS simulation

Hi Gabe: I have looked at the email below, I also has the same question. As you mentioned, I just modified the FSConfig.py in function makeArmSystem with “self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, InterruptLine=1, InterruptPin=1)

[gem5-users] 答复: Unable to find destination for [0x40000008:0x4000000c] on system.iobus

I just add Ethernet object and add it to pci_device, and when I bootup with fs.py, NoncoherentXBAR debug print will print “718298670320: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 0x1c090018 cmd ReadReq 718306245195: system.iobus: recvAtomic: packet src

[gem5-users] Unable to find destination for [0x40000008:0x4000000c] on system.iobus

Hi All: I just add a ethernet object in dist-bigLITTLE.py on VEXPRESS_GEM5_V1, but AddRange debug print “fatal: Unable to find destination for [0x4008:0x400c] on system.iobus So how to config the mem range in RealView.py or in any other code ? ” The function of create Ethernet is :

[gem5-users] How to enable dist-gem5 on GEM5 20.0.0.3 on ARM64

Hi All: Any one use dist-gem5 to bootup successfully on GEM5 20.0.0.3 on ARM64? In dist-gem5 website, the example only shows for arm32, and the kernel/img/boot_emm/vexpress_emm is just matched for arm32. I want to use the latest 4.14 kernel and

[gem5-users] Re: How to add a new pcie device on GEM5

ing a look at the VirtIO device…. (I don’t know if there are better examples, more experienced people are welcome to chime in) Giacomo From: Liyichao via gem5-users mailto:gem5-users@gem5.org>> Sent: 22 October 2020 11:51 To: gem5 users mailing list mailto:gem5-users@gem5.org>> Cc: Liyi

[gem5-users] How to add a new pcie device on GEM5

Hi All: Any one has experience on how to add ad new pcie device on GEM5? This device can be just a demo device which has only a few basic operation like read,write… So if I want to add a pcie device,any config I need to realize? Or any examples?

[gem5-users] Any one bootup with fs.py in gem5 version 20.1 with dramsim3 or nvmain succuessfully

Hi All: I use gem5 20.1 ,and bootup with fs.py and dramsim3 model,but some error printed. As I know, gem5 20.1 new feature has departed the medium interface from memctrl, however, these modifications are only for the DRAM model inside gem5, I think external memory Dramsim3

[gem5-users] Why fs_bigLITTLE.py always use /dev/vda1 as its storage disks device?

Hi All: How to modify the storage device driver,virtio_blk? As I know, the device name using fs.py is /dev/sda1. Because I have met a error using fs_bigLITTLE.py when I restore from checkpoint, the below print in system.terminal accured, and fs.py will never accur.(I have

[gem5-users] 答复: How I can notify the NVMAIN model when I use “m5 resetstats” so that the NVMAIN model can also reset the stats in its model

stats in its model Hi Liyichao, you can register a callback with the Stats::registerResetCallback function in base/statistics.hh. Gabe On Mon, Oct 12, 2020 at 7:15 PM Liyichao via gem5-users mailto:gem5-users@gem5.org>> wrote: Hi All: When I use gem5 + O3 based on armv8 with NVMAIN d

[gem5-users] How I can notify the NVMAIN model when I use “m5 resetstats” so that the NVMAIN model can also reset the stats in its model

Hi All: When I use gem5 + O3 based on armv8 with NVMAIN ddr4 model, I want to know how I can notify the NVMAIN model when I use “m5 resetstats” so that the NVMAIN model can also reset the stats in its model, e.g. bandwidth, latency, because I will first run warmup for a few

[gem5-users] Are there any ideas to accelerate the speed of m5.checkpoint on disks?

Hi All: Are there any ideas to accelerate the speed of m5.checkpoint on disks? In my NVME ssd , the speed of taking checkpoint is only about 145K/s. [cid:image001.png@01D68AAD.F3323EE0] 李翼超（Charlie） 华为技术有限公司 Huawei Technologies Co., Ltd. [Company_logo]

[gem5-users] If multiple GEM5 processes that use the KVM simulation single-core are started at the same time, the performance of each KVM is affected.

Hi All: I use KVM cpu type to simulate single core, and at the same time I started about 10+~20+ KVM cpu, each KVM cpu in one GEM5 process, then the speed of per KVM cpu be slowed down heavily.If I just start one KVM cpu in GEM5 process, the speed was 1.7G instrutions per second.

[gem5-users] 答复: Supplementing experiment Data///答复: How to make scheduleInstStop() function to stop simulate at an accurate expected instructions counts for one core KVM/ATOMIC/O3 CPU simulation?

Hi All: Are there any experts who can help me to explain the features of the scheduleInstStop() function? 李翼超（Charlie） 华为技术有限公司 Huawei Technologies Co., Ltd. [Company_logo] 部门：计算系统与组件开发部 [云与计算BG] 手　　机：15858232899

[gem5-users] Supplementing experiment Data///答复: How to make scheduleInstStop() function to stop simulate at an accurate expected instructions counts for one core KVM/ATOMIC/O3 CPU simulation?

Hi All: I use the scheduleInstStop() function to let the m5.simulate() stop at a point instrutions as my ROI start, for example: 1(100M) instrutions, but when the simulate stop, I print the instructions from last start simulation to the end, the count always exceed my specified

[gem5-users] How to make scheduleInstStop() function to stop simulate at an accurate expected instructions counts for one core KVM/ATOMIC/O3 CPU simulation?

Hi All: I use the scheduleInstStop() function to let the m5.simulate() stop at a point instrutions as my ROI start, for example: 1(100M) instrutions, but when the simulate stop, I print the instructions from last start simulation to the end, the count always exceed my specified