"Shmuel Metz , Seymour J." wrote in
message news:<20111220170650.bceecf58...@smtp.patriot.net>...
> In
> ,
> on 12/20/2011
>at 04:53 PM, "Vernooij, CP - SPLXM" said:
>
> >Of course, but I suppose you know what I meant:
>
> You're welcome to suppose what you wish. Just don't be surprised wh
>From Martin Packer:
| Chaucer spelt it "cherl".
He did indeed, and he explicated his use of it very neatly in
| For vileyns sinful deeds make a cherl.
in which vileyn/villein/villain is not yet pejorative. Shane's use
was, I think, the more modern, now standard one that makes churlish is
a n
In
,
on 12/20/2011
at 04:53 PM, "Vernooij, CP - SPLXM" said:
>Of course, but I suppose you know what I meant:
You're welcome to suppose what you wish. Just don't be surprised when
your suppositions are wrong more often than they're right.
--
Shmuel (Seymour J.) Metz, SysProg and JOAT
On Tue, 20 Dec 2011 09:19:35 +0100, Vernooij, CP wrote:
>I am quite sure that pr/sm always dispatched Logical CPs and Amdahls
>MDF dispatched entire domains (their word for lpar).
If by "dispatched entire domains" you mean that all of the
logical processors for a domain were a
"Shane" wrote in message
news:<20111220123112.2a437a52@xpfs>...
> On Mon, 19 Dec 2011 09:20:16 -0500 Tom Russell wrote:
>
> > PR/SM dispatches Logical CPs not Logical Partitions.
- I am quite sure that pr/sm always dispatched Logical CPs and Amdahls
MDF dispatched en
On Tue, 20 Dec 2011 10:33:14 -0500, Shmuel Metz wrote:
>If I recall correctly, MDF was implemented in what Amdahl
>called macrocode,
That's correct. Very similar to the millicode on current IBM
mainframes. A superset of 370 instructions that ran in
system state.
>not by dedicated hardware.
On Tue, 20 Dec 2011 09:14:36 -0500, Shmuel Metz wrote:
>How did MDF detect the end of a timeslice if not by an interrupt?
That is how it detected the end of a time slice. Early MDF code
would dispatch a different domain as soon as a processor entered
a wait state. That was determined to cause
mentation for Amdahl was
significantly simpler because of the macrocode use. 3090 had to respond
with pr/sm ... but that was a significantly more complex undertaking
because there wasn't any equivalent facility and they had to fallback to
horizontal microcode.
there was also issue in the ea
Of course, but I suppose you know what I meant: PR/SM sits waiting for
an LPAR to produce an interrupt and decides then what to do next. MDF
determines that it wants to take action after a certain timeslice,
whether the domains like it or not.
The fact that the end of the timeslice might be
In
,
on 12/20/2011
at 04:15 PM, "Vernooij, CP - SPLXM" said:
>Are you serious?
Certainly. If I recall correctly, MDF was implemented in what Amdahl
called macrocode, not by dedicated hardware. So what triggered the
redispatch at the end of a time slice if not an external interrupt?
--
orks/blogs/MartinPacker
From:
"McKown, John"
To:
IBM-MAIN@bama.ua.edu,
Date:
20/12/2011 13:10
Subject:
Re: Question on PR/SM dispatcher
Sent by:
IBM Mainframe Discussion List
A "churl" is a very old word for a "peasant" or "free man". But became to
be use
can also force it. Amdahl's MDF
> >did it. The main difference was that PR/SM is interrupt driven and
> >MDF was timeslice driven.
>
> How did MDF detect the end of a timeslice if not by an interrupt?
>
> --
> Shmuel (Seymour J.) Metz, SysProg and JOAT
>
In
,
on 12/19/2011
at 09:29 AM, "Vernooij, CP - SPLXM" said:
>You don't have to wait for it, you can also force it. Amdahl's MDF
>did it. The main difference was that PR/SM is interrupt driven and
>MDF was timeslice driven.
How did MDF detect the end of a tim
esapeake Life Insurance
Company(r), Mid-West National Life Insurance Company of TennesseeSM and The
MEGA Life and Health Insurance Company.SM
> -Original Message-
> From: IBM Mainframe Discussion List
> [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Vernooij, CP - SPLXM
>
"Shane" wrote in message
news:<20111220123112.2a437a52@xpfs>...
> On Mon, 19 Dec 2011 09:20:16 -0500 Tom Russell wrote:
>
> > PR/SM dispatches Logical CPs not Logical Partitions.
>
> I wonder if it'd be considered churlish to point out this wasn't
On Mon, 19 Dec 2011 09:20:16 -0500 Tom Russell wrote:
> PR/SM dispatches Logical CPs not Logical Partitions.
I wonder if it'd be considered churlish to point out this wasn't always
the case.
Shane ...
--
For IBM-M
PR/SM dispatches Logical CPs not Logical Partitions.
So Question 1 and 2 get the same answer. Any given Logical partiton can
have some logical CPs ready to run, and pther logical CPs in the WAIT
state. The ready to run CP will be dispatched on a real CP when it is
the highest priority
You don't have to wait for it, you can also force it. Amdahl's MDF did
it. The main difference was that PR/SM is interrupt driven and MDF was
timeslice driven. Therefor it did not have to wait for the ducks to line
up, but simply took an entire domain from the processors when its time
To dispatch entire LPARs would be waiting for 2n ducks to line up in a
row: An event with progressively high latency in the n>1 case. Which is
one reason we don't do it, I guess. (The 2n ducks would be the n logicals
and n physicals.)
Martin
Martin Packer,
Mainframe Performance Consultant, zCh
"Mauri Kanter" wrote in message
news:<7558267718421282.wa.itzuviem013.net...@bama.ua.edu>...
> Thank you Jim. Crystal Clear.
>
Mauri,
I was going to reply, that your view on pr/sm was incorrect: pr/sm does
not dispatch entire LPARs, but individual processors, if the LPAR&#
Thank you Jim. Crystal Clear.
--
For IBM-MAIN subscribe / signoff / archive access instructions,
send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
> Question 1
> ==
> Does PR/SM dispatches an LPAR only when the number of physical
> processors awaiting allows to dispatch all the logical processors
> required for an LPAR simultaneously?
No.
> For example suppose my machine has 3 physical CPUs, and with 3
Great questions. I have no idea of the answers, but will be very
interested to see them!
On Sun, Dec 18, 2011 at 10:50 AM, Mauri Kanter wrote:
> Good day list
>
> I would like to understand something that is not still clear to me regarding
> PR/SM dispatching.
> Just to be clear
Good day list
I would like to understand something that is not still clear to me regarding
PR/SM dispatching.
Just to be clear I'm asking only about shared processors (not dedicated) and
with dynamically determined time slices.
I'm interested to understand the LPAR dispatching
P pool will get rid of
any dedicated CPs. That means the other LPARs cannot use any dedicated CPs.
Meanwhile, the number of logical CPs in an LPAR must be less than or equal to
the number of physical CPs.
PR/SM Planning Guide also says:
The maximum initially online logical CPs defined for a s
Thanks for correcting my erroneous impression.
>ASHARED CPs *may* be dispatched on
"DEDICATED processors if resource is available (I am sure someone will
correct me this is not true).
Assuredly.
Dedicated processors are just that.
Dedicated!
Only the lPAR they're assigned to may run work on them
>ASHARED CPs *may* be dispatched on
"DEDICATED processors if resource is available (I am sure someone will
correct me this is not true).
Assuredly.
Dedicated processors are just that.
Dedicated!
Only the lPAR they're assigned to may run work on them, regardless of the
activity.
That's why I agree
>>Because there will be only
2 PCPs available for it, however, it has 8 LCPs configured.
>No. IBM does not prevent you from defining more LP's than CP's. However
the overhead becomes excessive when the LP/CP ratio exceeds (2 to 3) to
1.
Actually, PR/SM does NOT allow this
gt; production LPAR 1
> initial LCP 8
> reserved LCP 10
> weight 40
>
>
> Are you saying that all LPARs have 8 active(shared)/10 reserved LP's
> assigned?
>
> If so, this is a bad thing to do! PR/SM overhead is excessive (only
the
> active LP'
tial LCP 8
reserved LCP 10
weight 40
The maintenance LPARs, ICF LPARs and test LPARs have similar configuration but
less weight valule specified.
Now, we plan to assign each test LPARs with 3 dedicated CPs due to some test
requirements. That is to say, the 2 test LPARs wi
follows.
production LPAR 1
initial LCP 8
reserved LCP 10
weight 40
Are you saying that all LPARs have 8 active(shared)/10 reserved LP's
assigned?
If so, this is a bad thing to do! PR/SM overhead is excessive (only the
active LP's affect the overhead).
Can
8
reserved LCP 10
weight 40
Are you saying that all LPARs have 8 active(shared)/10 reserved LP's
assigned?
If so, this is a bad thing to do! PR/SM overhead is excessive (only the
active LP's affect the overhead).
The logical/physical ratio should (ROT) not exceed 2 to
physical CPs in
total.
We have referred to the z9 PR/SM planning guide. It's saying we just need to
create new image profiles and deactive/active test LPARs. Then the changes will
be available.
Meanwhile, however, does this operation have any impact on other LPARs running
in the same CPC
hi all,
pr/sm includes the following controls:
* Global performance data control authority
* I/O configuration control authority
* Logical partition isolation
does anybody know whether there are bits in memory to detect the status of
these controls?
--
further
On Wed, 18 Aug 2010 08:10:53 -0400, Charles Mills wrote:
>Is there an API or anything similar whereby a vendor-written program could
>have visibility into a z box at the PR/SM level (other than CSRSI)? Could
>"see" and potentially make configuration changes to "the who
See "CPCs with the Sysplex Failure Manager (SFM)" on page 3-20. Use the
Customize/Delete Activation Profiles task available from the CPC
Operational Customization tasks list to open a reset or image profile to
enable cross-partition authority for an LP. The Cross partition
authority selection is l
me Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf
Of Rick Fochtman
Sent: Wednesday, August 18, 2010 5:21 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: API or visibility into PR/SM for Vendor-written programs?
---
Is there an API o
For security ,you need to enable these functions.LPARs can read other LPARs
configuration or do changes...It is needed for HD or to reset one LPAR from
another LPARs SA code as an example
-Taken from pr/sm planning guide...SB10-7153-00
Global performance data control authority
This
On 18 Aug 2010 14:22:00 -0700, in bit.listserv.ibm-main you wrote:
>---
>Is there an API or anything similar whereby a vendor-written program
>could have visibility into a z box at the PR/SM level (other than
>CSRSI)
---
Is there an API or anything similar whereby a vendor-written program
could have visibility into a z box at the PR/SM level (other than
CSRSI)? Could "see" and potentially make configuration changes to "the
hn
> Sent: Wednesday, August 18, 2010 6:12 AM
> To: IBM-MAIN@bama.ua.edu
> Subject: Re: API or visibility into PR/SM for Vendor-written programs?
>
> > -Original Message-
> > From: IBM Mainframe Discussion List On Behalf Of Charles Mills
> >
> > Thanks.
> >
&
-Original Message-
From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On
Behalf Of Chase, John
Sent: Wednesday, August 18, 2010 8:12 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: API or visibility into PR/SM for Vendor-written programs?
> -Original Message-
> Fro
3:55 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: [IBM-MAIN] API or visibility into PR/SM for Vendor-written
programs?
Thanks.
(Does anyone else find these IBM sign-on's to be inscrutable? When I go to
the links below it wants me to sign in. When I sign in it rejects my
credentials. When
@bama.ua.edu
Subject: Re: API or visibility into PR/SM for Vendor-written programs?
You may check these docs from IBM resourcelink website...
Using BCP/II API you can change weigths ,cap values enable disable softcap
/hardcap etc and exchange data as well.
Also using SNMP interfaces you can get high
> -Original Message-
> From: IBM Mainframe Discussion List On Behalf Of Charles Mills
>
> Thanks.
>
> (Does anyone else find these IBM sign-on's to be inscrutable? When I
go to
> the links below it wants me to sign in. When I sign in it rejects my
> credentials. When I click on "forgot my
: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf
Of Meral Temel (Garanti Teknoloji)
Sent: Wednesday, August 18, 2010 8:49 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: API or visibility into PR/SM for Vendor-written programs?
You may check these docs from IBM resourcelink website...
U
-MAIN@bama.ua.edu
Subject: [IBM-MAIN] API or visibility into PR/SM for Vendor-written programs?
I was asked this question by an associate who is extremely knowledgeable
relative to software virtualization but relatively unfamiliar with PR/SM
(and z/VM).
Is there an API or anything similar whereby
I was asked this question by an associate who is extremely knowledgeable
relative to software virtualization but relatively unfamiliar with PR/SM
(and z/VM).
Is there an API or anything similar whereby a vendor-written program could
have visibility into a z box at the PR/SM level (other than
]
Enviada em: sábado, 6 de fevereiro de 2010 04:17
Assunto: Re: PR/SM
>> Anyone know where to find a manual on PR/SM for z/OS? I've been looking
>> all
>> over and can't seem to find one.
>>
>I don't believe the question makes any sense -- it's like ask
On Sat, Feb 6, 2010 at 1:17 AM, Ted MacNEIL wrote:
> Instead of being pedantic, why not answer the (to me) obvious question?
>
How about Googling "pr/sm manual"? First hit. This ain't brain surgery.
Bu
>> Anyone know where to find a manual on PR/SM for z/OS? I've been looking
>> all
>> over and can't seem to find one.
>>
>I don't believe the question makes any sense -- it's like asking for a manual
>on "z10 for z/OS".
>PR/SM is
On Wed, 3 Feb 2010 16:02:42 -0600, gsg wrote:
>Anyone know where to find a manual on PR/SM for z/OS? I've been looking all
>over and can't seem to find one.
>
Resource link.
https://www-304.ibm.com/servers/resourcelink/svc03100.nsf?OpenDatabase
--
Mark Zelden
Sr. S
> -Original Message-
> From: IBM Mainframe Discussion List
> [mailto:ibm-m...@bama.ua.edu] On Behalf Of gsg
> Sent: Wednesday, February 03, 2010 4:03 PM
> To: IBM-MAIN@bama.ua.edu
> Subject: PR/SM
>
> Anyone know where to find a manual on PR/SM for z/OS? I'v
Let me rephrase my question. Where can I find information PR/SM?
--
For IBM-MAIN subscribe / signoff / archive access instructions,
send email to lists...@bama.ua.edu with the message: GET IBM-MAIN INFO
Search the archives at
On Wed, Feb 3, 2010 at 5:02 PM, gsg wrote:
> Anyone know where to find a manual on PR/SM for z/OS? I've been looking
> all
> over and can't seem to find one.
>
I don't believe the question makes any sense -- it's like asking for a
manual on "z10 for z/OS&
Anyone know where to find a manual on PR/SM for z/OS? I've been looking all
over and can't seem to find one.
TIA
--
For IBM-MAIN subscribe / signoff / archive access instructions,
send email to lists...@bama.ua.ed
On Wed, 24 Sep 2008 14:55:21 +0200, R.S.
<[EMAIL PROTECTED]> wrote:
>What does it mean "counterproductive" ?
>Assuming you really need the system and the system need in MSU is really
>small you can do the following:
>1. Assign small percentage (I've seen even sub-percent weights) despite
>it is "c
On Wed, 24 Sep 2008 07:46:56 -0500, Arthur Gutowski <[EMAIL PROTECTED]> wrote:
>On Tue, 23 Sep 2008 15:34:35 -0400, Knutson, Sam <[EMAIL PROTECTED]>
>wrote:
>
>>We have to figure out what we will be doing as we replace our smallest CEC
>with a z10 for the smallest LPARs as well.
>
>z/VM?
>
>Seriou
Arthur Gutowski wrote:
[...]
Seriously, we'll be having similar discussions, here. We have several tiny JES2
systems running alongside some comparatively huge JES3 systems and a habit
of keeping LPARs to an established "MIPS (or MSU) rating", though we've been
advised keeping an LPAR under 3-5
On Tue, 23 Sep 2008 15:34:35 -0400, Knutson, Sam <[EMAIL PROTECTED]>
wrote:
>We have to figure out what we will be doing as we replace our smallest CEC
with a z10 for the smallest LPARs as well.
z/VM?
Seriously, we'll be having similar discussions, here. We have several tiny
JES2
systems ru
On Tue, 23 Sep 2008 16:59:19 -0400, Don Deese <[EMAIL PROTECTED]> wrote:
>Reduced preemption was introduced with SP3.1. I don't think that I kept the
>microfiche for SP3.1, but I still have the microfiche for SP4.2 and Reduced
>Preemption was alive and well in SP4.2.
>
>Possibly you are confusing
>>Gee... wasn't reduced preemption with MVS/ESA V5.1 (not MVS/SP 3.1)?
Yes. Unfortunately, it removed MTTW (except for DISCRETIONARY), so where I/O
intensive workloads used to get in, when needed, since then they have to wait
on CPU intensive ones. This wrecked havoc on our batch service when we
Reduced preemption was introduced with SP3.1. I don't think that I kept the
microfiche for SP3.1, but I still have the microfiche for SP4.2 and Reduced
Preemption was alive and well in SP4.2.
Possibly you are confusing reduced preemption with the dispatcher redesign
that was available with SP5
On Tue, 23 Sep 2008 14:54:38 -0500, Mark Zelden <[EMAIL PROTECTED]>
wrote:
>On Tue, 23 Sep 2008 15:34:35 -0400, Knutson, Sam <[EMAIL PROTECTED]> wrote:
>
>
>>Managing Workloads on a Uniprocessor by Linda August 2007
>>
>>http://regions.cmg.org/regions/ncacmg/downloads/mar082007_session2.pdf
>>
>
>
On Tue, 23 Sep 2008 15:34:35 -0400, Knutson, Sam <[EMAIL PROTECTED]> wrote:
>Managing Workloads on a Uniprocessor by Linda August 2007
>
>http://regions.cmg.org/regions/ncacmg/downloads/mar082007_session2.pdf
>
Gee... wasn't reduced preemption with MVS/ESA V5.1 (not MVS/SP 3.1)?
Mark
--
Mark Ze
AM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Setting up PR/SM for very small Capacity LPARs on Fast Processors
Hi.
I'm working with migrating a customer to z9 hardware, and when it comes to
the PR/SM setup I have a few questions, which pops up from time to time I
believe.
When it comes to assignning Log
On Tue, 23 Sep 2008 12:22:27 +0200, Flemming Sigvardt
<[EMAIL PROTECTED]> wrote:
>Hi.
>
>I'm working with migrating a customer to z9 hardware, and when it comes to
>the PR/SM setup I have a few questions, which pops up from time to time I
>believe.
>
>Whe
Hi.
I'm working with migrating a customer to z9 hardware, and when it comes to
the PR/SM setup I have a few questions, which pops up from time to time I
believe.
When it comes to assignning Logical Processor to an LPAR, do we still have
a ROT of 2:1 ratio between Logical and Phy
question about PR/SM and I would be very thankful for any
answer.
- System z PR/SM is implemented as hardware and it is capability of
IBM mainframe hardware.
-
So far, so good.
- z/OS or z/VM
John Giltner writes:
>Depending on which zSeries Server you have the maximum number
>of LPARs PR/SM can create is either 15 (z990 and older) or 60
>(z9).
Here are the maximum number of LPARs available per single machine:
z900: 15
z800: 15
z990: 30
z890: 30 (*1)
z9 BC: 30 (*2)
z9 EC
---
Hi
Thank you for reading my email.
I have some question about PR/SM and I would be very thankful for any
answer.
- System z PR/SM is implemented as hardware and it is capability of
IBM mainframe hardware
[EMAIL PROTECTED] (R.S.) writes:
No.
PR/SM is microcode - a code under OS. Sometimes called "firmware.
z/OS runs in LPAR. Although it can obtaine i.e. LPAR name, it is still
"unaware" from PR/SM and LPARs features. z/OS works in "virtual
machine" (Logical PARtition) a
legolas wood wrote:
Hi
Thank you for reading my email.
I have some question about PR/SM and I would be very thankful for any
answer.
- System z PR/SM is implemented as hardware and it is capability of IBM
mainframe hardware.
Not really, as RS stated, PR/SM is microcode, special "sof
legolas wood wrote:
Hi
Thank you for reading my email.
I have some question about PR/SM and I would be very thankful for any
answer.
- System z PR/SM is implemented as hardware and it is capability of IBM
mainframe hardware.
- z/OS or z/VM are interfaces (command line or GUI ) that let us use
Hi
Thank you for reading my email.
I have some question about PR/SM and I would be very thankful for any
answer.
- System z PR/SM is implemented as hardware and it is capability of IBM
mainframe hardware.
- z/OS or z/VM are interfaces (command line or GUI ) that let us use the
above capability
On Fri, 2007-06-15 at 14:47 -0500, Al Sherkow wrote:
> You're really off here...
>
> The premise of your question is wrong, so it's hard to answer the question.
As Jim and Al have said, things don't work the way you postulated. In
fact, to use the vernacular - "you've got it arse about".
When
Rick --
You're really off here. PR/SM does not suspend logical processors for
"minutes to hours at a time". As Jim Mulder wrote Wednesday, it just does
not work that way. The suspension of the processor is a short duration. The
time-slicing generally dynamic and all the logical
Shane:
I appreciate the reference and have now read portions dealing with
capping. It just never quite got to the point of telling for certain
how PR/SM cuts off service, but it hints at it being a non-dispatch of
an LCP by a real CP.
I was not surprised by capping extending into lunch. What
There used to be a "PR/SM Planning" manual available via ResouceLink
that explained LPAR dispatch pretty well. Haven't looked in a while, but
it didn't cover soft capping last I looked.
The redbook site is always worth a quick search.
Remember (soft) capping is based on a 4 hour r
IBM Mainframe Discussion List wrote on 06/13/2007
12:37:38 PM:
> Ordinarily, as PR/SM dispatches CPs to LPARs, a Logical CP may have a
> task dispatched to it, but beneath it, it has no physical CP.
> Milliseconds later, the CP may well be back and the task actually
runs.
> But whe
IBM Mainframe Discussion List wrote on 06/13/2007
12:37:38 PM:
> Ordinarily, as PR/SM dispatches CPs to LPARs, a Logical CP may have a
> task dispatched to it, but beneath it, it has no physical CP.
> Milliseconds later, the CP may well be back and the task actually runs.
> But whe
groups of LPARs under an umbrella cap, which someone may have beta
tested by now. We are planning soft capping only, no hardware capping,
and wonder about its effects on our new hardware and reconfigured
systems.
Ordinarily, as PR/SM dispatches CPs to LPARs, a Logical CP may have a
task dispatched to
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