Re: Difference between STSI instruction and SYSEVENT QVS?

2024-02-04 Thread Welke, John
Just following on from Peter's reply, we recently activated Tailored Fit Pricing (TFP) on a z16 and found that STSI reports the new field, "Model-Variable-Capacity", but SYSEVENT QVS knows nothing about this field. Also, we were told by IBM that there was an MCL change, which we applied to

Re: SDSF PS Command column

2024-02-04 Thread Jon Perryman
On Sun, 4 Feb 2024 10:04:05 -0600, Paul Gilmartin wrote: >On Sat, 3 Feb 2024 21:47:56 -0600, Mark Zelden wrote: >>Agree to disagree. I haven't checked the doc and maybe it isn't documented >>that that field or >>any field is limited to 40 characters, but it is not a bug to be fixed. >> >I

Re: SDSF PS Command column

2024-02-04 Thread Jon Perryman
On Sat, 3 Feb 2024 09:24:07 +, Rob Scott wrote: >SDSF calls the BPXEKDA service returns truncated command information. Since BPXEKDA doesn't need the OMVS segment for the first 40 bytes of the command, why does it need it for the rest of the command? Isn't it just a null terminated field

Re: Registers in the RB

2024-02-04 Thread Seymour J Metz
CDE is irrelevant; an exit from an RB always gets the registers from the current registers and the exiting RB, and always gets the PSW from the previous RB. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר

Re: Registers in the RB

2024-02-04 Thread Joseph Reichman
That for all interrupts PSW and CDE if one exits is in old register in new Thanks > On Feb 4, 2024, at 6:40 PM, Seymour J Metz wrote: > > Yes, general registers go in the new RB, PSW in the old. Whent the task is > not running the newest RB holds the PSW and the TCB holds the general >

Re: Registers in the RB

2024-02-04 Thread Seymour J Metz
Yes, general registers go in the new RB, PSW in the old. Whent the task is not running the newest RB holds the PSW and the TCB holds the general registers. I havent checked how the top halves are handled. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח

Re: Where are Unix reason codes over 7371 documented

2024-02-04 Thread Mark Jacobs
BPXMTEXT is shipped in SYS1.SBPXEXEC and must be in SYSEXEC or SYSPROC to use. Mark Jacobs Sent from ProtonMail, Swiss-based encrypted email. GPG Public Key - https://api.protonmail.ch/pks/lookup?op=get=markjac...@protonmail.com On Sunday, February 4th, 2024 at 3:06 PM, Phil Smith III

Re: Where are Unix reason codes over 7371 documented

2024-02-04 Thread Phil Smith III
Colin Paice wrote: >tso command bpxmtext 7663730c I get: COMMAND BPXMTEXT NOT FOUND ? -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN

Re: Registers in the RB

2024-02-04 Thread Joseph Reichman
And they are in the manual you previously Posted ? Just for clarity sake Just ran a small test For the interrupt PSW which in the case of some PRB s might have a cde The registers that go along with that RBOPSW Are always in the next rb Regardless of the cause of the interrupt Hope

Re: Registers in the RB

2024-02-04 Thread Seymour J Metz
Yes, expressed in hexadecimal. Systems Codes has a complete list of program interrupt codes that can cause an S0C4 if not intercepted. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From:

Re: Registers in the RB

2024-02-04 Thread Seymour J Metz
S0C4 was originally only for IC04, and in OS/VS it was only IC04, IC10 and IC11, but nowadays it can also be because of, e.g. IC28. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM

Re: Registers in the RB

2024-02-04 Thread Joseph Reichman
 Seymour When you say for example IC10 you are referring what would be in RBINTCOD correct ? > On Feb 4, 2024, at 11:33 AM, Seymour J Metz wrote: > Since OS/VS, interrupt code 04 is less common amd an S0C4 is more likely to > be due to e.g., IC10, IC11. In MVT it's always IC04. > > -- >

Re: Registers in the RB

2024-02-04 Thread Seymour J Metz
Since OS/VS, interrupt code 04 is less common amd an S0C4 is more likely to be due to e.g., IC10, IC11. In MVT it's always IC04. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM

Re: Where are Unix reason codes over 7371 documented

2024-02-04 Thread Kirk Wolf
RE: decoding UNIX reason codes. It's a bit of a mess. You need to carefully read Chapter 3 "Description and location information". Eventually you fall through and find the errno2: 730C JRNetAccessDenied The user is not permitted to communicate with the specified network. Action: If access

Re: Registers in the RB

2024-02-04 Thread Joseph Reichman
I’m trying to understand so that u don’t mess things up The way Seymour explained it For purposes of example the hardware gives control to the program check FLIH for interrupt code 4 the program check FLIH issues ABEND abend code 0C4 reason 4 Joe Reichman On Sun, Feb 4, 2024 at 11:06 AM

Re: Registers in the RB

2024-02-04 Thread Binyamin Dissen
On Sun, 4 Feb 2024 10:29:59 -0500 Joseph Reichman wrote: :>But thought S0C4 is a program check It is. It may be a pic-4,-10, or -11. If PIC-4, PSW was updated. An error recovery routine that messes up things is worse than none. -- Binyamin Dissen http://www.dissensoftware.com Director,

Re: SDSF PS Command column

2024-02-04 Thread Paul Gilmartin
On Sat, 3 Feb 2024 21:47:56 -0600, Mark Zelden wrote: > >Agree to disagree. I haven't checked the doc and maybe it isn't documented >that that field or >any field is limited to 40 characters, but it is not a bug to be fixed. It >could be enhanced >in the service stream, but it is most

Re: Registers in the RB

2024-02-04 Thread Seymour J Metz
No, if you get a system BEND 0C1 then the program interrupt code was 01; the is no program interrupt code 0C1. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Discussion

Re: Registers in the RB

2024-02-04 Thread Seymour J Metz
The cited OS/VS2 PLM is for release 3.7; It's backlevel for the MVS turnkey system, but I don't know of an online repository that has the 3.8 version with SU updates. Similarly, the cited OS/360 MVT PLM is for R17, way back-level for the 21,8 turnkey system, and I don' know of a more recent

Re: Registers in the RB

2024-02-04 Thread Joseph Reichman
Can you for proposed that I understand differentiate between a program check and abend S0C1 is a program check S0C4 is not I understand the abend SVC 13 is not a program check But thought S0C4 is a program check Thank you > On Feb 4, 2024, at 10:27 AM, Joseph Reichman wrote: > >

Re: Registers in the RB

2024-02-04 Thread Joseph Reichman
Seymour thanks This Manuel is from from 1987 ? Micheal was 1976 Is this still valid ? I’ll read it in really not looking for easy way out Peter R said he answered in this general thread I did look back before posting The only thing I noticed was in the case of an abend for example 0F8

Re: Registers in the RB

2024-02-04 Thread Seymour J Metz
Where registers are stored depends on the type of interrupt, and there are five types, not just two. In the case of a program check*, what happens depends on the type, state and whether it is covered by a match [E]SPIE. In the case of a program check resulting in an S0Cx or S0Dx ABEND, the PSW

Re: Registers in the RB

2024-02-04 Thread Seymour J Metz
The processing for SYNCH is the same whether it is issued from a PRB or an SVRB; the caller's PSW goes into the old RB and the caller's general registers go into the new PRB.

Re: Registers in the RB

2024-02-04 Thread Michael Stein
On Sat, Feb 03, 2024 at 08:20:08PM -0500, Joseph Reichman wrote: > It was my understanding probably erroneously that when a RB I guess I am > talking about a PRB gets interrupted and that can happen in one of two > instances > > 1)An SVC > 2)A Program check e.g. S0C1,4, There are many

Re: SDSF able to provide a display/panel for System Recovery Boost (SRB) for Middleware Subsystems on z16?

2024-02-04 Thread Rob Scott
Roger SDSF for z/OS 3.1 introduces the Event Log (ELOG) feature and one of the intercepted data points is boost activity. If boost is used while the SDSF server is active, we will notice it and add a record to the event log and you can view using the ELOG command. Rob Scott Rocket Software

Re: Registers in the RB

2024-02-04 Thread Peter Relson
It was my understanding probably erroneously that when a RB I guess I am talking about a PRB gets interrupted and that can happen in one of  two instances 1)    An SVC 2)    A Program check e.g. S0C1,4 It is true that the understanding is erroneous. There are many more cases where any RB can be

Re: Difference between STSI instruction and SYSEVENT QVS?

2024-02-04 Thread Peter Relson
How about: STSI returns a lot of data that is not returned by SYSEVENT QVS? (or so I assume) How about: SYSEVENT QVS returns a lot of data that is not provided by STSI? (or so I assume) Now, if you were to ask about specific fields in SYSEVENT QVS, I think for certain ones the answer is