Peter
Thank you for explaining it I really think I get it
I agree I can generalize a recovery I am changing file192 thinking of it as
estate
Including cases where there is abend in
1) SVC
2) PC
For these I am going to locate the user registers and off set
And include for all cases whe
on List on behalf of
Joseph Reichman
:>> Sent: Sunday, February 4, 2024 11:45 AM
:>> To: IBM-MAIN@LISTSERV.UA.EDU
:>> Subject: Re: Registers in the RB
:>>
:>>
:>> Seymour
:>>
:>> When you say for example IC10 you are referring what would be in RBINT
The fact that registers are saved (or at least land) in the "new RB" and the
PSW in the "old RB" was described many posts earlier. That applies in all cases
where a new (not "first") RB is created. Note that just when that saving
happens can be kind of funky for a case such as XCTL(X).
The prob
From: IBM Mainframe Discussion List on behalf of
Joseph Reichman
Sent: Sunday, February 4, 2024 6:45 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Registers in the RB
That for all interrupts PSW and CDE if one exits is in old register in new
Thanks
> On Feb 4, 2024, at 6:40
sion List on behalf of
> Joseph Reichman
> Sent: Sunday, February 4, 2024 12:53 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Registers in the RB
>
> And they are in the manual you previously
>
> Posted ?
>
>
> Just for clarity sake
>
> Just ran a s
יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
From: IBM Mainframe Discussion List on behalf of
Joseph Reichman
Sent: Sunday, February 4, 2024 12:53 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Registers in the RB
And they are in the manual you previously
Posted ?
Just for
gt; http://mason.gmu.edu/~smetz3
> עַם יִשְׂרָאֵל חַי
> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
>
> From: IBM Mainframe Discussion List on behalf of
> Joseph Reichman
> Sent: Sunday, February 4, 2024 11:45 AM
> To: IBM-MAIN@LI
: IBM Mainframe Discussion List on behalf of
Joseph Reichman
Sent: Sunday, February 4, 2024 11:45 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Registers in the RB
Seymour
When you say for example IC10 you are referring what would be in RBINTCOD
correct ?
> On Feb 4, 2024, at 11:33 AM, Seymou
Mainframe Discussion List on behalf of
Binyamin Dissen
Sent: Sunday, February 4, 2024 11:05 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Registers in the RB
On Sun, 4 Feb 2024 10:29:59 -0500 Joseph Reichman
wrote:
:>But thought S0C4 is a program check
It is.
It may be a pic-4,-10, or -11.
unday, February 4, 2024 11:11 AM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Registers in the RB
>
> I’m trying to understand so that u don’t mess things up
>
> The way Seymour explained it
>
> For purposes of example the hardware gives control to the program check
> FLIH for inte
: IBM Mainframe Discussion List on behalf of
Joseph Reichman
Sent: Sunday, February 4, 2024 11:11 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Registers in the RB
I’m trying to understand so that u don’t mess things up
The way Seymour explained it
For purposes of example the hardware gives contr
I’m trying to understand so that u don’t mess things up
The way Seymour explained it
For purposes of example the hardware gives control to the program check
FLIH for interrupt code 4 the program check FLIH issues ABEND abend code
0C4 reason 4
Joe Reichman
On Sun, Feb 4, 2024 at 11:06 AM Binyam
On Sun, 4 Feb 2024 10:29:59 -0500 Joseph Reichman
wrote:
:>But thought S0C4 is a program check
It is.
It may be a pic-4,-10, or -11. If PIC-4, PSW was updated.
An error recovery routine that messes up things is worse than none.
--
Binyamin Dissen
http://www.dissensoftware.com
Director, Dis
List on behalf of
Joseph Reichman
Sent: Sunday, February 4, 2024 10:29 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Registers in the RB
Can you for proposed that I understand differentiate between a program check
and abend
S0C1 is a program check S0C4 is not
I understand the abend SVC 13 is
LISTSERV.UA.EDU
Subject: Re: Registers in the RB
Seymour thanks
This Manuel is from from 1987 ?
Micheal was 1976
Is this still valid ?
I’ll read it in really not looking for easy way out
Peter R said he answered in this general thread
I did look back before posting
The only thing I noticed was
pervisor_Control_Jun1987.pdf>
>> is newer.
>>
>> Sometimes they get better.
>>
>> --
>> Shmuel (Seymour J.) Metz
>> http://mason.gmu.edu/~smetz3
>> עַם יִשְׂרָאֵל חַי
>> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>>
>> __________
http://mason.gmu.edu/~smetz3
> עַם יִשְׂרָאֵל חַי
> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
>
> From: IBM Mainframe Discussion List on behalf of
> Michael Stein
> Sent: Sunday, February 4, 2024 4:06 AM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Su
Mainframe Discussion List on behalf of
Joseph Reichman
Sent: Saturday, February 3, 2024 8:20 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Registers in the RB
It was my understanding probably erroneously that when a RB I guess I am
talking about a PRB gets interrupted and that can happen in one of two
in
Sent: Sunday, February 4, 2024 4:06 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Registers in the RB
On Sat, Feb 03, 2024 at 08:20:08PM -0500, Joseph Reichman wrote:
> It was my understanding probably erroneously that when a RB I guess I am
> talking about a PRB gets interrupted and that can
On Sat, Feb 03, 2024 at 08:20:08PM -0500, Joseph Reichman wrote:
> It was my understanding probably erroneously that when a RB I guess I am
> talking about a PRB gets interrupted and that can happen in one of two
> instances
>
> 1)An SVC
> 2)A Program check e.g. S0C1,4,
There are many in
It was my understanding probably erroneously that when a RB I guess I am
talking about a PRB gets interrupted and that can happen in one of two
instances
1) An SVC
2) A Program check e.g. S0C1,4
It is true that the understanding is erroneous. There are many more cases where
any RB can be i
It was my understanding probably erroneously that when a RB I guess I am
talking about a PRB gets interrupted and that can happen in one of two
instances
1) An SVC
2) A Program check e.g. S0C1,4,
Then if the interrupt is because of an SVC the program registers will be
saved in the new
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