== Series Details ==
Series: drm/i915/gt: Automate CCS Mode setting during engine resets (rev4)
URL : https://patchwork.freedesktop.org/series/132932/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14668_full -> Patchwork_132932v4_full
==
== Series Details ==
Series: drm/i915/gt: Automate CCS Mode setting during engine resets (rev4)
URL : https://patchwork.freedesktop.org/series/132932/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14668 -> Patchwork_132932v4
== Series Details ==
Series: drm/i915/gt: Automate CCS Mode setting during engine resets (rev4)
URL : https://patchwork.freedesktop.org/series/132932/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
== Series Details ==
Series: drm/i915/gt: Automate CCS Mode setting during engine resets (rev4)
URL : https://patchwork.freedesktop.org/series/132932/
State : warning
== Summary ==
Error: dim checkpatch failed
523d06a4a2c2 drm/i915/gt: Automate CCS Mode setting during engine resets
-:20: WARNI
On Thu, Apr 25, 2024 at 11:22:30AM GMT, Matt Roper wrote:
On Thu, Apr 25, 2024 at 11:16:09AM -0700, Lucas De Marchi wrote:
Contrary to i915, in xe ADL-N is kept as a different platform, not a
subplatform of ADL-P. Since the display side doesn't need to
differentiate between P and N, i.e. IS_ALDE
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: bb7a2467e6beef44a80a17d45ebf2931e7631083 Add linux-next specific
files for 20240426
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202404262217.dt4hoodh-...@intel.com
Error
Hi Animesh,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm/drm-next
drm-exynos/exynos-drm-next next-20240426]
[cannot apply to drm-intel/for-linux-next-fixes linus/master v6.9-rc5]
[If your
On 4/23/2024 6:23 PM, Janusz Krzysztofik wrote:
From: Chris Wilson
The breadcrumbs use a GT wakeref for guarding the interrupt, but are
disarmed during release of the engine wakeref. This leaves a hole where
we may attach a breadcrumb just as the engine is parking (after it has
parked its bre
On 26/04/2024 16:47, Lucas De Marchi wrote:
On Wed, Apr 24, 2024 at 01:41:59PM GMT, Ryszard Knop wrote:
The drm-intel repo is moving from the classic fd.o git host to GitLab.
Update its location with a URL matching other fd.o GitLab kernel trees.
Signed-off-by: Ryszard Knop
Acked-by: Luca
On Wed, Apr 24, 2024 at 01:41:59PM GMT, Ryszard Knop wrote:
The drm-intel repo is moving from the classic fd.o git host to GitLab.
Update its location with a URL matching other fd.o GitLab kernel trees.
Signed-off-by: Ryszard Knop
Acked-by: Lucas De Marchi
Also Cc'ing maintainers
---
MAIN
On Fri, Apr 26, 2024 at 01:51:36PM +0300, Jani Nikula wrote:
> Clean up i915_reg.h.
>
> v2: Drop chicken regs and comments (Ville)
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> drivers/gpu/drm/i915/display/intel_fbc
On Fri, 26 Apr 2024, Jani Nikula wrote:
> Hey all, it's time to stop using the implicit dev_priv local variable in
> register macros. Yes, this is huge. It's also (almost) completely
> scripted.
Okay, I was first going to send the entire series, but chickened out and
hit ^C when git send-email wa
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_HSYNC register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/display/intel
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_HBLANK register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 7 ---
drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_HTOTAL register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/display/intel
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_RES2_G4X register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 3 ++-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 3 insertion
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_RES1_I915 register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 3 ++-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 3 insertio
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_BLUE register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+),
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_GREEN register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+)
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_RED register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+),
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_5_IVB register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+)
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_4_IVB register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+)
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_3_IVB register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+)
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_2_IVB register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+)
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_1_IVB register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 3 insertions(
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_CTL register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 12 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 7 insertions(+)
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PALETTE register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c | 29 ++
drivers/gpu/drm/i915/i915_reg.h| 2 +-
2 files changed, 20 insertions(+)
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DPLL register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 21 -
.../drm/i915/display/intel_display_power.c| 2 +-
.../i915/display/intel_display_power_well.c
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DPLL_MD register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dpll.c | 18 +++---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 12 insertions(+), 8 de
Hey all, it's time to stop using the implicit dev_priv local variable in
register macros. Yes, this is huge. It's also (almost) completely
scripted.
Thoughts?
BR,
Jani.
Here's the script:
#!/bin/bash
set -e
# Find all the registers implicitly relying
Hi,
On Fri, Apr 26, 2024 at 02:07:23AM +0200, Andi Shyti wrote:
> We missed setting the CCS mode during resume and engine resets.
> Create a workaround to be added in the engine's workaround list.
> This workaround sets the XEHP_CCS_MODE value at every reset.
>
> The issue can be reproduced by ru
== Series Details ==
Series: drm/i915: i915_reg.h cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/132381/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14663 -> Patchwork_132381v2
Summary
---
**SUCCESS
== Series Details ==
Series: drm/i915: i915_reg.h cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/132381/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1
Clean up i915_reg.h.
v2: Drop a redundant comment (Ville)
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
.../gpu/drm/i915/display/intel_sprite_regs.h | 348 ++
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1
Clean up i915_reg.h.
v2: Drop chicken regs and comments (Ville)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
drivers/gpu/drm/i915/display/intel_fbc_regs.h | 120 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +
drivers/gpu/drm/i91
For some reason the paletter registers were missed when adding
intel_color_regs.h. Finish the job. Adjust some comments while at it.
v2: Fix comments (Ville)
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_color_regs.h | 30 ++-
driver
There are too few registers to warrant a dedicated file for LPE audio
regs, but the audio reg file is better than i915_reg.h.
v2: Rebase
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_audio_regs.h | 16
drivers/gpu/drm/i915/display
v2 of https://lore.kernel.org/r/cover.1712933479.git.jani.nik...@intel.com
Jani Nikula (4):
drm/i915/audio: move LPE audio regs to intel_audio_regs.h
drm/i915/color: move palette registers to intel_color_regs.h
drm/i915/display: split out intel_fbc_regs.h from i915_reg.h
drm/i915/display:
On Mon, 22 Apr 2024, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: VLV/CHV DPIO register cleanup
> URL : https://patchwork.freedesktop.org/series/132691/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_14624 -> Patchwork_132691v1
> ===
== Series Details ==
Series: drm/i915/gt: Automate CCS Mode setting during engine resets (rev3)
URL : https://patchwork.freedesktop.org/series/132932/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14662 -> Patchwork_132932v3
== Series Details ==
Series: drm/i915/gt: Automate CCS Mode setting during engine resets (rev3)
URL : https://patchwork.freedesktop.org/series/132932/
State : warning
== Summary ==
Error: dim checkpatch failed
42db64e85eff drm/i915/gt: Automate CCS Mode setting during engine resets
-:20: WARNI
== Series Details ==
Series: drm/i915/mtl: Update workaround 14018778641 (rev4)
URL : https://patchwork.freedesktop.org/series/119517/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14662 -> Patchwork_119517v4
Summary
--
Hi @I915-ci-infra,
On Thursday, 25 April 2024 19:29:17 CEST Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/gt: Disarm breadcrumbs if engines are already idle (rev2)
> URL : https://patchwork.freedesktop.org/series/132786/
> State : failure
>
> == Summary ==
>
> CI Bug Log - chan
ig
(https://download.01.org/0day-ci/archive/20240426/202404261542.p0fckhhm-...@intel.com/config)
compiler: loongarch64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build):
(https://download.01.org/0day-ci/archive/20240426/202404261542.p0fckhhm-...@intel.com/reproduce)
If you fix the issue in
Posted V5 that change the order of the existing flow.
Found Tejas' email address is incorrect. Will correct in V6.
Gareth
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, April 25, 2024 7:31 PM
> To: Yu, Gareth ; intel-gfx@lists.freedesktop.org
> Cc: Yu, Gareth
> Subject: Re
The WA should be extended to cover VDBOX engine. We found that
28-channels 1080p VP9 encoding may hit this issue.
Signed-off-by: Chen, Angus
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/driver
Hi Dave & Sima,
Here's the drm-intel-gt-next PR for v6.10 in one shot.
We are adding a new uAPI for Mesa to request higher GT frequency for
compute contexts on GuC platform.
Then there is a W/A for DG2 to move to fixed CCS load balancing and
make all DG2 SKUs appear with single CCS with all the
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