> -Original Message-
> From: De Marchi, Lucas
> Sent: Wednesday, August 23, 2023 10:07 AM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D ; Srivatsa, Anusha
> ; De Marchi, Lucas
> Subject: [PATCH 22/42] drm/i915/xe2lpd:
t ready; we need to make sure this doesn't cause the
> display code to go back to trying to write this register.
>
> Signed-off-by: Matt Roper
> Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
> 1 file cha
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, July 26, 2023 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
> Srivatsa, Anusha ; Atwood, Matthew S
> ; Roper, Matthew D
> ; Bhadane,
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, July 26, 2023 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
> Srivatsa, Anusha ; Atwood, Matthew S
> ; Roper, Matthew D
> ; Bhadane,
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, July 26, 2023 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
> Srivatsa, Anusha ; Atwood, Matthew S
> ; Roper, Matthew D
> ; Bhadane,
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, July 26, 2023 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
> Srivatsa, Anusha ; Atwood, Matthew S
> ; Roper, Matthew D
> ; Bhadane,
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, July 26, 2023 12:33 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
> Srivatsa, Anusha ; Atwood, Matthew S
> ; Roper, Matthew D
> ; Bhadane,
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, July 26, 2023 12:33 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
> Srivatsa, Anusha ; Atwood, Matthew S
> ; Roper, Matthew D
> ; Bhadane,
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, July 26, 2023 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
> Srivatsa, Anusha ; Atwood, Matthew S
> ; Roper, Matthew D
> ; Bhadane,
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, July 26, 2023 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
> Srivatsa, Anusha ; Atwood, Matthew S
> ; Roper, Matthew D
> ; Bhadane,
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, July 26, 2023 12:33 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
> Srivatsa, Anusha ; Atwood, Matthew S
> ; Roper, Matthew D
> ; Bhadane,
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, July 26, 2023 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
> Srivatsa, Anusha ; Atwood, Matthew S
> ; Roper, Matthew D
> ; Bhadane,
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, July 26, 2023 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
> Srivatsa, Anusha ; Atwood, Matthew S
> ; Roper, Matthew D
> ; Bhadane,
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, July 26, 2023 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
> Srivatsa, Anusha ; Atwood, Matthew S
> ; Roper, Matthew D
> ; Bhadane,
I Like the acronym replacement approach - despite making the macro names
longer, it is consistent with how platform is referred everywhere in the driver.
For that,
Reviewed-by: Anusha Srivatsa
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Monday, July 10, 202
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Friday, June 30, 2023 4:40 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
> Srivatsa, Anusha ; Bhadane, Dnyaneshwar
>
> Subject: [v2] drm/i915/mtl: s/MTL
> -Original Message-
> From: Jani Nikula
> Sent: Tuesday, June 20, 2023 9:31 AM
> To: Bhadane, Dnyaneshwar ; intel-
> g...@lists.freedesktop.org
> Cc: Bhadane, Dnyaneshwar ; Srivatsa,
> Anusha ; Tvrtko Ursulin
> ; Joonas Lahtinen
>
> Subject: Re: [In
SL and EHL,
> and there's no point in one of them being an acronym and the other one not.
>
> And IS_JASPERLAKE_ELKHARTLAKE() would be too long.
>
Agreed on the long name.
Given that we are not touching Elkhartlake in this series, we can probably skip
jasperlake too?
Anusha
> BR,
> Jani.
>
> --
> Jani Nikula, Intel Open Source Graphics Center
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S ; Srivatsa, Anusha
> ; Bhadane, Dnyaneshwar
>
> Subject: [PATCH 00/11] Replace acronym with full
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Thursday, June 15, 2023 2:54 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha
> Subject: [PATCH 10/11] drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and
> subplatform defines
>
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S ; Srivatsa, Anusha
> ; Bhadane, Dnyaneshwar
>
> Subject: [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P fo
Apart from the platform subject prefix,
Reviewed-by: Anusha Srivatsa
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S ; Srivatsa, Anusha
> ; Bhadane, Dnyane
mentioning in the previous patches that gave a
r-b to.
Apart from the above mentioned platform prefix feedback,
Reviewed-by: Anusha Srivatsa
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc:
Reviewed-by: Anusha Srivatsa
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S ; Srivatsa, Anusha
> ; Bhadane, Dnyaneshwar
>
> Subject: [PATCH 04/11] drm/i9
Reviewed-by: Anusha Srivatsa
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S ; Srivatsa, Anusha
> ; Bhadane, Dnyaneshwar
>
> Subject: [PATCH 03/11] drm/i9
Reviewed-by: Anusha Srivatsa
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S ; Srivatsa, Anusha
> ; Bhadane, Dnyaneshwar
>
> Subject: [PATCH 02/11] drm/i9
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S ; Srivatsa, Anusha
> ; Bhadane, Dnyaneshwar
>
> Subject: [PATCH 01/11] drm/i915/TGL: s/TGL/TIGERLAKE fo
+Tvrtko
+Joonas
> -Original Message-
> From: Jani Nikula
> Sent: Monday, June 5, 2023 11:29 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for
> display and graphics step
>
> -Original Message-
> From: Jani Nikula
> Sent: Monday, June 5, 2023 8:14 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P for
> display and graphics step
>
> On Tue, 3
Replace all occurences of ADL -> ALDERLAKE in
platform and subplatform defines. This way there is a
consistent pattern to how platforms are referred. While
the change is minor and could be combined to have lesser patches,
splitting to per subpaltform for easier cherrypicks, if needed.
Anu
Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915
Driver refers to the platfrom Alderlake S as ADLS in places
and ALDERLAKE_S in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 2 +-
drivers/gpu/drm/i915
Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_step.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu
Driver refers to the platfrom Alderlake P as ADLP in places
and ALDERLAKE_P in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm
Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
> -Original Message-
> From: Lisovskiy, Stanislav
> Sent: Monday, January 30, 2023 5:59 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Lisovskiy, Stanislav ; Saarinen, Jani
> ; Srivatsa, Anusha
> Subject: [PATCH] drm/i915: Implement workaround for CDCLK
ss. This
> allows to
> remove _MMIO_PLL3() that is now unused.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
> ---
> .../drm/i915/display/intel_display_reg_defs.h | 1 -
> drivers/gpu/drm/i915/i915_reg.h | 59 +--
> 2 files ch
> -Original Message-
> From: De Marchi, Lucas
> Sent: Monday, January 23, 2023 9:16 AM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Jani Nikula
> ; De Marchi, Lucas
> Subject: [PATCH v2.1] drm/i915: Add _PICK_EVE
> -Original Message-
> From: Jani Nikula
> Sent: Monday, January 23, 2023 3:01 AM
> To: De Marchi, Lucas ; Srivatsa, Anusha
>
> Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_
0xa100
> + * #define FOO(x)_MMIO(_PICK_EVEN_RANGES(x, 3,
> \
> + * _FOO_A, _FOO_B,
> \
> + * _SUPER_FOO_A, _SUPER_FOO_B))
> + *
> + * This exp
rm/i915: Convert PALETTE() to
> _PICK_EVEN_2RANGES()
>
> PALETTE() can use _PICK_EVEN_2RANGES instead of _PICK, which reduces the
> size and is safer.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/i915_reg.h | 9 +
> 1 file
5: Convert MBUS_ABOX_CTL() to
> _PICK_EVEN_2RANGES()
>
> MBUS_ABOX_CTL() can use _PICK_EVEN_2RANGES instead of _PICK, which
> reduces the size and is safer.
>
> Signed-off-by: Lucas De Marchi
Looks good!
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/i915_reg.h |
] drm/i915: Convert _FIA() to
> _PICK_EVEN_2RANGES()
>
> _FIA() can use _PICK_EVEN_2RANGES instead of _PICK, which reduces the size
> and is safer.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_mg_phy_regs.h | 4 +++
hex filename
> 4026288 1857036984 4218975 40605f
> build64/drivers/gpu/drm/i915/i915.o.old
> 4025496 1857036984 4218183 405d47
> build64/drivers/gpu/drm/i915/i915.o.new
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
> ---
> dr
Verified that the new macro evaluates to the right register offsets.
Reviewed-by: Anusha Srivatsa
> -Original Message-
> From: Intel-gfx On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi,
Changes look good.
Reviewed-by: Anusha Srivatsa
> -Original Message-
> From: Intel-gfx On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas ; dri-
> de...@lists.freedesktop.org
> -Original Message-
> From: Lisovskiy, Stanislav
> Sent: Thursday, December 15, 2022 2:14 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> Subject: Re: [Intel-gfx] [PATCH 1/1] drm/i915: Implement workaround for
> CDCLK PLL disab
> -Original Message-
> From: Lisovskiy, Stanislav
> Sent: Wednesday, December 14, 2022 2:31 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> Subject: Re: [Intel-gfx] [PATCH 1/1] drm/i915: Implement workaround for
> CDCLK PLL disab
. If it is MTL or DG2, then it will have HAS_CDCLK_SQUASH set to
true always. Shouldn't vco be 0 instead of > 0. The commit message says the
hang can be observed when moving from 0 to > 0 vco.
Anusha
> +}
> +
> static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>
Thanks, looked at the rest of the platforms in the file and the changes look
good.
Reviewed-by: Anusha Srivatsa
> -Original Message-
> From: Sousa, Gustavo
> Sent: Tuesday, November 22, 2022 10:06 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> S
DMC_PATH DMC_PATH(dg2, 2, 08)
> +#define DG2_DMC_VERSION_REQUIRED DMC_VERSION(2, 8)
^this should be
(2,08)
Anusha
> MODULE_FIRMWARE(DG2_DMC_PATH);
>
> #define ADLP_DMC_PATHDMC_PATH(adlp, 2, 16)
> --
> 2.38.1
MTL supports both squash and crawl.
Cc: Clint Taylor
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index cf3b28d71d2b..d82f118809e9
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22
of
intel_modeset_calc_cdclk() which is directly in
the path of the sanitize() function (Ville)
v3: remove unwanted parenthesis(Ville)
Cc: Ville Syrjälä
Cc: Matt Roper
Suggested-by: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13
better looking (Ville)
v6: MTl should not follow PUnit mailbox communication as the rest of
gen11+ platforms.(Anusha)
Cc: Clint Taylor
Cc: Balasubramani Vivekanandan
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 181 +-
of
intel_modeset_calc_cdclk() which is directly in
the path of the sanitize() function (Ville)
v3: remove unwanted parenthesis(Ville)
Cc: Ville Syrjälä
Cc: Matt Roper
Suggested-by: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22
better looking (Ville)
v6: MTl should not follow PUnit mailbox communication as the rest of
gen11+ platforms.(Anusha)
Cc: Clint Taylor
Cc: Balasubramani Vivekanandan
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 177 +-
> -Original Message-
> From: Roper, Matthew D
> Sent: Wednesday, November 16, 2022 10:44 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Vivekanandan, Balasubramani
>
> Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915/display: Do both crawl and
&
ooking (Ville)
v6: MTl should not follow PUnit mailbox communication as the rest of
gen11+ platforms.(Anusha)
Cc: Clint Taylor
Cc: Balasubramani Vivekanandan
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 175 +
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22
of
intel_modeset_calc_cdclk() which is directly in
the path of the sanitize() function (Ville)
v3: remove unwanted parenthesis(Ville)
Cc: Ville Syrjälä
Cc: Matt Roper
Suggested-by: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13
> -Original Message-
> From: Roper, Matthew D
> Sent: Monday, November 14, 2022 4:43 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä
>
> Subject: Re: [PATCH 2/3] drm/i915/display: Do both crawl and squash when
> changing cdclk
&
> -Original Message-
> From: Roper, Matthew D
> Sent: Monday, November 14, 2022 4:01 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä
>
> Subject: Re: [PATCH 2/3] drm/i915/display: Do both crawl and squash when
> changing cdclk
&
> -Original Message-
> From: Roper, Matthew D
> Sent: Monday, November 14, 2022 2:16 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä
>
> Subject: Re: [PATCH 2/3] drm/i915/display: Do both crawl and squash when
> changing cdclk
&
crawl capability checks.(Ville)
v4: Rebase
- Move checks to be more consistent (Ville)
- Add comments (Bala)
v5:
- Further small changes. Move checks around.
- Make if-else better looking (Ville)
v6: MTl should not follow PUnit mailbox communication as the rest of
gen11+ platforms.(Anusha)
v7: (Matt
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22
of
intel_modeset_calc_cdclk() which is directly in
the path of the sanitize() function (Ville)
v3: remove unwanted parenthesis(Ville)
Cc: Ville Syrjälä
Cc: Matt Roper
Suggested-by: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, November 11, 2022 11:40 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Roper, Matthew D
>
> Subject: Re: [PATCH] drm/i915/display: Add missing checks for cdclk crawling
>
> On
of
intel_modeset_calc_cdclk() which is directly in
the path of the sanitize() function (Ville)
Cc: Ville Syrjälä
Cc: Matt Roper
Suggested-by: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git
with a valid frequency.
However the vco is declared as a unsigned variable.
With the above assumption, driver takes crawl path when not needed.
Add explicit check to not crawl in the case of an invalid PLL.
Cc: Matt Roper
Suggested-by: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, November 9, 2022 3:30 AM
> To: Roper, Matthew D
> Cc: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org; Vivekanandan, Balasubramani
>
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i91
> -Original Message-
> From: Roper, Matthew D
> Sent: Tuesday, November 8, 2022 3:43 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Vivekanandan, Balasubramani
>
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and
> sq
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22
crawl capability checks.(Ville)
v4: Rebase
- Move checks to be more consistent (Ville)
- Add comments (Bala)
v5:
- Further small changes. Move checks around.
- Make if-else better looking (Ville)
v6: MTl should not follow PUnit mailbox communication as the rest of
gen11+ platforms.(Anusha)
Cc: Clint
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22
crawl capability checks.(Ville)
v4: Rebase
- Move checks to be more consistent (Ville)
- Add comments (Bala)
v5:
- Further small changes. Move checks around.
- Make if-else better looking (Ville)
Cc: Balasubramani Vivekanandan
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/g
As per bSpec MTL has 38.4 MHz Reference clock.
Addin gthe cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +-
1 file
crawl capability checks.(Ville)
v4: Rebase
- Move checks to be more consistent (Ville)
- Add comments (Bala)
v5:
- Further small changes. Move checks around.
- Make if-else better looking (Ville)
Cc: Balasubramani Vivekanandan
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/g
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, October 28, 2022 2:05 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Vivekanandan, Balasubramani
>
> Subject: Re: [PATCH 1/2] drm/i915/display: Do both crawl and squash when
> changin
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915
crawl capability checks.(Ville)
v4: Rebase
- Move checks to be more consistent (Ville)
- Add comments (Bala)
Cc: Balasubramani Vivekanandan
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 157 +
1 file changed, 129 inse
From: Patchwork
Sent: Wednesday, October 26, 2022 10:07 AM
To: Srivatsa, Anusha
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for series starting with [CI,1/4]
drm/i915/display: Change terminology for cdclk actions
Patch Details
Series:
series starting with [CI,1/4] drm
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, October 26, 2022 12:52 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [CI 1/4] drm/i915/display: Change terminology for
> cdclk actions
>
> On Tue, 2
No functional change. Introduce dg2_cdclk_squash_program and
move squash_ctl register programming bits to this.
v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)
Cc: Jani Nikula
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed
No functional change. Moving segments out to simplify
bxt_set_cdlck()
v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)
Cc: Jani Nikula
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display
No functional changes. Changing terminology in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915
Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Balasubramani Vivekanandan
---
drivers/gpu/drm
No functional change. Introduce dg2_cdclk_squash_program and
move squash_ctl register programming bits to this.
v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)
Cc: Jani Nikula
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed
Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Balasubramani Vivekanandan
---
drivers/gpu/drm
No functional changes. Changing terminology in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915
No functional change. Moving segments out to simplify
bxt_set_cdlck()
v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)
Cc: Jani Nikula
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display
No functional changes. Changing terminolgy in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 16
No functional change. Introduce dg2_cdclk_squash_program and
move squash_ctl register programming bits to this.
v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)
Cc: Jani Nikula
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu
No functional change. Moving segments out to simplify
bxt_set_cdlck()
v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)
Cc: Jani Nikula
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++
1
Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 15
.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Anusha Srivatsa (4):
drm/i915/display: Change terminology for cdclk actions
drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
drm/i915/display: Move chunks of code out of bxt_set_cdclk()
drm/i915/display: Move squash_ctl register programming to
> -Original Message-
> From: Vivekanandan, Balasubramani
>
> Sent: Friday, October 21, 2022 12:08 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Cc: Ville Syrjälä
> Subject: Re: [PATCH 4/4] drm/i915/display: Move squash_ctl register
> prog
> -Original Message-
> From: Jani Nikula
> Sent: Friday, October 21, 2022 1:32 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Cc: Vivekanandan, Balasubramani
>
> Subject: Re: [Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of cod
> -Original Message-
> From: Jani Nikula
> Sent: Friday, October 21, 2022 1:41 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Cc: Vivekanandan, Balasubramani
>
> Subject: Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl
> regi
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