The patch
ASoC: es8316: Add support for inverted jack detect
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and se
The patch
regulator: as3722: Slightly improve readability
has been applied to the regulator tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours)
The patch
regmap: regmap-irq: fix getting type default values
has been applied to the regmap tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) an
On 29/03/19 4:22 PM, Faiz Abbas wrote:
> Some controllers on TI devices requires the HISPD bit to be cleared
> even in some high speed modes. Add a quirk that facilitates this
> requirement.
Could you use sdhci I/O accessors for this?
>
> Signed-off-by: Faiz Abbas
> ---
> drivers/mmc/host/sdhc
On 4/1/2019 9:56 PM, Peng Hao wrote:
of_find_device_by_node() takes a reference to the struct device
when it finds a match via get_device. When returning error we should
call put_device.
Signed-off-by: Peng Hao
---
arch/arm/mach-at91/pm.c | 6 --
1 file changed, 4 insertions(+), 2 dele
Paolo Bonzini writes:
>
> IIRC there was an enlightenment to tell Windows "I support auto-EOI but
> please don't use it". If this is what's happening, that would also fix it.
>
Unfortunately this doesn't save the day, Hyper-V behaves the
same. I'm more and move convinced that the secord IRQ was
Hi,
Le lundi 01 avril 2019 à 02:52 +0200, Jann Horn a écrit :
> One minor detail to keep in mind for the future is that in a
> straightforward implementation of this concept, if a non-capable
> process is running in a mount namespace, but in the initial network
> namespace, without any reachable
On 24/03/2019 16:14, Martin Blumenstingl wrote:
> This adds the video decoder clocks for Meson8, Meson8b and Meson8m2.
>
> The clock tree on Meson8 differs from the one one Meson8b and Meson8m2.
> Details can be found in patch #2.
>
> There are some checkpatch warnings in patch #2:
> WARNING: p
On 14/03/2019 at 17:26, Claudiu Beznea - M18063 wrote:
> From: Claudiu Beznea
>
> Change Microchip timers section name to be more generic.
>
> Signed-off-by: Claudiu Beznea
Acked-by: Nicolas Ferre
> ---
> MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
On 14/03/2019 at 17:26, Claudiu Beznea - M18063 wrote:
> From: Claudiu Beznea
>
> Add timer-microchip-pit64b.c as maintained file.
>
> Signed-off-by: Claudiu Beznea
Acked-by: Nicolas Ferre
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAIN
On Thu, Mar 21, 2019 at 11:15:56AM +0100, Alexandre Belloni wrote:
> The DA9062 and DA9063 have a year register that can go up to 0x3F.
>
> Signed-off-by: Alexandre Belloni
Thanks for this patch! Didn't know about the devm_rtc_device_register()
conversion going on. Glad I learned about it.
Revi
On 14/03/2019 at 17:26, Claudiu Beznea - M18063 wrote:
> From: Claudiu Beznea
>
> Add myself as maintainer for Microchip timers and clocksource
> drivers.
>
> Signed-off-by: Claudiu Beznea
Acked-by: Nicolas Ferre
Thanks Claudiu!
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
On 14/03/2019 at 17:26, Claudiu Beznea - M18063 wrote:
> From: Claudiu Beznea
>
> Add driver for Microchip PIT64B timer. Timer could be used in continuous
> mode or oneshot mode. The hardware has 2x32 bit registers for period
> emulating a 64 bit timer. The LSB_PR and MSB_PR registers are used to
On 14/03/2019 at 17:26, Claudiu Beznea - M18063 wrote:
> From: Claudiu Beznea
>
> Add device tree bindings for PIT64B timer.
>
> Signed-off-by: Claudiu Beznea
Acked-by: Nicolas Ferre
> ---
> Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 7 +++
> 1 file changed, 7 insertion
On Sat, 2019-03-30 at 16:56 +0100, Martin Blumenstingl wrote:
> Hi Jerome,
>
> On Sat, Mar 30, 2019 at 12:07 AM Jerome Brunet wrote:
> > On Fri, 2019-03-29 at 20:39 +0100, Martin Blumenstingl wrote:
> > > Hi Jerome,
> > >
> > > On Fri, Mar 29, 2019 at 4:34 PM Jerome Brunet
> > > wrote:
> > > >
Patch "5f5e4890d57a" removes the comment of _DSD data subnodes GUID. This
patch restores it.
Fixes: 5f5e4890d57a ("ACPI / property: Allow multiple property
compatible _DSD entries")
Cc: Joey Zheng
Signed-off-by: Shunyong Yang
---
drivers/acpi/property.c | 1 +
1 file changed, 1 insertion(+)
d
On Sat, 2019-03-30 at 16:58 +0100, Martin Blumenstingl wrote:
> On Fri, Mar 29, 2019 at 4:34 PM Jerome Brunet wrote:
> > As reported on this [0] mpll series, We are observing a lot of jitter
> > on the MPLL outputs of the g12a. No such jitter is seen on gx family.
> > On the axg family, only MPLL2
On 24/03/2019 16:11, Martin Blumenstingl wrote:
> This adds the VPU clock tree for Meson8, Meson8b and Meson8m2.
> The VPU clock tree is slightly different on all three SoCs. The details
> are explained in patch #4.
>
> Meson8m2 requires the previously unsupported "gp_pll" PLL. This PLL only
> exi
Paolo Bonzini writes:
> On 29/03/19 16:32, Liran Alon wrote:
>> Paolo I am not sure this is the case here. Please read my other
>> replies in this email thread.
>>
>> I think this is just a standard issue of a level-triggered interrupt
>> handler in L1 (Hyper-V) that performs EOI before it lower
On Mon, Apr 01, 2019 at 08:11:51AM +, Erwan Velu wrote:
> I'd suggest something like this and keep the 'CPUID not supported' part
> untouched.
>
> if (no_load) || (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
Yeah, that's the usual thing we do in such cases and the better idea,
I'll do
Hi Fabio,
On 30 March 2019 15:51 Fabio Estevam, wrote:
> Subject: [RFC] ARM: dts: imx: Fix the AR803X phy-mode
>
> Commit 6d4cd041f0af ("net: phy: at803x: disable delay only for RGMII mode")
> exposed an issue on imx DTS files using AR8031/AR8035 PHYs.
>
> The end result is that the boards can
On 21/03/2019 10:20, Neil Armstrong wrote:
> When submitted v2 of the G12A AO-CLK IDs, the CLKID_AO_CTS_OSCIN was moved
> to the internal non-exported bindings, but this clock is necessary for
> the second AO-CEC-B module since it embeds the 32768Hz dual-divider
> clock generator unlike the AO-CEC-
Dear Greg k-h,
I saw the patch is already in Linus's tree
But I found it is not my v3-patch
Can you help me to check this status kindly?
Thank you
BR,
Ricky
> -Original Message-
> From: gre...@linuxfoundation.org [mailto:gre...@linuxfoundation.org]
> Sent: Monday, April 01, 2019 3:04 PM
On Fri, Mar 29, 2019 at 11:26:34AM -0700, Paul E. McKenney wrote:
> When RCU core processing is offloaded from RCU_SOFTIRQ to the rcuc
> kthreads, a full and unconditional wakeup is required to initiate RCU
> core processing. In contrast, when RCU core processing is carried
> out by RCU_SOFTIRQ, a
On 4/1/2019 12:24 AM, Vincent Stehlé wrote:
When initializing the priv->data array starting from index 1, there is one
less element to consider than when initializing the full array.
Fixes: e717f8c6dfec8f76 ("iio: adc: Add the TI ads124s08 ADC code")
Signed-off-by: Vincent Stehlé
Cc: Dan Murp
On 19/03/2019 11:11, Maxime Jourdan wrote:
> This patch series adds the clocks related to the video decoder on G12A:
> VDEC_1, VDEC_HEVC and VDEC_HEVCF.
>
> As to not conflict with the IDs, this patch series is based on Neil's
> last unmerged patch series: "clk: meson: add support for PCIE PLL" [0
On 19/03/2019 11:11, Maxime Jourdan wrote:
> Add the necessary clock parts for:
>
> - VDEC_1: used to feed VDEC_1
> - VDEC_HEVC: the "back" part of the VDEC_HEVC block
> - VDEC_HEVCF: the "front" part of the VDEC_HEVC block
>
> In previous SoC generations (GXL, GXBB), there was only one VDEC_H
On Tue, Mar 26, 2019 at 10:56:26PM -0700, Sowjanya Komatineni wrote:
> Fixes: use unpacked mode when transfer length is less than 4 bytes.
>
> Packed mode expects minimum transfer length of 4 bytes.
This doesn't apply against current code, please check and resend.
Applying: spi: tegra114: use un
On Mon, Apr 1, 2019 at 10:16 AM Bartosz Golaszewski wrote:
>
> From: Bartosz Golaszewski
>
> It should have been 'management' not 'managemend'.
>
> Fixes: 7945f929f1a7 ("drivers: provide devm_platform_ioremap_resource()")
> Signed-off-by: Bartosz Golaszewski
Reviewed-by: Rafael J. Wysocki
> -
On 4/1/2019 7:05 AM, Yue Haibing wrote:
From: YueHaibing
If dccp_feat_push_change fails, we forget free the mem
which is alloced by kmemdup in dccp_feat_clone_sp_val.
Reported-by: Hulk Robot
Fixes: e8ef967a54f4 ("dccp: Registration routines for changing feature values")
Reviewed-by: Mukesh
On 2019-03-31 20:20:25 [+0200], Thomas Gleixner wrote:
>
> I think this should do the following:
>
> fpregs_lock();
> if (!test_thread_flag(TIF_NEED_FPU_LOAD)) {
> pagefault_disable();
> ret = copy_fpu_to_user(...);
> pagefault_enable();
>
Hi Matthias,
On 2019-04-01 13:29, Balakrishna Godavarthi wrote:
Hi Matthias,
Sorry for the late reply i was on vacation.
On 2019-03-08 05:00, Matthias Kaehlcke wrote:
On Thu, Mar 07, 2019 at 10:20:09AM -0800, Matthias Kaehlcke wrote:
Hi Balakrishna,
On Thu, Mar 07, 2019 at 10:35:08AM +0530,
From: Maoguang Meng
Update referenced frame buffer's reference count when playing vp9
content which has show_existing_frame flag, and copy enough buffer
data to current shown frame.
Signed-off-by: Maoguang Meng
---
.../media/platform/mtk-vcodec/vdec/vdec_vp9_if.c | 16 +++-
1 f
s/ready/read
On 4/1/2019 9:54 AM, Lingutla Chandrasekhar wrote:
If user updates any cpu's cpu_capacity, then the new value is going to
be applied to all its online sibling cpus. But this need not to be correct
always, as sibling cpus (in ARM, same micro architecture cpus) would have
different cp
On Thu, Mar 21, 2019 at 01:02:27PM -0700, Sodagudi Prasad wrote:
> On 2019-03-21 06:34, Julien Thierry wrote:
> > Hi Prasad,
> >
> > On 21/03/2019 02:07, Prasad Sodagudi wrote:
> > > Preserves the bitfields of PMCR_EL0(AArch64) during PMU reset.
> > > Reset routine should write a 1 to PMCR.C and P
On 29.03.19 17:51, Michael S. Tsirkin wrote:
> On Fri, Mar 29, 2019 at 04:45:58PM +0100, David Hildenbrand wrote:
>> On 29.03.19 16:37, David Hildenbrand wrote:
>>> On 29.03.19 16:08, Michael S. Tsirkin wrote:
On Fri, Mar 29, 2019 at 03:24:24PM +0100, David Hildenbrand wrote:
>
> We ha
From: Bartosz Golaszewski
It should have been 'management' not 'managemend'.
Fixes: 7945f929f1a7 ("drivers: provide devm_platform_ioremap_resource()")
Signed-off-by: Bartosz Golaszewski
---
drivers/base/platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/base
On 4/1/2019 10:29 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/nvmem/imx-iim
On Thu, Mar 28, 2019 at 08:27:21AM -0500, Rob Herring wrote:
> On Tue, Mar 12, 2019 at 11:22:50PM +0800, Icenowy Zheng wrote:
> > Allwinner V3 has the same main die with V3s, but with more pins wired.
> > There's a I2S bus on V3 that is not available on V3s.
> >
> > Add the V3-only peripheral's clo
On 4/1/2019 10:29 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/nvmem/mxs-oco
On 4/1/2019 10:29 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/nvmem/imx-oco
On 4/1/2019 10:34 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/watchdog/imx2
> index ea62e3f02d56..19854f01e2fa 100644
> --- a/drivers/cpufreq/intel_pstate.c
> +++ b/drivers/cpufreq/intel_pstate.c
> @@ -2608,7 +2608,9 @@ static int __init intel_pstate_init(void)
> } else {
> id = x86_match_cpu(intel_pstate_cpu_ids);
> if (!id) {
> -
On 4/1/2019 10:37 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/pinctrl/frees
Hi Stephen
On Sat 30-03-19 16:19:39, Stephen Rothwell wrote:
> In commit
>
> 47d92aa5d33a ("quota: fix a problem about transfer quota")
>
> Fixes tag
>
> Fixes: 7b9ca4c61("quota: Reduce contention on dq_data_lock")
>
> has these problem(s):
>
> - missing space between the SHA1 and the s
On 4/1/2019 10:39 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/gpio/gpio-mxc
pon., 1 kwi 2019 o 07:09 Anson Huang napisał(a):
>
> Use the new helper devm_platform_ioremap_resource() which wraps the
> platform_get_resource() and devm_ioremap_resource() together, to
> simplify the code.
>
> Signed-off-by: Anson Huang
> ---
> drivers/gpio/gpio-mxc.c | 4 +---
> 1 file chang
On Sat, Mar 30, 2019 at 12:20:18PM +0100, Borislav Petkov wrote:
> From: Borislav Petkov
>
> Clarify when one should use static_cpu_has() and when one should use
> boot_cpu_has().
>
> Requested-by: Nadav Amit
> Signed-off-by: Borislav Petkov
> Cc: x...@kernel.org
> ---
> arch/x86/include/asm/
On 4/1/2019 10:43 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/clk/imx/clk-i
On 4/1/2019 10:45 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/mailbox/imx-m
of_find_device_by_node() takes a reference to the struct device
when it finds a match via get_device. When returning error we should
call put_device.
Signed-off-by: Peng Hao
---
arch/arm/mach-at91/pm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-at91/p
On 4/1/2019 10:49 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/input/touch
On 4/1/2019 10:54 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/pwm/pwm-imx
On 4/1/2019 10:54 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/pwm/pwm-imx27
On Wed, Mar 27, 2019 at 01:18:39AM +0100, meg...@megous.com wrote:
> From: Ondrej Jirman
>
> A83T has 5 UART interfaces, but only the first two have their nodes
> defined in sun8i-a83t.dtsi. Add nodes for the missing interfaces.
>
> Signed-off-by: Ondrej Jirman
Applied, thanks!
Maxime
--
Maxime
Hi Matthias,
Sorry for the late reply i was on vacation.
On 2019-03-08 05:00, Matthias Kaehlcke wrote:
On Thu, Mar 07, 2019 at 10:20:09AM -0800, Matthias Kaehlcke wrote:
Hi Balakrishna,
On Thu, Mar 07, 2019 at 10:35:08AM +0530, Balakrishna Godavarthi
wrote:
> hi Matthias,
>
> On 2019-03-07
On 4/1/2019 10:58 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/input/keyboar
Export spi_mem_default_supports_op(), so that controller drivers
can use this.
spi-mem driver already exports this using EXPORT_SYMBOL,
but not declared it in spi-mem.h.
This patch declares spi_mem_default_supports_op() in spi-mem.h and
also removes the static from the function prototype.
Signed-o
Add support for QSPI controller driver used by Xilinx Zynq SOC.
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v2
- Updated the driver to call spi_mem_default_supports_op() from
ctrl->supports_op()
Changes in v1
- Added COMPILE_TEST macro
- converted MASKs to GENMASK() and BIT() macro
On Fri, Mar 29, 2019 at 02:42:43PM +0100, Michal Hocko wrote:
> Having a larger contiguous area is definitely nice to have but you also
> have to consider the other side of the thing. If we have a movable
> memblock with unmovable memory then we are breaking the movable
> property. So there should
This patch adds the dts binding document for Zynq SOC QSPI controller.
Reviewed-by: Rob Herring
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v2
- None
---
.../devicetree/bindings/spi/spi-zynq-qspi.txt | 25 ++
1 file changed, 25 insertions(+)
create mode 10064
On Fri, Mar 29, 2019 at 10:47:03AM -0500, Andrew F. Davis wrote:
> This device can detect the insertion/removal of headphones and headsets.
> Enable reporting this status by enabling this interrupt and forwarding
> this to upper-layers if a jack has been defined.
This doesn't apply against current
Xilinx Zynq uses a QSPI controller that implements all the functionality
required to support Quad SPI NOR flash devices.
This driver along with the SPI MEM and MTD layer is used to support
flash devices.
The flash device(s) can be connected in three configurations to this
controller:
1. Single - O
On 4/1/2019 10:59 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
---
drivers/rtc/rtc-snvs.c | 4 +---
1 file changed, 1 insertion(+), 3
On 29.03.2019 22:02, Arnaldo Carvalho de Melo wrote:
> Em Mon, Mar 18, 2019 at 08:40:26PM +0300, Alexey Budankov escreveu:
>>
>> Implemented --mmap-flush option that specifies minimal number of bytes
>> that is extracted from mmaped kernel buffer to store into a trace. The
>> default option value i
syzbot has bisected this bug to:
commit 63d86a7e85f84b8ac3b2f394570965aedbb03787
Author: Paul E. McKenney
Date: Tue May 1 20:08:46 2018 +
rcu: Convert rcu_grace_period_init tracepoint to gp_seq
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=17f86d2f20
start commit:
On Fri, Mar 29, 2019 at 10:56:36AM -0700, Gwendal Grignou wrote:
> In preparation to update cros_ec_commands.h to match ChromeOS EC code
> base, rename data structure that will be merged together.
>
> TEST=compile.
This doesn't apply against current code, please check and resend.
signature.asc
Hello,
Is there any way to get CMA area pages information (tool/application) ?
Regards,
Pankaj
*
eInfochips Business Disclaimer: This e-mail
On 01/04/2019 11:20:23+0530, Mukesh Ojha wrote:
>
> On 3/20/2019 6:02 PM, Alexandre Belloni wrote:
> > Use SPDX-License-Identifier instead of a verbose license text.
> >
> > Signed-off-by: Alexandre Belloni
>
> Please refer https://lkml.org/lkml/2019/2/13/570 for more discussion on
> this.
> o
On 4/1/2019 4:23 AM, Will Cunningham wrote:
Removed unnecessary parentheses.`
Remove the extra character at the end.
Fix the above thing then you can take.
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
Signed-off-by: Will Cunningham
---
drivers/staging/comedi/drivers/pcl818.c | 8
The Amlogic G12A SoC has a very similar VPU Power Controller setup
than the older GXBB, GXL & GXm SoCs.
This patch adds the variant support for G12A.
Signed-off-by: Neil Armstrong
---
Changes since v1:
- Move the GX mask fix to a separate patch
Dependencies:
- Depends on [1], but is reviewed, l
On Fri, Mar 29, 2019 at 03:23:00PM -0700, John Hubbard wrote:
> On 3/28/19 6:43 AM, Oscar Salvador wrote:
> > Hi,
> >
> > since last two RFCs were almost unnoticed (thanks David for the feedback),
> > I decided to re-work some parts to make it more simple and give it a more
> > testing, and drop t
On Thu, Mar 28, 2019 at 06:18:34PM +0800, Mason Yang wrote:
> Patch a MFD driver for Macronix MX25F0A SPI controller.
>
> Signed-off-by: Mason Yang
I can't tell what this commit is supposed to do based on this commit
message which makes it hard to review :(
signature.asc
Description: PGP signa
On Fri, Mar 29, 2019 at 04:38:20PM +0800, Chris Chiu wrote:
> On Thu, Mar 28, 2019 at 8:34 PM Mika Westerberg
> wrote:
> >
> > On Thu, Mar 28, 2019 at 08:19:59PM +0800, Chris Chiu wrote:
> > > On Thu, Mar 28, 2019 at 5:38 PM Daniel Drake wrote:
> > > >
> > > > On Thu, Mar 28, 2019 at 5:17 PM Andy
On Tue, Mar 26, 2019 at 10:56:45PM -0700, Sowjanya Komatineni wrote:
> With SW CS, during transfer completion CS is de-asserted by writing the
> default command1 register value to SPI_COMMAND1 register. With this both
> mode and CS state are set at the same time and if current transfer mode
> is di
From: Pankaj Suryawanshi
Sent: 29 March 2019 10:52
To: Matthew Wilcox
Cc: linux-kernel@vger.kernel.org; linux...@kvack.org
Subject: Re: [External] Re: Print map for total physical and virtual memory
From: Matthew
On 4/1/2019 11:37 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/soc/imx/gpcv2.
On 4/1/2019 11:37 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/soc/imx/gpc.c
On Tue, Mar 26, 2019 at 10:56:39PM -0700, Sowjanya Komatineni wrote:
> Tegra SPI driver default uses SW CS control for transfers and HW CS
> control can be enabled through SPI client device node DT property
> nvidia,enable-hw-based-cs and is used only for single transfers.
Why have a property - i
On 4/1/2019 11:51 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/irqchip/irq-im
The register bitmask to power on/off the VPU memories was incorectly set
to 0x2 instead of 0x3. While still working, let's use the recommended
vendor value instead.
Fixes: 75fcb5ca4b46 ("soc: amlogic: add Meson GX VPU Domains driver")
Signed-off-by: Neil Armstrong
---
drivers/soc/amlogic/meson-g
ARM Mali midgard GPU is similar to standard 64-bit stage 1 page tables, but
have a few differences. Add a new format type to represent the format. The
input address size is 48-bits and the output address size is 40-bits (and
possibly less?). Note that the later bifrost GPUs follow the standard
64-b
Hi Matthias,
On 2019-03-13 02:12, Matthias Kaehlcke wrote:
Rename STATE_IN_BAND_SLEEP_ENABLED to QCA_IN_BAND_SLEEP_ENABLED.
The constant represents a flag (multiple flags can be set at once),
not a unique state of the controller or driver.
Also make the flag an enum value instead of a pre-proce
On 4/1/2019 10:54 AM, Anson Huang wrote:
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/pwm/pwm-imx27.
On Mon, Apr 01, 2019 at 06:31:11AM +0200, Lukas Wunner wrote:
> On Thu, Mar 28, 2019 at 06:56:21PM +0200, Mika Westerberg wrote:
> > On Thu, Mar 28, 2019 at 03:17:57PM +, mario.limoncie...@dell.com wrote:
> > > > From: Mika Westerberg
> > > > Sent: Thursday, March 28, 2019 7:36 AM
> > > > *
On 2019-03-14 05:22, Matthias Kaehlcke wrote:
qca_set_baudrate() calls serdev_device_wait_until_sent() assuming that
the HCI is always associated with a serdev device. This isn't true for
ROME controllers instantiated through ldisc, where the call causes a
crash due to a NULL pointer dereferentia
On Tue, Mar 26, 2019 at 10:56:30PM -0700, Sowjanya Komatineni wrote:
> This patch dumps SPI registers on DMA or transfer timeout for debug
> purpose.
This is another non-bugfix patch which should be after the bugfixes.
signature.asc
Description: PGP signature
On Sat, Mar 30, 2019 at 07:46:38PM +0100, Matteo Croce wrote:
> Since commit ad67b74d2469d9b8 ("printk: hash addresses printed with %p"),
> two obfuscated kernel pointer are printed at every boot:
>
> vdso: 2 pages (1 code @ (ptrval), 1 data @ (ptrval))
>
> Remove the addresse
On Tue, Mar 26, 2019 at 10:56:25PM -0700, Sowjanya Komatineni wrote:
> Fixes: Use packed mode for 32 bits per word transfers to increase
> performance as each packet is a full 32-bit word.
This is an optimization rather than a bug fix, ideally it should be
later in the series to make things easier
On Tue, Mar 26, 2019 at 10:56:40PM -0700, Sowjanya Komatineni wrote:
> This patch adds below cs timing properties to allow SPI master configuring
> setup, hold and time interval between two SPI transactions to meet specific
> SPI client device requirements.
> CS setup time
> CS hold time
> CS in
Upon reboot, the Acer TravelMate X514-51T laptop appears to complete the
shutdown process, but then it hangs in BIOS POST with a black screen.
The problem is intermittent - at some points it has appeared related to
Secure Boot settings or different kernel builds, but ultimately we have
not been ab
> -Original Message-
> From: Igor Plyatov
> Sent: 2019年3月28日 19:06
> To: Robin Gong ; Uwe Kleine-König
>
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-...@vger.kernel.org; dl-linux-imx ; Fabio Estevam
> ; Pengutronix Kernel Team ;
> Sascha Hauer ; Shawn
On Wed, Mar 27, 2019 at 02:30:48PM +, Rasmus Villemoes wrote:
> I doubt patches 3 and 4 are acceptable, but I'd still like to get
> comments and/or alternative suggestions for making large transfers
> faster.
I see no problem with this from a framework point of view FWIW, it's
going to be a qu
On Mon, 1 Apr 2019, Peter Zijlstra wrote:
> On Sun, Mar 31, 2019 at 11:40:24PM +0200, Thomas Gleixner wrote:
> > --- a/arch/x86/include/asm/page_64_types.h
> > +++ b/arch/x86/include/asm/page_64_types.h
> > @@ -25,11 +25,14 @@
> > #define IRQ_STACK_ORDER (2 + KASAN_STACK_ORDER)
> > #define IRQ_S
On Mon, Apr 01, 2019 at 09:24:06AM +0200, Paolo Bonzini wrote:
> The MSR reads and writes are not done in the common case. Also, you
> cannot really expect boot_cpu_data to be in L1 in these functions since
> they run after the guest---or if they do, each L1 line you fill in with
> host data is on
On Sun, Mar 31, 2019 at 11:40:24PM +0200, Thomas Gleixner wrote:
> --- a/arch/x86/include/asm/page_64_types.h
> +++ b/arch/x86/include/asm/page_64_types.h
> @@ -25,11 +25,14 @@
> #define IRQ_STACK_ORDER (2 + KASAN_STACK_ORDER)
> #define IRQ_STACK_SIZE (PAGE_SIZE << IRQ_STACK_ORDER)
>
> -#define
Dear Greg k-h,
Very thanks for your reply kindly
Ricky
> -Original Message-
> From: gre...@linuxfoundation.org [mailto:gre...@linuxfoundation.org]
> Sent: Monday, April 01, 2019 3:04 PM
> To: 吳昊澄 Ricky
> Cc: a...@arndb.de; colin.k...@canonical.com; ax...@kernel.dk;
> linux-kernel@vger.ke
On 30/03/2019 20:29, Martin Blumenstingl wrote:
> Hello Uwe,
>
> On Mon, Mar 25, 2019 at 9:07 PM Uwe Kleine-König
> wrote:
> [...]
- Does stopping the PWM (i.e. clearing MISC_{A,B}_EN in the MISC_AB
register) freeze the output, or is the currently running period
completed fi
On 31/03/19 17:12, Borislav Petkov wrote:
> On Sun, Mar 31, 2019 at 04:20:11PM +0200, Paolo Bonzini wrote:
>> These are not slow path.
>
> Those functions do a *lot* of stuff like a bunch of MSR reads which are
> tens of cycles each at least.
The MSR reads and writes are not done in the common ca
Hi Guenter,
thanks for the review.
On 01/04/2019 06:10, Guenter Roeck wrote:
> On Sun, Mar 31, 2019 at 8:24 PM Daniel Lezcano
> wrote:
>>
>> The module support for the thermal subsystem does have a little sense:
>
> Do you mean "makes little sense" ?
yep :)
>> - some subsystems relying on it
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