On Tue, 2021-02-09 at 11:12 -0600, Eddie James wrote:
> In the event that the OCC is not initialized when the driver sends a
> poll
> command, the driver may receive an invalid response. This isn't an
> error
> condition unless there is no valid response before the timeout
> ex
restart, as the locking is broken somehow.
Fixes: 0795fb2021f0 ("net/ncsi: Stop monitor if channel times out or is
inactive")
Signed-off-by: Milton Miller
Signed-off-by: Eddie James
---
net/ncsi/ncsi-manage.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
The error bits in the FSI2PIB status are only cleared by a reset. So
the driver needs to perform a reset after seeing any of the FSI2PIB
errors, otherwise subsequent operations will also look like failures.
Fixes: 6b293258cded ("fsi: scom: Major overhaul")
Signed-off-by: Eddie James
--
On Thu, 2021-03-25 at 13:50 +, Mark Brown wrote:
> On Wed, Mar 24, 2021 at 05:05:16PM -0500, Eddie James wrote:
>
> > Updated restricted chips have trouble processing multiple sequenced
> > operations. So remove the capability to sequence multiple
> > operations an
Updated restricted chips have trouble processing multiple sequenced
operations. So remove the capability to sequence multiple operations and
reduce the maximum transfer size to 8 bytes.
Signed-off-by: Eddie James
---
drivers/spi/spi-fsi.c | 27 +++
1 file changed, 7
1:27:25 rain27bmc kernel: [<80734cdc>] (aspeed_master_read) from
[<807320f0>] (fsi_master_read+0x6c/0x1bc)
...
Signed-off-by: Eddie James
---
drivers/fsi/fsi-master-aspeed.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fsi/fsi-master-aspeed.c b/dr
In order to better debug problems starting up the driver, print
the response status from the OCC in the error logged when the first
poll command fails.
Signed-off-by: Eddie James
---
drivers/hwmon/occ/common.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers
Initialize the sequence number at one, rather than zero, in order
to prevent false matches with the zero-initialized OCC SRAM
buffer before the OCC is fully initialized.
Signed-off-by: Eddie James
---
drivers/hwmon/occ/common.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/hwmon
Log an error if the response checksum doesn't match the
calculated checksum.
Signed-off-by: Eddie James
---
drivers/fsi/fsi-occ.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/fsi/fsi-occ.c b/drivers/fsi/fsi-occ.c
index cb05b6dacc9d..524460995465 100644
state before returning the response in order to detect this condition and
continue waiting if necessary.
Eddie James (4):
fsi: occ: Don't accept response from un-initialized OCC
fsi: occ: Log error for checksum failure
hwmon: (occ) Start sequence number at one
hwmon: (occ) Print response
If the OCC is not initialized and responds as such, the driver
should continue waiting for a valid response until the timeout
expires.
Signed-off-by: Eddie James
---
drivers/fsi/fsi-occ.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/fsi/fsi-occ.c b/drivers/fsi/fsi-occ.c
index
Some PMBus chips don't respond with valid data when reading the
CAPABILITY register. Add a flag that device drivers can set so
that the PMBus core driver doesn't use CAPABILITY to determine it's
behavior.
Signed-off-by: Eddie James
---
drivers/hwmon/pmbus/pmbus_core.c | 8 +---
include
for this driver.
Signed-off-by: Eddie James
---
drivers/hwmon/pmbus/ibm-cffps.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwmon/pmbus/ibm-cffps.c b/drivers/hwmon/pmbus/ibm-cffps.c
index d6223871..ffde5aaa5036 100644
--- a/drivers/hwmon/pmbus/ibm-cffps.c
+++ b
this flag for the cffps driver.
Changes since v1:
- Rename the flag to PMBUS_NO_CAPABILITY and adjust the associated
comment accordingly.
Eddie James (2):
hwmon: (pmbus) Add a PMBUS_NO_CAPABILITY platform data flag
hwmon: (pmbus/ibm-cffps) Set the PMBUS_NO_CAPABILITY flag
drivers/hwmon/pmbus
On Mon, 2020-12-21 at 08:54 -0800, Guenter Roeck wrote:
> On 12/21/20 8:30 AM, Eddie James wrote:
> > Some PMBus chips don't respond with valid data when reading the
> > CAPABILITY register. For instance the register may report that the
> > chip supports PEC wh
to force PEC off. The second patch enables
this flag for the IBM CFFPS driver, which supports power supplies that
report invalid in the CAPABILITY register and must therefore force PEC
off.
Eddie James (2):
hwmon: (pmbus) Add a NO_PEC flag to probe chips with faulty CAPABILITY
hwmon: (pmbus/ibm
.
Signed-off-by: Eddie James
---
drivers/hwmon/pmbus/pmbus_core.c | 8 +---
include/linux/pmbus.h| 10 ++
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/hwmon/pmbus/pmbus_core.c b/drivers/hwmon/pmbus/pmbus_core.c
index 192442b3b7a2..3de1657dde35
.
Signed-off-by: Eddie James
---
drivers/hwmon/pmbus/ibm-cffps.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwmon/pmbus/ibm-cffps.c b/drivers/hwmon/pmbus/ibm-cffps.c
index d6223871..f8e3ae989e99 100644
--- a/drivers/hwmon/pmbus/ibm-cffps.c
+++ b/drivers/hwmon
: fsi: Check mux status before transfers")
Signed-off-by: Eddie James
---
drivers/spi/spi-fsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-fsi.c b/drivers/spi/spi-fsi.c
index 8a440c7078ef..3920cd3286d8 100644
--- a/drivers/spi/spi-fsi.c
+++ b/drivers/spi
On 9/10/20 4:00 AM, Brendan Higgins wrote:
On Wed, Sep 9, 2020 at 1:31 PM Eddie James wrote:
Mask the IRQ status to only the bits that the driver checks. This
prevents excessive driver warnings when operating in slave mode
when additional bits are set that the driver doesn't handle.
Signed
Add a new clock definition for the "APLLdivN" as described in the
AST2600 specification. This clock is simply the APLL divided by a
factor defined in the SCU registers. It is the input to the FSI
bus.
Signed-off-by: Eddie James
---
include/dt-bindings/clock/ast2600-clock.h | 1 +
1 fi
Add functionality to control the APLL clock on the AST2600. The APLL provides
the clock for the FSI master on the AST2600. Then add a devicetree property to
set the AST2600 FSI master bus frequency.
Eddie James (4):
dt-bindings: clock: Add AST2600 APLLdivN definition
clk: ast2600: Add
Register a clock with it's own operations to describe the APLL on
the AST2600. The clock is controlled by an SCU register containing
a multiplier and divider of the 25MHz input clock.
The functionality to change the APLL is necessary to finely control
the FSI bus frequency.
Signed-off-by: Eddie
Document the bus-frequency property.
Signed-off-by: Eddie James
---
Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt
b/Documentation/devicetree/bindings/fsi/fsi-master
Set the FSI bus frequency based on the value encoded in the
devicetree. The default value is 166MHz, which is the highest
frequency some FSI slaves can accept.
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
---
drivers/fsi/fsi-master-aspeed.c | 5 +
1 file changed, 5 insertions
From: Brad Bishop
The trailing - 8 bytes of transfer data in this size range is no
longer ignored.
Fixes: bbb6b2f9865b ("spi: Add FSI-attached SPI controller driver")
Signed-off-by: Brad Bishop
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
Signed-off-by: Joel Stanley
--
The SPI controllers are not accessible if the mux isn't set. Therefore,
check the mux status before starting a transfer and fail out if it isn't
set.
Signed-off-by: Eddie James
Signed-off-by: Joel Stanley
---
drivers/spi/spi-fsi.c | 40 +++-
1 file changed
driver. With FSI
frequencies slower than 200MHz, the SPI clock will simply run slower, but
safely.
Signed-off-by: Brad Bishop
Signed-off-by: Eddie James
Signed-off-by: Joel Stanley
---
drivers/spi/spi-fsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi
Add a compatible string for the restricted version of the SPI controller.
The restricted version cannot process sequence loop operations and
therefore has a smaller transfer size.
Signed-off-by: Eddie James
---
Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml | 1 +
1 file changed, 1
the controller won't start shifting
receive data.
It is likely not possible to avoid TDR underrun errors in this mode and
they are harmless, so do not check for them.
Fixes: bbb6b2f9865b ("spi: Add FSI-attached SPI controller driver")
Signed-off-by: Brad Bishop
Signed-off-by: Eddie James
to the length of the sequence register.
Fixes: bbb6b2f9865b ("spi: Add FSI-attached SPI controller driver")
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
Signed-off-by: Joel Stanley
---
drivers/spi/spi-fsi.c | 65 +++
1 file changed, 53 inserti
spi: fsi: Fix clock running too fast
spi: fsi: Fix use of the bneq+ sequencer instruction
Eddie James (3):
dt-bindings: fsi: fsi2spi: Add compatible string for restricted
version
spi: fsi: Implement restricted size for certain controllers
spi: fsi: Check mux status before transfers
Add a driver to get the button events from the panel and provide
them to userspace with the input subsystem. The panel is
connected with I2C and controls the bus, so the driver registers
as an I2C slave device.
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
---
MAINTAINERS
Set I2C bus 7 to multi-master mode and add the panel device that will
register as a slave.
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
---
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm
Set I2C bus 0 to multi-master mode and add the panel device that will
register as a slave.
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
---
arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
ver
- Use I2C_OWN_SLAVE_ADDRESS for both dts additions
Eddie James (5):
dt-bindings: input: Add documentation for IBM Operation Panel
input: misc: Add IBM Operation Panel driver
i2c: aspeed: Mask IRQ status to relevant bits
ARM: dts: Aspeed: Tacoma: Add IBM Operation Panel I2C device
ARM: d
Document the bindings for the IBM Operation Panel, which provides
a simple interface to control a server. It has a display and three
buttons.
Also update MAINTAINERS for the new file.
Signed-off-by: Eddie James
Reviewed-by: Rob Herring
Acked-by: Joel Stanley
---
.../bindings/input/ibm,op
Mask the IRQ status to only the bits that the driver checks. This
prevents excessive driver warnings when operating in slave mode
when additional bits are set that the driver doesn't handle.
Signed-off-by: Eddie James
Reviewed-by: Tao Ren
---
drivers/i2c/busses/i2c-aspeed.c | 2 ++
1 file
Mask the IRQ status to only the bits that the driver checks. This
prevents excessive driver warnings when operating in slave mode
when additional bits are set that the driver doesn't handle.
Signed-off-by: Eddie James
---
drivers/i2c/busses/i2c-aspeed.c | 2 ++
1 file changed, 2 insertions
Set I2C bus 7 to multi-master mode and add the panel device that will
register as a slave.
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
---
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm
mask in the Aspeed I2C driver
- Use I2C_OWN_SLAVE_ADDRESS for both dts additions
Eddie James (5):
dt-bindings: input: Add documentation for IBM Operation Panel
input: misc: Add IBM Operation Panel driver
i2c: aspeed: Mask IRQ status to relevant bits
ARM: dts: Aspeed: Tacoma: Add IBM Operation
Set I2C bus 0 to multi-master mode and add the panel device that will
register as a slave.
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
---
arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
Document the bindings for the IBM Operation Panel, which provides
a simple interface to control a server. It has a display and three
buttons.
Also update MAINTAINERS for the new file.
Signed-off-by: Eddie James
Acked-by: Joel Stanley
---
.../bindings/input/ibm,op-panel.yaml | 39
Add a driver to get the button events from the panel and provide
them to userspace with the input subsystem. The panel is
connected with I2C and controls the bus, so the driver registers
as an I2C slave device.
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
---
MAINTAINERS
On 9/1/20 1:11 AM, Wolfram Sang wrote:
+ switch (event) {
+ case I2C_SLAVE_STOP:
+ command_size = panel->idx;
+ fallthrough;
+ case I2C_SLAVE_WRITE_REQUESTED:
+ panel->idx = 0;
+ break;
+ case
On 8/25/20 1:38 AM, Joel Stanley wrote:
On Thu, 20 Aug 2020 at 16:12, Eddie James wrote:
Mask the IRQ status to only the bits that the driver checks. This
prevents excessive driver warnings when operating in slave mode
when additional bits are set that the driver doesn't handle.
Signed-off
On 8/20/20 12:14 PM, Mark Brown wrote:
On Thu, Aug 20, 2020 at 12:02:25PM -0500, Eddie James wrote:
Add documentation for the "fsi2spi,restricted" property which indicates
a controller shouldn't sequence loops and therefore has a smaller
transfer size.
In what situation might s
On 8/20/20 12:12 PM, Mark Brown wrote:
On Thu, Aug 20, 2020 at 12:02:23PM -0500, Eddie James wrote:
From: Brad Bishop
Use a clock divider tuned to a 200MHz FSI clock. Use of the previous
divider at 200MHz results in corrupt data from endpoint devices. Ideally
the clock divider would
to the length of the sequence register.
Fixes: bbb6b2f9865b ("spi: Add FSI-attached SPI controller driver")
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
Signed-off-by: Joel Stanley
---
drivers/spi/spi-fsi.c | 65 +++
1 file changed, 53 inserti
-by: Brad Bishop
Signed-off-by: Eddie James
Signed-off-by: Joel Stanley
---
drivers/spi/spi-fsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-fsi.c b/drivers/spi/spi-fsi.c
index 8f64af0140e0..559d0ff981f3 100644
--- a/drivers/spi/spi-fsi.c
+++ b/drivers/spi
reads into chunks and cap write size
Eddie James (3):
dt-bindings: fsi: fsi2spi: Document new restricted property
spi: fsi: Implement restricted size for certain controllers
spi: fsi: Check mux status before transfers
.../devicetree/bindings/fsi/ibm,fsi2spi.yaml | 10 ++
drivers/misc/eeprom
the controller won't start shifting
receive data.
It is likely not possible to avoid TDR underrun errors in this mode and
they are harmless, so do not check for them.
Fixes: bbb6b2f9865b ("spi: Add FSI-attached SPI controller driver")
Signed-off-by: Brad Bishop
Signed-off-by: Eddie James
From: Brad Bishop
Make use of spi_max_transfer_size to avoid requesting transfers that are
too large for some spi controllers.
Signed-off-by: Brad Bishop
Signed-off-by: Eddie James
Signed-off-by: Joel Stanley
---
drivers/misc/eeprom/at25.c | 94 ++
1 file
The SPI controllers are not accessible if the mux isn't set. Therefore,
check the mux status before starting a transfer and fail out if it isn't
set.
Signed-off-by: Eddie James
Signed-off-by: Joel Stanley
---
drivers/spi/spi-fsi.c | 40 +++-
1 file changed
Add documentation for the "fsi2spi,restricted" property which indicates
a controller shouldn't sequence loops and therefore has a smaller
transfer size.
Signed-off-by: Eddie James
Acked-by: Joel Stanley
Signed-off-by: Joel Stanley
---
Documentation/devicetree/bindings/fsi/ibm,fs
From: Brad Bishop
The trailing - 8 bytes of transfer data in this size range is no
longer ignored.
Fixes: bbb6b2f9865b ("spi: Add FSI-attached SPI controller driver")
Signed-off-by: Brad Bishop
Signed-off-by: Eddie James
Reviewed-by: Joel Stanley
Signed-off-by: Joel Stanley
--
Add a driver to get the button events from the panel and provide
them to userspace with the input subsystem. The panel is
connected with I2C and controls the bus, so the driver registers
as an I2C slave device.
Signed-off-by: Eddie James
---
MAINTAINERS| 1 +
drivers/input
data to the host system when someone presses a button on the
controller.
Eddie James (5):
dt-bindings: input: Add documentation for IBM Operation Panel
input: misc: Add IBM Operation Panel driver
i2c: aspeed: Mask IRQ status to relevant bits
ARM: dts: Aspeed: Tacoma: Add IBM Operation Panel
Document the bindings for the IBM Operation Panel, which provides
a simple interface to control a server. It has a display and three
buttons.
Also update MAINTAINERS for the new file.
Signed-off-by: Eddie James
---
.../bindings/input/ibm,op-panel.yaml | 38
Set I2C bus 7 to multi-master mode and add the panel device that will
register as a slave.
Signed-off-by: Eddie James
---
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
b/arch/arm/boot/dts
Set I2C bus 0 to multi-master mode and add the panel device that will
register as a slave.
Signed-off-by: Eddie James
---
arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
b/arch/arm/boot/dts/aspeed
Mask the IRQ status to only the bits that the driver checks. This
prevents excessive driver warnings when operating in slave mode
when additional bits are set that the driver doesn't handle.
Signed-off-by: Eddie James
---
drivers/i2c/busses/i2c-aspeed.c | 1 +
1 file changed, 1 insertion
IBM created an implementation of the PCA9552 on a PIC16F
microcontroller. Document the new compatible string for this device.
Signed-off-by: Eddie James
---
Documentation/devicetree/bindings/leds/leds-pca955x.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
IBM created an implementation of the PCA9552 on a PIC16F
microcontroller. The I2C device addresses are different from the
hardware PCA9552, so add a new compatible string and associated
platform data to be able to probe this device.
Signed-off-by: Eddie James
Reviewed-by: Vishwanatha Subbanna
the vendor part of the compatible string to ibm
- Change the enum in the driver to be ibm_
Eddie James (2):
dt-bindings: leds: pca955x: Add IBM implementation compatible string
leds: pca955x: Add an IBM software implementation of the PCA9552 chip
Documentation/devicetree/bindings/leds/leds
On 7/9/20 3:50 PM, Andy Shevchenko wrote:
On Thu, Jul 9, 2020 at 11:16 PM Eddie James wrote:
IBM created an implementation of the PCA9552 on a PIC16F
microcontroller. The I2C device addresses are different from the
hardware PCA9552, so add a new compatible string and associated
platform data
On 7/11/20 8:48 AM, Pavel Machek wrote:
Hi!
IBM created an implementation of the PCA9552 on a PIC16F
microcontroller. Document the new compatible string for this device.
Is the implementation opensource?
Hi, no it is not.
Signed-off-by: Eddie James
+++ b/Documentation/devicetree
On 7/12/20 10:33 PM, Xu Wang wrote:
In case of error, the function platform_device_register_full()
returns ERR_PTR() and never returns NULL. The NULL test in the
return value check should be replaced with IS_ERR().
Thanks,
Reviewed-by: Eddie James
Signed-off-by: Xu Wang
---
drivers
When calculating the clock divider, start dividing at 2 instead of 1.
The divider is divided by two at the end of the calculation, so starting
at 1 may result in a divider of 0, which shouldn't happen.
Signed-off-by: Eddie James
---
drivers/mmc/host/sdhci-of-aspeed.c | 2 +-
1 file changed, 1
The EMMC clock can be derived from either the HPLL or the MPLL. Register
a clock mux so that the rate is calculated correctly based upon the
parent.
Signed-off-by: Eddie James
Reviewed-by: Andrew Jeffery
---
drivers/clk/clk-ast2600.c | 49 ---
1 file changed
There were two problems affecting clock speeds to the eMMC chip. Firstly, the
AST2600 clock was not muxed correctly to be derived from the MPLL. Secondly,
the SDHCI clock control divider was not calculated correctly. This series
addresses these problems.
Eddie James (2):
clk: AST2600: Add mux
IBM created an implementation of the PCA9552 on a PIC16F
microcontroller. The I2C device addresses are different from the
hardware PCA9552, so add a new compatible string and associated
platform data to be able to probe this device.
Signed-off-by: Eddie James
Reviewed-by: Vishwanatha Subbanna
IBM created an implementation of the PCA9552 on a PIC16F
microcontroller. Document the new compatible string for this device.
Signed-off-by: Eddie James
---
Documentation/devicetree/bindings/leds/leds-pca955x.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
IBM created an implementation of the PCA9552 on a PIC16F
microcontroller. The I2C device addresses are different from the
hardware PCA9552, so add a new compatible string and associated
platform data to be able to probe this device, and document the new
string.
Eddie James (2):
dt-bindings
In order to access more than the second hub link, 23-bit addressing is
required. The core provides the highest two bits of address as the slave
ID to the master.
OpenBMC-Staging-Count: 1
Signed-off-by: Eddie James
Acked-by: Jeremy Kerr
Signed-off-by: Joel Stanley
---
drivers/fsi/fsi-master
On 7/4/20 1:39 AM, Wolfram Sang wrote:
On Tue, Jun 09, 2020 at 03:15:55PM -0500, Eddie James wrote:
Ports should be defined in the devicetree if they are to be enabled on
the system.
The patch description does not really fit anymore, does it? There is no
change in behaviour, we just remove
Ports should be defined in the devicetree if they are to be enabled on
the system.
Signed-off-by: Eddie James
Signed-off-by: Joel Stanley
---
Changes since v1:
- Remove the check for null device node since that is checked in
of_device_is_available
drivers/i2c/busses/i2c-fsi.c | 2 +-
1
lots
of unecessary devices.
Changes since v1:
- Remove the check for null device node since that is checked in
of_device_is_available
Eddie James (2):
i2c: fsi: Fix the port number field in status register
i2c: fsi: Prevent adding adapters for ports without dts nodes
drivers/i2c/busses
The port number field in the status register was not correct, so fix it.
Fixes: d6ffb6300116 ("i2c: Add FSI-attached I2C master algorithm")
Signed-off-by: Eddie James
Signed-off-by: Joel Stanley
---
drivers/i2c/busses/i2c-fsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On 6/8/20 11:31 AM, Andy Shevchenko wrote:
On Mon, Jun 8, 2020 at 7:05 PM Eddie James wrote:
Ports should be defined in the devicetree if they are to be enabled on
the system.
...
for (port_no = 0; port_no < ports; port_no++) {
np = fsi_i2c_find_port_of_node(
Ports should be defined in the devicetree if they are to be enabled on
the system.
Signed-off-by: Eddie James
Signed-off-by: Joel Stanley
---
drivers/i2c/busses/i2c-fsi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-fsi.c b/drivers/i2c/busses
lots
of unecessary devices.
Eddie James (2):
i2c: fsi: Fix the port number field in status register
i2c: fsi: Prevent adding adapters for ports without dts nodes
drivers/i2c/busses/i2c-fsi.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
--
2.24.0
The port number field in the status register was not correct, so fix it.
Fixes: d6ffb6300116 ("i2c: Add FSI-attached I2C master algorithm")
Signed-off-by: Eddie James
Signed-off-by: Joel Stanley
---
drivers/i2c/busses/i2c-fsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On 5/6/20 10:57 AM, Guenter Roeck wrote:
On Fri, May 01, 2020 at 10:08:33AM -0500, Eddie James wrote:
The latest version of the On-Chip Controller (OCC) has a different
format for the temperature sensor data. Add a new temperature sensor
version to handle this data.
Signed-off-by: Eddie
recover in this situation.
Signed-off-by: Eddie James
Acked-by: Andrew Jeffery
---
drivers/soc/aspeed/aspeed-xdma.c | 32
include/uapi/linux/aspeed-xdma.h | 4
2 files changed, 36 insertions(+)
diff --git a/drivers/soc/aspeed/aspeed-xdma.c b/drivers/soc
to "device", "root-complex"
Eddie James (8):
dt-bindings: soc: Add Aspeed XDMA Engine
soc: aspeed: Add XDMA Engine Driver
soc: aspeed: xdma: Add user interface
soc: aspeed: xdma: Add reset ioctl
ARM: dts: Aspeed: AST2600: Update XDMA engine node
ARM: dts: Aspeed:
Document the bindings for the Aspeed AST25XX and AST26XX XDMA engine.
Signed-off-by: Eddie James
Reviewed-by: Andrew Jeffery
---
.../devicetree/bindings/soc/aspeed/xdma.yaml | 103 +
MAINTAINERS| 6 ++
2 files changed, 109
Correct the pcie-device property, and add the Aspeed SCU interrupt
controller include.
Signed-off-by: Eddie James
---
arch/arm/boot/dts/aspeed-g5.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
ation,
the host data will be placed in the client's memory area.
Poll is also provided in order to determine when the DMA operation is
complete for non-blocking IO.
Signed-off-by: Eddie James
Reviewed-by: Andrew Jeffery
---
drivers/soc/aspeed/aspeed-xdma.c | 218 +++
-off-by: Eddie James
Reviewed-by: Andrew Jeffery
---
MAINTAINERS | 2 +
drivers/soc/aspeed/Kconfig | 8 +
drivers/soc/aspeed/Makefile | 1 +
drivers/soc/aspeed/aspeed-xdma.c | 955 +++
include/uapi/linux/aspeed-xdma.h | 38
Add the PCI-E root complex reset, correct the pcie-device property, and
add the Aspeed SCU interrupt controller include.
Signed-off-by: Eddie James
---
arch/arm/boot/dts/aspeed-g6.dtsi | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b
Add a reserved memory node for the VGA memory. Add the XDMA engine node,
enable it, and point it's memory region to the VGA memory.
Signed-off-by: Eddie James
---
arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts
Add a reserved memory node for the VGA memory. Add the XDMA engine node,
enable it, and point it's memory region to the VGA memory.
Signed-off-by: Eddie James
---
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts
The latest version of the On-Chip Controller (OCC) has a different
format for the temperature sensor data. Add a new temperature sensor
version to handle this data.
Signed-off-by: Eddie James
---
drivers/hwmon/occ/common.c | 75 ++
1 file changed, 75
The OCC in the P10 has a number of differences from the P9. Add some logic to
handle the differences in accessing the OCC from the service processor, and
support the new temperature sensor type.
Eddie James (3):
dt-bindings: fsi: Add P10 OCC device documentation
fsi: occ: Add support for P10
The P10 OCC has a different SRAM address for the command and response
buffers. In addition, the SBE commands to access the SRAM have changed
format. Add versioning to the driver to handle these differences.
Signed-off-by: Eddie James
---
drivers/fsi/fsi-occ.c | 126
Add the P10 compatible string.
Signed-off-by: Eddie James
---
Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt
b/Documentation/devicetree/bindings/fsi/ibm
Document this string that indicates that any version of the power supply
may be connected. In this case, the driver must detect the version
automatically.
Signed-off-by: Eddie James
---
Documentation/devicetree/bindings/hwmon/ibm,cffps1.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git
is applicable.
Eddie James (2):
dt-bindings: hwmon: Document ibm,cffps compatible string
hwmon: (pmbus/ibm-cffps) Add version detection capability
.../devicetree/bindings/hwmon/ibm,cffps1.txt | 3 ++
drivers/hwmon/pmbus/ibm-cffps.c| 37 +++---
2 files changed
Add nodes for the interrupt controllers provided by the SCU.
Signed-off-by: Eddie James
---
arch/arm/boot/dts/aspeed-g6.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 3a1422f..d89f1e6 100644
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