On Wed, 30 Nov 2016 20:14:11 +0100
Jernej Škrabec wrote:
> Dne četrtek, 01. december 2016 ob 03:03:14 CET je Icenowy Zheng napisal(a):
> > 2016年12月1日 02:49于 Jernej Skrabec 写道：
> >
> > > Hi Jean-François,
> > >
> > > Dne sreda, 30. november 2016 10.35.08 UTC+1 je oseba Jean-François Moine
> nap
On Tue, 29 Nov 2016 22:59:32 +0100
Maxime Ripard wrote:
> > > I'm still not sure which pipeline should I use.
> > >
> > > And, it seems that HDMI Slow Clock is not needed?
> > >
> > > (seems that it's only for EDID, but simplefb won't use EDID)
> >
> > So, I don't see how this may work.
> > Ho
On Mon, 28 Nov 2016 17:59:00 +0800
Icenowy Zheng wrote:
> As there's currently a fork of U-Boot which provides simplefb support
> for H3, a simplefb node can be added to the device tree.
>
> Signed-off-by: Icenowy Zheng
> ---
>
> I'm still not sure which pipeline should I use.
>
> And, it see
On Sun, 30 Oct 2016 10:06:20 +0800
Chen-Yu Tsai wrote:
> >> Yes, I know that the burst size is always a power of 2.
> >> The best way to check it would be to change the {src,dts}_maxburst to a
> >> bitmap of the possible bursts as 0x0d for 1,4 and 8 bytes. But this
> >> asks for a lot of changes.
On Tue, 25 Oct 2016 07:38:55 +0200
LABBE Corentin wrote:
> > On Sat, Oct 22, 2016 at 03:53:28PM +0200, Corentin Labbe wrote:
> > > Since SID's content is constant over reboot,
> >
> > That's not true, at least not across all the Allwinner SoCs, and
> > especially not on the A10 and A20 that this
On Tue, 4 Oct 2016 18:55:54 +0200
Maxime Ripard wrote:
> On Tue, Oct 04, 2016 at 12:40:11PM +0200, Jean-Francois Moine wrote:
> > On Tue, 4 Oct 2016 11:46:14 +0200
> > Mylène Josserand wrote:
> >
> > > Add the case of a burst of 4 which is handled by the S
On Thu, 20 Oct 2016 15:49:06 +0200
Maxime Ripard wrote:
> The allwinner,pull property set to NO_PULL was really considered our
> default (and wasn't even changing the default value in the code).
>
> Remove these properties to make it obvious that we do not set anything in
> such a case.
>
> Sig
On Tue, 18 Oct 2016 12:03:49 +0200
Maxime Ripard wrote:
> The fourth one being the major one. Every time I raised the issue on
> IRC, the answer basically was "we don't care about analog", so I'm a
> bit pessimistic about whether dealing with this in the core would be
> accepted, hence why I chos
On Tue, 18 Oct 2016 13:42:09 +0800
Chen-Yu Tsai wrote:
> On the A31, the DMA engine only works if AHB1 is clocked from PLL6.
> In addition, the hstimer is clocked from AHB1, and if AHB1 is clocked
> from the CPU clock, and cpufreq is working, we get an unstable timer.
>
> Force the AHB1 clock to
ai_name);
>
> int snd_soc_of_get_dai_name(struct device_node *of_node,
> const char **dai_name)
> --
> 1.9.1
I already proposed this patch
http://mailman.alsa-project.org/pipermail/alsa-devel/2015-January/086870.html
but it seems people were not interested.
I hope now is the right time.
Acked-by: Jean-Francois Moine
--
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef | http://moinejf.free.fr/
On Mon, 17 Oct 2016 08:30:49 +
Kuninori Morimoto wrote:
> These are OF graph base simple-card patch-set.
> 1) - 3) : simple-scu-card cleanup
> 4) - 10) : soc-core prepare for OF graph card
> 11) - 17) : OF graph new feature
> 18) - 23) : OF graph base simple-card
>
> I posted 11) - 17) OF
On Fri, 7 Oct 2016 10:25:55 +0200
Corentin Labbe wrote:
> The sun8i-emac hardware is present on the Orange PI 2.
> It uses the internal PHY.
>
> This patch create the needed emac node.
>
> Signed-off-by: Corentin Labbe
> ---
> arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8
> 1 file
On Mon, 10 Oct 2016 14:35:11 +0200
LABBE Corentin wrote:
> On Mon, Oct 10, 2016 at 02:30:46PM +0200, Maxime Ripard wrote:
> > On Fri, Oct 07, 2016 at 10:25:57AM +0200, Corentin Labbe wrote:
> > > Enable the sun8i-emac driver in the multi_v7 default configuration
> > >
> > > Signed-off-by: Corent
On Mon, 10 Oct 2016 14:31:51 +0200
Maxime Ripard wrote:
> Hi,
>
> On Fri, Oct 07, 2016 at 10:25:51AM +0200, Corentin Labbe wrote:
> > This patch add the dt node for the syscon register present on the
> > Allwinner H3.
> >
> > Only two register are present in this syscon and the only one useful
On Wed, 5 Oct 2016 11:48:24 +0200
Corentin Labbe wrote:
> This patch add support for the sunxi-sid driver to the device tree for
> sun8i-h3.
>
> Signed-off-by: Corentin Labbe
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/
On Wed, 5 Oct 2016 08:04:26 +0200
Code Kipper wrote:
> > +static int sun8i_probe(struct platform_device *pdev)
> > +{
> > + struct snd_soc_dai_link *link = &sun8i_dai_link;
> > + struct device_node *np = pdev->dev.of_node;
> > + int ret;
> > +
> > + /* register the soc car
On Tue, 4 Oct 2016 14:12:21 +0200
Thomas Petazzoni wrote:
> > > Add the case of a burst of 4 which is handled by the SoC.
> > >
> > > Signed-off-by: Mylène Josserand
> > > ---
> > > drivers/dma/sun6i-dma.c | 2 ++
> > > 1 file changed, 2 insertions(+)
> > >
> > > diff --git a/drivers/dma/sun6
On Tue, 4 Oct 2016 11:46:18 +0200
Mylène Josserand wrote:
> The sun8i audio codec is using PRCM registers to configure all the
> analog part of the audio codec. It is added as a subnode of the PRCM
> with his resource (offset of 0x1c0).
>
> Signed-off-by: Mylène Josserand
> ---
> drivers/mfd/
On Tue, 4 Oct 2016 11:46:14 +0200
Mylène Josserand wrote:
> Add the case of a burst of 4 which is handled by the SoC.
>
> Signed-off-by: Mylène Josserand
> ---
> drivers/dma/sun6i-dma.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma
On Sat, 24 Sep 2016 16:35:05 +0800
Chen-Yu Tsai wrote:
> On Fri, Sep 23, 2016 at 4:58 PM, Jean-Francois Moine wrote:
> > This patch series adds support for the X-Powers AXP803 and AXP813 PMICs.
> > It is based on the previous patch series
> > regulator: axp20x:
On Sat, 24 Sep 2016 16:29:11 +0800
Chen-Yu Tsai wrote:
[snip]
> > static int axp20x_regulator_probe(struct platform_device *pdev)
> > {
> > + struct device *dev = pdev->dev.parent;
>
> There are 2 struct device's in play in this function, 1 from the parent,
> and 1 for the platfo
The axp20x driver contains device specific and device independant parts.
This patch moves the independant parts to new .c/.h files.
Signed-off-by: Jean-Francois Moine
---
drivers/regulator/Makefile | 2 +-
drivers/regulator/axp-regulator.c| 308
The X-Powers AXP813 PMIC is close to the AXP803.
It is used in some Allwinner boards as the Sinovoip BananaPi M3+.
Signed-off-by: Jean-Francois Moine
---
Documentation/devicetree/bindings/mfd/axp20x.txt | 9 +-
drivers/mfd/axp20x.c | 2 +
drivers/regulator
The X-Powers AXP803 PMIC is close to the AXP809 with more outputs.
It is used in some Allwinner boards as the Sinovoip BananaPi M64
and the Pine A64.
Signed-off-by: Jean-Francois Moine
---
not tested
---
Documentation/devicetree/bindings/mfd/axp20x.txt | 32 +++-
drivers/mfd/axp20x.c
interrupts
v2:
- fix lack of support of dcdc frequency
- notice that the AXP803 is also handled
- send the patch to the DT maintainers
Jean-Francois Moine (4):
regulator: axp20x: move device independant parts to new files
regulator: axp20x: duplicate the MFD axp20x-rsb code
regulator: axp20x: add
The axp20x rsb driver handles many different devices.
Duplicating its code in a generic regulator driver permits
to probe/remove individual devices.
Signed-off-by: Jean-Francois Moine
---
drivers/regulator/axp-regulator.c | 39 +++
drivers/regulator/axp
This patch series just simplifies a bit the code of the AXP20x driver.
It does not contain any fonctional changes.
It will be used as a base for adding new AXP devices (patches to come).
It applies on linux-next.
Jean-Francois Moine (3):
regulator: axp20x: simplify poly-phase handling
Using ancillary variables for handling the linked regulators simplifies
the loop of regulator creation and makes easier the addition of new
regulator types.
Signed-off-by: Jean-Francois Moine
---
drivers/regulator/axp20x-regulator.c | 24
1 file changed, 16 insertions
Use the pointer to the main regulator device instead of the pointer
to the child platform device.
Signed-off-by: Jean-Francois Moine
---
drivers/regulator/axp20x-regulator.c | 45 ++--
1 file changed, 23 insertions(+), 22 deletions(-)
diff --git a/drivers
Building a list (bitmap) of the slaves included in poly-phase groups
at probe startup time simplifies the treatment in the regulator
creation loop.
Signed-off-by: Jean-Francois Moine
---
drivers/regulator/axp20x-regulator.c | 45 +---
1 file changed, 21
On Tue, 16 Aug 2016 23:04:47 +0800
Icenowy Zheng wrote:
> > Also, please, may you give me a pointer to the AXP813 documentation?
> I got it on BaiduPan.
> https://pan.baidu.com/share/link?shareid=120641733&uk=2121502978&fid=169295081716431
> Here's a link, you can download it if you can read Chin
On Tue, 16 Aug 2016 19:30:17 +0800
Icenowy Zheng wrote:
> > The X-Powers AXP803 and AXP813 PMICs are close to the AXP809 with some
> > more outputs.
> AXP803 and AXP813 is quite different.
> AXP803 have 6 DCDCs and 16 LDOs&Switch.
> AXP813 have 7 DCDCs and 15 LDOs&Switch.
> and AXP813 have an aud
On Mon, 15 Aug 2016 16:13:14 +0800
Chen-Yu Tsai wrote:
> +/*
> + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
> + * the base (2x, 4x and 8x), and one variable divider (the one true
> + * pll audio).
> + *
> + * We don't have any need for the variable divider for now, so we
On Tue, 9 Aug 2016 18:02:47 +0800
Chen-Yu Tsai wrote:
> > The 'parent's of the bus gates are of no interest.
> > They are supposed to be (no clear documentation) apb1, apb2, ahb1 and
> > ahb2, but, as you well noticed in the patch 5/7, these clocks are fixed
> > and have no gate. Some of them are
On Mon, 8 Aug 2016 18:21:45 +0100
Andre Przywara wrote:
> The Allwinner H3 SoC introduced bus clock gates with potentially
> different parents per clock gate register. The H3 driver chose to
> hardcode the actual parent clock relation in the code.
> Add a new driver (which has the potential to d
On Mon, 1 Aug 2016 20:01:49 +0800
Chen-Yu Tsai wrote:
> On Mon, Aug 1, 2016 at 8:00 PM, Jean-Francois Moine wrote:
> > On Mon, 1 Aug 2016 17:13:34 +0800
> > Chen-Yu Tsai wrote:
> >
> >> > But I don't see why you are keeping the simple-gates. The bus gat
On Mon, 1 Aug 2016 17:13:34 +0800
Chen-Yu Tsai wrote:
> > But I don't see why you are keeping the simple-gates. The bus gate may
> > be ungated/gated when the clock is enabled/disabled, and that's what
> > Allwinner's software does.
>
> For peripherals that have a separate mod clock, having them
On Mon, 1 Aug 2016 02:43:06 +0100
André Przywara wrote:
> As this became quite a long read, here a TL;DR:
> - We consider using an SCPI based clock system for the A64, alongside
> allwinner,simple-gates and fixed clocks. We try to avoid any Allwinner
> specific clocks (apart from the simple-gates
On Thu, 28 Jul 2016 22:19:44 +0200
Maxime Ripard wrote:
> > Documentation/devicetree/bindings/mfd/axp20x.txt | 32 -
> > drivers/mfd/axp20x-rsb.c | 1 +
> > drivers/mfd/axp20x.c | 3 +
> > drivers/regulator/axp20x-regulator.c
On Thu, 28 Jul 2016 22:07:05 +0200
Maxime Ripard wrote:
> > > Let me know what you think,
> >
> > I don't see the interest to have common code for 32bits and 64bits.
> > The clock driver of a SoC will never evolve, so, it is simpler to
> > copy the source common with the H3 into a clean A64 cloc
On Thu, 28 Jul 2016 15:28:42 +0200
Maxime Ripard wrote:
> On Wed, Jul 27, 2016 at 10:36:49AM +0200, Jean-Francois Moine wrote:
> > On Wed, 27 Jul 2016 09:40:20 +0200
> > Maxime Ripard wrote:
> >
> > > > > Parenting functions would also not work as expected,
On Tue, 26 Jul 2016 22:30:28 +0200
Maxime Ripard wrote:
> ere is the previous A64 patches made by Andre [1], reworked to use
> the new sunxi-ng clock framework.
>
> This uses the current H3 clock code, as both are really similar. The
> first patches are just meant to rework slightly the H3 code,
On Tue, 26 Jul 2016 15:04:27 +0800
Chen-Yu Tsai wrote:
> Some clocks on the A31 have fixed pre-dividers on multiple parents.
> Add support for them.
This could be done by intermediate clocks.
--
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef | http://mo
On Wed, 27 Jul 2016 09:40:20 +0200
Maxime Ripard wrote:
> > > Parenting functions would also not work as expected,
> > > clk_hw_get_parent_by_index being the obvious example, in that case
> > > returning the empty string for an invalid parent, while it should
> > > really return NULL.
> >
> > I
On Wed, 27 Jul 2016 08:59:34 +0200
Maxime Ripard wrote:
> On Tue, Jul 26, 2016 at 07:43:06PM +0200, Jean-Francois Moine wrote:
> > On Tue, 26 Jul 2016 15:04:26 +0800
> > Chen-Yu Tsai wrote:
> >
> > > Some clock muxes have holes, i.e. invalid or unconnected in
On Tue, 26 Jul 2016 15:04:26 +0800
Chen-Yu Tsai wrote:
> Some clock muxes have holes, i.e. invalid or unconnected inputs,
> between parent mux values.
>
> Add support for specifying a mux table to map clock parents to
> mux values.
Putting empty strings in the holes should work. No?
Ex:
static
On Tue, 26 Jul 2016 15:04:30 +0800
Chen-Yu Tsai wrote:
> +static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
> + { .index = 0, .div = 750, },
> + { .index = 3, .div = 4, },
> + { .index = 4, .div = 4, },
> +};
No end of table.
--
Ken ar c'hentañ | ** Breizh
On Fri, 15 Jul 2016 12:38:54 +0200
Ondřej Jirman wrote:
> > If so, then yes, trying to switch to the 24MHz oscillator before
> > applying the factors, and then switching back when the PLL is stable
> > would be a nice solution.
> >
> > I just checked, and all the SoCs we've had so far have that
On Fri, 1 Jul 2016 08:34:21 +0200
Ondřej Jirman wrote:
> > The documentation says that only the CPU and DDR PLLs can be dynamically
> > changed after boot.
>
> The question is what exactly is meant by after boot. :) Anyway, if the
> kernel has no business changing some other PLLs, if there's cod
On Fri, 1 Jul 2016 02:50:57 +0200
Ondřej Jirman wrote:
> > Since this is really specific, I guess you could simply make the
> > clk_ops for the nkmp clocks public, and just re-implement set_rate
> > using that logic.
>
> I would argue that this may be necessary for other PLL clocks too, if
> you
On Wed, 29 Jun 2016 21:05:34 +0200
Maxime Ripard wrote:
> +static void __init sun8i_h3_ccu_setup(struct device_node *node)
> +{
> + void __iomem *reg;
> + u32 val;
> +
> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> + if (IS_ERR(reg)) {
> + pr_err(
On Tue, 21 Jun 2016 16:47:52 +0200
Maxime Ripard wrote:
> > But I had some problems with some features as the 'mode select' in the
> > A83T MMC2 clock.
> > Also, I think that you did not go far enough in the changes.
>
> At some point, you also have to support what's used out there,
> otherwise
On Tue, 7 Jun 2016 22:41:39 +0200
Maxime Ripard wrote:
> The current code has been tested on the H3 and an Orange Pi PC,
> including making sure that MMC still works, so the general approach
> seems ok.
>
> Let me know what you think,
Hi Maxime,
I used your code in both the H3 and A83T, and i
On Tue, 7 Jun 2016 22:41:47 +0200
Maxime Ripard wrote:
> Add support for the various dividers (linear, table or pow-of-two based)
> found in the CCU.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/clk/sunxi-ng/Makefile | 1 +
> drivers/clk/sunxi-ng/ccu_div.c | 136
>
On Tue, 7 Jun 2016 22:41:53 +0200
Maxime Ripard wrote:
> Add the list of clocks and resets found in the H3 CCU.
>
> Signed-off-by: Maxime Ripard
>
> ---
> Changes from v1:
> - Only build the H3 clocks description when MACH_SUN8I is set
> ---
> drivers/clk/sunxi-ng/Makefile| 2 +
>
On Tue, 7 Jun 2016 22:41:50 +0200
Maxime Ripard wrote:
> Introduce support for clocks that multiply and divide using linear factors.
>
> Signed-off-by: Maxime Ripard
>
> ---
> Changes from v1:
> - Fixed the maximums for both factors passed to the rational factor
> computation.
> ---
>
On Tue, 7 Jun 2016 22:41:47 +0200
Maxime Ripard wrote:
> Add support for the various dividers (linear, table or pow-of-two based)
> found in the CCU.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/clk/sunxi-ng/Makefile | 1 +
> drivers/clk/sunxi-ng/ccu_div.c | 136
>
On Tue, 7 Jun 2016 22:41:44 +0200
Maxime Ripard wrote:
> Some clocks in the Allwinner SoCs clocks unit are just simple gates. Add
> support for those clocks.
>
> Since it's a feature that can also be found in more complex clocks, provide
> a bunch of helpers that can be reused later on.
>
> Si
On Tue, 7 Jun 2016 22:41:41 +0200
Maxime Ripard wrote:
> Start our new clock infrastructure by adding the registration code, common
> structure and common code.
>
> Signed-off-by: Maxime Ripard
>
> ---
> Changes from v1:
> - Moved from of_iomap to of_io_request_and_map
> - Change lock bit
On Mon, 30 May 2016 20:45:32 +0200
Maxime Ripard wrote:
> I went over all the A83T clocks, and most of them could be
> covered. The issue only lies in the PLLs and their additional 1-bit
> dividers.
>
> If we just choos to ignore (one of) them, it should be pretty trivial
> to implement with the
On Fri, 5 Feb 2016 12:11:52 +0100
Maxime Ripard wrote:
> However, I'd like to keep per-soc and per-clocks compatibles in the
> DT, in case we need to protect a clock in the future.
What do you mean by "protect a clock"?
--
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef
On Thu, 4 Feb 2016 00:33:46 +0100
Krzysztof Adamski wrote:
> This patch adds support for APB0 in H3. It seems to be compatible with
> earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
> etc).
>
> Signed-off-by: Krzysztof Adamski
> ---
> Documentation/devicetree/bindings/clo
ing of PCM pins
>
> drivers/clk/sunxi/Makefile | 1 +
> drivers/clk/sunxi/clk-multi-gates.c | 105
>
> 2 files changed, 106 insertions(+)
> create mode 100644 drivers/clk/sunxi/clk-multi-gates.c
[snip]
Glad to see that th
On Fri, 29 Jan 2016 14:47:39 +0800
Yakir Yang wrote:
> The Innosilicon HDMI is a low power HDMI 1.4 transmitter
> IP, and it have been integrated on some rockchip CPUs
> (like RK3036, RK312x).
>
> Signed-off-by: Yakir Yang
> ---
> Changes in v8:
> - Don't check whether encoder output format is
On Thu, 24 Dec 2015 12:36:10 +
Russell King - ARM Linux wrote:
> It seems that you're trying to work around a limitation in Linux by
> modifying the hardware representation...
Sorry to come back to this topic, but I think you are wrong.
Looking at the imx6 DTs, the problem comes from the di
On Thu, 24 Dec 2015 10:52:07 +
Russell King - ARM Linux wrote:
> On Thu, Dec 24, 2015 at 09:15:28AM +0100, Jean-Francois Moine wrote:
> > Well, two topics:
> >
> > - adding a second 'of_compare' function complexifies the code
> > and people may won
On Wed, 23 Dec 2015 18:59:48 +
Russell King - ARM Linux wrote:
> > > Have a look at my v2 where I've introduced two compare functions and also
> > > modified the Rockchip compare_port() to use port->parent in the
> > > comparison. I
> > > guess that should solve your problem.
> >
> > Keepin
On Wed, 23 Dec 2015 10:05:34 +
Liviu Dudau wrote:
> > What was the reason to keep the "ports" node instead of the device?
>
> The function is an extract of common code sprinkled through a few DRM drivers,
> they all used port rather than port->parent.
Sorry for I could find such drivers. Ma
On Tue, 22 Dec 2015 17:38:00 +
Liviu Dudau wrote:
> On Fri, Nov 20, 2015 at 02:22:03PM +, Liviu Dudau wrote:
> > Hello,
> >
> > This is v2 of the patchset trying to make drm_of_component_probe() cope
> > with finding
> > both local crtc ports and remote encoder ones. Heiko Stübner was n
On Tue, 8 Dec 2015 09:32:24 +0100
Maxime Ripard wrote:
> If the H3 display block is done the same way than the A10 (and later)
> one on this aspect, then the TCON has two channels with two different
> streaming (or functional, you pick the name) clocks. The channel 0 is
> usually used for RGB, th
On Tue, 8 Dec 2015 08:53:54 +0100
Maxime Ripard wrote:
> Look, we all agreed on a solution that raised all objections, but
> yours.
>
> I'm going to take Jens patch.
OK. Good luck for the next SoCs!
--
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef | h
On Mon, 7 Dec 2015 19:44:30 +0100
Jens Kuske wrote:
> >> + "bus_lcd0", "bus_lcd1",
> >> "bus_deint",
>
> > "bus_tcon0", "bus_tcon1", "bus_deint",
> >
> > (the tcon1 clock is used by both lcd0 and lcd1, while
> > the tcon0 clock is used for TV output f
On Mon, 7 Dec 2015 08:31:02 -0600
Rob Herring wrote:
> On Sun, Dec 06, 2015 at 10:04:12AM +0100, Jean-Francois Moine wrote:
> > The H3 has a clock gate definition similar to the other Allwinner SoCs,
> > but with a different parent clock for each single gate.
> >
> &
On Fri, 4 Dec 2015 22:24:42 +0100
Jens Kuske wrote:
> The Allwinner H3 is a home entertainment system oriented SoC with
> four Cortex-A7 cores and a Mali-400MP2 GPU.
>
> Signed-off-by: Jens Kuske
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 497
>
> 1 fi
.
Signed-off-by: Jean-Francois Moine
---
This patch replaces a part of Jens Kuske's patch
[PATCH v5 1/4] clk: sunxi: Add H3 clocks support
---
Documentation/devicetree/bindings/clock/sunxi.txt | 25 +++
drivers/clk/sunxi/clk-simple-gates.c
On Wed, 4 Nov 2015 08:30:14 -0800
Maxime Ripard wrote:
> Hi Arnd,
>
> On Fri, Oct 30, 2015 at 09:27:03AM +0100, Arnd Bergmann wrote:
> > On Tuesday 27 October 2015 17:50:24 Jens Kuske wrote:
> > >
> > > +static int sun8i_h3_bus_reset_xlate(struct reset_controller_dev *rcdev,
> > > +
On Tue, 27 Oct 2015 17:50:25 +0100
Jens Kuske wrote:
> The Allwinner H3 is a home entertainment system oriented SoC with
> four Cortex-A7 cores and a Mali-400MP2 GPU.
>
> Signed-off-by: Jens Kuske
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 482
>
> 1 fi
On Tue, 27 Oct 2015 17:50:20 +0100
Jens Kuske wrote:
> Changes since v3:
> - add a clock driver specific to the bus gates instead of listing parents in
> the DTSI
> - skip the holes in the reset controller with of_xlate()
Hi, Maxime, there we are :(. The H3 description is hardcoded and the
nex
On Sat, 24 Oct 2015 09:13:28 +0200
Maxime Ripard wrote:
> Or simply
>
> bus_gates {
> clocks = <&ahb1>, <&ahb2>;
> clock-indices = <5>, <6>, <8>, ...
> clock-output-names = "bus_ce", "bus_dma", "bus_mmc0"
> };
I don't understand: the apb1, apb2, ahb1 and ahb2 clocks may be
pro
On Fri, 23 Oct 2015 20:14:06 +0200
Maxime Ripard wrote:
> On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote:
> > + bus_gates: clk@01c20060 {
> > + #clock-cells = <1>;
> > + compatible = "allwinner,sun8i-h3-bus-gates-clk";
> > +
On Wed, 21 Oct 2015 18:20:27 +0200
Jens Kuske wrote:
> The Allwinner H3 is a home entertainment system oriented SoC with
> four Cortex-A7 cores and a Mali-400MP2 GPU.
>
> Signed-off-by: Jens Kuske
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 499
>
> 1 fi
On Thu, 22 Oct 2015 10:47:35 +0200
Maxime Ripard wrote:
> Not really. The uart0 reset is the bit 16, in the reset register 4.
>
> 4 * 32 + 16 = 44.
>
> Not 112, but still not 208 either.
The registers are numbered 1..5, then
(4 - 1) * 32 + 16 = 112
--
Ken ar c'hentañ | ** Breizh
On Thu, 22 Oct 2015 10:05:08 +0200
Maxime Ripard wrote:
> > + uart0: serial@01c28000 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x01c28000 0x400>;
> > + interrupts = ;
> > + reg-shift = <2>;
> > +
On Wed, 21 Oct 2015 21:18:45 +0200
Hans de Goede wrote:
> Great to see that you've started working on this again. Last weekend I
> ended up working on this too together with Reinder E.N. de Haan
>
> (added to the Cc).
>
> We took a slightly different approach for the gates clocks, see:
>
> ht
Sorry to enter this thread a bit late.
About the number of probe deferred messages, I proposed a simple patch to
reduce them:
https://lkml.org/lkml/2013/8/20/218
I was wondering how many messages this patch could save...
--
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef
t; timeout condition check covers the wait-queue related failure condition.
>
> Signed-off-by: Nicholas Mc Guire
Acked-by: Jean-Francois Moine
--
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef | http://moinejf.free.fr/
--
To unsubscribe from
The tda998x CODEC maintains the audio constraints according to
the HDMI device parameters (EDID) and sets dynamically the input ports
in the TDA998x I2C driver on start/stop audio streaming.
Signed-off-by: Jean-Francois Moine
---
drivers/gpu/drm/i2c/tda998x_drv.c | 80
encoder use.
Signed-off-by: Jean-Francois Moine
---
drivers/gpu/drm/i2c/tda998x_drv.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c
b/drivers/gpu/drm/i2c/tda998x_drv.c
index bcf96f7..7a9d9a7 100644
--- a/drivers/gpu/drm/i2c
/tda998x.h prepares to the definition of
a tda998x CODEC.
Signed-off-by: Jean-Francois Moine
---
.../devicetree/bindings/drm/i2c/tda998x.txt| 51
drivers/gpu/drm/i2c/tda998x_drv.c | 90 +++---
include/sound/tda998x.h| 8
From: Russell King - ARM Linux
Add a helper for the EDID like data structure, which is typically passed
from a HDMI adapter to its associated audio driver. This informs the
audio driver of the capabilities of the attached HDMI sink.
Signed-off-by: Jean-Francois Moine
---
include/sound
Signed-off-by: Jean-Francois Moine
---
sound/core/pcm_drm_eld.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/sound/core/pcm_drm_eld.c b/sound/core/pcm_drm_eld.c
index 47d9b60..a553d30 100644
--- a/sound/core/pcm_drm_eld.c
+++ b/sound/core/pcm_drm_eld.c
@@ -42,7 +42,6 @@ static int
From: Russell King - ARM Linux
Add a function to find the start of the SADs in the ELD. This
complements the helper to retrieve the SAD count.
Signed-off-by: Jean-Francois Moine
---
include/drm/drm_edid.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/drm
rew Jackson)
v3: fix bad rate (Andrew Jackson)
v2: check double stream start (Mark Brown)
Jean-Francois Moine (6):
drm/edid: add function to help find SADs
sound/core: add DRM ELD helper
sound/core: remove the trace from the DRM ELD helper
drm/i2c: tda998x: Add support of a DT graph of port
On Fri, 01 May 2015 11:30:18 +0200
Sebastian Hesselbarth wrote:
> > I applied the patches 2 and 3, and the audio and video in the Cubox
> > work fine again. Thanks.
>
> Ok, good. You mentioned that on v3.19-rc1 it still "works" i.e. despite
> the broken/missing clk_get/clk_prepare_enable?
>
>
On Thu, 30 Apr 2015 19:45:50 +0200
Sebastian Hesselbarth wrote:
> For Si5351 clock driver, Michael Welling and Jean-Francois Moine reported
> issues with recent v4.x kernels due to broken/missing/wrong parent clock
> claming. This patch set now deals with the issues reported.
>
>
The tda998x CODEC maintains the audio format and rate constraints according
to the HDMI device parameters (EDID) and sets dynamically the input ports
in the TDA998x I2C driver on start/stop audio streaming.
Signed-off-by: Jean-Francois Moine
---
drivers/gpu/drm/i2c/tda998x_drv.c | 124
/tda998x.h prepares to the definition of
a tda998x CODEC.
Signed-off-by: Jean-Francois Moine
---
.../devicetree/bindings/drm/i2c/tda998x.txt| 51 +
drivers/gpu/drm/i2c/tda998x_drv.c | 88 +++---
include/sound/tda998x.h| 8
encoder use.
Signed-off-by: Jean-Francois Moine
---
drivers/gpu/drm/i2c/tda998x_drv.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c
b/drivers/gpu/drm/i2c/tda998x_drv.c
index a2ed391..e9b497e 100644
--- a/drivers/gpu/drm/i2c
DEC to the TDA998x
- move the CODEC to sound/soc (Mark Brown)
- update the audio_sample_rate from the EDID (Andrew Jackson)
v3: fix bad rate (Andrew Jackson)
v2: check double stream start (Mark Brown)
Jean-Francois Moine (3):
drm/i2c: tda998x: Add support of a DT graph of ports
gt; as I've only accepted to contribute under the terms of GPLv2.
>
> Ok, I guess this is a NACK for GPLv2+ but an Acked-by if we limit the
> GPL part to GPLv2 only?
>
> If so, is everybody else who already Acked the GPLv2+ part also fine
> with reducing the GPL version to "
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