On Tue, Sep 25, 2012 at 03:22:04AM +0200, Sebastian Hesselbarth wrote:
On 09/25/2012 02:02 AM, Sebastian Hesselbarth wrote:
During the review process of dove DT patches, Tauros2 cache
init call was changed and DT support added. This patch fixes
the call to Tauros2 init and adds a DT node.
On Tue, Sep 25, 2012 at 02:02:17AM +0200, Sebastian Hesselbarth wrote:
The watchdog on dove requires an interrupt that is not yet
available on DT. Therefore, the watchdog DT node is removed
until the corresponding chained intc is available.
Hi Sebastian
Just for my understanding: Is the
request. But:
Acked-by: Andrew Lunn and...@lunn.ch
None of my questions should be considered as NACKs for these patches.
Andrew
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On Tue, Sep 25, 2012 at 11:18:26AM +0200, Thomas Petazzoni wrote:
Dear Sebastian Hesselbarth,
On Tue, 25 Sep 2012 11:11:42 +0200, Sebastian Hesselbarth wrote:
I didn't try to post all the dove on mach-mvebu patches in the current
release cycle, because mach-mvebu is still evolving to
On Tue, Sep 25, 2012 at 12:14:39PM +0200, Thomas Petazzoni wrote:
Dear Andrew Lunn,
On Tue, 25 Sep 2012 11:46:10 +0200, Andrew Lunn wrote:
I principle, i agree. However, i'm not too sure about mach-orion5x
mach-mv78xx0. orion5x has probably been broken since -rc1 was released
incompatible pointer type [enabled by default]
/home/arnd/linux-arm/arch/arm/mach-mv78xx0/addr-map.c:59:2: warning: (near
initialization for 'addr_map_cfg.win_cfg_base') [enabled by default]
Signed-off-by: Arnd Bergmann a...@arndb.de
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
On Tue, Nov 06, 2012 at 10:28:45PM +0100, S?ren Moch wrote:
resent as plain text, sorry.
For Armada 370/XP we have the same problem that for the commit
cb01b63, so we applied the same solution: The default 256 KiB
coherent pool may be too small for some of the Kirkwood devices, so
grant.lik...@secretlab.ca
Cc: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Cc: Andrew Lunn and...@lunn.ch
Signed-off-by: Linus Walleij linus.wall...@linaro.org
---
ChangeLog v1-v2:
- Keep irq_create_mapping() and do not replace
On Wed, Oct 24, 2012 at 03:49:21PM +0200, Gregory CLEMENT wrote:
From: Lior Amsalem al...@marvell.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Lior Amsalem al...@marvell.com
---
arch/arm/boot/dts/armada-370-db.dts |3 +++
On Fri, Oct 26, 2012 at 02:30:45PM +0200, Gregory CLEMENT wrote:
Hello,
this patch set adds the SATA support for Armada 370 and Armada XP. Few
changes have been done since the first version by taking in account
the comments received for the first version.
The evaluation boards for Armada
On Fri, Oct 26, 2012 at 02:48:04PM +0200, Thomas Petazzoni wrote:
On Fri, 26 Oct 2012 14:39:08 +0200, Andrew Lunn wrote:
What about the openblocks-ax3?
Gr??gory does not (yet) have an OpenBlocks AX3, but I'm planning to do
the work for SATA soon for this platform. However, supporting
On Fri, Oct 26, 2012 at 09:31:54AM -0400, Jason Cooper wrote:
On Fri, Oct 26, 2012 at 02:30:47PM +0200, Gregory CLEMENT wrote:
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Lior Amsalem al...@marvell.com
---
arch/arm/boot/dts/armada-370-xp.dtsi |9
Now, about white spaces vs tab, I don't know what is the rule for .dts
file.
I personally use tabs, but i don't see anything in the
Documentation/CodingStyle.
Maybe ask on the device tree mailing list?
Andrew
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diff --git a/arch/arm/boot/dts/mbx001.dts b/arch/arm/boot/dts/mbx001.dts
new file mode 100644
index 000..88a5a11
--- /dev/null
+++ b/arch/arm/boot/dts/mbx001.dts
Hi Gregory
Maybe it would be good to prefix this with armada-370. It then fits
with armada-370-db.dts, and all the kirkwood
If the gpio_request_one() fails, or returns EPROBE_DEFER, the
regulator must be device_unregister()ed. When this is not done,
there are WARNING: from sysfs:
WARNING: at fs/sysfs/file.c:343 sysfs_open_file+0x238/0x268()
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/regulator/core.c
-electrons.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Tested-by: Andrew Lunn and...@lunn.ch
I tested this on a Kirkwood QNAP after removing the call to
init_dma_coherent_pool_size().
Andrew
---
mm/dmapool.c | 27 +++
1 file changed, 7
On Mon, Nov 12, 2012 at 10:48:02AM +0100, Soeren Moch wrote:
On 11.11.2012 18:22, Andrew Lunn wrote:
On Thu, Nov 08, 2012 at 07:38:57AM +0100, Marek Szyprowski wrote:
dmapool always calls dma_alloc_coherent() with GFP_ATOMIC flag,
regardless
the flags provided by the caller. This causes
On Thu, Mar 21, 2013 at 05:26:15PM +0100, Gregory CLEMENT wrote:
From: Lior Amsalem al...@marvell.com
For mvebu IOs are 32 bits and we have 40 bits memory due to LPAE so
make sure we give 32 bits addresses to the IOs.
Hi Gregory, Lior
I don't really understand what this comment is supposed
/*
- * 4 GB of plug-in RAM modules by default but only 3GB
- * are visible, the amount of memory available can be
- * changed by the bootloader according the size of the
- * module actually plugged
+ * 8 GB of
On Thu, Mar 21, 2013 at 09:22:36PM +0100, Thomas Petazzoni wrote:
Dear Andrew Lunn,
On Thu, 21 Mar 2013 21:15:33 +0100, Andrew Lunn wrote:
Could you recommend a document which introduces LPAE.
Only being able to address 7GB seems a bit odd to me. I kind of
expected you set up
On Thu, Mar 21, 2013 at 05:12:01PM -0400, Alan Stern wrote:
On Thu, 21 Mar 2013, Alan Stern wrote:
On Thu, 21 Mar 2013, Soeren Moch wrote:
Now I found out what is going on here:
In itd_urb_transaction() we allocate 9 iTDs for each URB with
number_of_packets == 64 in my case.
by configuring mpp0
to gpio, while used also by nand (nand_io2 on mpp0).
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Tested-by: Soeren Moch sm...@web.de
Acked-by: Andrew Lunn and...@lunn.ch
---
Cc: Soeren Moch sm...@web.de
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew
On Sat, Mar 23, 2013 at 01:58:22PM +0100, Sebastian Hesselbarth wrote:
This patch just adds the missing MACH_GURUPLUG_DT to kirkwood_defconfig.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Reported-by: Soeren Moch sm...@web.de
Acked-by: Andrew Lunn and...@lunn.ch
...@gmail.com
Acked-by: Andrew Lunn and...@lunn.ch
---
Cc: Russell King li...@arm.linux.org.uk
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm/Kconfig |2 +-
1 file changed, 1 insertion
messages can be removed from the failure code paths.
Signed-off-by: Silviu-Mihai Popescu silviupopescu1...@gmail.com
---
Acked-by: Andrew Lunn and...@lunn.ch
Thanks
Andrew
drivers/cpufreq/kirkwood-cpufreq.c |8 +++-
drivers/cpuidle/cpuidle-kirkwood.c |6
devm_rtc_device_register() from the akpm tree.
I fixed it up (I think - see below) and can carry the fix as necessary
(no action is required).
Hi Stephan
Looks O.K. to me.
Acked-by: Andrew Lunn and...@lunn.ch
--
Cheers,
Stephen Rothwells...@canb.auug.org.au
diff
Now I activated the debug messages in em28xx. From the messages I
see no correlation of the pool exhaustion and lost sync. Also I
cannot see any error messages from the em28xx driver.
I see a lot of init_isoc/stop_urbs (maybe EPG scan?) without
draining the coherent pool (checked with 'cat
(restart_poweroff_remove),
+ .remove = restart_poweroff_remove,
.driver = {
.name = poweroff-restart,
.owner = THIS_MODULE,
--
1.8.1.2
Acked-by: Andrew Lunn and...@lunn.ch
Thanks
Andrew
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On Wed, Jan 23, 2013 at 04:30:53PM +0100, Soeren Moch wrote:
On 19.01.2013 19:59, Andrew Lunn wrote:
Please find attached a debug log generated with your patch.
I used the sata disk and two em28xx dvb sticks, no other usb devices,
no ethernet cable connected, tuners on saa716x-based card
Now (in the last hour) stable, occasionally lower numbers:
3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396
3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396
3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396 3396
3396 3396 3396 3396
On Wed, Jan 16, 2013 at 12:43:57PM +0100, Stefan Peter wrote:
Hi Andrew
on 15.01.2013 13:51, Andrew Lunn wrote:
On Tue, Jan 15, 2013 at 01:13:12PM +0100, Stefan Peter wrote:
In order to be able to use the ecc-mode, add the bch module to the default
settings for the kirwood boards
On Thu, Jan 17, 2013 at 08:26:45PM +, Arnd Bergmann wrote:
On Thursday 17 January 2013, Soeren Moch wrote:
On 17.01.2013 11:49, Arnd Bergmann wrote:
On Wednesday 16 January 2013, Soeren Moch wrote:
I will see what I can do here. Is there an easy way to track the buffer
usage
Please find attached a debug log generated with your patch.
I used the sata disk and two em28xx dvb sticks, no other usb devices,
no ethernet cable connected, tuners on saa716x-based card not used.
What I can see in the log: a lot of coherent mappings from sata_mv
and orion_ehci, a few
I had a closer look at how kirkwood probes its id. I mentionend kirkwood_id()
earlier but in fact it is kirkwood_pcie_id(). I assume pcie registers are shut
down with pcie clk gated? That would require to have pcie running at least at
boot-time on all boards.
While it is still possible to
thinks that autoprobing is not going to happen,
Tested-by: Andrew Lunn and...@lunn.ch
However, i still think it would be nice to have auto probing.
Andrew
Cc: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Cc: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc: Grant Likely
Hi Thomas
Hum, which patches are stalling the integration into the Marvell tree?
l2 cache, I think.
The trees Jason built for pull requests in the direction of arm-soc
had the l2 cache patch as the very first in the series. Now that these
patches have run into some trouble, its blocking all
On Thu, Sep 20, 2012 at 03:30:40PM +, Arnd Bergmann wrote:
On Monday 17 September 2012, Linus Walleij wrote:
You found the weak spot between two consolidation tracks.
Getting rid of a broadcast autodetect functions from say
mach/foo-id-probe.h is nominally done by passing the data
So, wouldn't we need a small, architecture-independent, infrastructure,
through which architecture-specific code could register at boot
time which SoC we are running on, and drivers could query this
information from the common infrastructure?
Of course, the major problem is to figure out
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common
binding
+part and usage.
+
+Required properties:
+- compatible:
+++ b/Documentation/devicetree/bindings/mmc/sdhci-dove.txt
@@ -0,0 +1,12 @@
+* Marvell sdhci-dove controller
+
+Required properties:
+- compatible: Should be marvell,dove-sdhci.
+
+Example:
+
+sdio0: sdio@92000 {
+ compatible = marvell,dove-sdhci;
+ reg = 0x92000 0x100;
+
for
'addr_map_cfg.win_cfg_base') [enabled by default]
Signed-off-by: Arnd Bergmann a...@arndb.de
Cc: Andrew Lunn and...@lunn.ch
Cc: Michael Walle mich...@walle.cc
Cc: Nicolas Pitre n...@linaro.org
---
arch/arm/mach-mv78xx0/addr-map.c |2 +-
1 file changed, 1 insertion(+), 1 deletion
Hi Sebastian
-static void __init clk_init(void)
+static void __init dove_clk_init(void)
{
tclk = clk_register_fixed_rate(NULL, tclk, NULL, CLK_IS_ROOT,
-get_tclk());
+dove_tclk);
/disabled at the same time.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King li...@arm.linux.org.uk
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: Rabeeh
On Mon, Aug 20, 2012 at 11:09:51AM +0200, Linus Walleij wrote:
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
sebastian.hesselba...@gmail.com wrote:
This patch adds a pinctrl driver core for Marvell SoCs plus DT
binding documentation. This core driver will be used by SoC family
On Sat, Aug 25, 2012 at 03:01:33PM +0200, Mikael Pettersson wrote:
My Kirkwood-based QNAP TS-119P+ boots fine with the 3.5 kernel. With
3.6-rc2 and 3.6-rc3 however sata_mv complains:
sata_mv sata_mv.0: cannot get optional clkdev
sata_mv sata_mv.0: slots 32 ports 2
and then the kernel
On Fri, Dec 07, 2012 at 03:55:07PM -0700, Jason Gunthorpe wrote:
The intent of this patch is to expose the other bridge cause
interrupts to users in the kernel.
- Add orion_bridge_irq_init to create a new edge triggered interrupt
chip based on the bridge cause register
- Remove all
On Sat, Dec 08, 2012 at 07:57:48PM -0700, Jason Gunthorpe wrote:
On Sat, Dec 08, 2012 at 12:26:24PM +0100, Andrew Lunn wrote:
1) It should have an IRQ domain, like the other IRQ chips we have.
2) It should have a DT binding, like the other IRQ chips we have.
I was going to look at a DT
On Thu, Dec 13, 2012 at 03:51:59PM -0500, Dave Jones wrote:
On Thu, Dec 13, 2012 at 08:21:57PM +, Linux Kernel wrote:
Gitweb:
http://git.kernel.org/linus/;a=commit;h=96ff0f5c7efd4a2205c48a76a6a1fcd2731e6128
Commit: 96ff0f5c7efd4a2205c48a76a6a1fcd2731e6128
Parent:
I think it needs to be on the menuconfig, rather than the child options.
I don't have OF_GPIO, but I still got asked for the former.
The menuconfig enables a class of drivers (at least theoretically in the
future, when more such drivers turn up), and there's no reason to
believe that all
Its a generic driver. I know its useful on various Marvell kirkwood
and orion5x devices. I've also heard it useful on some Tegra boards.
Are you asking i list these boards?
No, but at least mentioning the architecture might have clued me in
quicker that this wasn't some now
Hi Gregory
Nice work
On Fri, Nov 16, 2012 at 07:01:59PM +0100, Gregory CLEMENT wrote:
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
.../bindings/clock/mvebu-gated-clock.txt | 43 ++
arch/arm/mach-mvebu/Kconfig|1 +
What is the ddr clock for? Does bad things happen if you turn it off?
Kirkwood has a similar clock, dunit, which i decided not to export,
since when you turn it off, the whole SoC locks up.
Well of course if you code run in DDR then it could be a problem. But
I think it could be useful
.
[ 64.312377] BUG: scheduling while atomic: crond/151/0x4300
[ 79.771862] BUG: scheduling while atomic: swapper/0/0x4500
[ 81.826267] BUG: scheduling while atomic: swapper/0/0x4500
[ 90.330911] BUG: scheduling while atomic: swapper/0/0x4500
Working with Andrew Lunn
diff -ruN a/drivers/staging/rtl8712/rtl871x_sta_mgt.c
b/drivers/staging/rtl8712/rtl871x_sta_mgt.c
--- a/drivers/staging/rtl8712/rtl871x_sta_mgt.c 2012-11-05
03:57:06.0 -0500
+++ b/drivers/staging/rtl8712/rtl871x_sta_mgt.c 2012-11-13
12:54:28.0 -0500
@@ -55,8 +55,8 @@
On Sun, Nov 18, 2012 at 02:18:37PM -0600, Larry Finger wrote:
On 11/18/2012 12:11 PM, Andrew Lunn wrote:
Just to clarify the issue here:
union pn48 {
u64 val;
#if defined(__BIG_ENDIAN)
struct {
u8 TSC7;
u8 TSC6;
Any instance
On Mon, Nov 19, 2012 at 04:46:11PM +0100, Thomas Petazzoni wrote:
Dear Andrew Lunn,
On Sat, 17 Nov 2012 14:54:35 +0100, Andrew Lunn wrote:
What is the ddr clock for? Does bad things happen if you turn it off?
Kirkwood has a similar clock, dunit, which i decided not to export,
since
;
}
}
return 0;
Hi Axel
Good catch, thanks.
Acked-by: Andrew Lunn and...@lunn.ch
Andrew
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On Tue, Jan 15, 2013 at 01:13:12PM +0100, Stefan Peter wrote:
In order to be able to use the ecc-mode, add the bch module to the default
settings for the kirwood boards and enable the activation in orin-nand.c
Signed-off-by: Stefan Peter s.pe...@mpl.ch
---
diff --git
On Mon, Jul 29, 2013 at 02:29:06PM +0200, Sebastian Hesselbarth wrote:
This adds an initial DT file for the Globalscale D2Plug with Dove SoC.
Currently, one LED is missing and I have not been able to get SD8787 driver
working. Those will be taken care of later.
Hi Sebastion
I took a hard look
On Mon, Jul 29, 2013 at 12:21:22PM -0300, Ezequiel Garcia wrote:
If CONFIG_HAVE_CLK is not selected, then all the clk API turn out
into stubs, so there's no need to have the ifdefs.
The only side-effect of this patch is the extra tiny kmalloc,
but that's not enough reason to have such ugly
On Wed, Jul 17, 2013 at 10:09:10AM +0800, Wei Yongjun wrote:
From: Wei Yongjun yongjun_...@trendmicro.com.cn
Convert to use devm_* APIs to avoid resources leak on error handling case.
Signed-off-by: Wei Yongjun yongjun_...@trendmicro.com.cn
---
drivers/mtd/nand/orion_nand.c | 29
all DT parsing and uses cpu-of_node instead.
Cc: Andrew Lunn and...@lunn.ch
Cc: Jason Cooper ja...@lakedaemon.net
Acked-by: Viresh Kumar viresh.ku...@linaro.org
Signed-off-by: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
---
drivers/cpufreq/kirkwood-cpufreq.c | 14 --
1
On Tue, Jul 30, 2013 at 10:03:56AM +0200, Sebastian Hesselbarth wrote:
On 07/29/2013 08:45 PM, Andrew Lunn wrote:
On Mon, Jul 29, 2013 at 02:29:06PM +0200, Sebastian Hesselbarth wrote:
This adds an initial DT file for the Globalscale D2Plug with Dove SoC.
Currently, one LED is missing and I
On Thu, Nov 07, 2013 at 01:46:44PM +0100, Sebastian Hesselbarth wrote:
On 11/07/13 06:07, Jisheng Zhang wrote:
PL310 supports Prefetch offset/control register from r2p0 and Power
control register from r3p0. This patch adds the support to configure
these two registers if there are. The dt
=569943d0639c85a451ea853087cbd5f738247dd9
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc: Russell King li...@arm.linux.org.uk
Cc: Grant Likely grant.lik...@linaro.org
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Ezequiel Garcia
Sebastian, does __clk_enabled work properly for the mvebu clock
provider? I don't see a clk_ops.is_enabled for mvebu.. (don't know
much about clk)
Hi Jason
It is implemented in drivers/clk/clk-gate.c, which is what mvebu is
using.
Andrew
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-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Tested-by: Andrew Lunn and...@lunn.ch
Andrew
---
Cc: Mike Turquette mturque...@linaro.org
Cc: Russell King li...@arm.linux.org.uk
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc: Grant Likely grant.lik
use of new public clk_is_enabled (adds dependency [1])
- add warning about gated clock missing MAC property
(Suggested by Jason Gunthorpe)
v1-v2:
- check for gated clock before accessing eth registers
(Suggested by Andrew Lunn)
[1] http://www.spinics.net/lists/arm-kernel/msg277392.html
On Sat, Oct 05, 2013 at 10:24:30PM +0200, Uwe Kleine-König wrote:
On Fri, Oct 04, 2013 at 12:08:30PM +0200, Sebastian Hesselbarth wrote:
To determine if a clk has been previously enabled, provide a public
clk_is_enabled function. This is especially helpful to check the state
of clk-gate
On Sun, Oct 06, 2013 at 11:06:09AM +0200, Gerhard Sittig wrote:
On Sat, Oct 05, 2013 at 22:42 +0200, Andrew Lunn wrote:
On Sat, Oct 05, 2013 at 10:24:30PM +0200, Uwe Kleine-König wrote:
On Fri, Oct 04, 2013 at 12:08:30PM +0200, Sebastian Hesselbarth wrote:
To determine if a clk has
Andrew has mentioned, that some bootloaders might disable clocks but
leave the nodes enabled. Reading those registers would lock up
the HW, of course. So we thought about to check clk gate status first,
which this patch is about.
Of course, we can do clk_enable, read, clk_disable as said
On Fri, Sep 13, 2013 at 06:32:21PM +0530, Viresh Kumar wrote:
- if (freqs.old != freqs.new) {
- local_irq_disable();
-
- /* Disable interrupts to the CPU */
- reg = readl_relaxed(priv.base);
- reg |= CPU_SW_INT_BLK;
-
for this driver.
Cc: Andrew Lunn and...@lunn.ch
Signed-off-by: Viresh Kumar viresh.ku...@linaro.org
---
drivers/cpufreq/kirkwood-cpufreq.c | 22 +++---
1 file changed, 3 insertions(+), 19 deletions(-)
Hi Viresh
You can add:
Tested-by: Andrew Lunn and...@lunn.ch
to
[PATCH
works fine so far. The benchmark has been
running for ten minutes, whereas before it was lucky to reach ten
seconds.
Tested-by: Andrew Lunn and...@lunn.ch
drivers/cpufreq/cpufreq.c | 110
+-
include/linux/cpufreq.h | 14 ++
2 files changed
...@st.com
Hi Srinivas
Please CC: the Marvell maintainers for patches like this.
I added them in CC:
Acked-by: Andrew Lunn and...@lunn.ch
---
.../dts/orion5x-lacie-ethernet-disk-mini-v2.dts|2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts
...@st.com
Acked-by: Andrew Lunn and...@lunn.ch
---
arch/arm/boot/dts/dove.dtsi |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index cc27916..b4a6559 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm
On Sun, Feb 23, 2014 at 05:58:39PM +0100, Sebastian Hesselbarth wrote:
commit 1211ce53077164e0d34641d0ca5fb4d4a7574498
(net: phy: resume/suspend PHYs on attach/detach)
introduced a feature to suspend PHYs when entering halted state.
Unfortunately, not all bootloaders properly power-up PHYs
On Mon, Feb 24, 2014 at 11:37:15AM -0800, Florian Fainelli wrote:
2014-02-24 11:15 GMT-08:00 Andrew Lunn and...@lunn.ch:
On Sun, Feb 23, 2014 at 05:58:39PM +0100, Sebastian Hesselbarth wrote:
commit 1211ce53077164e0d34641d0ca5fb4d4a7574498
(net: phy: resume/suspend PHYs on attach/detach
On Tue, Feb 25, 2014 at 11:38:52PM +0100, Sebastian Hesselbarth wrote:
On 02/24/2014 08:15 PM, Andrew Lunn wrote:
On Sun, Feb 23, 2014 at 05:58:39PM +0100, Sebastian Hesselbarth wrote:
commit 1211ce53077164e0d34641d0ca5fb4d4a7574498
(net: phy: resume/suspend PHYs on attach/detach
As to the comment from davem about not using a kernel parameter. How
about turning it all around. Put a boolean parameter into DT PHY node
to indicate when it is safe to power down an idle phy?
Ah ah, nice try, but I do not think this belongs in DT, this is purely
a software issue here,
The only case we need to handle is when the interface is brought down,
suspend_halted=true will also power down the PHY, you reboot into
u-boot, and you attempt a network boot right after that, in that case
the PHY interface is still powered down and this does not work.
Correct. And since my
On Mon, Mar 03, 2014 at 03:02:15PM +, Russell King - ARM Linux wrote:
On Mon, Feb 17, 2014 at 08:00:36PM +, Jason Cooper wrote:
The corresponding driver didn't make it into v3.14, so we need to remove
the node. Dove systems fail to boot with the node present and no
driver.
I could have sworn this was discussed with this particular patchset, but
I'm unable to find the conversation in my archives. Neither during the
patch submission process, nor the (long) pull request thread.
Perhaps it was an irc conversation? Andrew, Sebastian, can you find a
link? iirc,
So we have cpufreq, pm domains and an irq controller. What's the plan
for this, who's going to look at sorting this out?
Andrew, Sebastian? I'm currently task-saturated...
I doubt i will be doing anything with it for the remainder of this
cycle. I would like to finish converting kirkwood
On Tue, Mar 04, 2014 at 02:01:36PM +, Russell King - ARM Linux wrote:
On Tue, Mar 04, 2014 at 02:54:52PM +0100, Andrew Lunn wrote:
So we have cpufreq, pm domains and an irq controller. What's the plan
for this, who's going to look at sorting this out?
Andrew, Sebastian? I'm
the resource and derive it from other resources. As soon
as PMU binding is worked out, we will update the driver to make use of it.
The last patch is optional and Linus Walleij can reject it, if he is already
done for v3.15.
Hi Sebastian
Whole set of three:
Acked-by: Andrew Lunn
From the spec, it looks like this is probably true of DFSDone as well.
The cpufreq driver makes use of DFSDone. I've never had it loop
endlessly. There is also no action needed to clear it in the DFS
hardware.
Andrew
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On Thu, Mar 06, 2014 at 01:11:08PM +0100, Gregory CLEMENT wrote:
The Armada 385 RD board is the reference design board from Marvell
for the Armada 385 SoC. This commit adds a Device Tree description for
this board, which enables the following features:
* Network interfaces
* I2C bus
*
Hi Gregory
I guess checkpatch.pl is probably complaining about missing vendor
prefix?
yes and also about m25p128 itself because it was not explicitly written
in Documentation/devicetree/bindings/. Actually it was written to see the
m25p_ids table in drivers/mtd/devices/m25p80.c
I think you can use aliases to get the order correct, independent of
how you list them in DT. That should be a lot safer than assuming
things are instantiated from top to bottom.
It sounds interesting, how would you do this?
As there already is in armada-370-xp.dtsi
Can't we fix this so the probe order doesn't affect the name?
Is that sane?
You are not supposed to trust the device name, since probing can
happen in parallel, on different buses. udev should have rules to name
the interfaces based on the MAC address. On my Debian system i have:
+/dts-v1/;
+#include berlin2q.dtsi
+
+/ {
+ model = Marvell BG2-Q DMP;
+ compatible = marvell,berlin2q-dmp, marvell,berlin2q,
marvell,berlin; +
+ memory {
+ device_type = memory;
+ reg = 0x 0x4000;
The memory size of BG2Q DMP is 2GB.
+The following is a list of provided IDs for Armada 380/385:
+ID Clock Peripheral
+---
+0audio Audio
+2ge2 Gigabit Ethernet 2
+3ge1 Gigabit Ethernet 1
+4ge0 Gigabit Ethernet 0
+5
with shared registers. It has done it before, so I consider it broken
anyway.
I (or somebody else) will take care of proper watchdog later.
- An updated branch can be found on
git://github.com/shesselba/linux-dove.git orion-irqchip-for-v3.11_v4
Hi Sebastian
You can add a
Tested-by: Andrew Lunn
On Thu, May 02, 2013 at 09:48:50PM +0200, Sebastian Hesselbarth wrote:
On 05/02/2013 09:35 PM, Jason Gunthorpe wrote:
I have kirkwood HW but I haven't had time to make newer kernels run on
it, otherwise I'd test it too :(
I also have kirkwood HW but that will cut me from email as I use it as
...@linutronix.de
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Thomas Petazzoni thomas.petazz...@free-electrons.com
Cc: Gregory Clement gregory.clem
.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Changelog:
v3-v4:
- convert to new device tree binding
Cc: David Miller da...@davemloft.net
Cc: Lennert Buytenhek buyt...@wantstofly.org
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc
On Tue, May 21, 2013 at 06:41:38PM +0200, Sebastian Hesselbarth wrote:
This patch set picks up work by Florian Fainelli bringing full DT
support to mv643xx_eth and Marvell SoCs using it.
Hi Sebastian
I tested on my QNAP and topkick. Works great.
Tested-by: Andrew Lunn and...@lunn.ch
Why are you not keen on this? It seems like normal device driver
practice, that is what the data field of of_device_id is typically
used for..
I'm not keen on it because we don't have a document saying All kirkwood
SoCs need PSC1 set to X after reset. We know it, but have we tested
the
On Tue, Oct 29, 2013 at 07:17:46PM +0100, Johan Hovold wrote:
On Wed, Oct 23, 2013 at 01:18:21PM +0200, Andrew Lunn wrote:
Add the missing C_MSPAR(tty) macro.
Please rename the macro C_CMSPAR to be consistent with the other
termios-flag macros (with C_BAUD being the exception that confirms
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