On Wed, Jan 20, 2016 at 01:23:39PM +0100, Lothar Waßmann wrote:
> The TX51-8xxx module series is a System On Module manufactured by
> Ka-Ro electronics GmbH with the following characteristics:
> ProcessorFreescale i.MX515
> up to 800 MHz (commercial)
> up
On Wed, Jan 20, 2016 at 01:57:03PM +0100, Lothar Waßmann wrote:
> ENET_OUT is used as reference clock for the ethernet PHY on the Ka-Ro
> TX6 modules. Specify this clock in DTB to let it be managed correctly
> by the driver.
>
> Signed-off-by: Lothar Waßmann
Applied,
On Wed, Jan 20, 2016 at 01:57:02PM +0100, Lothar Waßmann wrote:
> The reference clock for the SGTL5000 is generated by a 26MHz crystal
> oscillator on the Ka-Ro electronics STK5 eval kits. Use the correct
> frequency setting in DTB.
>
> Signed-off-by: Lothar Waßmann
On Wed, Jan 20, 2016 at 01:57:04PM +0100, Lothar Waßmann wrote:
> The second last digit of the Ka-Ro electronics TX-module names denotes
> the HW revision of the module. HW rev 1 and 3 of the TX6 modules can
> use the same DTB. Change this digit to 'x' to indicate that the DTB
> file can be used
On Fri, Feb 26, 2016 at 12:54:12PM +0100, Arnd Bergmann wrote:
> i.MX only needs to select ARM_CPU_SUSPEND manually for the
> very specific case that CONFIG_PM_SLEEP is disabled and imx6
> is used with CONFIG_PM enabled for runtime PM.
>
> If we are building a kernel only for CPUs that are not
On Thu, Feb 25, 2016 at 03:56:55PM -0800, Stephen Boyd wrote:
> On 01/12, Lothar Waßmann wrote:
> > This patchset adds the clock which is necessary to operate the KPP
> > unit on i.MX6UL.
> > The first patch removes bogus whitespace before TABs in indentation.
> > The second patch adds the clock
On Fri, Feb 26, 2016 at 03:08:52PM +0100, Lothar Waßmann wrote:
> Pad DISPB2_SER_RS has no function DISP1_EXT_CLK.
> The definition is obviusly a copy/paste error from
> MX51_PAD_DISPB2_SER_RS__DISP1_PIN16.
>
> Signed-off-by: Lothar Waßmann
Applied, thanks.
On Fri, Feb 26, 2016 at 03:52:57PM +0100, Lothar Waßmann wrote:
> This patchset adds missing input_sel settings to imx6ul-pinfunc.h.
> The first patch is a cleanup patch with no functional changes
> intended.
Applied both, thanks.
On Fri, Feb 19, 2016 at 03:59:02PM -0500, Julien Grossholtz wrote:
> Add dts nodes for TS-4800 FPGA gpio chips.
>
> Signed-off-by: Julien Grossholtz
> ---
> arch/arm/boot/dts/imx51-ts4800.dts | 29 +
> 1 file changed, 29
On Wed, Jan 20, 2016 at 11:09:09AM +0100, Lothar Waßmann wrote:
> The TXUL-0010/-0011 modules are Computers On Module manufactured by
> Ka-Ro electronics GmbH with the following characteristics:
> ProcessorFreescale i.MX 6UltraLite MCIMX6G2, 528 MHz
> RAM 256MB 16-bit DDR3 SDRAM
On Wed, Jan 20, 2016 at 11:08:53AM +0100, Lothar Waßmann wrote:
> This patchset adds more functionality to the i.MX6UL machines.
>
> The first three patches are cleanup patches with no functional changes
> intended.
> The other patches make various subsystems functional.
>
> ARM: dts: imx6ul:
On Wed, Feb 24, 2016 at 06:45:34PM +0530, Laxman Dewangan wrote:
> Use devm_pinctrl_register() for pin control registration and remove
> need of .remove callback.
>
> Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
> Cc: Shawn Guo <shawn...@kernel.org>
s marked with
> 'status = disabled' are not probed.
>
> Cc: <sta...@vger.kernel.org>
> Suggested-by: Wolfgang Netbal <wolfgang.net...@sigmatek.at>
> Signed-off-by: Fabio Estevam <fabio.este...@nxp.com>
Acked-by: Shawn Guo <shawn...@kernel.org>
Arnd, Olof,
On Wed, Feb 10, 2016 at 04:02:25PM -0800, Stefan Agner wrote:
> Assign Ethernet clock parents explicitly. The VF610 Tower Board
> uses the external Ethernet clock input which is connected to
> a 50MHz clock.
>
> The Vybrid SoC has two ethernet interfaces (fec0 and fec1) which
> use the same clock
On Fri, Feb 05, 2016 at 05:36:28AM +, Bhupesh Sharma wrote:
> > From: Shi, Yang
> > Sent: Friday, February 05, 2016 5:19 AM
> >
> > On 2/4/2016 2:37 PM, Bjorn Helgaas wrote:
> > > On Wed, Jan 27, 2016 at 10:05:40AM -0800, Shi, Yang wrote:
> > >> Correct FSL folks email address to nxp.com,
On Wed, Feb 10, 2016 at 10:39:47AM +0530, Rajesh Bhagat wrote:
> Add "snps,quirk-frame-length-adjustment" property to USB3 node for erratum
> A009116.
> This property provides value of GFLADJ_30MHZ for post silicon frame length
> adjustment.
The commit log should be generally wrapped around
On Tue, Feb 09, 2016 at 05:08:07PM -0600, Lijun Pan wrote:
> Add "snps,quirk-frame-length-adjustment" property to
> USB3 node for erratum A009116. This property provides
> value of GFLADJ_30MHZ for post silicon frame length
> adjustment.
>
> Signed-off-by: Lijun Pan
On Fri, Feb 05, 2016 at 05:12:19PM +0100, Marcel Ziswiler wrote:
> Petr Štetiar (2):
> ARM: dts: imx6: Add support for Toradex Apalis iMX6Q/D SoM
> ARM: dts: imx6: Add support for Toradex Ixora carrier board
Applied both, thanks.
On Mon, Feb 08, 2016 at 01:55:08AM +0100, Heinrich Schuchardt wrote:
> Downstream packages like Debian flash-kernel use
> /proc/device-tree/model
> to determine which dtb file to install.
>
> Hence each dts in the Linux kernel should provide a unique model
> identifier.
>
> Commit 8536239e371f
On Wed, Feb 10, 2016 at 06:08:18PM -0800, Stefan Agner wrote:
> Enable configuration options useful for Vybrid:
> - NFC NAND driver
> - USB dual-role controller support
> - FTM PWM driver
> - DSPI SPI driver
> - Colibri VF50 Touchscreen support.
>
> Beside that, enable useful configurations such
On Wed, Feb 03, 2016 at 09:37:45AM -0800, Joshua Clayton wrote:
> Uniwest evi is a portable electrical eddy current non-destructive
> testing device.
>
> Signed-off-by: Joshua Clayton
Applied, thanks.
On Mon, Feb 15, 2016 at 06:14:13PM -0800, Stefan Agner wrote:
> Drop the fake simple-bus container 'regulators' and put the
> regulators directly under the root node. This also makes the
> artificial 'reg' properties superfluous.
>
> Signed-off-by: Stefan Agner
Applied both,
On Wed, Feb 17, 2016 at 03:40:58PM -0800, Stefan Agner wrote:
> Drop the fake simple-bus container 'regulators' and put the
> regulators directly under the root node. This also makes the
> artificial 'reg' properties superfluous. While at it, remove
> the unnecessary regulator-always-on property
On Wed, Feb 17, 2016 at 03:44:16PM -0800, Stefan Agner wrote:
> The Colibri standard does not define a pin for SD-Card write-
> protection. Use the disable-wp property to indicate that there
> is no physical WP line present.
>
> Signed-off-by: Stefan Agner
Applied, thanks.
>
On Wed, Feb 17, 2016 at 04:37:00PM -0800, Stefan Agner wrote:
> All Freescale Vybrid SoC include a Cortex-A5 core which supports
> ARM's standard PMU (performance monitoring unit). Include the
> monitoring unit into the Cortex-A5 base device tree vf500.dtsi.
>
> Signed-off-by: Stefan Agner
On Tue, Feb 16, 2016 at 09:16:01AM +0530, Bhuvanchandra DV wrote:
> Add pinmux for UART_A RTS, CTS pin's.
>
> Signed-off-by: Bhuvanchandra DV
> Acked-by: Stefan Agner
Applied, thanks.
Please copy linux-arm-ker...@lists.infradead.org instead of
On Wed, Feb 03, 2016 at 04:16:44PM +0800, Alison Wang wrote:
> According to the new mapping table, the partition for NOR flash
> is added.
How do you know that everyone using the board wants the NOR flash to be
partitioned this way? It's really a matter of software configuration
and may vary
+LAKML
On Thu, Jan 28, 2016 at 02:17:21AM +, Richard Zhu wrote:
> Hi Shawn:
> Thanks for your comments.
> Further review would copied to Stefan Agner.
Please do not top-posting.
> On Wed, Jan 06, 2016 at 04:06:43PM +0800, Richard Zhu wrote:
> > From: Richard Zhu
On Tue, Feb 09, 2016 at 05:08:07PM -0600, Lijun Pan wrote:
> Add "snps,quirk-frame-length-adjustment" property to
> USB3 node for erratum A009116. This property provides
> value of GFLADJ_30MHZ for post silicon frame length
> adjustment.
>
> Signed-off-by: Lijun Pan
>
On Fri, Feb 12, 2016 at 05:53:00PM +0530, Sanchayan Maity wrote:
> Add iio_hwmon node to expose the temperature channel on Vybrid as
> hardware monitor device using the iio_hwmon driver.
>
> Signed-off-by: Sanchayan Maity
> ---
>
> Hello,
>
> The first version of the
On Wed, Mar 30, 2016 at 02:09:16PM -0700, Guenter Roeck wrote:
> The question was if the property name should be ext-reset-output or
> fsl,ext-reset-output. In my opinion, it should be fsl,ext-reset-output
> because it is not a generic property. Tim disagrees.
>
> So we have two options: Change
On Tue, Mar 08, 2016 at 09:03:59AM +0100, Lothar Waßmann wrote:
> DT maintainers don't like the 'simple-bus' container around the
> regulator nodes. So remove it.
>
> Signed-off-by: Lothar Waßmann
> ---
> arch/arm/boot/dts/imx6qdl-tx6.dtsi | 178
>
On Tue, Mar 08, 2016 at 09:04:03AM +0100, Lothar Waßmann wrote:
> Add support for the following i.MX6 based modules from Ka-Ro
> electronics GmbH:
> TX6S-8034:
> ProcessorFreescale i.MX 6 Solo, 800MHz
> RAM 256MiB DDR3 SDRAM
> ROM 128MiB NAND Flash
> Power supply Single 3.1V
/mxs: Prepare driver for hardware with different
> offsets")
> Signed-off-by: Vladimir Zapolskiy <v...@mleia.com>
Acked-by: Shawn Guo <shawn...@kernel.org>
On Thu, Mar 31, 2016 at 08:29:44AM +0200, Lothar Waßmann wrote:
> NB: There is no need to quote the full original mail when you have no
> further comments on the remaining part. This would save people
> from having to scroll through the mail needlessly looking for further
> comments.
I generally
On Tue, Mar 08, 2016 at 09:03:56AM +0100, Lothar Waßmann wrote:
> This patch set updates the Ka-Ro electronics i.MX6 based module
> support and adds support for some new modules and a new baseboard.
>
> changes vs. v1:
> - relicense DTS files under GPLv2/X11
> - dropped patches which have been
On Wed, Mar 09, 2016 at 06:16:45PM -0800, Stefan Agner wrote:
> Add Vybrids massive on-chip SRAM areas. Make use of the memory
> region functionality to denominate the retained SRAM area in
> LPSTOP2 and LPSTOP3.
>
> Signed-off-by: Stefan Agner
This one looks fine to me. I was
On Wed, Mar 09, 2016 at 06:16:43PM -0800, Stefan Agner wrote:
> Signed-off-by: Stefan Agner
So this patch cannot be applied before the fsl,vf610-gpc driver gets
landed on mainline.
Shawn
> ---
> arch/arm/boot/dts/vfxxx.dtsi | 10 +-
> 1 file changed, 9 insertions(+),
On Wed, Mar 09, 2016 at 06:16:44PM -0800, Stefan Agner wrote:
> Enable GPIO wakeup key on Vybrid PAD 41 which is routed to the
> Colibri default wakeup pin SO-DIMM 45.
>
> Signed-off-by: Stefan Agner
I think this one can be merged independently, right? One small comment
below
On Wed, Mar 09, 2016 at 06:16:42PM -0800, Stefan Agner wrote:
> +static int __init vf610_gpc_of_init(struct device_node *node,
> +struct device_node *parent)
> +{
> + struct irq_domain *domain, *domain_parent;
> + int i;
> +
> + domain_parent =
On Wed, Mar 09, 2016 at 06:16:46PM -0800, Stefan Agner wrote:
> Signed-off-by: Stefan Agner
> ---
> arch/arm/boot/dts/vfxxx.dtsi | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
> index
ring remains unchanged with
> this commit.
>
> Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
>
> We also delete the MODULE_LICENSE tag etc. since all that information
> is already contained at the top of the file in the comments.
>
> Cc: Shawn Guo <sha
es which have been applied already
> - added some cleanup patches
>
> changes vs. v2:
> - dropped patches which have been applied already
> - addressed comments from Shawn Guo
> - added patch to remove LED pinctrl from hoggrp
> - added patch to enable rtscts support on UART
On Sun, Mar 27, 2016 at 05:51:13PM +0200, Maciej S. Szmigiero wrote:
> The official UDOO board kit has 7 and 15.6 inch touchscreen LCD panels
> as options.
>
> This patch adds support for 7 inch panel only, but the 15.6 inch one
> should be easy to add using the same regulator, backlight device
On Wed, Mar 02, 2016 at 01:52:15PM +0800, Yunhui Cui wrote:
> This patch adds dts nodes for DSPI on LS1043A-RDB.
>
> Signed-off-by: Yunhui Cui
> Signed-off-by: Yuan Yao
The patch subject prefix should be like 'arm64: dts: ls1043a-rdb: '. I
fixed it up
On Wed, Mar 09, 2016 at 06:22:05PM +0800, Yuan Yao wrote:
> new compatible string: "fsl,ls2080a-dspi".
>
> Signed-off-by: Yuan Yao
> Acked-by: Rob Herring
Drop the space after 'fsl,' and applied the patch.
Shawn
On Wed, Apr 13, 2016 at 09:42:02AM +0800, kernel test robot wrote:
> FYI, we noticed the below changes on
>
> https://github.com/0day-ci/linux
> Shawn-Guo/scatterlist-use-sg_dma_len-in-sg_set_page/20160411-105225
> commit c38ecfb12e9a4c0c17d0879090741d6ce2a200de ("scatterlis
On Wed, Mar 09, 2016 at 06:22:06PM +0800, Yuan Yao wrote:
> Signed-off-by: Yuan Yao
> Acked-by: Han xu
Changed subject prefix to 'arm64: dts: ls2080a: ', and then applied the
patch.
Shawn
> ---
> Changed in v6:
> No changes.
>
> Changed in v5:
> Resend base
On Fri, Apr 01, 2016 at 03:54:40PM -0500, Stuart Yoder wrote:
> From: Stuart Yoder
>
> updates to the fsl-mc node for full functionality:
>-msi-parent is needed for interrupt support
>-ranges is needed to enable the bus driver to translate bus addresses
>-dpmac
On Mon, Apr 04, 2016 at 10:28:39PM -0700, Stefan Agner wrote:
> Add the dcu and tcon nodes to enable the Display Controller Unit
> and Timing Controller in Vybrid's SoC level device-tree file.
>
> Signed-off-by: Stefan Agner
Applied 7 ~ 9, thanks.
On Wed, Apr 06, 2016 at 07:02:07PM +0800, Minghuan Lian wrote:
> Add SCFG MSI dts node and add msi-parent property to PCIe dts node
> that points to the corresponding MSI node.
>
> Signed-off-by: Minghuan Lian
Applied, thanks.
On Fri, Apr 01, 2016 at 11:13:39PM -0700, Stefan Agner wrote:
> The Vybrid based Colibri modules provide a on-module PHY which is
> connected to the second FEC instance FEC1. Since the on-module
> Ethernet port is considered as primary ethernet interface, alias
> fec1 as ethernet0. This also makes
On Mon, Apr 04, 2016 at 10:28:33PM -0700, Stefan Agner wrote:
> Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy
> mixes the bus clock with the display controllers pixel clock. Tests
> have shown that the gates in CCM_CCGR3/9 registers do not control
> the DCU pixel clock, but
On Thu, Mar 31, 2016 at 02:45:01PM +0800, Yuan Yao wrote:
> From: Yuan Yao
>
> Signed-off-by: Yuan Yao
Please style of 'arm64: dts: ls1043a: ' for subject prefix.
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 16
>
On Mon, Apr 11, 2016 at 11:31:04AM +0100, Robin Murphy wrote:
> Hi Shawn,
>
> On 11/04/16 03:47, Shawn Guo wrote:
> >The macro sg_dma_len(sg) is commonly used to retrieve length of sg,
> >which could be 'dma_length' or 'length' field, depending on whether
> >NE
.
The patch changes sg_set_page() to use sg_dma_len() for sg length setup
as well, so that NEED_SG_DMA_LENGTH case can be handled.
Signed-off-by: Shawn Guo <shawn...@kernel.org>
---
include/linux/scatterlist.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include
On Wed, Mar 30, 2016 at 02:23:03PM +0200, Lothar Waßmann wrote:
> commit ee36027427c7 ("clk: imx: Add clock support for imx6qp")
> introduced a regression due to a subtle typo in the 'can_root' clock
> definition. The effect is that trying to configure the bitrate of the
> can interfaces fails
On Tue, Mar 01, 2016 at 10:59:54AM -0800, Stephen Boyd wrote:
> This flag is a no-op now. Remove usage of the flag.
>
> Cc: Shawn Guo <shawn...@kernel.org>
> Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
Acked-by: Shawn Guo <shawn...@kernel.org>
> ---
>
On Tue, Mar 01, 2016 at 10:59:49AM -0800, Stephen Boyd wrote:
> This flag is a no-op now. Remove usage of the flag.
>
> Cc: Shawn Guo <shawn...@kernel.org>
> Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
Acked-by: Shawn Guo <shawn...@kernel.org>
> ---
>
- added imx6ul specific compatibles as requested by Lucas Stach
>
> Changes vs. v2:
> - dropped patches which have already been applied in the meantime
> - addressed comments by Shawn Guo
>
>
On Wed, Mar 02, 2016 at 02:11:22PM +0800, Alison Wang wrote:
> According to the current clock driver for Freescale QorIQ platform, new
> clock binding will be used for LS1021A.
Is this a simple clock binding updating/replacing, or does it actually
include some clock assignment changes? I expect
On Thu, Mar 31, 2016 at 11:01:58AM -0700, Tim Harvey wrote:
> On Wed, Mar 30, 2016 at 6:57 PM, Shawn Guo <shawn...@kernel.org> wrote:
> > On Wed, Mar 30, 2016 at 02:09:16PM -0700, Guenter Roeck wrote:
> >> The question was if the property name should be ext-reset-outp
On Wed, Mar 09, 2016 at 06:16:56PM -0800, Stefan Agner wrote:
> Add system suspend and resume support for Vybrid SoC. The standby
> sleep state puts the SoC in STOP mode. The SoC can be woken through
> an interrupt from GPC (Global Power Controller). The GPC can use any
> interrupt as wake-up
;
> >>Any suggestions on whether a vendor specific prefix is necessary?
> >
> >Any comments?
> >
>
> Is this something you can help with, since you are the iMX
> architecture/devicetree maintainer? Appreciate any feedback.
FWIW,
Acked-by: Shawn Guo <shawn...@kernel.o
On Wed, Mar 09, 2016 at 06:16:47PM -0800, Stefan Agner wrote:
> The 2-bit gates found i.MX and Vybrid SoC support different clock
> configuration:
>
> 0b00: clk disabled
> 0b01: clk enabled in RUN mode but disabled in WAIT and STOP mode
> 0b10: clk enabled in RUN, WAIT and STOP mode (only Vybrid)
On Wed, Mar 09, 2016 at 06:16:50PM -0800, Stefan Agner wrote:
> @@ -414,9 +460,12 @@ static void __init vf610_clocks_init(struct device_node
> *ccm_node)
> for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
> clk_prepare_enable(clk[clks_init_on[i]]);
>
> +
On Wed, Mar 09, 2016 at 06:16:51PM -0800, Stefan Agner wrote:
> In order to allow wake support in STOP sleep mode, clocks are
> needed. Use imx_clk_gate2_cgr to disable automatic clock gating
> in low power mode STOP. This allows to enable wake by UART using:
> echo enabled >
On Fri, Mar 11, 2016 at 02:29:30PM +0530, Sanchayan Maity wrote:
> Add OCROM node and introduce phandles to OCROM, MSCM and NVMEM
> OCOTP for use by the Vybrid SoC bus driver.
>
> Signed-off-by: Sanchayan Maity
> ---
> arch/arm/boot/dts/vfxxx.dtsi | 12 +++-
>
On Thu, Apr 21, 2016 at 11:45:20AM +0800, Dong Aisheng wrote:
> On Fri, Jan 29, 2016 at 02:49:23PM -0800, Stefan Agner wrote:
> > If a clock gets enabled early during boot time, it can lead to a PLL
> > startup. The wait_lock function makes sure that the PLL is really
> > stareted up before it
On Mon, Apr 25, 2016 at 06:09:33PM -0700, Joshua Clayton wrote:
> When compiled with "W=1", dtc complains: e.g.
> "Warning (unit_address_vs_reg):
> Node /soc/ipu@0280/port@2/endpoint@0
> has a unit name, but no reg property"
>
> Endpoint nodes don't have a reg property, and the addresses
> in
On Wed, Apr 20, 2016 at 05:38:04PM -0300, Sergio Prado wrote:
> Embest MarS Board [1] is a multi-core platform based on Freescale i.MX6
> Cortex-A9 Dual Core, running up to 1GHz with 1 GB of RAM, 4GB of eMMC
> and with a 4MB SPI flash.
>
> [1] http://www.embest-tech.com/shop/star/marsboard.html
>
On Tue, Apr 26, 2016 at 01:51:13PM +0800, Dong Aisheng wrote:
> Hi Shawn,
>
> On Tue, Apr 26, 2016 at 9:23 AM, Shawn Guo <shawn...@kernel.org> wrote:
> > On Thu, Apr 21, 2016 at 11:45:20AM +0800, Dong Aisheng wrote:
> >> On Fri, Jan 29, 2016 at 02:49:
On Wed, Apr 27, 2016 at 10:57:21AM +0800, Dong Aisheng wrote:
> On Wed, Apr 27, 2016 at 9:58 AM, Shawn Guo <shawn...@kernel.org> wrote:
> > On Tue, Apr 26, 2016 at 07:27:03PM +0800, Dong Aisheng wrote:
> >> Shawn,
> >> What's your suggestion?
> >
> > I
On Tue, Apr 26, 2016 at 07:27:03PM +0800, Dong Aisheng wrote:
> Shawn,
> What's your suggestion?
I think this needs more discussion, and I just dropped Stefan's patch
from my tree.
We need to firstly understand why this is happening. The .prepare hook
is defined to be non-atomic context, and so
On Tue, Apr 26, 2016 at 08:38:22PM -0300, Sergio Prado wrote:
> Embest MarS Board [1] is a multi-core platform based on Freescale i.MX6
> Cortex-A9 Dual Core, running up to 1GHz with 1 GB of RAM, 4GB of eMMC
> and with a 4MB SPI flash.
>
> [1] http://www.embest-tech.com/shop/star/marsboard.html
>
On Tue, Apr 19, 2016 at 04:43:27PM -0500, Stuart Yoder wrote:
> Stuart Yoder (2):
> Documentation: fsl-mc: binding updates for MSIs, ranges, PHYs
> arm64: dts: ls2080a: fsl-mc dt node updates
Applied both, thanks.
On Thu, Apr 28, 2016 at 02:07:03PM -0700, Stefan Agner wrote:
> The clock parent of the AHB root clock when using mux option 1
> is the SYS PLL 270MHz clock. This is specified in Table 5-11
> Clock Root Table of the i.MX 7Dual Applications Processor
> Reference Manual.
>
> While it could be a
On Fri, Apr 29, 2016 at 10:20:49PM +0200, Marcel Ziswiler wrote:
> Add parallel LCD display support for the EDT ET057090DHU 5.7" LCD TFT
> panel.
>
> Signed-off-by: Marcel Ziswiler
Applied, thanks.
On Tue, May 03, 2016 at 06:50:21PM +0800, Dong Aisheng wrote:
> Hi Shawn,
>
> On Tue, May 3, 2016 at 4:32 PM, Shawn Guo <shawn...@kernel.org> wrote:
> > On Thu, Apr 28, 2016 at 02:07:03PM -0700, Stefan Agner wrote:
> >> The clock parent of the AHB root
On Fri, Apr 29, 2016 at 10:19:01AM +0200, Uwe Kleine-König wrote:
> Hello,
>
> $Subject ~= s/imx/imx7/
Updated the subject and applied the patch.
Shawn
On Fri, Apr 29, 2016 at 10:40:18PM +0200, Marcel Ziswiler wrote:
> The GPIO-based bitbanging I2C driver is required to make HDMI work on
> the Apalis iMX6 module plugged into a Ixora carrier board featuring a
> DDC channel to read a screen's EDID being hooked up to regular GPIOs.
>
>
On Fri, Apr 15, 2016 at 06:00:53PM -0700, Stephen Boyd wrote:
> On 01/29, Stefan Agner wrote:
> > If a clock gets enabled early during boot time, it can lead to a PLL
> > startup. The wait_lock function makes sure that the PLL is really
> > stareted up before it gets used. However, the function
On Thu, Apr 14, 2016 at 11:12:06AM -0500, Rob Herring wrote:
> On Wed, Apr 13, 2016 at 06:08:26PM +0800, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > new compatible string: "fsl,ls1043a-qspi".
> >
> > Signed-off-by: Yuan Yao
> > ---
> >
On Sat, Apr 16, 2016 at 10:26:06PM +0200, Arnd Bergmann wrote:
> Building the imx pinctrl driver without regmap fails with multiple
> build errors like:
>
> drivers/pinctrl/freescale/pinctrl-imx.c: In function 'imx_pinctrl_probe':
> drivers/pinctrl/freescale/pinctrl-imx.c:723:9: error: variable
On Wed, Apr 13, 2016 at 08:39:32PM +, Stuart Yoder wrote:
> > > @@ -265,6 +265,93 @@
> > > compatible = "fsl,qoriq-mc";
> > > reg = <0x0008 0x0c00 0 0x40>,/* MC portal
> > > base */
> > > <0x 0x0834 0
On Mon, Apr 18, 2016 at 10:02 AM, Shawn Guo <shawn...@kernel.org> wrote:
> On Wed, Apr 13, 2016 at 08:39:32PM +, Stuart Yoder wrote:
>> > > @@ -265,6 +265,93 @@
>> > > compatible = "fsl,qoriq-mc";
>> > >
On Wed, Apr 13, 2016 at 04:05:23PM -0500, Stuart Yoder wrote:
> updates to the fsl-mc node for full functionality:
>-msi-parent is needed for interrupt support
>-ranges is needed to enable the bus driver to translate bus addresses
>-dpmac nodes provide a basis for relating dpmac
On Mon, Jul 25, 2016 at 11:42:35PM -0700, Stefan Agner wrote:
> Since we have a SoC level node we should make use of it and have
> all nodes which are within the SoC, inside that node. This also
> saves an extra interrupt-parent properties. While at it, also
> order the Coresight nodes according
On Mon, Jul 11, 2016 at 02:18:48PM +0200, Lothar Waßmann wrote:
> The power and reset handling of the FEC ethernet driver is sufficient
> to get the ethernet PHY on the TX28 into a usable state.
> Remove the code that does the PHY initialization on startup.
>
> Signed-off-by: Lothar Waßmann
On Mon, Jul 11, 2016 at 09:08:11PM +0300, Tuomas Tynkkynen wrote:
> The Wandboard Quad comes with a SATA port. Enable the IMX SATA driver by
> default to make it easy to have the root filesystem on it.
>
> Signed-off-by: Tuomas Tynkkynen
Applied both, thanks.
On Thu, Aug 04, 2016 at 12:22:37PM +0200, Fabien Lahoudere wrote:
> In order to use sdma with UART, we need to add DMA configuration in device
> tree.
>
> Signed-off-by: Fabien Lahoudere
Changed subject prefix to 'ARM: dts: imx53: ', and applied patch.
Shawn
On Thu, Aug 04, 2016 at 03:47:32PM +0200, Fabien Lahoudere wrote:
> We have the following messages that tell csi devices are not used:
> imx-ipuv3 1800.ipu: no port@0 node in /soc/ipu@1800, not using CSI0
> imx-ipuv3 1800.ipu: no port@1 node in /soc/ipu@1800, not using CSI1
>
> So
On Mon, Aug 01, 2016 at 10:04:53AM -0400, Lucile Quirion wrote:
> diff --git a/arch/arm/boot/dts/imx6dl-ts4900.dts
> b/arch/arm/boot/dts/imx6dl-ts4900.dts
> new file mode 100644
> index 000..909fd5c
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-ts4900.dts
> +/dts-v1/;
> +#include
On Tue, Jun 28, 2016 at 02:54:44PM +0200, and...@inversepath.com wrote:
> + {
> + pinctrl_esdhc1: esdhc1grp {
> + fsl,pins = <
> + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
> + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
> +
One more comment below.
On Tue, Jun 28, 2016 at 02:54:44PM +0200, and...@inversepath.com wrote:
> + {
> + pinctrl_esdhc1: esdhc1grp {
> + fsl,pins = <
> + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
> + MX53_PAD_SD1_DATA1__ESDHC1_DAT1
use the new
> name instead, as done in commit 26cefdd15db1 for the other occurrence.
>
> Fixes: 26cefdd15db1 ("ARM: dts: imx: replace legacy wakeup property with
> 'wakeup-source'")
> Cc: Sudeep Holla <sudeep.ho...@arm.com>
> Cc: Shawn Guo <shawn...@kernel.org>
On Tue, Jul 05, 2016 at 06:04:09AM +0200, Andreas Färber wrote:
> + {
> + status = "okay";
> + phy-handle = <>;
We generally have 'status' at the bottom of property list.
Shawn
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> +
On Tue, Jul 05, 2016 at 06:04:10AM +0200, Andreas Färber wrote:
> Enable the SDHC node and model the SDIO_PWR GPIO as a regulator.
> Use the SD card as default trigger for the red LED.
>
> Cc: Ettore Chimenti
> Signed-off-by: Andreas Färber
> ---
>
On Tue, Aug 09, 2016 at 11:15:42AM -0400, Lucile Quirion wrote:
> Lucile Quirion (2):
> of: documentation: add bindings documentation for TS-4900
> ARM: dts: TS-4900: add basic device tree
Applied both, thanks.
On Mon, Aug 08, 2016 at 05:00:41PM +0200, Andreas Färber wrote:
> Am 08.08.2016 um 16:12 schrieb Shawn Guo:
> > On Tue, Jul 05, 2016 at 06:04:10AM +0200, Andreas Färber wrote:
> >> Enable the SDHC node and model the SDIO_PWR GPIO as a regulator.
> >> Use the SD card as
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