Hi Hans,
On 03/09/2014 03:41 PM, Hans de Goede wrote:
Hi Maxime,
Yesterday I've been playing a bit with my Mele A1000G Quad, with the purpose of
trying to get usb and mmc working there. I already have wens' gmac patches for
the
A31 in my tree, so for starters I tried to get that to work.
Hi,
On 03/10/2014 11:04 AM, Kaspter Ju wrote:
Hi Hans,
On 03/09/2014 03:41 PM, Hans de Goede wrote:
Hi Maxime,
Yesterday I've been playing a bit with my Mele A1000G Quad, with the purpose
of
trying to get usb and mmc working there. I already have wens' gmac patches
for the
A31 in my
Hi,
On 02/14/14 16:01, Zoltan HERPAI wrote:
http://wiki.openwrt.org/toh/cubietech/cubieboard
http://wiki.openwrt.org/doc/hardware/soc/soc.allwinner.sunxi#installation.process
Just a note, going over this list I noticed that the boot partition was
required to be fat on an SD card, that is not
Am Montag, den 10.03.2014, 12:17 +0100 schrieb Boris BREZILLON:
Hello Jason,
Le 29/01/2014 20:10, Jason Gunthorpe a écrit :
On Wed, Jan 29, 2014 at 03:46:20PM -0300, Ezequiel Garcia wrote:
After CE# has been pulled high and then transitioned low again, the host
should issue a Set
Hi Andriy,
On Wed, Mar 05, 2014 at 02:07:55PM +, Shevchenko, Andriy wrote:
+ return PTR_ERR(pll6);
+ }
+
+ ret = clk_set_parent(mux, pll6);
+ if (ret) {
+ dev_err(pdev-dev, Couldn't reparent AHB1 on PLL6\n);
+ return ret;
+ }
+
+
Hey Nathan,
On 02/17/14 19:39, Nathan Buckley wrote:
I rebuild the kernel to include I2C output. This can be seen here.
http://pastebin.com/vV1prk5P
Unsure what else to do to debug the issue.
From the sound of it, the controller isn't fully compatible with the
supplied source.
Maybe wrong
On 02/18/14 11:48, Benjamin Henrion wrote:
A10 PIC flasher with GPIOs:
http://dangerousprototypes.com/2014/02/18/picberry-r-pi-allwinner-a10-pic-programmer-using-gpio-connector/
Very interesting concept, I did see it on DP a while ago. We should add
some info to our wiki. Personally I'd only
On 02/21/14 21:55, Luc Verhaegen wrote:
On Thu, Feb 20, 2014 at 09:50:59AM -0800, Jeremy Darling wrote:
I've been looking at this board with the 7 touch display as something new
to play with. But reading the comments on the sellers page it seems many
people haven't had any luck with getting
On Mon, Mar 10, 2014 at 1:43 PM, Olliver Schinagl
oliver+l...@schinagl.nl wrote:
On 02/18/14 11:48, Benjamin Henrion wrote:
A10 PIC flasher with GPIOs:
http://dangerousprototypes.com/2014/02/18/picberry-r-pi-allwinner-a10-pic-programmer-using-gpio-connector/
Very interesting concept, I did
On 03/01/14 12:35, Puneet B wrote:
Hi i am using humming board..
Have you ever bothered to go through the new device howto?
http://linux-sunxi.org/New_Device_howto
After all this time we spent on doing your work for you, taking the 10
minutes to do the new device howto would have been
2014. március 10., hétfő 13:32:39 UTC+1 időpontban Olliver Schinagl a
következőt írta:
Hey Rudi,
I can't say that I have, and I think atleast half of my kernel images
are lzo compressed.
Do you still have this with the 3.4.7* series?
Olliver
On 02/17/14 14:52,
On 03/05/14 09:43, xavier.rovira.lanacc...@gmail.com wrote:
Is it possible to encode mpeg2 with CedarX?
in homepate it is said encode mpeg must be checked.
Still a todo item. If you can help, patches welcome!
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Hello,
Le 29/01/2014 15:34, Boris BREZILLON a écrit :
Define a struct containing the standard NAND timings as described in NAND
datasheets.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
include/linux/mtd/nand.h | 49 ++
1 file
Yeah, I finally got all of this working :) I've submitted a pull request to
get the Olinuxino Lime added to the meta-sunxi tree.
/Peter
2014-03-10 14:50 GMT+01:00 Olliver Schinagl oliver+l...@schinagl.nl:
On 03/06/14 16:21, Peter Olsson wrote:
I'm on 3.4.67. However, I just managed to get
Now that we have a DMA driver, we can add the DMA bindings in the DTSI for the
controller and the devices supported that can use DMA.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 29 +
1 file changed, 29
Since we start to have a lot of clocks to protect, some of them in a few boards
only, it becomes difficult to handle the clock protection without having to add
per machine exceptions.
Move these where they belong, in the machine definition code.
Signed-off-by: Maxime Ripard
Right now, AHB is an indirect child clock of the CPU clock. If that happens to
change, since the CPU clock has no other consumers declared in Linux, it would
be shut down, which is not really a good idea.
Prevent this by forcing it enabled.
Signed-off-by: Maxime Ripard
Prevent the SDRAM controller from being gated by force-enabling it in the
machine code.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/mach-sunxi/sun6i.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-sunxi/sun6i.c b/arch/arm/mach-sunxi/sun6i.c
Hi Olliver,
Do you still have this with the 3.4.7* series?
Yes.
Yes I have seen the same on 3.4.79+ too. At least head of commits is
'8ea347bcb4b4a5e50ec0343afac579e933ce8402'.
Tried exactly this version with the same result.
I think the problem started with the upstream merge of the
On Monday 10 March 2014 15:41:51 Maxime Ripard wrote:
+/*
+ * Hardware representation of the LLI
+ *
+ * The hardware will be fed the physical address of this structure,
+ * and read its content in order to start the transfer.
+ */
+struct sun6i_dma_lli {
+ u32
On 03/09/14 07:10, Kyle Bassett wrote:
Try increase .emr1 more than 0x4 .
Hi,
Do we know what is the difference between '.emr1=0' and other settings such
as '.emr1=0x4'?
We know extremely little on how the memory controller really works. This
setting moving over from a different platform
Hey Hans,
I played with the a31 stuff in u-boot a while ago. Lacking hardware,
there was little I was able to do, but check out this patch that might
(or not at all) work/give an idea for the p2wi and pmic stuff.
Hi Arnd,
On Mon, Mar 10, 2014 at 04:34:04PM +0100, Arnd Bergmann wrote:
On Monday 10 March 2014 15:41:51 Maxime Ripard wrote:
+/*
+ * Hardware representation of the LLI
+ *
+ * The hardware will be fed the physical address of this structure,
+ * and read its content in order to start
On Monday 10 March 2014 17:51:56 Maxime Ripard wrote:
Neither pll6 nor ahb1_mux are listed in the DT binding. Also, why
is it the driver's business to set the parent?
Those are global clocks, so it's not really part pof the driver
binding itself. But I can add them.
No better don't
On 10 March 2014 16:58, Olliver Schinagl oliver+l...@schinagl.nl wrote:
On 03/09/14 07:10, Kyle Bassett wrote:
Try increase .emr1 more than 0x4 .
Hi,
Do we know what is the difference between '.emr1=0' and other settings
such
as '.emr1=0x4'?
We know extremely little on how the memory
Hi,
On 03/10/2014 06:34 PM, Chen-Yu Tsai wrote:
On Mon, Mar 10, 2014 at 6:25 PM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 03/10/2014 11:04 AM, Kaspter Ju wrote:
Hi Hans,
On 03/09/2014 03:41 PM, Hans de Goede wrote:
Hi Maxime,
Yesterday I've been playing a bit with my Mele A1000G
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Hash: SHA1
Hi,
On 03/09/2014 10:41 AM, Maxime Ripard wrote:
Hi Hans,
On Sun, Mar 09, 2014 at 08:41:35AM +0100, Hans de Goede wrote:
Hi Maxime,
Yesterday I've been playing a bit with my Mele A1000G Quad, with the purpose
of trying to get usb and mmc
On Fri, Mar 07, 2014 at 01:20:58AM +, Ian Campbell wrote:
I have observed timeouts on a cubietruck.
The increase to 40ms is completely arbitrary and Works For Me(tm). I
couldn't find a good reference for how long you are supposed to wait,
although googling around it seems like tens of
It depends on your needs. If simply want to expand some DI/DO, ADC/DAC
or some other peripheral, USB maybe a good, cheap and expandible
option. I don't see too much needs in SRAM interface. If you
desperately need a parellel interface, you can use nand flash
controller with a small CPLD.
On Sunday, March 9, 2014 10:13:08 AM UTC-4, Alejandro Mery wrote:
On 09/03/14 13:09, Olliver Schinagl wrote:
Mnemoc,
have you checked and merged this yet?
thanks for the reminder. it fails to compile when hwmon is m
like on sun7i_defconfig:
LD .tmp_vmlinux1
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