Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
Looks like we still have issues with pSeries and Cell idle code
vs. the lazy irq state. In fact, the reset fixes that went upstream
are exposing the problem more by causing BUG_ON() to trigger (which
this patch turns into a WARN_ON
Stephen Rothwell s...@canb.auug.org.au writes:
Hi Aneesh,
On Mon, 9 Jul 2012 18:43:33 +0530 Aneesh Kumar K.V
aneesh.ku...@linux.vnet.ibm.com wrote:
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index 1c65a59..1c984a6 100644
---
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, July 10, 2012 12:39 AM
To: Liu Shengzhou-B36685
Cc: bhelg...@google.com; linux-...@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH] PCI: Add pcie_irq=other to enable non MSI/INTx interrupt
for port
Stephen Rothwell s...@canb.auug.org.au writes:
Hi Aneesh,
On Mon, 9 Jul 2012 18:43:33 +0530 Aneesh Kumar K.V
aneesh.ku...@linux.vnet.ibm.com wrote:
diff --git a/arch/powerpc/mm/hash_native_64.c
b/arch/powerpc/mm/hash_native_64.c
index 660b8bb..308e29d 100644
---
The following 4 patches enabling fsl-dma and talitos offload raid
operations for improving raid performance and balancing CPU load.
Write performance will be improved by 40% tested by iozone. CPU load
will be reduced by 8%.
Qiang Liu (4):
Talitos: move the data structure into header file
The following 4 patches enabling fsl-dma and talitos offload raid
operations for improving raid performance and balancing CPU load.
Write performance will be improved by 40% tested by iozone. CPU load
will be reduced by 8%.
Qiang Liu (4):
Talitos: move the data structure into header file
Move the declaration of talitos data structure into talitos.h.
Cc: Herbert Xu herb...@gondor.apana.org.au
Cc: David S. Miller da...@davemloft.net
Signed-off-by: Qiang Liu qiang@freescale.com
---
drivers/crypto/talitos.c | 108 --
Expose Talitos's XOR functionality to be used for RAID parity
calculation via the Async_tx layer.
Cc: Herbert Xu herb...@gondor.apana.org.au
Cc: David S. Miller da...@davemloft.net
Signed-off-by: Dipen Dudhat dipen.dud...@freescale.com
Signed-off-by: Maneesh Gupta maneesh.gu...@freescale.com
- delete attribute of DMA_INTERRUPT because fsl-dma doesn't support
this function, exception will be thrown if talitos is used to compute xor
at the same time;
- change the release process of dma descriptor for avoiding exception when
enable config NET_DMA, release dma descriptor from 1st to last
An error will be happened when test with mass data:
DMA-API: device driver tries to sync DMA memory it has not allocated;
DMA-API: debugging out of memory - disabling
dma mapping memory of request-desc is not released by right device,
it should be private-dev but not dev;
Cc: Herbert Xu
The following 4 patches enabling fsl-dma and talitos offload raid
operations for improving raid performance and balancing CPU load.
Write performance will be improved by 40% tested by iozone. CPU load
will be reduced by 8%.
Qiang Liu (4):
Talitos: move the data structure into header file
The issue log on core1 is:
root@mpc8572ds:~# ifconfig eth0 10.192.208.244
net eth0: could not attach to PHY
SIOCSIFFLAGS: No such device
To attach PHY node mdio@24520 should not be disabled in dts of core1.
Because all PHYs are controlled through this node as follows:
mdio@24520 {
phy0:
With 2-cell format interrupts of MSI PCIe ethernet card can not work.
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jia Hongtao b38...@freescale.com
---
arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts |8
arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts |8
2
On Tue, 2012-07-10 at 16:10 +1000, Michael Neuling wrote:
Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
Looks like we still have issues with pSeries and Cell idle code
vs. the lazy irq state. In fact, the reset fixes that went upstream
are exposing the problem more by causing
Add memory attribute in inline assembly language as a compiler
barrier to make sure 4.6.x GCC don't reorder mfmsr().
Signed-off-by: Tiejun Chen tiejun.c...@windriver.com
---
arch/powerpc/include/asm/reg.h |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git
From: Zhicheng Fan b32...@freescale.com
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/boot/dts/fsl/p1021si-post.dtsi | 16 ++-
arch/powerpc/boot/dts/p1025rdb.dtsi | 40 +++
2 files changed, 55 insertions(+), 1 deletions(-)
diff
On Tue, 2012-07-10 at 15:59 +0800, Tiejun Chen wrote:
Add memory attribute in inline assembly language as a compiler
barrier to make sure 4.6.x GCC don't reorder mfmsr().
Out of curiosity, did you see a case where it was re-ordered
improperly ?
Cheers,
Ben.
Signed-off-by: Tiejun Chen
- hard_irq_disable();
- if (!lazy_irq_pending())
+ if (prep_irq_for_idle()) {
cede_processor();
+#ifdef CONFIG_TRACE_IRQFLAG
this is IRQFLAGS (missing S). I'll fix it while I commit, the same
typo is in another place in irq.c as well, I'll commit a fix for that
too
On 07/10/2012 04:19 PM, Benjamin Herrenschmidt wrote:
On Tue, 2012-07-10 at 15:59 +0800, Tiejun Chen wrote:
Add memory attribute in inline assembly language as a compiler
barrier to make sure 4.6.x GCC don't reorder mfmsr().
Out of curiosity, did you see a case where it was re-ordered
On 07/10/2012 04:22 PM, tiejun.chen wrote:
On 07/10/2012 04:19 PM, Benjamin Herrenschmidt wrote:
On Tue, 2012-07-10 at 15:59 +0800, Tiejun Chen wrote:
Add memory attribute in inline assembly language as a compiler
barrier to make sure 4.6.x GCC don't reorder mfmsr().
Out of curiosity, did
Hi Linus !
It looks like my rewrite of our lazy irq scheme is still exposing
interesting issues left and right. The previous fixes are now
causing an occasional BUG_ON to trigger (which this patch turns
into a WARN_ON while at it), due to another issue of disconnect
of the lazy irq state vs. the
+ u32 eisr, eimr;
+ int errint;
+ unsigned int cascade_irq;
+
+ eisr = fsl_mpic_err_read(mpic-err_regs, eisr_offset);
+ eimr = fsl_mpic_err_read(mpic-err_regs, eimr_offset);
+
+ if (!(eisr ~eimr))
+ return IRQ_NONE;
+
+ while (eisr) {
+
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Tuesday, July 10, 2012 7:17 AM
To: Wood Scott-B07421
Cc: Sethi Varun-B16395; Hamciuc Bogdan-BHAMCIU1; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH 3/3 v2] powerpc/mpic: FSL MPIC error interrupt
Hi Christoph,
2012/07/10 0:18, Christoph Lameter wrote:
On Mon, 9 Jul 2012, Yasuaki Ishimatsu wrote:
Even if you apply these patches, you cannot remove the physical memory
completely since these patches are still under development. I want you to
cooperate to improve the physical memory
Hi, All,
Is there any concern for this patch, it's been a long time.
Thanks!
Best Regards,
Shaohui Xie
-Original Message-
From: Xie Shaohui-B21989
Sent: Tuesday, May 08, 2012 2:07 PM
To: linux-watch...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
Cc: Xie Shaohui-B21989
Subject:
Hi, All,
Is there any concern for this patch, it's been a long time.
Thanks!
Best Regards,
Shaohui Xie
-Original Message-
From: Xie Shaohui-B21989
Sent: Friday, May 11, 2012 1:34 PM
To: linux-watch...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
Cc: Xie Shaohui-B21989
Subject:
* Enable NAND, MSI, PAMU,
* Enable FSL RAID on P5020
* Enable general RAID features (MD + async-tx)
* Enable RTC on P2041RDB
* Enable UIO SRIO UIO DMA
Signed-off-by: Harninder Rai harninder@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Minghuan Lian
* Enable NAND, MSI, PAMU,
* Enable FSL RAID on P5020
* Enable general RAID features (MD + async-tx)
* Enable RTC on P2041RDB
* Enable UIO SRIO UIO DMA
Signed-off-by: Harninder Rai harninder@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Minghuan Lian
* Enable USB, MMC, SATA, MTD, NAND, PAMU, RTC
* Enable FSL RAID on P5020
* Enable general RAID features (MD + async-tx)
* Enable RTC on P2041RDB
* Enable UIO SRIO UIO DMA
* Enable USDPAA SHMEM driver
* Enable ePAPR HV support
* Enable PCI-E support
Signed-off-by: Haiying Wang
P1021RDB-PC Overview
-
1Gbyte DDR3 (on board DDR)
16Mbyte NOR flash
32Mbyte eSLC NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
Real-time clock on I2C bus
SD/MMC connector to interface with the SD memory card
PCIex
- x1 PCIe slot or x1 PCIe to dual SATA
Create the dts files for each core and splits the devices between
the two cores for P1021RDB-PC.
Core0 has l2, serial0, i2c, spi, gpio, tdm,dma, usb, eth0, eth1,
sdhc, crypto, global-util, message, pci0, pci1, msi, crypto.
Core1 has l2, serial1, eth2.
Signed-off-by: Xu Jiucheng
On May 8, 2012, at 10:46 PM, Bhushan Bharat-R65777 wrote:
.org] On Behalf Of Shaohui Xie
Sent: Tuesday, May 08, 2012 11:37 AM
To: linux-watch...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
Cc: Xie Shaohui-B21989
Subject: [PATCH 1/2] powerpc/watchdog: move booke watchdog param
related
On Jul 10, 2012, at 5:22 AM, Xie Shaohui-B21989 wrote:
Hi, All,
Is there any concern for this patch, it's been a long time.
Thanks!
Best Regards,
Shaohui Xie
As commented, we should use PPC_FSL_BOOK3E, not CONFIG_PPC_FSL_BOOK3E.
- k
-Original Message-
From: Xie
On Jul 10, 2012, at 6:40 AM, Kumar Gala wrote:
On Jul 10, 2012, at 5:22 AM, Xie Shaohui-B21989 wrote:
Hi, All,
Is there any concern for this patch, it's been a long time.
Thanks!
Best Regards,
Shaohui Xie
As commented, we should use PPC_FSL_BOOK3E, not CONFIG_PPC_FSL_BOOK3E.
On Jul 10, 2012, at 5:40 AM, Shengzhou Liu wrote:
* Enable NAND, MSI, PAMU,
* Enable FSL RAID on P5020
* Enable general RAID features (MD + async-tx)
* Enable RTC on P2041RDB
* Enable UIO SRIO UIO DMA
Signed-off-by: Harninder Rai harninder@freescale.com
Signed-off-by: Shaohui Xie
On Jul 10, 2012, at 5:40 AM, Shengzhou Liu wrote:
* Enable USB, MMC, SATA, MTD, NAND, PAMU, RTC
* Enable FSL RAID on P5020
* Enable general RAID features (MD + async-tx)
* Enable RTC on P2041RDB
* Enable UIO SRIO UIO DMA
* Enable USDPAA SHMEM driver
* Enable ePAPR HV support
* Enable
On Jul 10, 2012, at 4:39 AM, Sethi Varun-B16395 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Tuesday, July 10, 2012 7:17 AM
To: Wood Scott-B07421
Cc: Sethi Varun-B16395; Hamciuc Bogdan-BHAMCIU1; linuxppc-
d...@lists.ozlabs.org
Subject:
On Jul 10, 2012, at 3:39 AM, Xu Jiucheng wrote:
P1021RDB-PC Overview
-
1Gbyte DDR3 (on board DDR)
16Mbyte NOR flash
32Mbyte eSLC NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
Real-time clock on I2C bus
SD/MMC connector to interface with the SD memory
We need to use CONFIG_FSL_SOC_BOOKE instead of CONFIG_PPC_85xx as
CONFIG_PPC_85xx isn't defined when we build support for 64-bit embedded
FSL PPC SoCs.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
drivers/usb/host/ehci-fsl.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
On Feb 29, 2012, at 7:20 PM, Olivia Yin wrote:
From: Liu Yu yu@freescale.com
So that we can call it when improving SPE switch like book3e did for fp
switch.
Signed-off-by: Liu Yu yu@freescale.com
Signed-off-by: Olivia Yin hong-hua@freescale.com
---
v2: add Signed-off-by
On Jul 9, 2012, at 3:46 AM, Varun Sethi wrote:
We should use the MPIC_LARG_VECTORS flag while intializing the MPIC.
This prevents us from eating in to hardware vector number space (MSIs)
while setting up internal sources.
Signed-off-by: Varun Sethi varun.se...@freescale.com
---
On May 11, 2012, at 12:33 AM, Shaohui Xie wrote:
CONFIG_FSL_BOOKE is only defined in 32-bit, CONFIG_PPC_FSL_BOOK3E is
defined in both 32-bit and 64-bit, so use CONFIG_PPC_FSL_BOOK3E to make
driver work in 32-bit 64-bit.
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes
On Jul 10, 2012, at 1:08 AM, Jia Hongtao wrote:
The issue log on core1 is:
root@mpc8572ds:~# ifconfig eth0 10.192.208.244
net eth0: could not attach to PHY
SIOCSIFFLAGS: No such device
To attach PHY node mdio@24520 should not be disabled in dts of core1.
Because all PHYs are controlled
On Jul 10, 2012, at 1:08 AM, Jia Hongtao wrote:
With 2-cell format interrupts of MSI PCIe ethernet card can not work.
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jia Hongtao b38...@freescale.com
---
arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts |8
On Nov 11, 2011, at 10:05 AM, Kokoris, Ioannis wrote:
Hi,
QE Microcode Initialization using qe_upload_microcode() does not work on
P1021 if the IRAM-Ready register is not set after the microcode upload. This
patch adds a definition for the I-RAM Ready register and sets it uppon
On Tue, Jul 10, 2012 at 3:39 AM, Xu Jiucheng jiucheng...@freescale.com wrote:
Create the dts files for each core and splits the devices between
the two cores for P1021RDB-PC.
Core0 has l2, serial0, i2c, spi, gpio, tdm,dma, usb, eth0, eth1,
sdhc, crypto, global-util, message, pci0, pci1, msi,
On Jul 10, 2012, at 2:52 AM, Zhicheng wrote:
From: Zhicheng Fan b32...@freescale.com
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/boot/dts/fsl/p1021si-post.dtsi | 16 ++-
arch/powerpc/boot/dts/p1025rdb.dtsi | 40 +++
2 files
On Mar 30, 2012, at 12:38 AM, Shawn Guo wrote:
Freescale PowerPC SoCs share a number of IP blocks with Freescale
ARM/IMX SoCs, FlexCAN, SSI, FEC, eSDHC, USB, etc. There are some
effort consolidating those drivers to make them work for both
architectures.
One outstanding difference
On 07/10/2012 01:13 AM, Liu Shengzhou-B36685 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, July 10, 2012 12:39 AM
To: Liu Shengzhou-B36685
Cc: bhelg...@google.com; linux-...@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH] PCI: Add
On Jul 10, 2012, at 10:31 AM, Scott Wood wrote:
On 07/10/2012 01:13 AM, Liu Shengzhou-B36685 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, July 10, 2012 12:39 AM
To: Liu Shengzhou-B36685
Cc: bhelg...@google.com; linux-...@vger.kernel.org; linuxppc-
On 07/10/2012 03:39 AM, Xu Jiucheng wrote:
+ crypto@3 {
+status = disabled;
+};
Whitespace.
+
+ mpic: pic@4 {
+ protected-sources =
+ 16 /* ecm, mem, L2, pci0,
On 07/10/2012 05:58 PM, Yasuaki Ishimatsu wrote:
Hi Christoph,
2012/07/10 0:18, Christoph Lameter wrote:
On Mon, 9 Jul 2012, Yasuaki Ishimatsu wrote:
Even if you apply these patches, you cannot remove the physical memory
completely since these patches are still under development. I want
On 07/10/2012 01:08 AM, Jia Hongtao wrote:
The issue log on core1 is:
root@mpc8572ds:~# ifconfig eth0 10.192.208.244
net eth0: could not attach to PHY
SIOCSIFFLAGS: No such device
To attach PHY node mdio@24520 should not be disabled in dts of core1.
Because all PHYs are controlled through
On Jun 27, 2012, at 6:50 PM, Scott Wood wrote:
Similar to how the primary PCI bridge is identified by looking
for an isa subnode, we determine whether to apply uli exclusions
by looking for a uli subnode.
Signed-off-by: Scott Wood scottw...@freescale.com
---
Besides being an example of a
--- On Mon, 7/2/12, Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
From: Benjamin Herrenschmidt b...@kernel.crashing.org
Subject: Re: [git pull] Please pull powerpc.git merge branch
To: Gerhard Pircher gerhard_pirc...@gmx.net
Cc: linuxppc-dev list linuxppc-...@ozlabs.org
Date:
Hi Ben,
On Tue, 2012-07-10 at 13:20 +1000, Benjamin Herrenschmidt wrote:
regarding the precise semantics of lv1_pause() ?
Here's what's in PS3's setup.c:
static void ps3_power_save(void)
{
/*
* lv1_pause() puts the PPE thread into inactive state until an
* irq on an
On Mon, Jul 9, 2012 at 10:59 PM, Qiang Liu qiang@freescale.com wrote:
- delete attribute of DMA_INTERRUPT because fsl-dma doesn't support
this function, exception will be thrown if talitos is used to compute xor
at the same time;
- change the release process of dma descriptor for avoiding
Qiang Liu wrote:
An error will be happened when test with mass data:
Please don't use the phrase fix the issue in patch summaries. It's
redundant.
This patch should be titled,
drivers/crypto: fix memory leak in Talitos driver
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
On 05.07.2012, at 16:41, Stuart Yoder wrote:
From: Stuart Yoder stuart.yo...@freescale.com
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
Ben, ping?
Alex
---
-v4: fixed build issues in exception-64s.h and exceptions-64s.S
arch/powerpc/include/asm/exception-64s.h |4 ++--
Hi Jiang,
2012/07/11 1:50, Jiang Liu wrote:
On 07/10/2012 05:58 PM, Yasuaki Ishimatsu wrote:
Hi Christoph,
2012/07/10 0:18, Christoph Lameter wrote:
On Mon, 9 Jul 2012, Yasuaki Ishimatsu wrote:
Even if you apply these patches, you cannot remove the physical memory
completely since these
On Tue, 10 Jul 2012 13:56:46 +0800
Qiang Liu qiang@freescale.com wrote:
Move the declaration of talitos data structure into talitos.h.
Cc: Herbert Xu herb...@gondor.apana.org.au
Cc: David S. Miller da...@davemloft.net
Signed-off-by: Qiang Liu qiang@freescale.com
---
this patch has
On 07/11/2012 08:09 AM, Yasuaki Ishimatsu wrote:
Hi Jiang,
2012/07/11 1:50, Jiang Liu wrote:
On 07/10/2012 05:58 PM, Yasuaki Ishimatsu wrote:
Hi Christoph,
2012/07/10 0:18, Christoph Lameter wrote:
On Mon, 9 Jul 2012, Yasuaki Ishimatsu wrote:
Even if you apply these patches, you cannot
The QEMU stuff is related to the PCI refactoring because currently
we have a hard time selecting a primary bus under QEMU, and also because
the generic qemu e500 platform wants a full list of FSL PCI compatibles
to check.
Patchset rebased on Kumar's next branch.
Scott Wood (3):
This gives the kernel a paravirtualized machine to target, without
requiring both sides to pretend to be targeting a specific board
that likely has little to do with the host in KVM scenarios. This
avoids the need to add new boards to QEMU just to be able to
run KVM on new CPUs.
As this is the
As an alternative incremental starting point to Jia Hongtao's patchset,
get the FSL PCI init out of the board files, but do not yet convert to a
platform driver.
Rather than having each board supply a magic register offset for
determining the primary bus, we look for which PCI host bridge
Similar to how the primary PCI bridge is identified by looking
for an isa subnode, we determine whether to apply uli exclusions
by looking for a uli subnode.
Signed-off-by: Scott Wood scottw...@freescale.com
---
v2: Rebased on Kumar's next
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 97
Unlike classic, we don't really need the MSR change to be atomic with the
branch. This eliminates a trap as a KVM guest (in the absence of
hardware hypervisor extensions), where mtmsr is paravirtualized but rfi
is not. For a virtualized guest without any paravirtualization, this
eliminates an
On Tue, 2012-07-10 at 19:34 -0500, Scott Wood wrote:
Unlike classic, we don't really need the MSR change to be atomic with the
branch. This eliminates a trap as a KVM guest (in the absence of
hardware hypervisor extensions), where mtmsr is paravirtualized but rfi
is not. For a virtualized
On 07/10/2012 07:36 PM, Benjamin Herrenschmidt wrote:
On Tue, 2012-07-10 at 19:34 -0500, Scott Wood wrote:
Unlike classic, we don't really need the MSR change to be atomic with the
branch. This eliminates a trap as a KVM guest (in the absence of
hardware hypervisor extensions), where mtmsr is
On 11.07.2012, at 02:34, Scott Wood wrote:
Unlike classic, we don't really need the MSR change to be atomic with the
branch. This eliminates a trap as a KVM guest (in the absence of
hardware hypervisor extensions), where mtmsr is paravirtualized but rfi
is not. For a virtualized guest
On 07/10/2012 07:44 PM, Alexander Graf wrote:
On 11.07.2012, at 02:34, Scott Wood wrote:
+#ifdef CONFIG_BOOKE
+/*
+ * We're not changing address space on Book E, and the extra rfi
+ * can hurt when virtualized without hardware support -- whereas
+ * mtmsr can be
On Tue, 2012-07-10 at 19:41 -0500, Scott Wood wrote:
On 07/10/2012 07:36 PM, Benjamin Herrenschmidt wrote:
On Tue, 2012-07-10 at 19:34 -0500, Scott Wood wrote:
Unlike classic, we don't really need the MSR change to be atomic with the
branch. This eliminates a trap as a KVM guest (in the
On Tue, 2012-07-10 at 19:47 -0500, Scott Wood wrote:
On 07/10/2012 07:44 PM, Alexander Graf wrote:
On 11.07.2012, at 02:34, Scott Wood wrote:
+#ifdef CONFIG_BOOKE
+ /*
+ * We're not changing address space on Book E, and the extra rfi
+ * can hurt when virtualized without
Hi Jiang,
2012/07/11 9:21, Jiang Liu wrote:
On 07/11/2012 08:09 AM, Yasuaki Ishimatsu wrote:
Hi Jiang,
2012/07/11 1:50, Jiang Liu wrote:
On 07/10/2012 05:58 PM, Yasuaki Ishimatsu wrote:
Hi Christoph,
2012/07/10 0:18, Christoph Lameter wrote:
On Mon, 9 Jul 2012, Yasuaki Ishimatsu wrote:
At 07/09/2012 06:21 PM, Yasuaki Ishimatsu Wrote:
This patch series aims to support physical memory hot-remove.
[RFC PATCH v3 1/13] memory-hotplug : rename remove_memory to offline_memory
[RFC PATCH v3 2/13] memory-hotplug : add physical memory hotplug code to
acpi_memory_device_remove
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, July 11, 2012 2:15 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org
Subject: Re: [PATCH 1/2] powerpc/mpc8572ds: Fix eTSEC is not available on
core1 of AMP boot issue
On 07/10/2012
-Original Message-
From: Dan Williams [mailto:dan.j.willi...@intel.com]
Sent: Wednesday, July 11, 2012 3:39 AM
To: Liu Qiang-B32616
Cc: linux-cry...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Li Yang-
R58472; Phillips Kim-R1AAHA; Vinod Koul
Subject: Re: [PATCH 3/4] fsl-dma:
-Original Message-
From: Tabi Timur-B04825
Sent: Wednesday, July 11, 2012 5:26 AM
To: Liu Qiang-B32616
Cc: linux-cry...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Herbert
Xu; Li Yang-R58472; David S. Miller
Subject: Re: [linuxppc-release] [PATCH 4/4] Talitos: fix the issue of
At 07/11/2012 09:52 AM, Wen Congyang Wrote:
At 07/09/2012 06:21 PM, Yasuaki Ishimatsu Wrote:
This patch series aims to support physical memory hot-remove.
[RFC PATCH v3 1/13] memory-hotplug : rename remove_memory to offline_memory
[RFC PATCH v3 2/13] memory-hotplug : add physical memory
-Original Message-
From: Phillips Kim-R1AAHA
Sent: Wednesday, July 11, 2012 8:11 AM
To: Liu Qiang-B32616
Cc: linux-cry...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Li Yang-
R58472; Herbert Xu; David S. Miller; Geanta Neag Horia Ioan-B05471
Subject: Re: [PATCH 1/4] Talitos:
On Wed, Jun 27, 2012 at 07:34:11PM +, Kim Phillips wrote:
On Wed, 27 Jun 2012 10:58:32 +0530
Bharat Bhushan r65...@freescale.com wrote:
This resolves the Linux boot crash issue when swiotlb=force is set
in bootargs on systems which have memory more than 4G.
Acked-by: Kim Phillips
At 07/09/2012 06:33 PM, Yasuaki Ishimatsu Wrote:
I don't think that all pages of virtual mapping in removed memory can be
freed, since page which type is MIX_SECTION_INFO is difficult to free.
So, the patch only frees page which type is SECTION_INFO at first.
CC: David Rientjes
diff --git a/arch/powerpc/kernel/machine_kexec.c
b/arch/powerpc/kernel/machine_kexec.c
index c957b12..0c9695d 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -207,6 +207,12 @@ static struct property crashk_size_prop = {
.value =
2012/07/11 14:06, Wen Congyang wrote:
Hi Wen,
At 07/09/2012 06:33 PM, Yasuaki Ishimatsu Wrote:
I don't think that all pages of virtual mapping in removed memory can be
freed, since page which type is MIX_SECTION_INFO is difficult to free.
So, the patch only frees page which type is
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