you can mark a
BAR as e.g. both fixed size and reserved.
This series tries to address all the problems above.
Personally, I think that the code is more readable, both the endpoint
controller drivers, but also pci-epc-core.c.
Thank you for cleaning this up!
FWIW:
Reviewed-by: Kishon Vijay
Hi Xiaowei,
On 24/09/19 7:48 am, Xiaowei Bao wrote:
> dw_pcie_ep_raise_msix_irq was never called in the exisitng driver
> before, because the ls1046a platform don't support the MSIX feature
> and msix_capable was always set to false.
> Now that add the ls1088a platform with MSIX support, but the e
Gustavo,
On 06/11/19 3:10 PM, Gustavo Pimentel wrote:
> On Thu, Aug 29, 2019 at 6:13:18, Kishon Vijay Abraham I
> wrote:
>
> Hi, this email slip away from my attention...
>
>> Gustavo,
>>
>> On 27/08/19 6:55 PM, Andrew Murray wrote:
>>> On Sat, Aug
Gustavo,
On 27/08/19 6:55 PM, Andrew Murray wrote:
> On Sat, Aug 24, 2019 at 12:08:40AM +, Xiaowei Bao wrote:
>>
>>
>>> -Original Message-
>>> From: Andrew Murray
>>> Sent: 2019年8月23日 21:58
>>> To: Xiaowei Bao
>>> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
>>>
Hi,
(Fixed Lorenzo's email address. All the patches in the series have wrong email
id)
On 23/08/19 8:09 AM, Xiaowei Bao wrote:
>
>
>> -Original Message-
>> From: Kishon Vijay Abraham I
>> Sent: 2019年8月22日 19:44
>> To: Xiaowei Bao ; bhelg..
Hi,
On 22/08/19 4:52 PM, Xiaowei Bao wrote:
> The different PCIe controller in one board may be have different
> capability of MSI or MSIX, so change the way of getting the MSI
> capability, make it more flexible.
please use different pci_epc_features table for different boards.
Thanks
Kishon
>
Hi,
On 16/08/19 8:28 AM, Xiaowei Bao wrote:
>
>
>> -Original Message-
>> From: Andrew Murray
>> Sent: 2019年8月15日 19:54
>> To: Xiaowei Bao
>> Cc: jingooh...@gmail.com; gustavo.pimen...@synopsys.com;
>> bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
>> shawn...@kernel.org
On 13/08/19 11:58 AM, Xiaowei Bao wrote:
> The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1
> is 32bit, BAR2 and BAR4 is 64bit, this is determined by hardware,
> so set the bar_fixed_64bit with 0x14.
>
> Signed-off-by: Xiaowei Bao
Acked-by: Kishon Vijay Abraha
On 13/08/19 8:23 AM, Xiaowei Bao wrote:
> The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1
> is 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware,
Do you mean BAR2 instead of BAR3 here?
Thanks
Kishon
> so set the bar_fixed_64bit with 0x14.
>
> Signed-off-by: Xiao
Hi Xiaowei,
On 21/01/19 3:14 PM, Xiaowei Bao wrote:
> Add the PCIe EP mode support for layerscape platform.
>
> Signed-off-by: Xiaowei Bao
> Reviewed-by: Minghuan Lian
> Reviewed-by: Zhiqiang Hou
This patch looks good to me, except for using epc->features which I've tried to
get rid of in [1]
(Removed Niklas as mails to him is bouncing)
Hi,
Please fix your email client. Refer Documentation/process/email-clients.rst
On 05/11/18 2:45 PM, Xiaowei Bao wrote:
>
>
> -Original Message-
> From: Kishon Vijay Abraham I
> Sent: 2018年11月5日 16:57
> To: X
Hi,
On 31/10/18 4:08 PM, Xiaowei Bao wrote:
>
>
> -Original Message-
> From: Kishon Vijay Abraham I
> Sent: 2018年10月31日 12:15
> To: Xiaowei Bao ; bhelg...@google.com;
> robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; lorenzo.pieral..
Hi,
On 31/10/18 8:03 AM, Xiaowei Bao wrote:
>
>
> -Original Message-
> From: Xiaowei Bao
> Sent: 2018年10月26日 17:19
> To: 'Kishon Vijay Abraham I' ; bhelg...@google.com;
> robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
&
Hi,
On Thursday 25 October 2018 04:39 PM, Xiaowei Bao wrote:
> Add the PCIe EP mode support for layerscape platform.
>
> Signed-off-by: Xiaowei Bao
> ---
> drivers/pci/controller/dwc/Makefile|2 +-
> drivers/pci/controller/dwc/pci-layerscape-ep.c | 161
> ++
+Grygorii, linux-omap
On Friday 06 July 2018 02:06 PM, Lukas Wunner wrote:
> [cc += Kishon Vijay Abraham]
>
> On Thu, Jul 05, 2018 at 11:18:28AM +0200, Rafael J. Wysocki wrote:
>> OK, so calling devices_kset_move_last() from really_probe() clearly is
>> a mistake.
>>
>> I'm not really sure what t
Hi,
On Friday 10 November 2017 09:18 AM, Bao Xiaowei wrote:
> Add the pcie controller ep function support of layerscape base on
> pcie ep framework.
>
> Signed-off-by: Bao Xiaowei
> ---
> v2:
> - fix the ioremap function used but no ioumap issue
> - optimize the code structure
> - add code c
Hi Bao,
On Friday 10 November 2017 09:18 AM, Bao Xiaowei wrote:
> Add the property of inbound and outbound windows number for ep
> driver.
>
> Signed-off-by: Bao Xiaowei
> Acked-by: Minghuan Lian
> ---
> v2:
> - no change
> v3:
> - modify the commit message
> v4:
> - no change
>
> arch/
On Monday 05 June 2017 02:23 PM, Jisheng Zhang wrote:
> The dw_pcie_host_ops structures are never modified. Constify these
> structures such that these can be write-protected.
>
> Signed-off-by: Jisheng Zhang
Acked-by: Kishon Vijay Abraham I
> ---
> drivers/pc
Cc: Richard Zhu
Cc: Lucas Stach
Cc: Murali Karicheri
Cc: Thomas Petazzoni
Cc: Niklas Cassel
Cc: Jesper Nilsson
Cc: Joao Pinto
Cc: Zhou Wang
Cc: Gabriele Paoloni
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci-dra7xx.c | 10 +++--
drivers/pci/dwc/pci-exynos.c
endpoint mode support to designware driver.
Cc: Jingoo Han
Cc: Richard Zhu
Cc: Lucas Stach
Cc: Murali Karicheri
Cc: Thomas Petazzoni
Cc: Niklas Cassel
Cc: Jesper Nilsson
Cc: Joao Pinto
Cc: Zhou Wang
Cc: Gabriele Paoloni
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci
Populate cpu_addr_fixup ops to extract the least 28 bits of the
corresponding cpu address.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci-dra7xx.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci
address range is fixed, device mode requires
different addresses to be programmed based on the host buffer address.
Add a new ops to get the least 28 bits of the corresponding 32 bit
CPU address and invoke it before programming the address translation
unit.
Signed-off-by: Kishon Vijay Abraham I
erged before sending the next revision of endpoint
series.
The entire endpoint support is pushed here:
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/pci-endpoint.git next
[1] -> https://lkml.org/lkml/2017/2/15/273
[2] -> https://lkml.org/lkml/2017/1/13/562
Kishon Vijay Abraham I (4):
Hi Tony,
On Saturday 21 January 2017 12:00 AM, Tony Lindgren wrote:
> * Kishon Vijay Abraham I [170112 02:34]:
>> Add pcie1 dt node in order for the controller to operate in
>> endpoint mode. However since none of the dra7 based boards have
>> slots configured to operate i
Hi,
On Thursday 19 January 2017 03:16 AM, Rob Herring wrote:
> On Thu, Jan 12, 2017 at 03:56:19PM +0530, Kishon Vijay Abraham I wrote:
>> Update device tree binding documentation of TI's dra7xx PCI
>> controller to include property for enabling legacy mode.
>>
>
zzoni
Cc: Niklas Cassel
Cc: Jesper Nilsson
Cc: Joao Pinto
Cc: Zhou Wang
Cc: Gabriele Paoloni
Cc: Stanimir Varbanov
Cc: Pratyush Anand
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci-dra7xx.c |3 ++-
drivers/pci/dwc/pci-exynos.c |3 ++-
drivers/pci/dw
Zhu
Cc: Lucas Stach
Cc: Murali Karicheri
Cc: Minghuan Lian
Cc: Mingkai Hu
Cc: Roy Zang
Cc: Thomas Petazzoni
Cc: Niklas Cassel
Cc: Jesper Nilsson
Cc: Joao Pinto
Cc: Zhou Wang
Cc: Gabriele Paoloni
Cc: Stanimir Varbanov
Cc: Pratyush Anand
Signed-off-by: Kishon Vijay Abraham I
and pcie-designware-host.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pcie-designware.c | 18 +++---
drivers/pci/dwc/pcie-designware.h |1 -
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware.c
b/drivers/pci/dwc/pcie
-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pcie-designware.c | 70
drivers/pci/dwc/pcie-designware.h | 71 +
2 files changed, 71 insertions(+), 70 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware.c
b
that use ATU
The patches has been pushed to
git://git.ti.com/linux-phy/linux-phy.git dwc-rework
Kishon Vijay Abraham I (10):
PCI: dwc: designware: Move the register defines to designware header
file
PCI: dwc: *all*: Add platform_set_drvdata
PCI: dwc: *all*: Rename cfg_read/cfg_write to
Split pcie-designware.c into pcie-designware-host.c that contains
the host specific parts of the driver and pcie-designware.c that
contains the parts used by both host driver and endpoint driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/Makefile |2 +-
drivers
CONFIG_PCI is used to enable the host mode PCI. In preparation for adding
endpoint mode support to designware driver, remove the dependency of
designware to CONFIG_PCI and make only the host specific part depend on
CONFIG_PCI.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/Makefile
Now that pci designware host has a separate file, create a new
config symbol to select the host only driver. This will enable
to independently select host support and endpoint suppor
(when it's added).
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/Kconfig |
No functional change. Fix all checkpatch warnings and check errors
in pcie-designware.c
Acked-By: Joao Pinto
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pcie-designware.c | 42 ++---
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a
v
Cc: Pratyush Anand
Reviewed-By: Joao Pinto
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci-dra7xx.c | 16
drivers/pci/dwc/pci-exynos.c |4 ++--
drivers/pci/dwc/pci-keystone-dw.c |4 ++--
drivers/pci/dwc/pcie-designware.c | 12 ++--
driver
No functional change. Get device pointer at the beginning of
dw_pcie_host_init instead of getting it all over dw_pcie_host_init.
This is in preparation for splitting struct pcie_port into host and
core structures (Once split pcie_port will not have device pointer).
Signed-off-by: Kishon Vijay
Hi,
On Tuesday 24 January 2017 09:32 PM, Christoph Hellwig wrote:
> On Thu, Jan 12, 2017 at 03:56:20PM +0530, Kishon Vijay Abraham I wrote:
>> Add PCI endpoint test driver that can verify base address
>> register, legacy interrupt/MSI interrupt and read/write/copy
>> buf
Hi Joao,
On Monday 16 January 2017 03:57 PM, Joao Pinto wrote:
>
> Hi,
>
> Às 5:21 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
>> Hi Joao,
>>
>> On Friday 13 January 2017 10:19 PM, Joao Pinto wrote:
>>> Às 10:26 AM de 1/12/2017, Kishon Vi
Hi Tony,
On Friday 13 January 2017 10:45 PM, Tony Lindgren wrote:
> * Kishon Vijay Abraham I [170112 02:35]:
>> The PCIe programming sequence in TRM suggests CLKSTCTRL of PCIe should
>> be set to SW_WKUP. There are no issues when CLKSTCTRL is set to HW_AUTO
>> in RC mode. Ho
Hi Christoph,
On Friday 13 January 2017 11:36 PM, Christoph Hellwig wrote:
> Hi Kishon,
>
> a couple comments on the configfs layout based on my experiments with
> your previous drop to implement a NVMe device using it.
Thanks for trying it out!
>
> I don't think most of these configfs files sh
Hi Joao,
On Friday 13 January 2017 11:20 PM, Joao Pinto wrote:
> Hi Kishon,
>
> Às 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>> Now that pci designware host has a separate file, create a new
>> config symbol to select the host only driver. This is in pre
Hi Joao,
On Friday 13 January 2017 10:19 PM, Joao Pinto wrote:
> Às 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>> Split pcie-designware.c into pcie-designware-host.c that contains
>> the host specific parts of the driver and pcie-designware.c that
>> contains t
Hi,
On Friday 13 January 2017 10:43 PM, Joao Pinto wrote:
> Hi,
>
> Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>> *num-lanes* dt property is parsed in dw_pcie_host_init. However
>> *num-lanes* property is applicable to both root complex mode and
>> end
Zhu
Cc: Lucas Stach
Cc: Murali Karicheri
Cc: Minghuan Lian
Cc: Mingkai Hu
Cc: Roy Zang
Cc: Thomas Petazzoni
Cc: Niklas Cassel
Cc: Jesper Nilsson
Cc: Joao Pinto
Cc: Zhou Wang
Cc: Gabriele Paoloni
Cc: Stanimir Varbanov
Cc: Pratyush Anand
Signed-off-by: Kishon Vijay Abraham I
---
I&#x
functions
that is specific to an endpoint function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/Makefile|2 +
drivers/pci/Kconfig |1 +
drivers/pci/endpoint/Kconfig| 21 ++
drivers/pci/endpoint/Makefile |6 +
drivers/pci/endpoint
Add endpoint mode support to designware driver. This uses the
EP Core layer introduced recently to add endpoint mode support.
*Any* function driver can now use this designware device
in order to achieve the EP functionality.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/Kconfig
No functional change. Fix all checkpatch warnings and check errors
in pcie-designware.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pcie-designware.c | 42 ++---
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/pci/dwc/pcie
doesn't have to enable msi_interrupts.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci-dra7xx.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 8a1fccd..eb3a9c6 1
support is added, all the
endpoint related setup can be added in a separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci-dra7xx.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7
Add binding documentation for pci-test endpoint function that helps in
adding and configuring pci-test endpoint function.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/PCI/00-INDEX |2 ++
.../PCI/endpoint/function/binding/pci-test.txt | 17
n
Cc: Murali Karicheri
Cc: Joao Pinto
Cc: Stanimir Varbanov
Cc: Pratyush Anand
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci-dra7xx.c | 16
drivers/pci/dwc/pci-exynos.c |4 ++--
drivers/pci/dwc/pci-keystone-dw.c |4 ++--
drivers/pci/dwc
Split pcie-designware.c into pcie-designware-host.c that contains
the host specific parts of the driver and pcie-designware.c that
contains the parts used by both host driver and endpoint driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/Makefile |2 +-
drivers
endpoint mode support to designware driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci-dra7xx.c |8 ++--
drivers/pci/dwc/pci-exynos.c | 16 +++
drivers/pci/dwc/pci-imx6.c | 58 +++
drivers/pci/dwc/pci-keystone-dw.c
This adds a new endpoint function driver (to program the virtual
test device) making use of the EP-core library.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/Kconfig |2 +
drivers/pci/endpoint/Makefile |3 +-
drivers/pci/endpoint
Introduce a new configfs entry to configure the EP function (like
configuring the standard configuration header entries) and to
bind the EP function with EP controller.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/Kconfig |4 +-
drivers/pci/endpoint/Makefile
Add Documentation to help users use endpoint library to enable endpoint
mode in the PCI controller and add new PCI endpoint functions.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/PCI/00-INDEX |2 +
Documentation/PCI/endpoint/pci-endpoint.txt | 190
No functional change. Move the register defines and other macros from
pcie-designware.c to pcie-designware.h. This is in preparation to
split the pcie-designware.c file into designware core file and host
specific file.
While at that also fix a checkpatch warning.
Signed-off-by: Kishon Vijay
Now that pci designware host has a separate file, create a new
config symbol to select the host only driver. This is in preparation
to enable endpoint support to designware driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/Kconfig | 26
Add device tree binding documentation for pci dra7xx EP mode.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 37 ++
1 file changed, 30 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt
Update device tree binding documentation of TI's dra7xx PCI
controller to include property for enabling legacy mode.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/ti-pci.txt |4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devic
Vijay Abraham I
---
arch/arm/mach-omap2/clockdomains7xx_data.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c
b/arch/arm/mach-omap2/clockdomains7xx_data.c
index 6c67965..67ebff8 100644
--- a/arch/arm/mach-omap2
Add maintainer for the newly introduced PCI EP framework.
Signed-off-by: Kishon Vijay Abraham I
---
MAINTAINERS |9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8672f18..021f676 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9407,6 +9407,15 @@ F
: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci-dra7xx.c | 10 +++--
drivers/pci/dwc/pci-exynos.c | 10 +++--
drivers/pci/dwc/pci-imx6.c | 67
drivers/pci/dwc/pci-keystone-dw.c | 15 ---
drivers/pci/dwc/pcie-armada8k.c
No functional change. Get device pointer at the beginning of
dw_pcie_host_init instead of getting it all over dw_pcie_host_init.
This is in preparation for splitting struct pcie_port into host and
core structures (Once split pcie_port will not have device pointer).
Signed-off-by: Kishon Vijay
Add Documentation to help users use pci endpoint to configure
pci endpoint function and to bind the endpoint function
with endpoint controller.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/PCI/00-INDEX |2 +
Documentation/PCI/endpoint/pci-endpoint-cfs.txt
Add specification for the *pci test* virtual function device. The endpoint
function driver and the host pci driver should be created based on this
specification.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/PCI/00-INDEX |2 +
Documentation/PCI/endpoint/pci
.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci-dra7xx.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 333aa56..7666e3e 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
and pcie-designware-host.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pcie-designware.c | 18 +++---
drivers/pci/dwc/pcie-designware.h |1 -
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware.c
b/drivers/pci/dwc/pcie
Add device tree binding documentation for pci designware EP mode.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/designware-pcie.txt| 26 ++--
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci
address range is fixed, device mode requires
different addresses to be programmed based on the host buffer address.
Add a new ops to get the least 28 bits of the corresponding 32 bit
CPU address and invoke it before programming the address translation
unit.
Signed-off-by: Kishon Vijay Abraham I
Add PCI endpoint test driver that can verify base address
register, legacy interrupt/MSI interrupt and read/write/copy
buffers between host and device. The corresponding pci-epf-test
function driver should be used on the EP side.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/Kconfig
Add a simple test script that invokes the pcitest userspace tool
to perform all the PCI endpoint tests (BAR tests, interrupt tests,
read tests, write tests and copy tests).
Signed-off-by: Kishon Vijay Abraham I
---
tools/pci/pcitest.sh | 56
Add pcie1 dt node in order for the controller to operate in
endpoint mode. However since none of the dra7 based boards have
slots configured to operate in endpoint mode, keep EP mode
disabled.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/am572x-idk.dts|7
: OKAY
WRITE (1024001 bytes): OKAY
Copy Tests
COPY ( 1 bytes): OKAY
COPY ( 1024 bytes): OKAY
COPY ( 1025 bytes): OKAY
COPY (1024000 bytes): OKAY
COPY (1024001 bytes): OKAY
Kishon Vijay Abraham I (37):
PCI: dwc: dra7xx: Grou
The PCIe controller integrated in dra7xx SoCs is capable of operating
in endpoint mode. Add endpoint mode support to dra7xx driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/Kconfig | 31 +-
drivers/pci/dwc/Makefile |4 +-
drivers/pci/dwc/pci
Add a userspace tool to invoke the ioctls exposed by the
PCI endpoint test driver to perform various PCI tests.
Signed-off-by: Kishon Vijay Abraham I
---
tools/pci/pcitest.c | 186 +++
1 file changed, 186 insertions(+)
create mode 100644 tools
CONFIG_PCI is used to enable the host mode PCI. In preparation for adding
endpoint mode support to designware driver, remove the dependency of
designware to CONFIG_PCI and make only the host specific part depend on
CONFIG_PCI.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/Makefile
Add Documentation for pci-endpoint-test driver.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/misc-devices/pci-endpoint-test.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/misc-devices/pci-endpoint-test.txt
diff --git a
Populate cpu_addr_fixup ops to extract the least 28 bits of the
corresponding cpu address.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci-dra7xx.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci
Add start_link and stop_link ops in dw_pcie_ops to start or stop
the link. This will be used by endpoint functions to start the
link once the setup has been done.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pcie-designware.h |2 ++
1 file changed, 2 insertions(+)
diff --git a
i
Cc: Niklas Cassel
Cc: Jesper Nilsson
Cc: Joao Pinto
Cc: Zhou Wang
Cc: Gabriele Paoloni
Cc: Stanimir Varbanov
Cc: Pratyush Anand
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci-dra7xx.c |3 ++-
drivers/pci/dwc/pci-exynos.c |3 ++-
drivers/pci/dw
Hi Arnd,
On Thursday 19 May 2016 02:37 PM, Arnd Bergmann wrote:
> On Thursday 19 May 2016 00:45:16 Olof's autobuilder wrote:
>> Errors:
>>
>> arm64.allmodconfig:
>> samples/seccomp/bpf-fancy.c:13:27: fatal error: linux/seccomp.h: No such
>> file or directory
>> samples/seccomp/dropper.c:2
roller and an index should be passed. Based on the binding
information that is added in the platform file, get_phy will return the
approappropriate PHY.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/mach-shmobile/board-marzen.c |2 +-
drivers/power/ab8500_charger.c|2 +-
dri
ng "usb: musb: add driver for control module" patch series.
Did basic enumeration testing in omap4 panda, omap4 sdp and omap3 beagle.
Kishon Vijay Abraham I (6):
usb: otg: Add an API to bind the USB controller and PHY
ARM: OMAP: USB: Add phy binding information
usb: otg: utils: cha
Signed-off-by: Kishon Vijay Abraham I
---
drivers/usb/otg/otg.c | 77 +++
include/linux/usb/phy.h |8 +
2 files changed, 85 insertions(+)
diff --git a/drivers/usb/otg/otg.c b/drivers/usb/otg/otg.c
index dbf2043..e9799bb 100644
--- a/drivers
Added a phandle in the dt node for usb_otg to bind the PHY with the USB
controller and also updated the documentation with the binding information.
Signed-off-by: Kishon Vijay Abraham I
---
I'll add this patch in this series "usb: musb: add driver for control module"
which conta
OMAP platforms here.
Signed-off-by: Kishon Vijay Abraham I
---
This kind-of binding should be done in all the platforms (I've done only
for OMAP platform).
arch/arm/mach-omap2/usb-musb.c |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/usb-musb.c
The OMAP glue has been modified to get PHY by phandle for dt boot.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/usb/musb/omap2430.c |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index 3628a50..08709cf
s the binding information. This API should be
called by platform specific initialization code.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/usb/otg/otg.c | 37 +
include/linux/usb/phy.h | 22 ++
2 files changed, 59 insertions(+)
usb_get_phy will return -ENODEV if it's not able to find the phy. Hence
fixed all the callers of usb_get_phy to check for this error condition
instead of relying on a non-zero value as success condition.
Signed-off-by: Kishon Vijay Abraham I
---
Developed on
git://git.kernel.org/pub/scm/
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