you can mark a
BAR as e.g. both fixed size and reserved.
This series tries to address all the problems above.
Personally, I think that the code is more readable, both the endpoint
controller drivers, but also pci-epc-core.c.
Thank you for cleaning this up!
FWIW:
Reviewed-by: Kishon Vijay
MSIX support, but the existing
> dw_pcie_ep_raise_msix_irq doesn't work, so use the doorbell method to
> support the MSIX feature.
It does work after [1]. So the commit message might not be exactly true.
[1] -> https://lore.kernel.org/r/20200225081703.8857-1-kis...@ti.com
Thanks
Kishon
>
Gustavo,
On 06/11/19 3:10 PM, Gustavo Pimentel wrote:
> On Thu, Aug 29, 2019 at 6:13:18, Kishon Vijay Abraham I
> wrote:
>
> Hi, this email slip away from my attention...
>
>> Gustavo,
>>
>> On 27/08/19 6:55 PM, Andrew Murray wrote:
>>> On Sat, Aug
MSIX
>> feature in ls1088a, it is not OK, so I changed to another way. Thanks.
>
> Right, so the existing pci-layerscape-ep.c driver never supported MSIX yet it
> erroneously had a switch case statement to call dw_pcie_ep_raise_msix_irq
> which
> would never get used.
>
> Now that we're adding a platform with MSIX support the existing
> dw_pcie_ep_raise_msix_irq doesn't work (for this platform) so we are adding a
> different method.
Gustavo, can you confirm dw_pcie_ep_raise_msix_irq() works for designware as it
didn't work for both me and Xiaowei?
Thanks
Kishon
Hi,
(Fixed Lorenzo's email address. All the patches in the series have wrong email
id)
On 23/08/19 8:09 AM, Xiaowei Bao wrote:
>
>
>> -Original Message-----
>> From: Kishon Vijay Abraham I
>> Sent: 2019年8月22日 19:44
>> To: Xiaowei Bao ; bhelg...@goo
Hi,
On 22/08/19 4:52 PM, Xiaowei Bao wrote:
> The different PCIe controller in one board may be have different
> capability of MSI or MSIX, so change the way of getting the MSI
> capability, make it more flexible.
please use different pci_epc_features table for different boards.
Than
hink the dw_pcie_ep_raise_msix_irq function is not
> correct,
> because I think we can't get the MSIX table from the address ep->phys_base +
> tbl_addr,
> but I also don't know where I can get the correct MSIX table.
Sometime back when I tried raising MSI-X from EP, it was failing. It's quite
possible dw_pcie_ep_raise_msix_irq function is not correct.
MSI-X table can be obtained from the inbound ATU corresponding to the MSIX bar.
IMO MSI-X support in EP mode needs rework. For instance set_msix should also
take BAR number as input to be configured in the MSI-X capability. The function
driver (pci-epf-test.c) should allocate memory taking into account the MSI-X
table.
Thanks
Kishon
On 13/08/19 11:58 AM, Xiaowei Bao wrote:
> The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1
> is 32bit, BAR2 and BAR4 is 64bit, this is determined by hardware,
> so set the bar_fixed_64bit with 0x14.
>
> Signed-off-by: Xiaowei Bao
Acked-by: Kishon Vijay Abraha
On 13/08/19 8:23 AM, Xiaowei Bao wrote:
> The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1
> is 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware,
Do you mean BAR2 instead of BAR3 here?
Thanks
Kishon
> so set the bar_fixed_64bit with 0x14.
>
o
get rid of in [1]. After Lorenzo's review, one of us have to change it to the
new design.
Thanks
Kishon
[1] -> https://patchwork.kernel.org/project/linux-pci/list/?series=66177
> ---
> v2:
> - remove the EP mode check function.
> v3:
> - modif the return value when enter defa
(Removed Niklas as mails to him is bouncing)
Hi,
Please fix your email client. Refer Documentation/process/email-clients.rst
On 05/11/18 2:45 PM, Xiaowei Bao wrote:
>
>
> -Original Message-
> From: Kishon Vijay Abraham I
> Sent: 2018年11月5日 16:57
> To: X
Hi,
On 31/10/18 4:08 PM, Xiaowei Bao wrote:
>
>
> -Original Message-
> From: Kishon Vijay Abraham I
> Sent: 2018年10月31日 12:15
> To: Xiaowei Bao ; bhelg...@google.com;
> robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; lorenzo.pieral..
Hi,
On 31/10/18 8:03 AM, Xiaowei Bao wrote:
>
>
> -Original Message-
> From: Xiaowei Bao
> Sent: 2018年10月26日 17:19
> To: 'Kishon Vijay Abraham I' ; bhelg...@google.com;
> robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; l
return -ENOMEM;
> +
> + dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
> + pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
> + if (IS_ERR(pci->dbi_base))
> + return PTR_ERR(pci->dbi_base);
> +
> + pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
> + pci->dev = dev;
> + pci->ops = _pcie_ep_ops;
> + pcie->pci = pci;
> +
> + if (ls_pcie_is_bridge(pcie))
> + return -ENODEV;
For an endpoint this condition should never occur. This should only mean, a
wrong compatible has been used in dt.
Thanks
Kishon
+Grygorii, linux-omap
On Friday 06 July 2018 02:06 PM, Lukas Wunner wrote:
> [cc += Kishon Vijay Abraham]
>
> On Thu, Jul 05, 2018 at 11:18:28AM +0200, Rafael J. Wysocki wrote:
>> OK, so calling devices_kset_move_last() from really_probe() clearly is
>> a mistake.
>>
it ls_add_pcie_port(struct ls_pcie *pcie)
> {
> struct dw_pcie *pci = pcie->pci;
> @@ -309,18 +415,18 @@ static int __init ls_pcie_probe(struct platform_device
> *pdev)
> if (IS_ERR(pci->dbi_base))
> return PTR_ERR(pci->dbi_base);
>
> - pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
> + pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_BASE;
>
> - if (!ls_pcie_is_bridge(pcie))
> - return -ENODEV;
> + pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
>
> platform_set_drvdata(pdev, pcie);
>
> - ret = ls_add_pcie_port(pcie);
> - if (ret < 0)
> - return ret;
> + if (!ls_pcie_is_bridge(pcie))
> + ret = ls_add_pcie_ep(pcie, pdev);
HOST or EP mode should be obtained directly from dt.
Thanks
Kishon
; device_type = "pci";
> dma-coherent;
> num-lanes = <4>;
> + num-ib-windows = <6>;
> + num-ob-windows = <6>;
EP specific properties shouldn't be added in RC dt node. Ideally you should
have a separate dt node for RC and EP.
Thanks
Kishon
On Monday 05 June 2017 02:23 PM, Jisheng Zhang wrote:
> The dw_pcie_host_ops structures are never modified. Constify these
> structures such that these can be write-protected.
>
> Signed-off-by: Jisheng Zhang <jszh...@marvell.com>
Acked-by: Kishon Vijay Abraha
Nilsson <jesper.nils...@axis.com>
Cc: Joao Pinto <joao.pi...@synopsys.com>
Cc: Zhou Wang <wangzh...@hisilicon.com>
Cc: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 10 +
Cc: Niklas Cassel <niklas.cas...@axis.com>
Cc: Jesper Nilsson <jesper.nils...@axis.com>
Cc: Joao Pinto <joao.pi...@synopsys.com>
Cc: Zhou Wang <wangzh...@hisilicon.com>
Cc: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Kishon Vijay Abraham I <ki
Populate cpu_addr_fixup ops to extract the least 28 bits of the
corresponding cpu address.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7
the address range is fixed, device mode requires
different addresses to be programmed based on the host buffer address.
Add a new ops to get the least 28 bits of the corresponding 32 bit
CPU address and invoke it before programming the address translation
unit.
Signed-off-by: Kishon Vijay Abraham I <
before sending the next revision of endpoint
series.
The entire endpoint support is pushed here:
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/pci-endpoint.git next
[1] -> https://lkml.org/lkml/2017/2/15/273
[2] -> https://lkml.org/lkml/2017/1/13/562
Kishon Vijay Abraham I (4):
PC
Hi Tony,
On Saturday 21 January 2017 12:00 AM, Tony Lindgren wrote:
> * Kishon Vijay Abraham I <kis...@ti.com> [170112 02:34]:
>> Add pcie1 dt node in order for the controller to operate in
>> endpoint mode. However since none of the dra7 based boards have
>>
Hi,
On Thursday 19 January 2017 03:16 AM, Rob Herring wrote:
> On Thu, Jan 12, 2017 at 03:56:19PM +0530, Kishon Vijay Abraham I wrote:
>> Update device tree binding documentation of TI's dra7xx PCI
>> controller to include property for enabling legacy mode.
>>
>>
om>
Cc: Jesper Nilsson <jesper.nils...@axis.com>
Cc: Joao Pinto <joao.pi...@synopsys.com>
Cc: Zhou Wang <wangzh...@hisilicon.com>
Cc: Gabriele Paoloni <gabriele.paol...@huawei.com>
Cc: Stanimir Varbanov <svarba...@mm-sol.com>
Cc: Pratyush Anand <pratyush.an...@gm
abriele.paol...@huawei.com>
Cc: Stanimir Varbanov <svarba...@mm-sol.com>
Cc: Pratyush Anand <pratyush.an...@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 80 -
drivers/pci/dwc/pci-exynos.c | 78 +
and pcie-designware-host.c
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pcie-designware.c | 18 +++---
drivers/pci/dwc/pcie-designware.h |1 -
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware.c
b/d
jpi...@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pcie-designware.c | 70
drivers/pci/dwc/pcie-designware.h | 71 +
2 files changed, 71 insertions(+), 70 deletions(-)
r iATU unroll only on platforms that use ATU
The patches has been pushed to
git://git.ti.com/linux-phy/linux-phy.git dwc-rework
Kishon Vijay Abraham I (10):
PCI: dwc: designware: Move the register defines to designware header
file
PCI: dwc: *all*: Add platform_set_drvdata
PCI: dwc: *all*:
Split pcie-designware.c into pcie-designware-host.c that contains
the host specific parts of the driver and pcie-designware.c that
contains the parts used by both host driver and endpoint driver.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/Ma
CONFIG_PCI is used to enable the host mode PCI. In preparation for adding
endpoint mode support to designware driver, remove the dependency of
designware to CONFIG_PCI and make only the host specific part depend on
CONFIG_PCI.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
d
Now that pci designware host has a separate file, create a new
config symbol to select the host only driver. This will enable
to independently select host support and endpoint suppor
(when it's added).
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/K
No functional change. Fix all checkpatch warnings and check errors
in pcie-designware.c
Acked-By: Joao Pinto <jpi...@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pcie-designware.c | 42 ++---
1 file
i.com>
Cc: Joao Pinto <joao.pi...@synopsys.com>
Cc: Stanimir Varbanov <svarba...@mm-sol.com>
Cc: Pratyush Anand <pratyush.an...@gmail.com>
Reviewed-By: Joao Pinto <jpi...@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pci-dra7
No functional change. Get device pointer at the beginning of
dw_pcie_host_init instead of getting it all over dw_pcie_host_init.
This is in preparation for splitting struct pcie_port into host and
core structures (Once split pcie_port will not have device pointer).
Signed-off-by: Kishon Vijay
Hi,
On Tuesday 24 January 2017 09:32 PM, Christoph Hellwig wrote:
> On Thu, Jan 12, 2017 at 03:56:20PM +0530, Kishon Vijay Abraham I wrote:
>> Add PCI endpoint test driver that can verify base address
>> register, legacy interrupt/MSI interrupt and read/write/copy
>>
Hi Joao,
On Monday 16 January 2017 03:57 PM, Joao Pinto wrote:
>
> Hi,
>
> Às 5:21 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
>> Hi Joao,
>>
>> On Friday 13 January 2017 10:19 PM, Joao Pinto wrote:
>>> Às 10:26 AM de 1/12/2017, Kishon Vi
Hi Tony,
On Friday 13 January 2017 10:45 PM, Tony Lindgren wrote:
> * Kishon Vijay Abraham I <kis...@ti.com> [170112 02:35]:
>> The PCIe programming sequence in TRM suggests CLKSTCTRL of PCIe should
>> be set to SW_WKUP. There are no issues when CLKSTCTRL is set to HW_AUTO
&
Hi Christoph,
On Friday 13 January 2017 11:36 PM, Christoph Hellwig wrote:
> Hi Kishon,
>
> a couple comments on the configfs layout based on my experiments with
> your previous drop to implement a NVMe device using it.
Thanks for trying it out!
>
> I don't think most of th
Hi Joao,
On Friday 13 January 2017 11:20 PM, Joao Pinto wrote:
> Hi Kishon,
>
> Às 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>> Now that pci designware host has a separate file, create a new
>> config symbol to select the host only driver. This is in pre
Hi Joao,
On Friday 13 January 2017 10:19 PM, Joao Pinto wrote:
> Às 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>> Split pcie-designware.c into pcie-designware-host.c that contains
>> the host specific parts of the driver and pcie-designware.c that
>> contains t
Hi,
On Friday 13 January 2017 10:43 PM, Joao Pinto wrote:
> Hi,
>
> Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>> *num-lanes* dt property is parsed in dw_pcie_host_init. However
>> *num-lanes* property is applicable to both root complex mode and
>> end
abriele.paol...@huawei.com>
Cc: Stanimir Varbanov <svarba...@mm-sol.com>
Cc: Pratyush Anand <pratyush.an...@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
I've pushed the series to
git://git.ti.com/linux-phy/linux-phy.git pci_ep_v1
I have access to only dra7 base
functions
that is specific to an endpoint function.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/Makefile|2 +
drivers/pci/Kconfig |1 +
drivers/pci/endpoint/Kconfig| 21 ++
drivers/pci/endpoint/Makefile |6 +
d
Add endpoint mode support to designware driver. This uses the
EP Core layer introduced recently to add endpoint mode support.
*Any* function driver can now use this designware device
in order to achieve the EP functionality.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drive
No functional change. Fix all checkpatch warnings and check errors
in pcie-designware.c
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pcie-designware.c | 42 ++---
1 file changed, 21 insertions(+), 21 deletions(-)
diff
doesn't have to enable msi_interrupts.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 8
nt support is added, all the
endpoint related setup can be added in a separate function.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/dri
Add binding documentation for pci-test endpoint function that helps in
adding and configuring pci-test endpoint function.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
Documentation/PCI/00-INDEX |2 ++
.../PCI/endpoint/function/binding/pci-te
<jingooh...@gmail.com>
Cc: Murali Karicheri <m-kariche...@ti.com>
Cc: Joao Pinto <joao.pi...@synopsys.com>
Cc: Stanimir Varbanov <svarba...@mm-sol.com>
Cc: Pratyush Anand <pratyush.an...@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
driv
Split pcie-designware.c into pcie-designware-host.c that contains
the host specific parts of the driver and pcie-designware.c that
contains the parts used by both host driver and endpoint driver.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/Ma
endpoint mode support to designware driver.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c |8 ++--
drivers/pci/dwc/pci-exynos.c | 16 +++
drivers/pci/dwc/pci-imx6.c | 58 +++
drivers/p
This adds a new endpoint function driver (to program the virtual
test device) making use of the EP-core library.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/endpoint/Kconfig |2 +
drivers/pci/endpoint/Makefile |3 +-
drive
Introduce a new configfs entry to configure the EP function (like
configuring the standard configuration header entries) and to
bind the EP function with EP controller.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/endpoint/Kconfig |4 +-
drivers/pci/en
Add Documentation to help users use endpoint library to enable endpoint
mode in the PCI controller and add new PCI endpoint functions.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
Documentation/PCI/00-INDEX |2 +
Documentation/PCI/endpoint/pci-endpoi
No functional change. Move the register defines and other macros from
pcie-designware.c to pcie-designware.h. This is in preparation to
split the pcie-designware.c file into designware core file and host
specific file.
While at that also fix a checkpatch warning.
Signed-off-by: Kishon Vijay
Now that pci designware host has a separate file, create a new
config symbol to select the host only driver. This is in preparation
to enable endpoint support to designware driver.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/Kconfig
Add device tree binding documentation for pci dra7xx EP mode.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 37 ++
1 file changed, 30 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bi
Update device tree binding documentation of TI's dra7xx PCI
controller to include property for enabling legacy mode.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
Documentation/devicetree/bindings/pci/ti-pci.txt |4
1 file changed, 4 insertions(+)
diff --git a/Documen
The PCIe programming sequence in TRM suggests CLKSTCTRL of PCIe should
be set to SW_WKUP. There are no issues when CLKSTCTRL is set to HW_AUTO
in RC mode. However in EP mode, the host system is not able to access the
MEMSPACE and setting the CLKSTCTRL to SW_WKUP fixes it.
Signed-off-by: Kishon
Add maintainer for the newly introduced PCI EP framework.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
MAINTAINERS |9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8672f18..021f676 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -
-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 10 +++--
drivers/pci/dwc/pci-exynos.c | 10 +++--
drivers/pci/dwc/pci-imx6.c | 67
drivers/pci/dwc/pci-keystone-dw.c | 15 ---
drivers/p
No functional change. Get device pointer at the beginning of
dw_pcie_host_init instead of getting it all over dw_pcie_host_init.
This is in preparation for splitting struct pcie_port into host and
core structures (Once split pcie_port will not have device pointer).
Signed-off-by: Kishon Vijay
Add Documentation to help users use pci endpoint to configure
pci endpoint function and to bind the endpoint function
with endpoint controller.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
Documentation/PCI/00-INDEX |2 +
Documentation/PCI/endpoi
Add specification for the *pci test* virtual function device. The endpoint
function driver and the host pci driver should be created based on this
specification.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
Documentation/PCI/00-INDEX |2 +
Documentati
.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 333aa56..7666e3e 100644
--- a/drivers/p
and pcie-designware-host.c
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pcie-designware.c | 18 +++---
drivers/pci/dwc/pcie-designware.h |1 -
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware.c
b/d
Add device tree binding documentation for pci designware EP mode.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
.../devicetree/bindings/pci/designware-pcie.txt| 26 ++--
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/Documentation/devi
the address range is fixed, device mode requires
different addresses to be programmed based on the host buffer address.
Add a new ops to get the least 28 bits of the corresponding 32 bit
CPU address and invoke it before programming the address translation
unit.
Signed-off-by: Kishon Vijay Abraham I <
Add PCI endpoint test driver that can verify base address
register, legacy interrupt/MSI interrupt and read/write/copy
buffers between host and device. The corresponding pci-epf-test
function driver should be used on the EP side.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
d
Add a simple test script that invokes the pcitest userspace tool
to perform all the PCI endpoint tests (BAR tests, interrupt tests,
read tests, write tests and copy tests).
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
tools/pci/pcitest.sh
Add pcie1 dt node in order for the controller to operate in
endpoint mode. However since none of the dra7 based boards have
slots configured to operate in endpoint mode, keep EP mode
disabled.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
arch/arm/boot/dts/am572x-i
OKAY
WRITE (1024001 bytes): OKAY
Copy Tests
COPY ( 1 bytes): OKAY
COPY ( 1024 bytes): OKAY
COPY ( 1025 bytes): OKAY
COPY (1024000 bytes): OKAY
COPY (1024001 bytes): OKAY
Kishon Vijay Abraham I (37):
PCI: dwc: dra7xx: Group all host
The PCIe controller integrated in dra7xx SoCs is capable of operating
in endpoint mode. Add endpoint mode support to dra7xx driver.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/Kconfig | 31 +-
drivers/pci/dwc/Makefile |4 +-
drive
Add a userspace tool to invoke the ioctls exposed by the
PCI endpoint test driver to perform various PCI tests.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
tools/pci/pcitest.c | 186 +++
1 file changed, 186 insertions(+)
creat
CONFIG_PCI is used to enable the host mode PCI. In preparation for adding
endpoint mode support to designware driver, remove the dependency of
designware to CONFIG_PCI and make only the host specific part depend on
CONFIG_PCI.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
d
Add Documentation for pci-endpoint-test driver.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
Documentation/misc-devices/pci-endpoint-test.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/misc-devices/pci-endpoint-test.txt
Populate cpu_addr_fixup ops to extract the least 28 bits of the
corresponding cpu address.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7
Add start_link and stop_link ops in dw_pcie_ops to start or stop
the link. This will be used by endpoint functions to start the
link once the setup has been done.
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
---
drivers/pci/dwc/pcie-designware.h |2 ++
1 file changed, 2 inse
om>
Cc: Jesper Nilsson <jesper.nils...@axis.com>
Cc: Joao Pinto <joao.pi...@synopsys.com>
Cc: Zhou Wang <wangzh...@hisilicon.com>
Cc: Gabriele Paoloni <gabriele.paol...@huawei.com>
Cc: Stanimir Varbanov <svarba...@mm-sol.com>
Cc: Pratyush Anand <pratyush.an...@gm
; 1 drivers/soc/mediatek/mtk-pmic-wrap.c:1086:16: warning: large integer
>> implicitly truncated to unsigned type [-Woverflow]
>
> I sent out a patch on May 12 for this, got no reply. I've applied my own patch
> now on the arm-soc fixes branch.
>
>> 1 drivers/phy/phy-exynos-mipi-video.c:238:13: warning: 'val' may be
>> used uninitialized in this function [-Wmaybe-uninitialized]
>
> I sent a patch on May 11, it was reviewed by Krzysztof Kozlowski, but not yet
> applied.
Is it okay if I send this during the -rc cycle?
Thanks
Kishon
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On Monday 21 January 2013 06:51 PM, Roger Quadros wrote:
On 01/16/2013 05:01 PM, Kishon Vijay Abraham I wrote:
Added an API devm_usb_get_phy_by_phandle(), to get usb phy by passing a
device node phandle value. This function will return a pointer to
the phy on success, -EPROBE_DEFER
Hi,
On Monday 21 January 2013 06:48 PM, Roger Quadros wrote:
On 01/16/2013 05:01 PM, Kishon Vijay Abraham I wrote:
The OMAP glue has been modified to get PHY by phandle for dt boot.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/usb/musb/omap2430.c |7 ++-
1 file
On Friday 18 January 2013 05:18 PM, Felipe Balbi wrote:
On Wed, Jan 16, 2013 at 08:30:56PM +0530, Kishon Vijay Abraham I wrote:
New platforms are being added which has multiple PHY's (of same type) and
which has multiple USB controllers. The binding information has to be
present in the PHY
Hi,
On Thursday 17 January 2013 03:09 PM, Roger Quadros wrote:
On 01/16/2013 05:00 PM, Kishon Vijay Abraham I wrote:
This is in preparation for the changes in PHY library to support adding
and getting multiple PHYs of the same type. In the new design, the
binding information between the PHY
Hi,
On Thursday 17 January 2013 03:07 PM, Roger Quadros wrote:
On 01/16/2013 05:00 PM, Kishon Vijay Abraham I wrote:
New platforms are added which has multiple PHY's (of same type) and
which has multiple USB controllers. The binding information has to be
present in the PHY library (otg.c
Hi,
On Thursday 17 January 2013 05:41 PM, Vivek Gautam wrote:
Hi Kishon,
On Wed, Jan 16, 2013 at 8:30 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
This is in preparation for the changes in PHY library to support adding
and getting multiple PHYs of the same type. In the new design
Hi,
On Thursday 17 January 2013 09:37 PM, Roger Quadros wrote:
On 01/16/2013 05:00 PM, Kishon Vijay Abraham I wrote:
In order to add support for multipe PHY's of the same type, the API's
for adding PHY and getting PHY has been changed. Now the binding
information of the PHY and controller
the binding information. This API should be
called by platform specific initialization code.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/usb/otg/otg.c | 37 +
include/linux/usb/phy.h | 22 ++
2 files changed, 59
The OMAP glue has been modified to get PHY by phandle for dt boot.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/usb/musb/omap2430.c |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index
platforms here.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
This kind-of binding should be done in all the platforms (I've done only
for OMAP platform).
arch/arm/mach-omap2/usb-musb.c |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/usb-musb.c
Added a phandle in the dt node for usb_otg to bind the PHY with the USB
controller and also updated the documentation with the binding information.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
I'll add this patch in this series usb: musb: add driver for control module
which contains
...@pengutronix.de
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/usb/otg/otg.c | 77 +++
include/linux/usb/phy.h |8 +
2 files changed, 85 insertions(+)
diff --git a/drivers/usb/otg/otg.c b/drivers/usb/otg/otg.c
index dbf2043
for control module patch series.
Did basic enumeration testing in omap4 panda, omap4 sdp and omap3 beagle.
Kishon Vijay Abraham I (6):
usb: otg: Add an API to bind the USB controller and PHY
ARM: OMAP: USB: Add phy binding information
usb: otg: utils: change the phy lib to support multiple PHYs
and an index should be passed. Based on the binding
information that is added in the platform file, get_phy will return the
approappropriate PHY.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-shmobile/board-marzen.c |2 +-
drivers/power/ab8500_charger.c|2
usb_get_phy will return -ENODEV if it's not able to find the phy. Hence
fixed all the callers of usb_get_phy to check for this error condition
instead of relying on a non-zero value as success condition.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Developed on
git://git.kernel.org/pub
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