On Freitag, 3. August 2018 06:28:00 CEST Tomas Vanek via OpenOCD-devel wrote:
> On 03.08.2018 2:28, Christopher Head wrote:
> > On August 1, 2018 12:15:18 PM PDT, Tomas Vanek via OpenOCD-devel wrote:
> >> and MEM-AP access goes through DCache.
> >> Of course, some fancy ui wold be nice. Might be
On 03.08.2018 2:28, Christopher Head wrote:
On August 1, 2018 12:15:18 PM PDT, Tomas Vanek via OpenOCD-devel
wrote:
and MEM-AP access goes through DCache.
Of course, some fancy ui wold be nice. Might be set by default in
target.cfg or so.
Yes, that’s perfect, thanks! I’m a little curious why
On August 1, 2018 12:15:18 PM PDT, Tomas Vanek via OpenOCD-devel
wrote:
>and MEM-AP access goes through DCache.
>Of course, some fancy ui wold be nice. Might be set by default in
>target.cfg or so.
Yes, that’s perfect, thanks! I’m a little curious why it’s not the default? It
looks like there
On Mittwoch, 1. August 2018 19:13:58 CEST Christopher Head wrote:
> Hello!
> I was wondering about how OpenOCD was meant to interoperate with CPU caches.
> Right now, the Cortex M target has no cache management at all, which means
> that, on devices whose debug buses connect directly to RAM, any
On 02.08.2018 15:35, Antonio Borneo wrote:
On Wed, Aug 1, 2018 at 9:15 PM, Tomas Vanek via OpenOCD-devel
wrote:
On 01.08.2018 19:13, Christopher Head wrote:
Hello!
I was wondering about how OpenOCD was meant to interoperate with CPU
caches. Right now, the Cortex M target has no cache
On Wed, Aug 1, 2018 at 9:15 PM, Tomas Vanek via OpenOCD-devel
wrote:
> On 01.08.2018 19:13, Christopher Head wrote:
>>
>> Hello!
>> I was wondering about how OpenOCD was meant to interoperate with CPU
>> caches. Right now, the Cortex M target has no cache management at all, which
>> means that,
On 01.08.2018 19:13, Christopher Head wrote:
Hello!
I was wondering about how OpenOCD was meant to interoperate with CPU caches.
Right now, the Cortex M target has no cache management at all, which means
that, on devices whose debug buses connect directly to RAM, any memory access
through
Hello!
I was wondering about how OpenOCD was meant to interoperate with CPU caches.
Right now, the Cortex M target has no cache management at all, which means
that, on devices whose debug buses connect directly to RAM, any memory access
through OpenOCD shows what’s in RAM, which may not be the
